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PCI: Define macro for Marvell vendor ID
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
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1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1 55 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 56 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 57 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 58};
59
60enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
5f173107 65 board_ahci_yes_fbs,
1da177e4 66
441577ef
TH		 67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
83f2b963
TH		 69 board_ahci_mcp77,
70 board_ahci_mcp89,
441577ef
TH		 71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
438ac6d5 88#ifdef CONFIG_PM
c1332875
TH		 89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 91#endif
ad616ffb 92
fad16e7a
TH		 93static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
029cfd6b
TH		 97static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
a1efdaba 99 .hardreset = ahci_vt8251_hardreset,
029cfd6b 100};
edc93052 101
029cfd6b
TH		 102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
a1efdaba 104 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 105};
106
98ac62de 107static const struct ata_port_info ahci_port_info[] = {
441577ef 108 /* by features */
facb8fa6 109 [board_ahci] = {
1188c0d8 110 .flags = AHCI_FLAG_COMMON,
14bdef98 111 .pio_mask = ATA_PIO4,
469248ab 112 .udma_mask = ATA_UDMA6,
1da177e4
LT		 113 .port_ops = &ahci_ops,
114 },
facb8fa6 115 [board_ahci_ign_iferr] = {
441577ef 116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 117 .flags = AHCI_FLAG_COMMON,
14bdef98 118 .pio_mask = ATA_PIO4,
469248ab 119 .udma_mask = ATA_UDMA6,
441577ef 120 .port_ops = &ahci_ops,
bf2af2a2 121 },
facb8fa6 122 [board_ahci_nosntf] = {
441577ef 123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 124 .flags = AHCI_FLAG_COMMON,
14bdef98 125 .pio_mask = ATA_PIO4,
469248ab 126 .udma_mask = ATA_UDMA6,
41669553
TH		 127 .port_ops = &ahci_ops,
128 },
facb8fa6 129 [board_ahci_yes_fbs] = {
5f173107
TH		 130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
441577ef 136 /* by chipsets */
facb8fa6 137 [board_ahci_mcp65] = {
83f2b963
TH		 138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
ae01b249 140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
facb8fa6 145 [board_ahci_mcp77] = {
83f2b963
TH		 146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
facb8fa6 152 [board_ahci_mcp89] = {
83f2b963 153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 154 .flags = AHCI_FLAG_COMMON,
14bdef98 155 .pio_mask = ATA_PIO4,
469248ab 156 .udma_mask = ATA_UDMA6,
441577ef 157 .port_ops = &ahci_ops,
55a61604 158 },
facb8fa6 159 [board_ahci_mv] = {
417a1a6d 160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 163 .pio_mask = ATA_PIO4,
cd70c266
JG		 164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
facb8fa6 167 [board_ahci_sb600] = {
441577ef
TH		 168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 171 .flags = AHCI_FLAG_COMMON,
14bdef98 172 .pio_mask = ATA_PIO4,
e39fc8c9 173 .udma_mask = ATA_UDMA6,
345347c5 174 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 175 },
facb8fa6 176 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
345347c5 181 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 182 },
facb8fa6 183 [board_ahci_vt8251] = {
441577ef 184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
441577ef 188 .port_ops = &ahci_vt8251_ops,
1b677afd 189 },
1da177e4
LT		 190};
191
3b7d697d 192static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 193 /* Intel */
54bb3a94
JG		 194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 268 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
269 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
271 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
151743fd
JR		 284 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
285 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
286 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
287 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
288 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
289 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
291 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
fe7fa31a 292
e34bb370
TH		 293 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
294 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
295 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 296 /* JMicron 362B and 362C have an AHCI function with IDE class code */
297 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
298 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 299
300 /* ATI */
c65ec1c2 301 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 302 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
303 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
304 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
305 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
306 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
307 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 308
e2dd90b1 309 /* AMD */
5deab536 310 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 311 /* AMD is using RAID class only for ahci controllers */
312 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
313 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
314
fe7fa31a 315 /* VIA */
54bb3a94 316 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 317 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 318
319 /* NVIDIA */
e297d99e
TH		 320 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
321 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
322 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
323 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
324 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
325 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
326 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
327 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 328 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
329 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
330 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
331 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
332 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
333 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
334 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
335 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
336 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
337 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
341 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
342 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
343 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
344 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
345 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
346 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
347 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
348 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
349 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
350 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
357 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
358 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
359 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
360 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
361 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
362 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
363 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
364 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
365 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
366 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
369 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
370 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
371 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
372 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
373 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
374 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
375 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
376 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
377 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
378 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
381 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
382 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
383 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
384 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
385 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
386 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
387 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
388 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
389 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
390 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
393 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
394 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
395 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
396 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
397 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
398 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
399 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
400 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
401 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
402 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 404
95916edd 405 /* SiS */
20e2de4a
TH		 406 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
407 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
408 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 409
318893e1
AR		 410 /* ST Microelectronics */
411 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
412
cd70c266
JG		 413 /* Marvell */
414 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 415 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 416 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 417 .class = PCI_CLASS_STORAGE_SATA_AHCI,
418 .class_mask = 0xffffff,
5f173107 419 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 420 { PCI_DEVICE(0x1b4b, 0x9125),
421 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
642d8925
MJ		 422 { PCI_DEVICE(0x1b4b, 0x917a),
423 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
17c60c6b
AC		 424 { PCI_DEVICE(0x1b4b, 0x9192),
425 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
50be5e36
TH		 426 { PCI_DEVICE(0x1b4b, 0x91a3),
427 .driver_data = board_ahci_yes_fbs },
cd70c266 428
c77a036b
MN		 429 /* Promise */
430 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
431
c9703765 432 /* Asmedia */
7b4f6eca
AC		 433 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
434 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
435 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
436 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 437
7f9c9f8e
HD		 438 /* Enmotus */
439 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
440
415ae2b5
JG		 441 /* Generic, PCI class code for AHCI */
442 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 443 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 444
1da177e4
LT		 445 { } /* terminate list */
446};
447
448
449static struct pci_driver ahci_pci_driver = {
450 .name = DRV_NAME,
451 .id_table = ahci_pci_tbl,
452 .probe = ahci_init_one,
24dc5f33 453 .remove = ata_pci_remove_one,
438ac6d5 454#ifdef CONFIG_PM
c1332875 455 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 456 .resume = ahci_pci_device_resume,
457#endif
458};
1da177e4 459
365cfa1e
AV		 460#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
461static int marvell_enable;
462#else
463static int marvell_enable = 1;
464#endif
465module_param(marvell_enable, int, 0644);
466MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 467
1da177e4 468
365cfa1e
AV		 469static void ahci_pci_save_initial_config(struct pci_dev *pdev,
470 struct ahci_host_priv *hpriv)
471{
472 unsigned int force_port_map = 0;
473 unsigned int mask_port_map = 0;
67846b30 474
365cfa1e
AV		 475 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
476 dev_info(&pdev->dev, "JMB361 has only one port\n");
477 force_port_map = 1;
1da177e4
LT		 478 }
479
365cfa1e
AV		 480 /*
481 * Temporary Marvell 6145 hack: PATA port presence
482 * is asserted through the standard AHCI port
483 * presence register, as bit 4 (counting from 0)
d28f87aa 484 */
365cfa1e
AV		 485 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
486 if (pdev->device == 0x6121)
487 mask_port_map = 0x3;
488 else
489 mask_port_map = 0xf;
490 dev_info(&pdev->dev,
491 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
492 }
1da177e4 493
365cfa1e
AV		 494 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
495 mask_port_map);
1da177e4
LT		 496}
497
365cfa1e 498static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 499{
365cfa1e 500 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 501
365cfa1e 502 ahci_reset_controller(host);
1da177e4 503
365cfa1e
AV		 504 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
505 struct ahci_host_priv *hpriv = host->private_data;
506 u16 tmp16;
d6ef3153 507
365cfa1e
AV		 508 /* configure PCS */
509 pci_read_config_word(pdev, 0x92, &tmp16);
510 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
511 tmp16 |= hpriv->port_map;
512 pci_write_config_word(pdev, 0x92, tmp16);
513 }
d6ef3153
SH		 514 }
515
1da177e4
LT		 516 return 0;
517}
518
365cfa1e 519static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 520{
365cfa1e
AV		 521 struct ahci_host_priv *hpriv = host->private_data;
522 struct pci_dev *pdev = to_pci_dev(host->dev);
523 void __iomem *port_mmio;
78cd52d0 524 u32 tmp;
365cfa1e 525 int mv;
78cd52d0 526
365cfa1e
AV		 527 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
528 if (pdev->device == 0x6121)
529 mv = 2;
530 else
531 mv = 4;
532 port_mmio = __ahci_port_base(host, mv);
78cd52d0 533
365cfa1e 534 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 535
365cfa1e
AV		 536 /* clear port IRQ */
537 tmp = readl(port_mmio + PORT_IRQ_STAT);
538 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
539 if (tmp)
540 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 541 }
542
365cfa1e 543 ahci_init_controller(host);
edc93052
TH		 544}
545
365cfa1e
AV		 546static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
547 unsigned long deadline)
d6ef3153 548{
365cfa1e
AV		 549 struct ata_port *ap = link->ap;
550 bool online;
d6ef3153
SH		 551 int rc;
552
365cfa1e 553 DPRINTK("ENTER\n");
d6ef3153 554
365cfa1e 555 ahci_stop_engine(ap);
d6ef3153 556
365cfa1e
AV		 557 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
558 deadline, &online, NULL);
d6ef3153
SH		 559
560 ahci_start_engine(ap);
d6ef3153 561
365cfa1e 562 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 563
365cfa1e
AV		 564 /* vt8251 doesn't clear BSY on signature FIS reception,
565 * request follow-up softreset.
566 */
567 return online ? -EAGAIN : rc;
7d50b60b
TH		 568}
569
365cfa1e
AV		 570static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
571 unsigned long deadline)
7d50b60b 572{
365cfa1e 573 struct ata_port *ap = link->ap;
1c954a4d 574 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 575 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
576 struct ata_taskfile tf;
577 bool online;
578 int rc;
7d50b60b 579
365cfa1e 580 ahci_stop_engine(ap);
028a2596 581
365cfa1e
AV		 582 /* clear D2H reception area to properly wait for D2H FIS */
583 ata_tf_init(link->device, &tf);
584 tf.command = 0x80;
585 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 586
365cfa1e
AV		 587 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
588 deadline, &online, NULL);
028a2596 589
365cfa1e 590 ahci_start_engine(ap);
c1332875 591
365cfa1e
AV		 592 /* The pseudo configuration device on SIMG4726 attached to
593 * ASUS P5W-DH Deluxe doesn't send signature FIS after
594 * hardreset if no device is attached to the first downstream
595 * port && the pseudo device locks up on SRST w/ PMP==0. To
596 * work around this, wait for !BSY only briefly. If BSY isn't
597 * cleared, perform CLO and proceed to IDENTIFY (achieved by
598 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
599 *
600 * Wait for two seconds. Devices attached to downstream port
601 * which can't process the following IDENTIFY after this will
602 * have to be reset again. For most cases, this should
603 * suffice while making probing snappish enough.
604 */
605 if (online) {
606 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
607 ahci_check_ready);
608 if (rc)
609 ahci_kick_engine(ap);
c1332875 610 }
c1332875
TH		 611 return rc;
612}
613
365cfa1e 614#ifdef CONFIG_PM
c1332875
TH		 615static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
616{
cca3974e 617 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 618 struct ahci_host_priv *hpriv = host->private_data;
d8993349 619 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 620 u32 ctl;
621
9b10ae86
TH		 622 if (mesg.event & PM_EVENT_SUSPEND &&
623 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 624 dev_err(&pdev->dev,
625 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 626 return -EIO;
627 }
628
3a2d5b70 629 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 630 /* AHCI spec rev1.1 section 8.3.3:
631 * Software must disable interrupts prior to requesting a
632 * transition of the HBA to D3 state.
633 */
634 ctl = readl(mmio + HOST_CTL);
635 ctl &= ~HOST_IRQ_EN;
636 writel(ctl, mmio + HOST_CTL);
637 readl(mmio + HOST_CTL); /* flush */
638 }
639
640 return ata_pci_device_suspend(pdev, mesg);
641}
642
643static int ahci_pci_device_resume(struct pci_dev *pdev)
644{
cca3974e 645 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 646 int rc;
647
553c4aa6
TH		 648 rc = ata_pci_device_do_resume(pdev);
649 if (rc)
650 return rc;
c1332875
TH		 651
652 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 653 rc = ahci_pci_reset_controller(host);
c1332875
TH		 654 if (rc)
655 return rc;
656
781d6550 657 ahci_pci_init_controller(host);
c1332875
TH		 658 }
659
cca3974e 660 ata_host_resume(host);
c1332875
TH		 661
662 return 0;
663}
438ac6d5 664#endif
c1332875 665
4447d351 666static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 667{
1da177e4 668 int rc;
1da177e4 669
318893e1
AR		 670 /*
671 * If the device fixup already set the dma_mask to some non-standard
672 * value, don't extend it here. This happens on STA2X11, for example.
673 */
674 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
675 return 0;
676
1da177e4 677 if (using_dac &&
6a35528a
YH		 678 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
679 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 680 if (rc) {
284901a9 681 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 682 if (rc) {
a44fec1f
JP		 683 dev_err(&pdev->dev,
684 "64-bit DMA enable failed\n");
1da177e4
LT		 685 return rc;
686 }
687 }
1da177e4 688 } else {
284901a9 689 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 690 if (rc) {
a44fec1f 691 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 692 return rc;
693 }
284901a9 694 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 695 if (rc) {
a44fec1f
JP		 696 dev_err(&pdev->dev,
697 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 698 return rc;
699 }
700 }
1da177e4
LT		 701 return 0;
702}
703
439fcaec
AV		 704static void ahci_pci_print_info(struct ata_host *host)
705{
706 struct pci_dev *pdev = to_pci_dev(host->dev);
707 u16 cc;
708 const char *scc_s;
709
710 pci_read_config_word(pdev, 0x0a, &cc);
711 if (cc == PCI_CLASS_STORAGE_IDE)
712 scc_s = "IDE";
713 else if (cc == PCI_CLASS_STORAGE_SATA)
714 scc_s = "SATA";
715 else if (cc == PCI_CLASS_STORAGE_RAID)
716 scc_s = "RAID";
717 else
718 scc_s = "unknown";
719
720 ahci_print_info(host, scc_s);
721}
722
edc93052
TH		 723/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
724 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
725 * support PMP and the 4726 either directly exports the device
726 * attached to the first downstream port or acts as a hardware storage
727 * controller and emulate a single ATA device (can be RAID 0/1 or some
728 * other configuration).
729 *
730 * When there's no device attached to the first downstream port of the
731 * 4726, "Config Disk" appears, which is a pseudo ATA device to
732 * configure the 4726. However, ATA emulation of the device is very
733 * lame. It doesn't send signature D2H Reg FIS after the initial
734 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
735 *
736 * The following function works around the problem by always using
737 * hardreset on the port and not depending on receiving signature FIS
738 * afterward. If signature FIS isn't received soon, ATA class is
739 * assumed without follow-up softreset.
740 */
741static void ahci_p5wdh_workaround(struct ata_host *host)
742{
743 static struct dmi_system_id sysids[] = {
744 {
745 .ident = "P5W DH Deluxe",
746 .matches = {
747 DMI_MATCH(DMI_SYS_VENDOR,
748 "ASUSTEK COMPUTER INC"),
749 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
750 },
751 },
752 { }
753 };
754 struct pci_dev *pdev = to_pci_dev(host->dev);
755
756 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
757 dmi_check_system(sysids)) {
758 struct ata_port *ap = host->ports[1];
759
a44fec1f
JP		 760 dev_info(&pdev->dev,
761 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 762
763 ap->ops = &ahci_p5wdh_ops;
764 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
765 }
766}
767
2fcad9d2
TH		 768/* only some SB600 ahci controllers can do 64bit DMA */
769static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 770{
771 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 772 /*
773 * The oldest version known to be broken is 0901 and
774 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 775 * Enable 64bit DMA on 1501 and anything newer.
776 *
03d783bf
TH		 777 * Please read bko#9412 for more info.
778 */
58a09b38
SH		 779 {
780 .ident = "ASUS M2A-VM",
781 .matches = {
782 DMI_MATCH(DMI_BOARD_VENDOR,
783 "ASUSTeK Computer INC."),
784 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
785 },
03d783bf 786 .driver_data = "20071026", /* yyyymmdd */
58a09b38 787 },
e65cc194
MN		 788 /*
789 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
790 * support 64bit DMA.
791 *
792 * BIOS versions earlier than 1.5 had the Manufacturer DMI
793 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
794 * This spelling mistake was fixed in BIOS version 1.5, so
795 * 1.5 and later have the Manufacturer as
796 * "MICRO-STAR INTERNATIONAL CO.,LTD".
797 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
798 *
799 * BIOS versions earlier than 1.9 had a Board Product Name
800 * DMI field of "MS-7376". This was changed to be
801 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
802 * match on DMI_BOARD_NAME of "MS-7376".
803 */
804 {
805 .ident = "MSI K9A2 Platinum",
806 .matches = {
807 DMI_MATCH(DMI_BOARD_VENDOR,
808 "MICRO-STAR INTER"),
809 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
810 },
811 },
ff0173c1
MN		 812 /*
813 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
814 * 64bit DMA.
815 *
816 * This board also had the typo mentioned above in the
817 * Manufacturer DMI field (fixed in BIOS version 1.5), so
818 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
819 */
820 {
821 .ident = "MSI K9AGM2",
822 .matches = {
823 DMI_MATCH(DMI_BOARD_VENDOR,
824 "MICRO-STAR INTER"),
825 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
826 },
827 },
3c4aa91f
MN		 828 /*
829 * All BIOS versions for the Asus M3A support 64bit DMA.
830 * (all release versions from 0301 to 1206 were tested)
831 */
832 {
833 .ident = "ASUS M3A",
834 .matches = {
835 DMI_MATCH(DMI_BOARD_VENDOR,
836 "ASUSTeK Computer INC."),
837 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
838 },
839 },
58a09b38
SH		 840 { }
841 };
03d783bf 842 const struct dmi_system_id *match;
2fcad9d2
TH		 843 int year, month, date;
844 char buf[9];
58a09b38 845
03d783bf 846 match = dmi_first_match(sysids);
58a09b38 847 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 848 !match)
58a09b38
SH		 849 return false;
850
e65cc194
MN		 851 if (!match->driver_data)
852 goto enable_64bit;
853
2fcad9d2
TH		 854 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
855 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 856
e65cc194
MN		 857 if (strcmp(buf, match->driver_data) >= 0)
858 goto enable_64bit;
859 else {
a44fec1f
JP		 860 dev_warn(&pdev->dev,
861 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
862 match->ident);
2fcad9d2
TH		 863 return false;
864 }
e65cc194
MN		 865
866enable_64bit:
a44fec1f 867 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 868 return true;
58a09b38
SH		 869}
870
1fd68434
RW		 871static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
872{
873 static const struct dmi_system_id broken_systems[] = {
874 {
875 .ident = "HP Compaq nx6310",
876 .matches = {
877 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
878 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
879 },
880 /* PCI slot number of the controller */
881 .driver_data = (void *)0x1FUL,
882 },
d2f9c061
MR		 883 {
884 .ident = "HP Compaq 6720s",
885 .matches = {
886 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
887 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
888 },
889 /* PCI slot number of the controller */
890 .driver_data = (void *)0x1FUL,
891 },
1fd68434
RW		 892
893 { } /* terminate list */
894 };
895 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
896
897 if (dmi) {
898 unsigned long slot = (unsigned long)dmi->driver_data;
899 /* apply the quirk only to on-board controllers */
900 return slot == PCI_SLOT(pdev->devfn);
901 }
902
903 return false;
904}
905
9b10ae86
TH		 906static bool ahci_broken_suspend(struct pci_dev *pdev)
907{
908 static const struct dmi_system_id sysids[] = {
909 /*
910 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
911 * to the harddisk doesn't become online after
912 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 913 *
914 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
915 *
916 * Use dates instead of versions to match as HP is
917 * apparently recycling both product and version
918 * strings.
919 *
920 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 921 */
922 {
923 .ident = "dv4",
924 .matches = {
925 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
926 DMI_MATCH(DMI_PRODUCT_NAME,
927 "HP Pavilion dv4 Notebook PC"),
928 },
9deb3431 929 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 930 },
931 {
932 .ident = "dv5",
933 .matches = {
934 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
935 DMI_MATCH(DMI_PRODUCT_NAME,
936 "HP Pavilion dv5 Notebook PC"),
937 },
9deb3431 938 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 939 },
940 {
941 .ident = "dv6",
942 .matches = {
943 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
944 DMI_MATCH(DMI_PRODUCT_NAME,
945 "HP Pavilion dv6 Notebook PC"),
946 },
9deb3431 947 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 948 },
949 {
950 .ident = "HDX18",
951 .matches = {
952 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
953 DMI_MATCH(DMI_PRODUCT_NAME,
954 "HP HDX18 Notebook PC"),
955 },
9deb3431 956 .driver_data = "20090430", /* F.23 */
9b10ae86 957 },
cedc9bf9
TH		 958 /*
959 * Acer eMachines G725 has the same problem. BIOS
960 * V1.03 is known to be broken. V3.04 is known to
25985edc 961 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 962 * that we don't have much idea about. For now,
963 * blacklist anything older than V3.04.
9deb3431
TH		 964 *
965 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 966 */
967 {
968 .ident = "G725",
969 .matches = {
970 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
971 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
972 },
9deb3431 973 .driver_data = "20091216", /* V3.04 */
cedc9bf9 974 },
9b10ae86
TH		 975 { } /* terminate list */
976 };
977 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 978 int year, month, date;
979 char buf[9];
9b10ae86
TH		 980
981 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
982 return false;
983
9deb3431
TH		 984 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
985 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 986
9deb3431 987 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 988}
989
5594639a
TH		 990static bool ahci_broken_online(struct pci_dev *pdev)
991{
992#define ENCODE_BUSDEVFN(bus, slot, func) \
993 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
994 static const struct dmi_system_id sysids[] = {
995 /*
996 * There are several gigabyte boards which use
997 * SIMG5723s configured as hardware RAID. Certain
998 * 5723 firmware revisions shipped there keep the link
999 * online but fail to answer properly to SRST or
1000 * IDENTIFY when no device is attached downstream
1001 * causing libata to retry quite a few times leading
1002 * to excessive detection delay.
1003 *
1004 * As these firmwares respond to the second reset try
1005 * with invalid device signature, considering unknown
1006 * sig as offline works around the problem acceptably.
1007 */
1008 {
1009 .ident = "EP45-DQ6",
1010 .matches = {
1011 DMI_MATCH(DMI_BOARD_VENDOR,
1012 "Gigabyte Technology Co., Ltd."),
1013 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1014 },
1015 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1016 },
1017 {
1018 .ident = "EP45-DS5",
1019 .matches = {
1020 DMI_MATCH(DMI_BOARD_VENDOR,
1021 "Gigabyte Technology Co., Ltd."),
1022 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1023 },
1024 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1025 },
1026 { } /* terminate list */
1027 };
1028#undef ENCODE_BUSDEVFN
1029 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1030 unsigned int val;
1031
1032 if (!dmi)
1033 return false;
1034
1035 val = (unsigned long)dmi->driver_data;
1036
1037 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1038}
1039
8e513217 1040#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1041static void ahci_gtf_filter_workaround(struct ata_host *host)
1042{
1043 static const struct dmi_system_id sysids[] = {
1044 /*
1045 * Aspire 3810T issues a bunch of SATA enable commands
1046 * via _GTF including an invalid one and one which is
1047 * rejected by the device. Among the successful ones
1048 * is FPDMA non-zero offset enable which when enabled
1049 * only on the drive side leads to NCQ command
1050 * failures. Filter it out.
1051 */
1052 {
1053 .ident = "Aspire 3810T",
1054 .matches = {
1055 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1056 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1057 },
1058 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1059 },
1060 { }
1061 };
1062 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1063 unsigned int filter;
1064 int i;
1065
1066 if (!dmi)
1067 return;
1068
1069 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1070 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1071 filter, dmi->ident);
f80ae7e4
TH		 1072
1073 for (i = 0; i < host->n_ports; i++) {
1074 struct ata_port *ap = host->ports[i];
1075 struct ata_link *link;
1076 struct ata_device *dev;
1077
1078 ata_for_each_link(link, ap, EDGE)
1079 ata_for_each_dev(dev, link, ALL)
1080 dev->gtf_filter |= filter;
1081 }
1082}
8e513217
MT		 1083#else
1084static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1085{}
1086#endif
f80ae7e4 1087
5ca72c4f
AG		 1088int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1089{
1090 int rc;
1091 unsigned int maxvec;
1092
1093 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1094 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1095 if (rc > 0) {
1096 if ((rc == maxvec) || (rc == 1))
1097 return rc;
1098 /*
1099 * Assume that advantage of multipe MSIs is negated,
1100 * so fallback to single MSI mode to save resources
1101 */
1102 pci_disable_msi(pdev);
1103 if (!pci_enable_msi(pdev))
1104 return 1;
1105 }
1106 }
1107
1108 pci_intx(pdev, 1);
1109 return 0;
1110}
1111
1112/**
1113 * ahci_host_activate - start AHCI host, request IRQs and register it
1114 * @host: target ATA host
1115 * @irq: base IRQ number to request
1116 * @n_msis: number of MSIs allocated for this host
1117 * @irq_handler: irq_handler used when requesting IRQs
1118 * @irq_flags: irq_flags used when requesting IRQs
1119 *
1120 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1121 * when multiple MSIs were allocated. That is one MSI per port, starting
1122 * from @irq.
1123 *
1124 * LOCKING:
1125 * Inherited from calling layer (may sleep).
1126 *
1127 * RETURNS:
1128 * 0 on success, -errno otherwise.
1129 */
1130int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1131{
1132 int i, rc;
1133
1134 /* Sharing Last Message among several ports is not supported */
1135 if (n_msis < host->n_ports)
1136 return -EINVAL;
1137
1138 rc = ata_host_start(host);
1139 if (rc)
1140 return rc;
1141
1142 for (i = 0; i < host->n_ports; i++) {
1143 rc = devm_request_threaded_irq(host->dev,
1144 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1145 dev_driver_string(host->dev), host->ports[i]);
1146 if (rc)
1147 goto out_free_irqs;
1148 }
1149
1150 for (i = 0; i < host->n_ports; i++)
1151 ata_port_desc(host->ports[i], "irq %d", irq + i);
1152
1153 rc = ata_host_register(host, &ahci_sht);
1154 if (rc)
1155 goto out_free_all_irqs;
1156
1157 return 0;
1158
1159out_free_all_irqs:
1160 i = host->n_ports;
1161out_free_irqs:
1162 for (i--; i >= 0; i--)
1163 devm_free_irq(host->dev, irq + i, host->ports[i]);
1164
1165 return rc;
1166}
1167
24dc5f33 1168static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1169{
e297d99e
TH		 1170 unsigned int board_id = ent->driver_data;
1171 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1172 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1173 struct device *dev = &pdev->dev;
1da177e4 1174 struct ahci_host_priv *hpriv;
4447d351 1175 struct ata_host *host;
5ca72c4f 1176 int n_ports, n_msis, i, rc;
318893e1 1177 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1178
1179 VPRINTK("ENTER\n");
1180
b429dd59 1181 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1182
06296a1e 1183 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1184
5b66c829
AC		 1185 /* The AHCI driver can only drive the SATA ports, the PATA driver
1186 can drive them all so if both drivers are selected make sure
1187 AHCI stays out of the way */
1188 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1189 return -ENODEV;
1190
c6353b45
TH		 1191 /*
1192 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1193 * ahci, use ata_generic instead.
1194 */
1195 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1196 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1197 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1198 pdev->subsystem_device == 0xcb89)
1199 return -ENODEV;
1200
7a02267e
MN		 1201 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1202 * At the moment, we can only use the AHCI mode. Let the users know
1203 * that for SAS drives they're out of luck.
1204 */
1205 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1206 dev_info(&pdev->dev,
1207 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1208
7f9c9f8e 1209 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1210 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1211 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1212 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1213 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1214
4447d351 1215 /* acquire resources */
24dc5f33 1216 rc = pcim_enable_device(pdev);
1da177e4
LT		 1217 if (rc)
1218 return rc;
1219
dea55137
TH		 1220 /* AHCI controllers often implement SFF compatible interface.
1221 * Grab all PCI BARs just in case.
1222 */
318893e1 1223 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1224 if (rc == -EBUSY)
24dc5f33 1225 pcim_pin_device(pdev);
0d5ff566 1226 if (rc)
24dc5f33 1227 return rc;
1da177e4 1228
c4f7792c
TH		 1229 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1230 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1231 u8 map;
1232
1233 /* ICH6s share the same PCI ID for both piix and ahci
1234 * modes. Enabling ahci mode while MAP indicates
1235 * combined mode is a bad idea. Yield to ata_piix.
1236 */
1237 pci_read_config_byte(pdev, ICH_MAP, &map);
1238 if (map & 0x3) {
a44fec1f
JP		 1239 dev_info(&pdev->dev,
1240 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1241 return -ENODEV;
1242 }
1243 }
1244
24dc5f33
TH		 1245 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1246 if (!hpriv)
1247 return -ENOMEM;
417a1a6d
TH		 1248 hpriv->flags |= (unsigned long)pi.private_data;
1249
e297d99e
TH		 1250 /* MCP65 revision A1 and A2 can't do MSI */
1251 if (board_id == board_ahci_mcp65 &&
1252 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1253 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1254
e427fe04
SH		 1255 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1256 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1257 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1258
2fcad9d2
TH		 1259 /* only some SB600s can do 64bit DMA */
1260 if (ahci_sb600_enable_64bit(pdev))
1261 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1262
318893e1 1263 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1264
5ca72c4f
AG		 1265 n_msis = ahci_init_interrupts(pdev, hpriv);
1266 if (n_msis > 1)
1267 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1268
4447d351 1269 /* save initial config */
394d6e53 1270 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1271
4447d351 1272 /* prepare host */
453d3131
RH		 1273 if (hpriv->cap & HOST_CAP_NCQ) {
1274 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1275 /*
1276 * Auto-activate optimization is supposed to be
1277 * supported on all AHCI controllers indicating NCQ
1278 * capability, but it seems to be broken on some
1279 * chipsets including NVIDIAs.
1280 */
1281 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1282 pi.flags |= ATA_FLAG_FPDMA_AA;
1283 }
1da177e4 1284
7d50b60b
TH		 1285 if (hpriv->cap & HOST_CAP_PMP)
1286 pi.flags |= ATA_FLAG_PMP;
1287
0cbb0e77 1288 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1289
1fd68434
RW		 1290 if (ahci_broken_system_poweroff(pdev)) {
1291 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1292 dev_info(&pdev->dev,
1293 "quirky BIOS, skipping spindown on poweroff\n");
1294 }
1295
9b10ae86
TH		 1296 if (ahci_broken_suspend(pdev)) {
1297 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1298 dev_warn(&pdev->dev,
1299 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1300 }
1301
5594639a
TH		 1302 if (ahci_broken_online(pdev)) {
1303 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1304 dev_info(&pdev->dev,
1305 "online status unreliable, applying workaround\n");
1306 }
1307
837f5f8f
TH		 1308 /* CAP.NP sometimes indicate the index of the last enabled
1309 * port, at other times, that of the last possible port, so
1310 * determining the maximum port number requires looking at
1311 * both CAP.NP and port_map.
1312 */
1313 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1314
1315 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1316 if (!host)
1317 return -ENOMEM;
4447d351
TH		 1318 host->private_data = hpriv;
1319
f3d7f23f 1320 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1321 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1322 else
1323 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1324
18f7ba4c
KCA		 1325 if (pi.flags & ATA_FLAG_EM)
1326 ahci_reset_em(host);
1327
4447d351 1328 for (i = 0; i < host->n_ports; i++) {
dab632e8 1329 struct ata_port *ap = host->ports[i];
4447d351 1330
318893e1
AR		 1331 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1332 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1333 0x100 + ap->port_no * 0x80, "port");
1334
18f7ba4c
KCA		 1335 /* set enclosure management message type */
1336 if (ap->flags & ATA_FLAG_EM)
008dbd61 1337 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1338
1339
dab632e8 1340 /* disabled/not-implemented port */
350756f6 1341 if (!(hpriv->port_map & (1 << i)))
dab632e8 1342 ap->ops = &ata_dummy_port_ops;
4447d351 1343 }
d447df14 1344
edc93052
TH		 1345 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1346 ahci_p5wdh_workaround(host);
1347
f80ae7e4
TH		 1348 /* apply gtf filter quirk */
1349 ahci_gtf_filter_workaround(host);
1350
4447d351
TH		 1351 /* initialize adapter */
1352 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1353 if (rc)
24dc5f33 1354 return rc;
1da177e4 1355
3303040d 1356 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1357 if (rc)
1358 return rc;
1da177e4 1359
781d6550 1360 ahci_pci_init_controller(host);
439fcaec 1361 ahci_pci_print_info(host);
1da177e4 1362
4447d351 1363 pci_set_master(pdev);
5ca72c4f
AG		 1364
1365 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1366 return ahci_host_activate(host, pdev->irq, n_msis);
1367
4447d351
TH		 1368 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1369 &ahci_sht);
907f4678 1370}
1da177e4 1371
2fc75da0 1372module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1373
1374MODULE_AUTHOR("Jeff Garzik");
1375MODULE_DESCRIPTION("AHCI SATA low-level driver");
1376MODULE_LICENSE("GPL");
1377MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1378MODULE_VERSION(DRV_VERSION);
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