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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
8c3d3d4b | 4 | * Maintained by: Tejun Heo <tj@kernel.org> |
af36d7f0 JG |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
1da177e4 LT |
38 | #include <linux/blkdev.h> |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
87507cfd | 41 | #include <linux/dma-mapping.h> |
a9524a76 | 42 | #include <linux/device.h> |
edc93052 | 43 | #include <linux/dmi.h> |
5a0e3ad6 | 44 | #include <linux/gfp.h> |
ee2aad42 | 45 | #include <linux/msi.h> |
1da177e4 | 46 | #include <scsi/scsi_host.h> |
193515d5 | 47 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 48 | #include <linux/libata.h> |
365cfa1e | 49 | #include "ahci.h" |
1da177e4 LT |
50 | |
51 | #define DRV_NAME "ahci" | |
7d50b60b | 52 | #define DRV_VERSION "3.0" |
1da177e4 | 53 | |
1da177e4 | 54 | enum { |
318893e1 | 55 | AHCI_PCI_BAR_STA2X11 = 0, |
b7ae128d | 56 | AHCI_PCI_BAR_CAVIUM = 0, |
7f9c9f8e | 57 | AHCI_PCI_BAR_ENMOTUS = 2, |
318893e1 | 58 | AHCI_PCI_BAR_STANDARD = 5, |
441577ef TH |
59 | }; |
60 | ||
61 | enum board_ids { | |
62 | /* board IDs by feature in alphabetical order */ | |
63 | board_ahci, | |
64 | board_ahci_ign_iferr, | |
66a7cbc3 | 65 | board_ahci_nomsi, |
67809f85 | 66 | board_ahci_noncq, |
441577ef | 67 | board_ahci_nosntf, |
5f173107 | 68 | board_ahci_yes_fbs, |
1da177e4 | 69 | |
441577ef | 70 | /* board IDs for specific chipsets in alphabetical order */ |
dbfe8ef5 | 71 | board_ahci_avn, |
441577ef | 72 | board_ahci_mcp65, |
83f2b963 TH |
73 | board_ahci_mcp77, |
74 | board_ahci_mcp89, | |
441577ef TH |
75 | board_ahci_mv, |
76 | board_ahci_sb600, | |
77 | board_ahci_sb700, /* for SB700 and SB800 */ | |
78 | board_ahci_vt8251, | |
79 | ||
80 | /* aliases */ | |
81 | board_ahci_mcp_linux = board_ahci_mcp65, | |
82 | board_ahci_mcp67 = board_ahci_mcp65, | |
83 | board_ahci_mcp73 = board_ahci_mcp65, | |
83f2b963 | 84 | board_ahci_mcp79 = board_ahci_mcp77, |
1da177e4 LT |
85 | }; |
86 | ||
2dcb407e | 87 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
a1efdaba TH |
88 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
89 | unsigned long deadline); | |
dbfe8ef5 DW |
90 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, |
91 | unsigned long deadline); | |
cb85696d JL |
92 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev); |
93 | static bool is_mcp89_apple(struct pci_dev *pdev); | |
a1efdaba TH |
94 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
95 | unsigned long deadline); | |
438ac6d5 | 96 | #ifdef CONFIG_PM |
c1332875 TH |
97 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
98 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
438ac6d5 | 99 | #endif |
ad616ffb | 100 | |
fad16e7a TH |
101 | static struct scsi_host_template ahci_sht = { |
102 | AHCI_SHT("ahci"), | |
103 | }; | |
104 | ||
029cfd6b TH |
105 | static struct ata_port_operations ahci_vt8251_ops = { |
106 | .inherits = &ahci_ops, | |
a1efdaba | 107 | .hardreset = ahci_vt8251_hardreset, |
029cfd6b | 108 | }; |
edc93052 | 109 | |
029cfd6b TH |
110 | static struct ata_port_operations ahci_p5wdh_ops = { |
111 | .inherits = &ahci_ops, | |
a1efdaba | 112 | .hardreset = ahci_p5wdh_hardreset, |
edc93052 TH |
113 | }; |
114 | ||
dbfe8ef5 DW |
115 | static struct ata_port_operations ahci_avn_ops = { |
116 | .inherits = &ahci_ops, | |
117 | .hardreset = ahci_avn_hardreset, | |
118 | }; | |
119 | ||
98ac62de | 120 | static const struct ata_port_info ahci_port_info[] = { |
441577ef | 121 | /* by features */ |
facb8fa6 | 122 | [board_ahci] = { |
1188c0d8 | 123 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 124 | .pio_mask = ATA_PIO4, |
469248ab | 125 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
126 | .port_ops = &ahci_ops, |
127 | }, | |
facb8fa6 | 128 | [board_ahci_ign_iferr] = { |
441577ef | 129 | AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR), |
417a1a6d | 130 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 131 | .pio_mask = ATA_PIO4, |
469248ab | 132 | .udma_mask = ATA_UDMA6, |
441577ef | 133 | .port_ops = &ahci_ops, |
bf2af2a2 | 134 | }, |
66a7cbc3 TH |
135 | [board_ahci_nomsi] = { |
136 | AHCI_HFLAGS (AHCI_HFLAG_NO_MSI), | |
137 | .flags = AHCI_FLAG_COMMON, | |
138 | .pio_mask = ATA_PIO4, | |
139 | .udma_mask = ATA_UDMA6, | |
140 | .port_ops = &ahci_ops, | |
141 | }, | |
67809f85 LK |
142 | [board_ahci_noncq] = { |
143 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), | |
144 | .flags = AHCI_FLAG_COMMON, | |
145 | .pio_mask = ATA_PIO4, | |
146 | .udma_mask = ATA_UDMA6, | |
147 | .port_ops = &ahci_ops, | |
148 | }, | |
facb8fa6 | 149 | [board_ahci_nosntf] = { |
441577ef | 150 | AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF), |
417a1a6d | 151 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 152 | .pio_mask = ATA_PIO4, |
469248ab | 153 | .udma_mask = ATA_UDMA6, |
41669553 TH |
154 | .port_ops = &ahci_ops, |
155 | }, | |
facb8fa6 | 156 | [board_ahci_yes_fbs] = { |
5f173107 TH |
157 | AHCI_HFLAGS (AHCI_HFLAG_YES_FBS), |
158 | .flags = AHCI_FLAG_COMMON, | |
159 | .pio_mask = ATA_PIO4, | |
160 | .udma_mask = ATA_UDMA6, | |
161 | .port_ops = &ahci_ops, | |
162 | }, | |
441577ef | 163 | /* by chipsets */ |
dbfe8ef5 DW |
164 | [board_ahci_avn] = { |
165 | .flags = AHCI_FLAG_COMMON, | |
166 | .pio_mask = ATA_PIO4, | |
167 | .udma_mask = ATA_UDMA6, | |
168 | .port_ops = &ahci_avn_ops, | |
169 | }, | |
facb8fa6 | 170 | [board_ahci_mcp65] = { |
83f2b963 TH |
171 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP | |
172 | AHCI_HFLAG_YES_NCQ), | |
ae01b249 | 173 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM, |
83f2b963 TH |
174 | .pio_mask = ATA_PIO4, |
175 | .udma_mask = ATA_UDMA6, | |
176 | .port_ops = &ahci_ops, | |
177 | }, | |
facb8fa6 | 178 | [board_ahci_mcp77] = { |
83f2b963 TH |
179 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP), |
180 | .flags = AHCI_FLAG_COMMON, | |
181 | .pio_mask = ATA_PIO4, | |
182 | .udma_mask = ATA_UDMA6, | |
183 | .port_ops = &ahci_ops, | |
184 | }, | |
facb8fa6 | 185 | [board_ahci_mcp89] = { |
83f2b963 | 186 | AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA), |
417a1a6d | 187 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 188 | .pio_mask = ATA_PIO4, |
469248ab | 189 | .udma_mask = ATA_UDMA6, |
441577ef | 190 | .port_ops = &ahci_ops, |
55a61604 | 191 | }, |
facb8fa6 | 192 | [board_ahci_mv] = { |
417a1a6d | 193 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI | |
17248461 | 194 | AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP), |
9cbe056f | 195 | .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA, |
14bdef98 | 196 | .pio_mask = ATA_PIO4, |
cd70c266 JG |
197 | .udma_mask = ATA_UDMA6, |
198 | .port_ops = &ahci_ops, | |
199 | }, | |
facb8fa6 | 200 | [board_ahci_sb600] = { |
441577ef TH |
201 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL | |
202 | AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 | | |
203 | AHCI_HFLAG_32BIT_ONLY), | |
e39fc8c9 | 204 | .flags = AHCI_FLAG_COMMON, |
14bdef98 | 205 | .pio_mask = ATA_PIO4, |
e39fc8c9 | 206 | .udma_mask = ATA_UDMA6, |
345347c5 | 207 | .port_ops = &ahci_pmp_retry_srst_ops, |
e39fc8c9 | 208 | }, |
facb8fa6 | 209 | [board_ahci_sb700] = { /* for SB700 and SB800 */ |
441577ef | 210 | AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL), |
aa431dd3 TH |
211 | .flags = AHCI_FLAG_COMMON, |
212 | .pio_mask = ATA_PIO4, | |
213 | .udma_mask = ATA_UDMA6, | |
345347c5 | 214 | .port_ops = &ahci_pmp_retry_srst_ops, |
aa431dd3 | 215 | }, |
facb8fa6 | 216 | [board_ahci_vt8251] = { |
441577ef | 217 | AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP), |
1b677afd SL |
218 | .flags = AHCI_FLAG_COMMON, |
219 | .pio_mask = ATA_PIO4, | |
220 | .udma_mask = ATA_UDMA6, | |
441577ef | 221 | .port_ops = &ahci_vt8251_ops, |
1b677afd | 222 | }, |
1da177e4 LT |
223 | }; |
224 | ||
3b7d697d | 225 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 226 | /* Intel */ |
54bb3a94 JG |
227 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
228 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
229 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
230 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
231 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 232 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
233 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
234 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
235 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
236 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
7a234aff | 237 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */ |
1b677afd | 238 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */ |
7a234aff TH |
239 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */ |
240 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */ | |
241 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */ | |
242 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */ | |
243 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */ | |
244 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */ | |
245 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */ | |
246 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */ | |
247 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */ | |
248 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */ | |
249 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */ | |
250 | { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */ | |
251 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */ | |
252 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */ | |
253 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */ | |
d4155e6f JG |
254 | { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */ |
255 | { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */ | |
16ad1ad9 | 256 | { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */ |
b2dde6af | 257 | { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */ |
16ad1ad9 | 258 | { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */ |
c1f57d9b DM |
259 | { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */ |
260 | { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */ | |
adcb5308 | 261 | { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 262 | { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */ |
c1f57d9b | 263 | { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */ |
adcb5308 | 264 | { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */ |
8e48b6b3 | 265 | { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */ |
c1f57d9b | 266 | { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */ |
5623cab8 SH |
267 | { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */ |
268 | { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */ | |
269 | { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */ | |
270 | { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */ | |
271 | { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */ | |
272 | { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */ | |
992b3fb9 SH |
273 | { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */ |
274 | { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */ | |
275 | { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */ | |
64a3903d | 276 | { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */ |
a4a461a6 | 277 | { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */ |
181e3cea SH |
278 | { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */ |
279 | { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */ | |
280 | { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */ | |
281 | { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */ | |
282 | { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */ | |
283 | { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */ | |
2cab7a4c | 284 | { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */ |
ea4ace66 SH |
285 | { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */ |
286 | { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */ | |
287 | { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */ | |
288 | { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */ | |
289 | { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */ | |
290 | { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */ | |
291 | { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */ | |
292 | { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */ | |
77b12bc9 JR |
293 | { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */ |
294 | { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */ | |
295 | { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */ | |
296 | { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */ | |
297 | { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */ | |
298 | { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */ | |
299 | { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */ | |
300 | { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */ | |
29e674dd SH |
301 | { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */ |
302 | { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */ | |
303 | { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */ | |
304 | { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */ | |
305 | { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */ | |
306 | { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */ | |
307 | { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */ | |
308 | { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */ | |
dbfe8ef5 DW |
309 | { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */ |
310 | { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */ | |
311 | { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */ | |
312 | { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */ | |
313 | { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */ | |
314 | { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */ | |
315 | { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */ | |
316 | { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */ | |
efda332c JR |
317 | { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */ |
318 | { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */ | |
151743fd JR |
319 | { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */ |
320 | { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */ | |
321 | { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */ | |
322 | { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */ | |
323 | { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */ | |
324 | { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */ | |
325 | { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */ | |
326 | { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */ | |
1cfc7df3 | 327 | { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */ |
9f961a5f JR |
328 | { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */ |
329 | { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */ | |
330 | { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */ | |
331 | { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */ | |
1b071a09 JR |
332 | { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */ |
333 | { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */ | |
334 | { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */ | |
335 | { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */ | |
336 | { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */ | |
337 | { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */ | |
338 | { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */ | |
339 | { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */ | |
249cd0a1 DR |
340 | { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */ |
341 | { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */ | |
342 | { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */ | |
c5967b79 | 343 | { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */ |
690000b9 | 344 | { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */ |
690000b9 | 345 | { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */ |
c5967b79 | 346 | { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */ |
690000b9 JR |
347 | { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */ |
348 | { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */ | |
4d92f009 AY |
349 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/ |
350 | { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/ | |
351 | { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/ | |
352 | { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/ | |
353 | { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/ | |
354 | { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/ | |
355 | { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/ | |
356 | { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/ | |
357 | { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/ | |
358 | { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/ | |
fe7fa31a | 359 | |
e34bb370 TH |
360 | /* JMicron 360/1/3/5/6, match class to avoid IDE function */ |
361 | { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
362 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, | |
1fefb8fd BH |
363 | /* JMicron 362B and 362C have an AHCI function with IDE class code */ |
364 | { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr }, | |
365 | { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr }, | |
91f15fb3 | 366 | /* May need to update quirk_jmicron_async_suspend() for additions */ |
fe7fa31a JG |
367 | |
368 | /* ATI */ | |
c65ec1c2 | 369 | { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */ |
e39fc8c9 SH |
370 | { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */ |
371 | { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */ | |
372 | { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */ | |
373 | { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */ | |
374 | { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */ | |
375 | { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */ | |
fe7fa31a | 376 | |
e2dd90b1 | 377 | /* AMD */ |
5deab536 | 378 | { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */ |
fafe5c3d | 379 | { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */ |
e2dd90b1 SH |
380 | /* AMD is using RAID class only for ahci controllers */ |
381 | { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
382 | PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci }, | |
383 | ||
fe7fa31a | 384 | /* VIA */ |
54bb3a94 | 385 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
bf335542 | 386 | { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
387 | |
388 | /* NVIDIA */ | |
e297d99e TH |
389 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */ |
390 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */ | |
391 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */ | |
392 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */ | |
393 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */ | |
394 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */ | |
395 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */ | |
396 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */ | |
441577ef TH |
397 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */ |
398 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */ | |
399 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */ | |
400 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */ | |
401 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */ | |
402 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */ | |
403 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */ | |
404 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */ | |
405 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */ | |
406 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */ | |
407 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */ | |
408 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */ | |
409 | { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */ | |
410 | { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */ | |
411 | { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */ | |
412 | { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */ | |
413 | { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */ | |
414 | { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */ | |
415 | { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */ | |
416 | { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */ | |
417 | { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */ | |
418 | { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */ | |
419 | { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */ | |
420 | { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */ | |
421 | { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */ | |
422 | { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */ | |
423 | { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */ | |
424 | { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */ | |
425 | { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */ | |
426 | { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */ | |
427 | { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */ | |
428 | { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */ | |
429 | { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */ | |
430 | { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */ | |
431 | { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */ | |
432 | { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */ | |
433 | { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */ | |
434 | { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */ | |
435 | { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */ | |
436 | { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */ | |
437 | { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */ | |
438 | { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */ | |
439 | { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */ | |
440 | { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */ | |
441 | { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */ | |
442 | { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */ | |
443 | { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */ | |
444 | { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */ | |
445 | { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */ | |
446 | { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */ | |
447 | { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */ | |
448 | { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */ | |
449 | { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */ | |
450 | { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */ | |
451 | { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */ | |
452 | { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */ | |
453 | { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */ | |
454 | { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */ | |
455 | { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */ | |
456 | { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */ | |
457 | { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */ | |
458 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */ | |
459 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */ | |
460 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */ | |
461 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */ | |
462 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */ | |
463 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */ | |
464 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */ | |
465 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */ | |
466 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */ | |
467 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */ | |
468 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */ | |
469 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */ | |
470 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */ | |
471 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */ | |
472 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */ | |
fe7fa31a | 473 | |
95916edd | 474 | /* SiS */ |
20e2de4a TH |
475 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
476 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */ | |
477 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 478 | |
318893e1 AR |
479 | /* ST Microelectronics */ |
480 | { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */ | |
481 | ||
cd70c266 JG |
482 | /* Marvell */ |
483 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | |
c40e7cb8 | 484 | { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */ |
69fd3157 | 485 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123), |
10aca06c AH |
486 | .class = PCI_CLASS_STORAGE_SATA_AHCI, |
487 | .class_mask = 0xffffff, | |
5f173107 | 488 | .driver_data = board_ahci_yes_fbs }, /* 88se9128 */ |
69fd3157 | 489 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125), |
467b41c6 | 490 | .driver_data = board_ahci_yes_fbs }, /* 88se9125 */ |
e098f5cb SG |
491 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178, |
492 | PCI_VENDOR_ID_MARVELL_EXT, 0x9170), | |
493 | .driver_data = board_ahci_yes_fbs }, /* 88se9170 */ | |
69fd3157 | 494 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a), |
642d8925 | 495 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
fcce9a35 | 496 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172), |
c5edfff9 MK |
497 | .driver_data = board_ahci_yes_fbs }, /* 88se9182 */ |
498 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182), | |
fcce9a35 | 499 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 */ |
69fd3157 | 500 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192), |
17c60c6b | 501 | .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */ |
754a292f AS |
502 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0), |
503 | .driver_data = board_ahci_yes_fbs }, | |
a40cf3f3 JT |
504 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */ |
505 | .driver_data = board_ahci_yes_fbs }, | |
69fd3157 | 506 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3), |
50be5e36 | 507 | .driver_data = board_ahci_yes_fbs }, |
6d5278a6 SB |
508 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230), |
509 | .driver_data = board_ahci_yes_fbs }, | |
d2518365 JC |
510 | { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), |
511 | .driver_data = board_ahci_yes_fbs }, | |
cd70c266 | 512 | |
c77a036b MN |
513 | /* Promise */ |
514 | { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */ | |
b32bfc06 | 515 | { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */ |
c77a036b | 516 | |
c9703765 | 517 | /* Asmedia */ |
7b4f6eca AC |
518 | { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */ |
519 | { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */ | |
520 | { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */ | |
521 | { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */ | |
c9703765 | 522 | |
67809f85 | 523 | /* |
66a7cbc3 TH |
524 | * Samsung SSDs found on some macbooks. NCQ times out if MSI is |
525 | * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731 | |
67809f85 | 526 | */ |
66a7cbc3 | 527 | { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi }, |
2b21ef0a | 528 | { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi }, |
67809f85 | 529 | |
7f9c9f8e HD |
530 | /* Enmotus */ |
531 | { PCI_DEVICE(0x1c44, 0x8000), board_ahci }, | |
532 | ||
415ae2b5 JG |
533 | /* Generic, PCI class code for AHCI */ |
534 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
c9f89475 | 535 | PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci }, |
415ae2b5 | 536 | |
1da177e4 LT |
537 | { } /* terminate list */ |
538 | }; | |
539 | ||
540 | ||
541 | static struct pci_driver ahci_pci_driver = { | |
542 | .name = DRV_NAME, | |
543 | .id_table = ahci_pci_tbl, | |
544 | .probe = ahci_init_one, | |
24dc5f33 | 545 | .remove = ata_pci_remove_one, |
438ac6d5 | 546 | #ifdef CONFIG_PM |
c1332875 | 547 | .suspend = ahci_pci_device_suspend, |
365cfa1e AV |
548 | .resume = ahci_pci_device_resume, |
549 | #endif | |
550 | }; | |
1da177e4 | 551 | |
365cfa1e AV |
552 | #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE) |
553 | static int marvell_enable; | |
554 | #else | |
555 | static int marvell_enable = 1; | |
556 | #endif | |
557 | module_param(marvell_enable, int, 0644); | |
558 | MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)"); | |
d28f87aa | 559 | |
1da177e4 | 560 | |
365cfa1e AV |
561 | static void ahci_pci_save_initial_config(struct pci_dev *pdev, |
562 | struct ahci_host_priv *hpriv) | |
563 | { | |
365cfa1e AV |
564 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) { |
565 | dev_info(&pdev->dev, "JMB361 has only one port\n"); | |
9a23c1d6 | 566 | hpriv->force_port_map = 1; |
1da177e4 LT |
567 | } |
568 | ||
365cfa1e AV |
569 | /* |
570 | * Temporary Marvell 6145 hack: PATA port presence | |
571 | * is asserted through the standard AHCI port | |
572 | * presence register, as bit 4 (counting from 0) | |
d28f87aa | 573 | */ |
365cfa1e AV |
574 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
575 | if (pdev->device == 0x6121) | |
9a23c1d6 | 576 | hpriv->mask_port_map = 0x3; |
365cfa1e | 577 | else |
9a23c1d6 | 578 | hpriv->mask_port_map = 0xf; |
365cfa1e AV |
579 | dev_info(&pdev->dev, |
580 | "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n"); | |
581 | } | |
1da177e4 | 582 | |
725c7b57 | 583 | ahci_save_initial_config(&pdev->dev, hpriv); |
1da177e4 LT |
584 | } |
585 | ||
365cfa1e | 586 | static int ahci_pci_reset_controller(struct ata_host *host) |
1da177e4 | 587 | { |
365cfa1e | 588 | struct pci_dev *pdev = to_pci_dev(host->dev); |
7d50b60b | 589 | |
365cfa1e | 590 | ahci_reset_controller(host); |
1da177e4 | 591 | |
365cfa1e AV |
592 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { |
593 | struct ahci_host_priv *hpriv = host->private_data; | |
594 | u16 tmp16; | |
d6ef3153 | 595 | |
365cfa1e AV |
596 | /* configure PCS */ |
597 | pci_read_config_word(pdev, 0x92, &tmp16); | |
598 | if ((tmp16 & hpriv->port_map) != hpriv->port_map) { | |
599 | tmp16 |= hpriv->port_map; | |
600 | pci_write_config_word(pdev, 0x92, tmp16); | |
601 | } | |
d6ef3153 SH |
602 | } |
603 | ||
1da177e4 LT |
604 | return 0; |
605 | } | |
606 | ||
365cfa1e | 607 | static void ahci_pci_init_controller(struct ata_host *host) |
78cd52d0 | 608 | { |
365cfa1e AV |
609 | struct ahci_host_priv *hpriv = host->private_data; |
610 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
611 | void __iomem *port_mmio; | |
78cd52d0 | 612 | u32 tmp; |
365cfa1e | 613 | int mv; |
78cd52d0 | 614 | |
365cfa1e AV |
615 | if (hpriv->flags & AHCI_HFLAG_MV_PATA) { |
616 | if (pdev->device == 0x6121) | |
617 | mv = 2; | |
618 | else | |
619 | mv = 4; | |
620 | port_mmio = __ahci_port_base(host, mv); | |
78cd52d0 | 621 | |
365cfa1e | 622 | writel(0, port_mmio + PORT_IRQ_MASK); |
78cd52d0 | 623 | |
365cfa1e AV |
624 | /* clear port IRQ */ |
625 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
626 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
627 | if (tmp) | |
628 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
78cd52d0 TH |
629 | } |
630 | ||
365cfa1e | 631 | ahci_init_controller(host); |
edc93052 TH |
632 | } |
633 | ||
365cfa1e AV |
634 | static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, |
635 | unsigned long deadline) | |
d6ef3153 | 636 | { |
365cfa1e | 637 | struct ata_port *ap = link->ap; |
039ece38 | 638 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e | 639 | bool online; |
d6ef3153 SH |
640 | int rc; |
641 | ||
365cfa1e | 642 | DPRINTK("ENTER\n"); |
d6ef3153 | 643 | |
365cfa1e | 644 | ahci_stop_engine(ap); |
d6ef3153 | 645 | |
365cfa1e AV |
646 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
647 | deadline, &online, NULL); | |
d6ef3153 | 648 | |
039ece38 | 649 | hpriv->start_engine(ap); |
d6ef3153 | 650 | |
365cfa1e | 651 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
d6ef3153 | 652 | |
365cfa1e AV |
653 | /* vt8251 doesn't clear BSY on signature FIS reception, |
654 | * request follow-up softreset. | |
655 | */ | |
656 | return online ? -EAGAIN : rc; | |
7d50b60b TH |
657 | } |
658 | ||
365cfa1e AV |
659 | static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, |
660 | unsigned long deadline) | |
7d50b60b | 661 | { |
365cfa1e | 662 | struct ata_port *ap = link->ap; |
1c954a4d | 663 | struct ahci_port_priv *pp = ap->private_data; |
039ece38 | 664 | struct ahci_host_priv *hpriv = ap->host->private_data; |
365cfa1e AV |
665 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
666 | struct ata_taskfile tf; | |
667 | bool online; | |
668 | int rc; | |
7d50b60b | 669 | |
365cfa1e | 670 | ahci_stop_engine(ap); |
028a2596 | 671 | |
365cfa1e AV |
672 | /* clear D2H reception area to properly wait for D2H FIS */ |
673 | ata_tf_init(link->device, &tf); | |
9bbb1b0e | 674 | tf.command = ATA_BUSY; |
365cfa1e | 675 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
7d50b60b | 676 | |
365cfa1e AV |
677 | rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), |
678 | deadline, &online, NULL); | |
028a2596 | 679 | |
039ece38 | 680 | hpriv->start_engine(ap); |
c1332875 | 681 | |
365cfa1e AV |
682 | /* The pseudo configuration device on SIMG4726 attached to |
683 | * ASUS P5W-DH Deluxe doesn't send signature FIS after | |
684 | * hardreset if no device is attached to the first downstream | |
685 | * port && the pseudo device locks up on SRST w/ PMP==0. To | |
686 | * work around this, wait for !BSY only briefly. If BSY isn't | |
687 | * cleared, perform CLO and proceed to IDENTIFY (achieved by | |
688 | * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA). | |
689 | * | |
690 | * Wait for two seconds. Devices attached to downstream port | |
691 | * which can't process the following IDENTIFY after this will | |
692 | * have to be reset again. For most cases, this should | |
693 | * suffice while making probing snappish enough. | |
694 | */ | |
695 | if (online) { | |
696 | rc = ata_wait_after_reset(link, jiffies + 2 * HZ, | |
697 | ahci_check_ready); | |
698 | if (rc) | |
699 | ahci_kick_engine(ap); | |
c1332875 | 700 | } |
c1332875 TH |
701 | return rc; |
702 | } | |
703 | ||
dbfe8ef5 DW |
704 | /* |
705 | * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports. | |
706 | * | |
707 | * It has been observed with some SSDs that the timing of events in the | |
708 | * link synchronization phase can leave the port in a state that can not | |
709 | * be recovered by a SATA-hard-reset alone. The failing signature is | |
710 | * SStatus.DET stuck at 1 ("Device presence detected but Phy | |
711 | * communication not established"). It was found that unloading and | |
712 | * reloading the driver when this problem occurs allows the drive | |
713 | * connection to be recovered (DET advanced to 0x3). The critical | |
714 | * component of reloading the driver is that the port state machines are | |
715 | * reset by bouncing "port enable" in the AHCI PCS configuration | |
716 | * register. So, reproduce that effect by bouncing a port whenever we | |
717 | * see DET==1 after a reset. | |
718 | */ | |
719 | static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class, | |
720 | unsigned long deadline) | |
721 | { | |
722 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
723 | struct ata_port *ap = link->ap; | |
724 | struct ahci_port_priv *pp = ap->private_data; | |
725 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
726 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
727 | unsigned long tmo = deadline - jiffies; | |
728 | struct ata_taskfile tf; | |
729 | bool online; | |
730 | int rc, i; | |
731 | ||
732 | DPRINTK("ENTER\n"); | |
733 | ||
734 | ahci_stop_engine(ap); | |
735 | ||
736 | for (i = 0; i < 2; i++) { | |
737 | u16 val; | |
738 | u32 sstatus; | |
739 | int port = ap->port_no; | |
740 | struct ata_host *host = ap->host; | |
741 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
742 | ||
743 | /* clear D2H reception area to properly wait for D2H FIS */ | |
744 | ata_tf_init(link->device, &tf); | |
745 | tf.command = ATA_BUSY; | |
746 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
747 | ||
748 | rc = sata_link_hardreset(link, timing, deadline, &online, | |
749 | ahci_check_ready); | |
750 | ||
751 | if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 || | |
752 | (sstatus & 0xf) != 1) | |
753 | break; | |
754 | ||
755 | ata_link_printk(link, KERN_INFO, "avn bounce port%d\n", | |
756 | port); | |
757 | ||
758 | pci_read_config_word(pdev, 0x92, &val); | |
759 | val &= ~(1 << port); | |
760 | pci_write_config_word(pdev, 0x92, val); | |
761 | ata_msleep(ap, 1000); | |
762 | val |= 1 << port; | |
763 | pci_write_config_word(pdev, 0x92, val); | |
764 | deadline += tmo; | |
765 | } | |
766 | ||
767 | hpriv->start_engine(ap); | |
768 | ||
769 | if (online) | |
770 | *class = ahci_dev_classify(ap); | |
771 | ||
772 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
773 | return rc; | |
774 | } | |
775 | ||
776 | ||
365cfa1e | 777 | #ifdef CONFIG_PM |
c1332875 TH |
778 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
779 | { | |
0a86e1c8 | 780 | struct ata_host *host = pci_get_drvdata(pdev); |
9b10ae86 | 781 | struct ahci_host_priv *hpriv = host->private_data; |
d8993349 | 782 | void __iomem *mmio = hpriv->mmio; |
c1332875 TH |
783 | u32 ctl; |
784 | ||
9b10ae86 TH |
785 | if (mesg.event & PM_EVENT_SUSPEND && |
786 | hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { | |
a44fec1f JP |
787 | dev_err(&pdev->dev, |
788 | "BIOS update required for suspend/resume\n"); | |
9b10ae86 TH |
789 | return -EIO; |
790 | } | |
791 | ||
3a2d5b70 | 792 | if (mesg.event & PM_EVENT_SLEEP) { |
c1332875 TH |
793 | /* AHCI spec rev1.1 section 8.3.3: |
794 | * Software must disable interrupts prior to requesting a | |
795 | * transition of the HBA to D3 state. | |
796 | */ | |
797 | ctl = readl(mmio + HOST_CTL); | |
798 | ctl &= ~HOST_IRQ_EN; | |
799 | writel(ctl, mmio + HOST_CTL); | |
800 | readl(mmio + HOST_CTL); /* flush */ | |
801 | } | |
802 | ||
803 | return ata_pci_device_suspend(pdev, mesg); | |
804 | } | |
805 | ||
806 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
807 | { | |
0a86e1c8 | 808 | struct ata_host *host = pci_get_drvdata(pdev); |
c1332875 TH |
809 | int rc; |
810 | ||
553c4aa6 TH |
811 | rc = ata_pci_device_do_resume(pdev); |
812 | if (rc) | |
813 | return rc; | |
c1332875 | 814 | |
cb85696d JL |
815 | /* Apple BIOS helpfully mangles the registers on resume */ |
816 | if (is_mcp89_apple(pdev)) | |
817 | ahci_mcp89_apple_enable(pdev); | |
818 | ||
c1332875 | 819 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
3303040d | 820 | rc = ahci_pci_reset_controller(host); |
c1332875 TH |
821 | if (rc) |
822 | return rc; | |
823 | ||
781d6550 | 824 | ahci_pci_init_controller(host); |
c1332875 TH |
825 | } |
826 | ||
cca3974e | 827 | ata_host_resume(host); |
c1332875 TH |
828 | |
829 | return 0; | |
830 | } | |
438ac6d5 | 831 | #endif |
c1332875 | 832 | |
4447d351 | 833 | static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac) |
1da177e4 | 834 | { |
1da177e4 | 835 | int rc; |
1da177e4 | 836 | |
318893e1 AR |
837 | /* |
838 | * If the device fixup already set the dma_mask to some non-standard | |
839 | * value, don't extend it here. This happens on STA2X11, for example. | |
840 | */ | |
841 | if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32)) | |
842 | return 0; | |
843 | ||
1da177e4 | 844 | if (using_dac && |
c54c719b QL |
845 | !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { |
846 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
1da177e4 | 847 | if (rc) { |
c54c719b | 848 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 849 | if (rc) { |
a44fec1f JP |
850 | dev_err(&pdev->dev, |
851 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
852 | return rc; |
853 | } | |
854 | } | |
1da177e4 | 855 | } else { |
c54c719b | 856 | rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 857 | if (rc) { |
a44fec1f | 858 | dev_err(&pdev->dev, "32-bit DMA enable failed\n"); |
1da177e4 LT |
859 | return rc; |
860 | } | |
c54c719b | 861 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
1da177e4 | 862 | if (rc) { |
a44fec1f JP |
863 | dev_err(&pdev->dev, |
864 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
865 | return rc; |
866 | } | |
867 | } | |
1da177e4 LT |
868 | return 0; |
869 | } | |
870 | ||
439fcaec AV |
871 | static void ahci_pci_print_info(struct ata_host *host) |
872 | { | |
873 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
874 | u16 cc; | |
875 | const char *scc_s; | |
876 | ||
877 | pci_read_config_word(pdev, 0x0a, &cc); | |
878 | if (cc == PCI_CLASS_STORAGE_IDE) | |
879 | scc_s = "IDE"; | |
880 | else if (cc == PCI_CLASS_STORAGE_SATA) | |
881 | scc_s = "SATA"; | |
882 | else if (cc == PCI_CLASS_STORAGE_RAID) | |
883 | scc_s = "RAID"; | |
884 | else | |
885 | scc_s = "unknown"; | |
886 | ||
887 | ahci_print_info(host, scc_s); | |
888 | } | |
889 | ||
edc93052 TH |
890 | /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is |
891 | * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't | |
892 | * support PMP and the 4726 either directly exports the device | |
893 | * attached to the first downstream port or acts as a hardware storage | |
894 | * controller and emulate a single ATA device (can be RAID 0/1 or some | |
895 | * other configuration). | |
896 | * | |
897 | * When there's no device attached to the first downstream port of the | |
898 | * 4726, "Config Disk" appears, which is a pseudo ATA device to | |
899 | * configure the 4726. However, ATA emulation of the device is very | |
900 | * lame. It doesn't send signature D2H Reg FIS after the initial | |
901 | * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues. | |
902 | * | |
903 | * The following function works around the problem by always using | |
904 | * hardreset on the port and not depending on receiving signature FIS | |
905 | * afterward. If signature FIS isn't received soon, ATA class is | |
906 | * assumed without follow-up softreset. | |
907 | */ | |
908 | static void ahci_p5wdh_workaround(struct ata_host *host) | |
909 | { | |
1bd06867 | 910 | static const struct dmi_system_id sysids[] = { |
edc93052 TH |
911 | { |
912 | .ident = "P5W DH Deluxe", | |
913 | .matches = { | |
914 | DMI_MATCH(DMI_SYS_VENDOR, | |
915 | "ASUSTEK COMPUTER INC"), | |
916 | DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"), | |
917 | }, | |
918 | }, | |
919 | { } | |
920 | }; | |
921 | struct pci_dev *pdev = to_pci_dev(host->dev); | |
922 | ||
923 | if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) && | |
924 | dmi_check_system(sysids)) { | |
925 | struct ata_port *ap = host->ports[1]; | |
926 | ||
a44fec1f JP |
927 | dev_info(&pdev->dev, |
928 | "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n"); | |
edc93052 TH |
929 | |
930 | ap->ops = &ahci_p5wdh_ops; | |
931 | ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA; | |
932 | } | |
933 | } | |
934 | ||
cb85696d JL |
935 | /* |
936 | * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when | |
937 | * booting in BIOS compatibility mode. We restore the registers but not ID. | |
938 | */ | |
939 | static void ahci_mcp89_apple_enable(struct pci_dev *pdev) | |
940 | { | |
941 | u32 val; | |
942 | ||
943 | printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n"); | |
944 | ||
945 | pci_read_config_dword(pdev, 0xf8, &val); | |
946 | val |= 1 << 0x1b; | |
947 | /* the following changes the device ID, but appears not to affect function */ | |
948 | /* val = (val & ~0xf0000000) | 0x80000000; */ | |
949 | pci_write_config_dword(pdev, 0xf8, val); | |
950 | ||
951 | pci_read_config_dword(pdev, 0x54c, &val); | |
952 | val |= 1 << 0xc; | |
953 | pci_write_config_dword(pdev, 0x54c, val); | |
954 | ||
955 | pci_read_config_dword(pdev, 0x4a4, &val); | |
956 | val &= 0xff; | |
957 | val |= 0x01060100; | |
958 | pci_write_config_dword(pdev, 0x4a4, val); | |
959 | ||
960 | pci_read_config_dword(pdev, 0x54c, &val); | |
961 | val &= ~(1 << 0xc); | |
962 | pci_write_config_dword(pdev, 0x54c, val); | |
963 | ||
964 | pci_read_config_dword(pdev, 0xf8, &val); | |
965 | val &= ~(1 << 0x1b); | |
966 | pci_write_config_dword(pdev, 0xf8, val); | |
967 | } | |
968 | ||
969 | static bool is_mcp89_apple(struct pci_dev *pdev) | |
970 | { | |
971 | return pdev->vendor == PCI_VENDOR_ID_NVIDIA && | |
972 | pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA && | |
973 | pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE && | |
974 | pdev->subsystem_device == 0xcb89; | |
975 | } | |
976 | ||
2fcad9d2 TH |
977 | /* only some SB600 ahci controllers can do 64bit DMA */ |
978 | static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) | |
58a09b38 SH |
979 | { |
980 | static const struct dmi_system_id sysids[] = { | |
03d783bf TH |
981 | /* |
982 | * The oldest version known to be broken is 0901 and | |
983 | * working is 1501 which was released on 2007-10-26. | |
2fcad9d2 TH |
984 | * Enable 64bit DMA on 1501 and anything newer. |
985 | * | |
03d783bf TH |
986 | * Please read bko#9412 for more info. |
987 | */ | |
58a09b38 SH |
988 | { |
989 | .ident = "ASUS M2A-VM", | |
990 | .matches = { | |
991 | DMI_MATCH(DMI_BOARD_VENDOR, | |
992 | "ASUSTeK Computer INC."), | |
993 | DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"), | |
994 | }, | |
03d783bf | 995 | .driver_data = "20071026", /* yyyymmdd */ |
58a09b38 | 996 | }, |
e65cc194 MN |
997 | /* |
998 | * All BIOS versions for the MSI K9A2 Platinum (MS-7376) | |
999 | * support 64bit DMA. | |
1000 | * | |
1001 | * BIOS versions earlier than 1.5 had the Manufacturer DMI | |
1002 | * fields as "MICRO-STAR INTERANTIONAL CO.,LTD". | |
1003 | * This spelling mistake was fixed in BIOS version 1.5, so | |
1004 | * 1.5 and later have the Manufacturer as | |
1005 | * "MICRO-STAR INTERNATIONAL CO.,LTD". | |
1006 | * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER". | |
1007 | * | |
1008 | * BIOS versions earlier than 1.9 had a Board Product Name | |
1009 | * DMI field of "MS-7376". This was changed to be | |
1010 | * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still | |
1011 | * match on DMI_BOARD_NAME of "MS-7376". | |
1012 | */ | |
1013 | { | |
1014 | .ident = "MSI K9A2 Platinum", | |
1015 | .matches = { | |
1016 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1017 | "MICRO-STAR INTER"), | |
1018 | DMI_MATCH(DMI_BOARD_NAME, "MS-7376"), | |
1019 | }, | |
1020 | }, | |
ff0173c1 MN |
1021 | /* |
1022 | * All BIOS versions for the MSI K9AGM2 (MS-7327) support | |
1023 | * 64bit DMA. | |
1024 | * | |
1025 | * This board also had the typo mentioned above in the | |
1026 | * Manufacturer DMI field (fixed in BIOS version 1.5), so | |
1027 | * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again. | |
1028 | */ | |
1029 | { | |
1030 | .ident = "MSI K9AGM2", | |
1031 | .matches = { | |
1032 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1033 | "MICRO-STAR INTER"), | |
1034 | DMI_MATCH(DMI_BOARD_NAME, "MS-7327"), | |
1035 | }, | |
1036 | }, | |
3c4aa91f MN |
1037 | /* |
1038 | * All BIOS versions for the Asus M3A support 64bit DMA. | |
1039 | * (all release versions from 0301 to 1206 were tested) | |
1040 | */ | |
1041 | { | |
1042 | .ident = "ASUS M3A", | |
1043 | .matches = { | |
1044 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1045 | "ASUSTeK Computer INC."), | |
1046 | DMI_MATCH(DMI_BOARD_NAME, "M3A"), | |
1047 | }, | |
1048 | }, | |
58a09b38 SH |
1049 | { } |
1050 | }; | |
03d783bf | 1051 | const struct dmi_system_id *match; |
2fcad9d2 TH |
1052 | int year, month, date; |
1053 | char buf[9]; | |
58a09b38 | 1054 | |
03d783bf | 1055 | match = dmi_first_match(sysids); |
58a09b38 | 1056 | if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) || |
03d783bf | 1057 | !match) |
58a09b38 SH |
1058 | return false; |
1059 | ||
e65cc194 MN |
1060 | if (!match->driver_data) |
1061 | goto enable_64bit; | |
1062 | ||
2fcad9d2 TH |
1063 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
1064 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
03d783bf | 1065 | |
e65cc194 MN |
1066 | if (strcmp(buf, match->driver_data) >= 0) |
1067 | goto enable_64bit; | |
1068 | else { | |
a44fec1f JP |
1069 | dev_warn(&pdev->dev, |
1070 | "%s: BIOS too old, forcing 32bit DMA, update BIOS\n", | |
1071 | match->ident); | |
2fcad9d2 TH |
1072 | return false; |
1073 | } | |
e65cc194 MN |
1074 | |
1075 | enable_64bit: | |
a44fec1f | 1076 | dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident); |
e65cc194 | 1077 | return true; |
58a09b38 SH |
1078 | } |
1079 | ||
1fd68434 RW |
1080 | static bool ahci_broken_system_poweroff(struct pci_dev *pdev) |
1081 | { | |
1082 | static const struct dmi_system_id broken_systems[] = { | |
1083 | { | |
1084 | .ident = "HP Compaq nx6310", | |
1085 | .matches = { | |
1086 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1087 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"), | |
1088 | }, | |
1089 | /* PCI slot number of the controller */ | |
1090 | .driver_data = (void *)0x1FUL, | |
1091 | }, | |
d2f9c061 MR |
1092 | { |
1093 | .ident = "HP Compaq 6720s", | |
1094 | .matches = { | |
1095 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1096 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"), | |
1097 | }, | |
1098 | /* PCI slot number of the controller */ | |
1099 | .driver_data = (void *)0x1FUL, | |
1100 | }, | |
1fd68434 RW |
1101 | |
1102 | { } /* terminate list */ | |
1103 | }; | |
1104 | const struct dmi_system_id *dmi = dmi_first_match(broken_systems); | |
1105 | ||
1106 | if (dmi) { | |
1107 | unsigned long slot = (unsigned long)dmi->driver_data; | |
1108 | /* apply the quirk only to on-board controllers */ | |
1109 | return slot == PCI_SLOT(pdev->devfn); | |
1110 | } | |
1111 | ||
1112 | return false; | |
1113 | } | |
1114 | ||
9b10ae86 TH |
1115 | static bool ahci_broken_suspend(struct pci_dev *pdev) |
1116 | { | |
1117 | static const struct dmi_system_id sysids[] = { | |
1118 | /* | |
1119 | * On HP dv[4-6] and HDX18 with earlier BIOSen, link | |
1120 | * to the harddisk doesn't become online after | |
1121 | * resuming from STR. Warn and fail suspend. | |
9deb3431 TH |
1122 | * |
1123 | * http://bugzilla.kernel.org/show_bug.cgi?id=12276 | |
1124 | * | |
1125 | * Use dates instead of versions to match as HP is | |
1126 | * apparently recycling both product and version | |
1127 | * strings. | |
1128 | * | |
1129 | * http://bugzilla.kernel.org/show_bug.cgi?id=15462 | |
9b10ae86 TH |
1130 | */ |
1131 | { | |
1132 | .ident = "dv4", | |
1133 | .matches = { | |
1134 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1135 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1136 | "HP Pavilion dv4 Notebook PC"), | |
1137 | }, | |
9deb3431 | 1138 | .driver_data = "20090105", /* F.30 */ |
9b10ae86 TH |
1139 | }, |
1140 | { | |
1141 | .ident = "dv5", | |
1142 | .matches = { | |
1143 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1144 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1145 | "HP Pavilion dv5 Notebook PC"), | |
1146 | }, | |
9deb3431 | 1147 | .driver_data = "20090506", /* F.16 */ |
9b10ae86 TH |
1148 | }, |
1149 | { | |
1150 | .ident = "dv6", | |
1151 | .matches = { | |
1152 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1153 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1154 | "HP Pavilion dv6 Notebook PC"), | |
1155 | }, | |
9deb3431 | 1156 | .driver_data = "20090423", /* F.21 */ |
9b10ae86 TH |
1157 | }, |
1158 | { | |
1159 | .ident = "HDX18", | |
1160 | .matches = { | |
1161 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
1162 | DMI_MATCH(DMI_PRODUCT_NAME, | |
1163 | "HP HDX18 Notebook PC"), | |
1164 | }, | |
9deb3431 | 1165 | .driver_data = "20090430", /* F.23 */ |
9b10ae86 | 1166 | }, |
cedc9bf9 TH |
1167 | /* |
1168 | * Acer eMachines G725 has the same problem. BIOS | |
1169 | * V1.03 is known to be broken. V3.04 is known to | |
25985edc | 1170 | * work. Between, there are V1.06, V2.06 and V3.03 |
cedc9bf9 TH |
1171 | * that we don't have much idea about. For now, |
1172 | * blacklist anything older than V3.04. | |
9deb3431 TH |
1173 | * |
1174 | * http://bugzilla.kernel.org/show_bug.cgi?id=15104 | |
cedc9bf9 TH |
1175 | */ |
1176 | { | |
1177 | .ident = "G725", | |
1178 | .matches = { | |
1179 | DMI_MATCH(DMI_SYS_VENDOR, "eMachines"), | |
1180 | DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"), | |
1181 | }, | |
9deb3431 | 1182 | .driver_data = "20091216", /* V3.04 */ |
cedc9bf9 | 1183 | }, |
9b10ae86 TH |
1184 | { } /* terminate list */ |
1185 | }; | |
1186 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
9deb3431 TH |
1187 | int year, month, date; |
1188 | char buf[9]; | |
9b10ae86 TH |
1189 | |
1190 | if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2)) | |
1191 | return false; | |
1192 | ||
9deb3431 TH |
1193 | dmi_get_date(DMI_BIOS_DATE, &year, &month, &date); |
1194 | snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date); | |
9b10ae86 | 1195 | |
9deb3431 | 1196 | return strcmp(buf, dmi->driver_data) < 0; |
9b10ae86 TH |
1197 | } |
1198 | ||
5594639a TH |
1199 | static bool ahci_broken_online(struct pci_dev *pdev) |
1200 | { | |
1201 | #define ENCODE_BUSDEVFN(bus, slot, func) \ | |
1202 | (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func))) | |
1203 | static const struct dmi_system_id sysids[] = { | |
1204 | /* | |
1205 | * There are several gigabyte boards which use | |
1206 | * SIMG5723s configured as hardware RAID. Certain | |
1207 | * 5723 firmware revisions shipped there keep the link | |
1208 | * online but fail to answer properly to SRST or | |
1209 | * IDENTIFY when no device is attached downstream | |
1210 | * causing libata to retry quite a few times leading | |
1211 | * to excessive detection delay. | |
1212 | * | |
1213 | * As these firmwares respond to the second reset try | |
1214 | * with invalid device signature, considering unknown | |
1215 | * sig as offline works around the problem acceptably. | |
1216 | */ | |
1217 | { | |
1218 | .ident = "EP45-DQ6", | |
1219 | .matches = { | |
1220 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1221 | "Gigabyte Technology Co., Ltd."), | |
1222 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"), | |
1223 | }, | |
1224 | .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0), | |
1225 | }, | |
1226 | { | |
1227 | .ident = "EP45-DS5", | |
1228 | .matches = { | |
1229 | DMI_MATCH(DMI_BOARD_VENDOR, | |
1230 | "Gigabyte Technology Co., Ltd."), | |
1231 | DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"), | |
1232 | }, | |
1233 | .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0), | |
1234 | }, | |
1235 | { } /* terminate list */ | |
1236 | }; | |
1237 | #undef ENCODE_BUSDEVFN | |
1238 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1239 | unsigned int val; | |
1240 | ||
1241 | if (!dmi) | |
1242 | return false; | |
1243 | ||
1244 | val = (unsigned long)dmi->driver_data; | |
1245 | ||
1246 | return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff); | |
1247 | } | |
1248 | ||
0cf4a7d6 JP |
1249 | static bool ahci_broken_devslp(struct pci_dev *pdev) |
1250 | { | |
1251 | /* device with broken DEVSLP but still showing SDS capability */ | |
1252 | static const struct pci_device_id ids[] = { | |
1253 | { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */ | |
1254 | {} | |
1255 | }; | |
1256 | ||
1257 | return pci_match_id(ids, pdev); | |
1258 | } | |
1259 | ||
8e513217 | 1260 | #ifdef CONFIG_ATA_ACPI |
f80ae7e4 TH |
1261 | static void ahci_gtf_filter_workaround(struct ata_host *host) |
1262 | { | |
1263 | static const struct dmi_system_id sysids[] = { | |
1264 | /* | |
1265 | * Aspire 3810T issues a bunch of SATA enable commands | |
1266 | * via _GTF including an invalid one and one which is | |
1267 | * rejected by the device. Among the successful ones | |
1268 | * is FPDMA non-zero offset enable which when enabled | |
1269 | * only on the drive side leads to NCQ command | |
1270 | * failures. Filter it out. | |
1271 | */ | |
1272 | { | |
1273 | .ident = "Aspire 3810T", | |
1274 | .matches = { | |
1275 | DMI_MATCH(DMI_SYS_VENDOR, "Acer"), | |
1276 | DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"), | |
1277 | }, | |
1278 | .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET, | |
1279 | }, | |
1280 | { } | |
1281 | }; | |
1282 | const struct dmi_system_id *dmi = dmi_first_match(sysids); | |
1283 | unsigned int filter; | |
1284 | int i; | |
1285 | ||
1286 | if (!dmi) | |
1287 | return; | |
1288 | ||
1289 | filter = (unsigned long)dmi->driver_data; | |
a44fec1f JP |
1290 | dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n", |
1291 | filter, dmi->ident); | |
f80ae7e4 TH |
1292 | |
1293 | for (i = 0; i < host->n_ports; i++) { | |
1294 | struct ata_port *ap = host->ports[i]; | |
1295 | struct ata_link *link; | |
1296 | struct ata_device *dev; | |
1297 | ||
1298 | ata_for_each_link(link, ap, EDGE) | |
1299 | ata_for_each_dev(dev, link, ALL) | |
1300 | dev->gtf_filter |= filter; | |
1301 | } | |
1302 | } | |
8e513217 MT |
1303 | #else |
1304 | static inline void ahci_gtf_filter_workaround(struct ata_host *host) | |
1305 | {} | |
1306 | #endif | |
f80ae7e4 | 1307 | |
ee2aad42 | 1308 | /* |
d684a90d DW |
1309 | * ahci_init_msix() - optionally enable per-port MSI-X otherwise defer |
1310 | * to single msi. | |
ee2aad42 RR |
1311 | */ |
1312 | static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports, | |
d684a90d | 1313 | struct ahci_host_priv *hpriv, unsigned long flags) |
5ca72c4f | 1314 | { |
d684a90d | 1315 | int nvec, i, rc; |
5ca72c4f | 1316 | |
ee2aad42 | 1317 | /* Do not init MSI-X if MSI is disabled for the device */ |
7b92b4f6 | 1318 | if (hpriv->flags & AHCI_HFLAG_NO_MSI) |
ee2aad42 RR |
1319 | return -ENODEV; |
1320 | ||
1321 | nvec = pci_msix_vec_count(pdev); | |
1322 | if (nvec < 0) | |
1323 | return nvec; | |
1324 | ||
d684a90d DW |
1325 | /* |
1326 | * Proper MSI-X implementations will have a vector per-port. | |
1327 | * Barring that, we prefer single-MSI over single-MSIX. If this | |
1328 | * check fails (not enough MSI-X vectors for all ports) we will | |
1329 | * be called again with the flag clear iff ahci_init_msi() | |
1330 | * fails. | |
1331 | */ | |
1332 | if (flags & AHCI_HFLAG_MULTI_MSIX) { | |
1333 | if (nvec < n_ports) | |
1334 | return -ENODEV; | |
1335 | nvec = n_ports; | |
1336 | } else if (nvec) { | |
1337 | nvec = 1; | |
1338 | } else { | |
1339 | /* | |
1340 | * Emit dev_err() since this was the non-legacy irq | |
1341 | * method of last resort. | |
1342 | */ | |
ee2aad42 RR |
1343 | rc = -ENODEV; |
1344 | goto fail; | |
1345 | } | |
1346 | ||
d684a90d DW |
1347 | for (i = 0; i < nvec; i++) |
1348 | hpriv->msix[i].entry = i; | |
1349 | rc = pci_enable_msix_exact(pdev, hpriv->msix, nvec); | |
ee2aad42 RR |
1350 | if (rc < 0) |
1351 | goto fail; | |
1352 | ||
d684a90d DW |
1353 | if (nvec > 1) |
1354 | hpriv->flags |= AHCI_HFLAG_MULTI_MSIX; | |
1355 | hpriv->irq = hpriv->msix[0].vector; /* for single msi-x */ | |
ee2aad42 | 1356 | |
d684a90d | 1357 | return nvec; |
ee2aad42 RR |
1358 | fail: |
1359 | dev_err(&pdev->dev, | |
1360 | "failed to enable MSI-X with error %d, # of vectors: %d\n", | |
1361 | rc, nvec); | |
1362 | ||
1363 | return rc; | |
1364 | } | |
1365 | ||
a1c82311 RR |
1366 | static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports, |
1367 | struct ahci_host_priv *hpriv) | |
5ca72c4f | 1368 | { |
ccf8f53c | 1369 | int rc, nvec; |
5ca72c4f | 1370 | |
7b92b4f6 | 1371 | if (hpriv->flags & AHCI_HFLAG_NO_MSI) |
a1c82311 | 1372 | return -ENODEV; |
7b92b4f6 | 1373 | |
fc061d96 AG |
1374 | nvec = pci_msi_vec_count(pdev); |
1375 | if (nvec < 0) | |
a1c82311 | 1376 | return nvec; |
7b92b4f6 AG |
1377 | |
1378 | /* | |
1379 | * If number of MSIs is less than number of ports then Sharing Last | |
1380 | * Message mode could be enforced. In this case assume that advantage | |
1381 | * of multipe MSIs is negated and use single MSI mode instead. | |
1382 | */ | |
fc061d96 | 1383 | if (nvec < n_ports) |
7b92b4f6 AG |
1384 | goto single_msi; |
1385 | ||
ccf8f53c AG |
1386 | rc = pci_enable_msi_exact(pdev, nvec); |
1387 | if (rc == -ENOSPC) | |
fc40363b | 1388 | goto single_msi; |
a1c82311 RR |
1389 | if (rc < 0) |
1390 | return rc; | |
5ca72c4f | 1391 | |
ab0f9e78 AG |
1392 | /* fallback to single MSI mode if the controller enforced MRSM mode */ |
1393 | if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) { | |
1394 | pci_disable_msi(pdev); | |
1395 | printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n"); | |
1396 | goto single_msi; | |
1397 | } | |
1398 | ||
c3ebd6a9 AG |
1399 | if (nvec > 1) |
1400 | hpriv->flags |= AHCI_HFLAG_MULTI_MSI; | |
1401 | ||
21bfd1aa | 1402 | goto out; |
7b92b4f6 AG |
1403 | |
1404 | single_msi: | |
21bfd1aa RR |
1405 | nvec = 1; |
1406 | ||
a1c82311 RR |
1407 | rc = pci_enable_msi(pdev); |
1408 | if (rc < 0) | |
1409 | return rc; | |
21bfd1aa RR |
1410 | out: |
1411 | hpriv->irq = pdev->irq; | |
a1c82311 | 1412 | |
21bfd1aa | 1413 | return nvec; |
a1c82311 | 1414 | } |
7b92b4f6 | 1415 | |
a1c82311 RR |
1416 | static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports, |
1417 | struct ahci_host_priv *hpriv) | |
1418 | { | |
1419 | int nvec; | |
1420 | ||
d684a90d DW |
1421 | /* |
1422 | * Try to enable per-port MSI-X. If the host is not capable | |
1423 | * fall back to single MSI before finally attempting single | |
1424 | * MSI-X. | |
1425 | */ | |
1426 | nvec = ahci_init_msix(pdev, n_ports, hpriv, AHCI_HFLAG_MULTI_MSIX); | |
1427 | if (nvec >= 0) | |
1428 | return nvec; | |
1429 | ||
a1c82311 RR |
1430 | nvec = ahci_init_msi(pdev, n_ports, hpriv); |
1431 | if (nvec >= 0) | |
1432 | return nvec; | |
1433 | ||
d684a90d DW |
1434 | /* try single-msix */ |
1435 | nvec = ahci_init_msix(pdev, n_ports, hpriv, 0); | |
ee2aad42 RR |
1436 | if (nvec >= 0) |
1437 | return nvec; | |
7b92b4f6 | 1438 | |
d684a90d | 1439 | /* legacy intx interrupts */ |
5ca72c4f | 1440 | pci_intx(pdev, 1); |
21bfd1aa | 1441 | hpriv->irq = pdev->irq; |
a1c82311 | 1442 | |
5ca72c4f AG |
1443 | return 0; |
1444 | } | |
1445 | ||
24dc5f33 | 1446 | static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 1447 | { |
e297d99e TH |
1448 | unsigned int board_id = ent->driver_data; |
1449 | struct ata_port_info pi = ahci_port_info[board_id]; | |
4447d351 | 1450 | const struct ata_port_info *ppi[] = { &pi, NULL }; |
24dc5f33 | 1451 | struct device *dev = &pdev->dev; |
1da177e4 | 1452 | struct ahci_host_priv *hpriv; |
4447d351 | 1453 | struct ata_host *host; |
c3ebd6a9 | 1454 | int n_ports, i, rc; |
318893e1 | 1455 | int ahci_pci_bar = AHCI_PCI_BAR_STANDARD; |
1da177e4 LT |
1456 | |
1457 | VPRINTK("ENTER\n"); | |
1458 | ||
b429dd59 | 1459 | WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
12fad3f9 | 1460 | |
06296a1e | 1461 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1da177e4 | 1462 | |
5b66c829 AC |
1463 | /* The AHCI driver can only drive the SATA ports, the PATA driver |
1464 | can drive them all so if both drivers are selected make sure | |
1465 | AHCI stays out of the way */ | |
1466 | if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) | |
1467 | return -ENODEV; | |
1468 | ||
cb85696d JL |
1469 | /* Apple BIOS on MCP89 prevents us using AHCI */ |
1470 | if (is_mcp89_apple(pdev)) | |
1471 | ahci_mcp89_apple_enable(pdev); | |
c6353b45 | 1472 | |
7a02267e MN |
1473 | /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. |
1474 | * At the moment, we can only use the AHCI mode. Let the users know | |
1475 | * that for SAS drives they're out of luck. | |
1476 | */ | |
1477 | if (pdev->vendor == PCI_VENDOR_ID_PROMISE) | |
a44fec1f JP |
1478 | dev_info(&pdev->dev, |
1479 | "PDC42819 can only drive SATA devices with this driver\n"); | |
7a02267e | 1480 | |
b7ae128d | 1481 | /* Some devices use non-standard BARs */ |
318893e1 AR |
1482 | if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06) |
1483 | ahci_pci_bar = AHCI_PCI_BAR_STA2X11; | |
7f9c9f8e HD |
1484 | else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000) |
1485 | ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS; | |
b7ae128d RR |
1486 | else if (pdev->vendor == 0x177d && pdev->device == 0xa01c) |
1487 | ahci_pci_bar = AHCI_PCI_BAR_CAVIUM; | |
318893e1 | 1488 | |
4447d351 | 1489 | /* acquire resources */ |
24dc5f33 | 1490 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1491 | if (rc) |
1492 | return rc; | |
1493 | ||
c4f7792c TH |
1494 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && |
1495 | (pdev->device == 0x2652 || pdev->device == 0x2653)) { | |
1496 | u8 map; | |
1497 | ||
1498 | /* ICH6s share the same PCI ID for both piix and ahci | |
1499 | * modes. Enabling ahci mode while MAP indicates | |
1500 | * combined mode is a bad idea. Yield to ata_piix. | |
1501 | */ | |
1502 | pci_read_config_byte(pdev, ICH_MAP, &map); | |
1503 | if (map & 0x3) { | |
a44fec1f JP |
1504 | dev_info(&pdev->dev, |
1505 | "controller is in combined mode, can't enable AHCI mode\n"); | |
c4f7792c TH |
1506 | return -ENODEV; |
1507 | } | |
1508 | } | |
1509 | ||
6fec8871 PB |
1510 | /* AHCI controllers often implement SFF compatible interface. |
1511 | * Grab all PCI BARs just in case. | |
1512 | */ | |
1513 | rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME); | |
1514 | if (rc == -EBUSY) | |
1515 | pcim_pin_device(pdev); | |
1516 | if (rc) | |
1517 | return rc; | |
1518 | ||
24dc5f33 TH |
1519 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
1520 | if (!hpriv) | |
1521 | return -ENOMEM; | |
417a1a6d TH |
1522 | hpriv->flags |= (unsigned long)pi.private_data; |
1523 | ||
e297d99e TH |
1524 | /* MCP65 revision A1 and A2 can't do MSI */ |
1525 | if (board_id == board_ahci_mcp65 && | |
1526 | (pdev->revision == 0xa1 || pdev->revision == 0xa2)) | |
1527 | hpriv->flags |= AHCI_HFLAG_NO_MSI; | |
1528 | ||
e427fe04 SH |
1529 | /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */ |
1530 | if (board_id == board_ahci_sb700 && pdev->revision >= 0x40) | |
1531 | hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL; | |
1532 | ||
2fcad9d2 TH |
1533 | /* only some SB600s can do 64bit DMA */ |
1534 | if (ahci_sb600_enable_64bit(pdev)) | |
1535 | hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY; | |
58a09b38 | 1536 | |
318893e1 | 1537 | hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar]; |
d8993349 | 1538 | |
0cf4a7d6 JP |
1539 | /* must set flag prior to save config in order to take effect */ |
1540 | if (ahci_broken_devslp(pdev)) | |
1541 | hpriv->flags |= AHCI_HFLAG_NO_DEVSLP; | |
1542 | ||
4447d351 | 1543 | /* save initial config */ |
394d6e53 | 1544 | ahci_pci_save_initial_config(pdev, hpriv); |
1da177e4 | 1545 | |
4447d351 | 1546 | /* prepare host */ |
453d3131 RH |
1547 | if (hpriv->cap & HOST_CAP_NCQ) { |
1548 | pi.flags |= ATA_FLAG_NCQ; | |
83f2b963 TH |
1549 | /* |
1550 | * Auto-activate optimization is supposed to be | |
1551 | * supported on all AHCI controllers indicating NCQ | |
1552 | * capability, but it seems to be broken on some | |
1553 | * chipsets including NVIDIAs. | |
1554 | */ | |
1555 | if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA)) | |
453d3131 | 1556 | pi.flags |= ATA_FLAG_FPDMA_AA; |
40fb59e7 MC |
1557 | |
1558 | /* | |
1559 | * All AHCI controllers should be forward-compatible | |
1560 | * with the new auxiliary field. This code should be | |
1561 | * conditionalized if any buggy AHCI controllers are | |
1562 | * encountered. | |
1563 | */ | |
1564 | pi.flags |= ATA_FLAG_FPDMA_AUX; | |
453d3131 | 1565 | } |
1da177e4 | 1566 | |
7d50b60b TH |
1567 | if (hpriv->cap & HOST_CAP_PMP) |
1568 | pi.flags |= ATA_FLAG_PMP; | |
1569 | ||
0cbb0e77 | 1570 | ahci_set_em_messages(hpriv, &pi); |
18f7ba4c | 1571 | |
1fd68434 RW |
1572 | if (ahci_broken_system_poweroff(pdev)) { |
1573 | pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN; | |
1574 | dev_info(&pdev->dev, | |
1575 | "quirky BIOS, skipping spindown on poweroff\n"); | |
1576 | } | |
1577 | ||
9b10ae86 TH |
1578 | if (ahci_broken_suspend(pdev)) { |
1579 | hpriv->flags |= AHCI_HFLAG_NO_SUSPEND; | |
a44fec1f JP |
1580 | dev_warn(&pdev->dev, |
1581 | "BIOS update required for suspend/resume\n"); | |
9b10ae86 TH |
1582 | } |
1583 | ||
5594639a TH |
1584 | if (ahci_broken_online(pdev)) { |
1585 | hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE; | |
1586 | dev_info(&pdev->dev, | |
1587 | "online status unreliable, applying workaround\n"); | |
1588 | } | |
1589 | ||
837f5f8f TH |
1590 | /* CAP.NP sometimes indicate the index of the last enabled |
1591 | * port, at other times, that of the last possible port, so | |
1592 | * determining the maximum port number requires looking at | |
1593 | * both CAP.NP and port_map. | |
1594 | */ | |
1595 | n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); | |
1596 | ||
1597 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4447d351 TH |
1598 | if (!host) |
1599 | return -ENOMEM; | |
4447d351 | 1600 | host->private_data = hpriv; |
d684a90d DW |
1601 | hpriv->msix = devm_kzalloc(&pdev->dev, |
1602 | sizeof(struct msix_entry) * n_ports, GFP_KERNEL); | |
1603 | if (!hpriv->msix) | |
1604 | return -ENOMEM; | |
21bfd1aa RR |
1605 | ahci_init_interrupts(pdev, n_ports, hpriv); |
1606 | ||
f3d7f23f | 1607 | if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
886ad09f | 1608 | host->flags |= ATA_HOST_PARALLEL_SCAN; |
f3d7f23f | 1609 | else |
d2782d96 | 1610 | dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); |
886ad09f | 1611 | |
18f7ba4c KCA |
1612 | if (pi.flags & ATA_FLAG_EM) |
1613 | ahci_reset_em(host); | |
1614 | ||
4447d351 | 1615 | for (i = 0; i < host->n_ports; i++) { |
dab632e8 | 1616 | struct ata_port *ap = host->ports[i]; |
4447d351 | 1617 | |
318893e1 AR |
1618 | ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar"); |
1619 | ata_port_pbar_desc(ap, ahci_pci_bar, | |
cbcdd875 TH |
1620 | 0x100 + ap->port_no * 0x80, "port"); |
1621 | ||
18f7ba4c KCA |
1622 | /* set enclosure management message type */ |
1623 | if (ap->flags & ATA_FLAG_EM) | |
008dbd61 | 1624 | ap->em_message_type = hpriv->em_msg_type; |
18f7ba4c KCA |
1625 | |
1626 | ||
dab632e8 | 1627 | /* disabled/not-implemented port */ |
350756f6 | 1628 | if (!(hpriv->port_map & (1 << i))) |
dab632e8 | 1629 | ap->ops = &ata_dummy_port_ops; |
4447d351 | 1630 | } |
d447df14 | 1631 | |
edc93052 TH |
1632 | /* apply workaround for ASUS P5W DH Deluxe mainboard */ |
1633 | ahci_p5wdh_workaround(host); | |
1634 | ||
f80ae7e4 TH |
1635 | /* apply gtf filter quirk */ |
1636 | ahci_gtf_filter_workaround(host); | |
1637 | ||
4447d351 TH |
1638 | /* initialize adapter */ |
1639 | rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64); | |
1da177e4 | 1640 | if (rc) |
24dc5f33 | 1641 | return rc; |
1da177e4 | 1642 | |
3303040d | 1643 | rc = ahci_pci_reset_controller(host); |
4447d351 TH |
1644 | if (rc) |
1645 | return rc; | |
1da177e4 | 1646 | |
781d6550 | 1647 | ahci_pci_init_controller(host); |
439fcaec | 1648 | ahci_pci_print_info(host); |
1da177e4 | 1649 | |
4447d351 | 1650 | pci_set_master(pdev); |
5ca72c4f | 1651 | |
21bfd1aa | 1652 | return ahci_host_activate(host, &ahci_sht); |
907f4678 | 1653 | } |
1da177e4 | 1654 | |
2fc75da0 | 1655 | module_pci_driver(ahci_pci_driver); |
1da177e4 LT |
1656 | |
1657 | MODULE_AUTHOR("Jeff Garzik"); | |
1658 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1659 | MODULE_LICENSE("GPL"); | |
1660 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1661 | MODULE_VERSION(DRV_VERSION); |