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[PATCH] libata: move dev->max_sectors configuration into ata_dev_configure()
[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
8676ce07 51#define DRV_VERSION "2.0"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
12fad3f9 59 AHCI_MAX_CMDS = 32,
dd410ff1 60 AHCI_CMD_SZ = 32,
12fad3f9 61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 62 AHCI_RX_FIS_SZ = 256,
a0ea7328 63 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 68 AHCI_RX_FIS_SZ,
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
4b10e559 72 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 75
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
78cd52d0 77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 78
79 board_ahci = 0,
bf2af2a2 80 board_ahci_vt8251 = 1,
41669553 81 board_ahci_ign_iferr = 2,
1da177e4
LT		 82
83 /* global controller registers */
84 HOST_CAP = 0x00, /* host capabilities */
85 HOST_CTL = 0x04, /* global host control */
86 HOST_IRQ_STAT = 0x08, /* interrupt status */
87 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
88 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
89
90 /* HOST_CTL bits */
91 HOST_RESET = (1 << 0), /* reset controller; self-clear */
92 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
93 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
94
95 /* HOST_CAP bits */
0be0aa98 96 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
22b49985 97 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
0be0aa98 98 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
979db803 99 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 100 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 101
102 /* registers for each SATA port */
103 PORT_LST_ADDR = 0x00, /* command list DMA addr */
104 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
105 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
106 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
107 PORT_IRQ_STAT = 0x10, /* interrupt status */
108 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
109 PORT_CMD = 0x18, /* port command */
110 PORT_TFDATA = 0x20, /* taskfile data */
111 PORT_SIG = 0x24, /* device TF signature */
112 PORT_CMD_ISSUE = 0x38, /* command issue */
113 PORT_SCR = 0x28, /* SATA phy register block */
114 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
115 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
116 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
117 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
118
119 /* PORT_IRQ_{STAT,MASK} bits */
120 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
121 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
122 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
123 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
124 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
125 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
126 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
127 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
128
129 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
130 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
131 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
132 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
133 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
134 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
135 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
136 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
137 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
138
78cd52d0
TH		 139 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
140 PORT_IRQ_IF_ERR |
141 PORT_IRQ_CONNECT |
4296971d 142 PORT_IRQ_PHYRDY |
78cd52d0
TH		 143 PORT_IRQ_UNK_FIS,
144 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
145 PORT_IRQ_TF_ERR |
146 PORT_IRQ_HBUS_DATA_ERR,
147 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
148 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
149 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 150
151 /* PORT_CMD bits */
02eaa666 152 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 153 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
154 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
155 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 156 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 157 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
158 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
159 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
160
0be0aa98 161 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 162 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
163 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
164 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 165
166 /* hpriv->flags bits */
167 AHCI_FLAG_MSI = (1 << 0),
bf2af2a2
BJ		 168
169 /* ap->flags bits */
4aeb0e32
TH		 170 AHCI_FLAG_NO_NCQ = (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
1da177e4
LT		 172};
173
174struct ahci_cmd_hdr {
175 u32 opts;
176 u32 status;
177 u32 tbl_addr;
178 u32 tbl_addr_hi;
179 u32 reserved[4];
180};
181
182struct ahci_sg {
183 u32 addr;
184 u32 addr_hi;
185 u32 reserved;
186 u32 flags_size;
187};
188
189struct ahci_host_priv {
190 unsigned long flags;
191 u32 cap; /* cache of HOST_CAP register */
192 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
193};
194
195struct ahci_port_priv {
196 struct ahci_cmd_hdr *cmd_slot;
197 dma_addr_t cmd_slot_dma;
198 void *cmd_tbl;
199 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 200 void *rx_fis;
201 dma_addr_t rx_fis_dma;
202};
203
204static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
205static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
206static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 207static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
7d12e780 208static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
1da177e4 209static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 210static int ahci_port_start(struct ata_port *ap);
211static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 212static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
213static void ahci_qc_prep(struct ata_queued_cmd *qc);
214static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 215static void ahci_freeze(struct ata_port *ap);
216static void ahci_thaw(struct ata_port *ap);
217static void ahci_error_handler(struct ata_port *ap);
ad616ffb 218static void ahci_vt8251_error_handler(struct ata_port *ap);
78cd52d0 219static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
c1332875
TH		 220static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
221static int ahci_port_resume(struct ata_port *ap);
222static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
223static int ahci_pci_device_resume(struct pci_dev *pdev);
907f4678 224static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 225
193515d5 226static struct scsi_host_template ahci_sht = {
1da177e4
LT		 227 .module = THIS_MODULE,
228 .name = DRV_NAME,
229 .ioctl = ata_scsi_ioctl,
230 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 231 .change_queue_depth = ata_scsi_change_queue_depth,
232 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 233 .this_id = ATA_SHT_THIS_ID,
234 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 235 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
236 .emulated = ATA_SHT_EMULATED,
237 .use_clustering = AHCI_USE_CLUSTERING,
238 .proc_name = DRV_NAME,
239 .dma_boundary = AHCI_DMA_BOUNDARY,
240 .slave_configure = ata_scsi_slave_config,
ccf68c34 241 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 242 .bios_param = ata_std_bios_param,
c1332875
TH		 243 .suspend = ata_scsi_device_suspend,
244 .resume = ata_scsi_device_resume,
1da177e4
LT		 245};
246
057ace5e 247static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 248 .port_disable = ata_port_disable,
249
250 .check_status = ahci_check_status,
251 .check_altstatus = ahci_check_status,
1da177e4
LT		 252 .dev_select = ata_noop_dev_select,
253
254 .tf_read = ahci_tf_read,
255
1da177e4
LT		 256 .qc_prep = ahci_qc_prep,
257 .qc_issue = ahci_qc_issue,
258
1da177e4
LT		 259 .irq_handler = ahci_interrupt,
260 .irq_clear = ahci_irq_clear,
261
262 .scr_read = ahci_scr_read,
263 .scr_write = ahci_scr_write,
264
78cd52d0
TH		 265 .freeze = ahci_freeze,
266 .thaw = ahci_thaw,
267
268 .error_handler = ahci_error_handler,
269 .post_internal_cmd = ahci_post_internal_cmd,
270
c1332875
TH		 271 .port_suspend = ahci_port_suspend,
272 .port_resume = ahci_port_resume,
273
1da177e4
LT		 274 .port_start = ahci_port_start,
275 .port_stop = ahci_port_stop,
1da177e4
LT		 276};
277
ad616ffb
TH		 278static const struct ata_port_operations ahci_vt8251_ops = {
279 .port_disable = ata_port_disable,
280
281 .check_status = ahci_check_status,
282 .check_altstatus = ahci_check_status,
283 .dev_select = ata_noop_dev_select,
284
285 .tf_read = ahci_tf_read,
286
287 .qc_prep = ahci_qc_prep,
288 .qc_issue = ahci_qc_issue,
289
290 .irq_handler = ahci_interrupt,
291 .irq_clear = ahci_irq_clear,
292
293 .scr_read = ahci_scr_read,
294 .scr_write = ahci_scr_write,
295
296 .freeze = ahci_freeze,
297 .thaw = ahci_thaw,
298
299 .error_handler = ahci_vt8251_error_handler,
300 .post_internal_cmd = ahci_post_internal_cmd,
301
302 .port_suspend = ahci_port_suspend,
303 .port_resume = ahci_port_resume,
304
305 .port_start = ahci_port_start,
306 .port_stop = ahci_port_stop,
307};
308
98ac62de 309static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 310 /* board_ahci */
311 {
312 .sht = &ahci_sht,
cca3974e 313 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
4296971d
TH		 314 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
315 ATA_FLAG_SKIP_D2H_BSY,
7da79312 316 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 317 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
318 .port_ops = &ahci_ops,
319 },
bf2af2a2
BJ		 320 /* board_ahci_vt8251 */
321 {
322 .sht = &ahci_sht,
cca3974e 323 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bf2af2a2 324 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
ad616ffb
TH		 325 ATA_FLAG_SKIP_D2H_BSY |
326 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
bf2af2a2
BJ		 327 .pio_mask = 0x1f, /* pio0-4 */
328 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
ad616ffb 329 .port_ops = &ahci_vt8251_ops,
bf2af2a2 330 },
41669553
TH		 331 /* board_ahci_ign_iferr */
332 {
333 .sht = &ahci_sht,
334 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
335 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
336 ATA_FLAG_SKIP_D2H_BSY |
337 AHCI_FLAG_IGN_IRQ_IF_ERR,
338 .pio_mask = 0x1f, /* pio0-4 */
339 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
340 .port_ops = &ahci_ops,
341 },
1da177e4
LT		 342};
343
3b7d697d 344static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 345 /* Intel */
54bb3a94
JG		 346 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
347 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
348 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
349 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
350 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
351 { PCI_VDEVICE(AL, 0x5288), board_ahci }, /* ULi M5288 */
352 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
353 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
354 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
355 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
356 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
357 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
358 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
359 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
360 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
f33d625f
JG		 361 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
362 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
363 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
364 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
365 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
366 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
367 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
368 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
369 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
370 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
371 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
fe7fa31a
JG		 372
373 /* JMicron */
41669553
TH		 374 { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */
375 { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */
376 { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */
377 { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */
378 { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */
fe7fa31a
JG		 379
380 /* ATI */
54bb3a94
JG		 381 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
382 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
fe7fa31a
JG		 383
384 /* VIA */
54bb3a94 385 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 386
387 /* NVIDIA */
54bb3a94
JG		 388 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
389 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
390 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
391 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
895663cd
PC		 392 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
393 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
394 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
395 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
396 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
397 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
398 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
399 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
fe7fa31a 400
95916edd 401 /* SiS */
54bb3a94
JG		 402 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
403 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
404 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 405
1da177e4
LT		 406 { } /* terminate list */
407};
408
409
410static struct pci_driver ahci_pci_driver = {
411 .name = DRV_NAME,
412 .id_table = ahci_pci_tbl,
413 .probe = ahci_init_one,
c1332875
TH		 414 .suspend = ahci_pci_device_suspend,
415 .resume = ahci_pci_device_resume,
907f4678 416 .remove = ahci_remove_one,
1da177e4
LT		 417};
418
419
420static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
421{
422 return base + 0x100 + (port * 0x80);
423}
424
ea6ba10b 425static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 426{
ea6ba10b 427 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 428}
429
1da177e4
LT		 430static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
431{
432 unsigned int sc_reg;
433
434 switch (sc_reg_in) {
435 case SCR_STATUS: sc_reg = 0; break;
436 case SCR_CONTROL: sc_reg = 1; break;
437 case SCR_ERROR: sc_reg = 2; break;
438 case SCR_ACTIVE: sc_reg = 3; break;
439 default:
440 return 0xffffffffU;
441 }
442
1e4f2a96 443 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 444}
445
446
447static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
448 u32 val)
449{
450 unsigned int sc_reg;
451
452 switch (sc_reg_in) {
453 case SCR_STATUS: sc_reg = 0; break;
454 case SCR_CONTROL: sc_reg = 1; break;
455 case SCR_ERROR: sc_reg = 2; break;
456 case SCR_ACTIVE: sc_reg = 3; break;
457 default:
458 return;
459 }
460
1e4f2a96 461 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 462}
463
9f592056 464static void ahci_start_engine(void __iomem *port_mmio)
7c76d1e8 465{
7c76d1e8
TH		 466 u32 tmp;
467
d8fcd116 468 /* start DMA */
9f592056 469 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 470 tmp |= PORT_CMD_START;
471 writel(tmp, port_mmio + PORT_CMD);
472 readl(port_mmio + PORT_CMD); /* flush */
473}
474
254950cd
TH		 475static int ahci_stop_engine(void __iomem *port_mmio)
476{
477 u32 tmp;
478
479 tmp = readl(port_mmio + PORT_CMD);
480
d8fcd116 481 /* check if the HBA is idle */
254950cd
TH		 482 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
483 return 0;
484
d8fcd116 485 /* setting HBA to idle */
254950cd
TH		 486 tmp &= ~PORT_CMD_START;
487 writel(tmp, port_mmio + PORT_CMD);
488
d8fcd116 489 /* wait for engine to stop. This could be as long as 500 msec */
254950cd
TH		 490 tmp = ata_wait_register(port_mmio + PORT_CMD,
491 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 492 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 493 return -EIO;
494
495 return 0;
496}
497
0be0aa98
TH		 498static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
499 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
500{
501 u32 tmp;
502
503 /* set FIS registers */
504 if (cap & HOST_CAP_64)
505 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
506 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
507
508 if (cap & HOST_CAP_64)
509 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
510 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
511
512 /* enable FIS reception */
513 tmp = readl(port_mmio + PORT_CMD);
514 tmp |= PORT_CMD_FIS_RX;
515 writel(tmp, port_mmio + PORT_CMD);
516
517 /* flush */
518 readl(port_mmio + PORT_CMD);
519}
520
521static int ahci_stop_fis_rx(void __iomem *port_mmio)
522{
523 u32 tmp;
524
525 /* disable FIS reception */
526 tmp = readl(port_mmio + PORT_CMD);
527 tmp &= ~PORT_CMD_FIS_RX;
528 writel(tmp, port_mmio + PORT_CMD);
529
530 /* wait for completion, spec says 500ms, give it 1000 */
531 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
532 PORT_CMD_FIS_ON, 10, 1000);
533 if (tmp & PORT_CMD_FIS_ON)
534 return -EBUSY;
535
536 return 0;
537}
538
539static void ahci_power_up(void __iomem *port_mmio, u32 cap)
540{
541 u32 cmd;
542
543 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
544
545 /* spin up device */
546 if (cap & HOST_CAP_SSS) {
547 cmd |= PORT_CMD_SPIN_UP;
548 writel(cmd, port_mmio + PORT_CMD);
549 }
550
551 /* wake up link */
552 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
553}
554
555static void ahci_power_down(void __iomem *port_mmio, u32 cap)
556{
557 u32 cmd, scontrol;
558
559 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
560
561 if (cap & HOST_CAP_SSC) {
562 /* enable transitions to slumber mode */
563 scontrol = readl(port_mmio + PORT_SCR_CTL);
564 if ((scontrol & 0x0f00) > 0x100) {
565 scontrol &= ~0xf00;
566 writel(scontrol, port_mmio + PORT_SCR_CTL);
567 }
568
569 /* put device into slumber mode */
570 writel(cmd | PORT_CMD_ICC_SLUMBER, port_mmio + PORT_CMD);
571
572 /* wait for the transition to complete */
573 ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_ICC_SLUMBER,
574 PORT_CMD_ICC_SLUMBER, 1, 50);
575 }
576
577 /* put device into listen mode */
578 if (cap & HOST_CAP_SSS) {
579 /* first set PxSCTL.DET to 0 */
580 scontrol = readl(port_mmio + PORT_SCR_CTL);
581 scontrol &= ~0xf;
582 writel(scontrol, port_mmio + PORT_SCR_CTL);
583
584 /* then set PxCMD.SUD to 0 */
585 cmd &= ~PORT_CMD_SPIN_UP;
586 writel(cmd, port_mmio + PORT_CMD);
587 }
588}
589
590static void ahci_init_port(void __iomem *port_mmio, u32 cap,
591 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
592{
593 /* power up */
594 ahci_power_up(port_mmio, cap);
595
596 /* enable FIS reception */
597 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
598
599 /* enable DMA */
600 ahci_start_engine(port_mmio);
601}
602
603static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
604{
605 int rc;
606
607 /* disable DMA */
608 rc = ahci_stop_engine(port_mmio);
609 if (rc) {
610 *emsg = "failed to stop engine";
611 return rc;
612 }
613
614 /* disable FIS reception */
615 rc = ahci_stop_fis_rx(port_mmio);
616 if (rc) {
617 *emsg = "failed stop FIS RX";
618 return rc;
619 }
620
621 /* put device into slumber mode */
622 ahci_power_down(port_mmio, cap);
623
624 return 0;
625}
626
d91542c1
TH		 627static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
628{
629 u32 cap_save, tmp;
630
631 cap_save = readl(mmio + HOST_CAP);
632 cap_save &= ( (1<<28) | (1<<17) );
633 cap_save |= (1 << 27);
634
635 /* global controller reset */
636 tmp = readl(mmio + HOST_CTL);
637 if ((tmp & HOST_RESET) == 0) {
638 writel(tmp | HOST_RESET, mmio + HOST_CTL);
639 readl(mmio + HOST_CTL); /* flush */
640 }
641
642 /* reset must complete within 1 second, or
643 * the hardware should be considered fried.
644 */
645 ssleep(1);
646
647 tmp = readl(mmio + HOST_CTL);
648 if (tmp & HOST_RESET) {
649 dev_printk(KERN_ERR, &pdev->dev,
650 "controller reset failed (0x%x)\n", tmp);
651 return -EIO;
652 }
653
654 writel(HOST_AHCI_EN, mmio + HOST_CTL);
655 (void) readl(mmio + HOST_CTL); /* flush */
656 writel(cap_save, mmio + HOST_CAP);
657 writel(0xf, mmio + HOST_PORTS_IMPL);
658 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
659
660 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
661 u16 tmp16;
662
663 /* configure PCS */
664 pci_read_config_word(pdev, 0x92, &tmp16);
665 tmp16 |= 0xf;
666 pci_write_config_word(pdev, 0x92, tmp16);
667 }
668
669 return 0;
670}
671
672static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
673 int n_ports, u32 cap)
674{
675 int i, rc;
676 u32 tmp;
677
678 for (i = 0; i < n_ports; i++) {
679 void __iomem *port_mmio = ahci_port_base(mmio, i);
680 const char *emsg = NULL;
681
682#if 0 /* BIOSen initialize this incorrectly */
683 if (!(hpriv->port_map & (1 << i)))
684 continue;
685#endif
686
687 /* make sure port is not active */
688 rc = ahci_deinit_port(port_mmio, cap, &emsg);
689 if (rc)
690 dev_printk(KERN_WARNING, &pdev->dev,
691 "%s (%d)\n", emsg, rc);
692
693 /* clear SError */
694 tmp = readl(port_mmio + PORT_SCR_ERR);
695 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
696 writel(tmp, port_mmio + PORT_SCR_ERR);
697
f4b5cc87 698 /* clear port IRQ */
d91542c1
TH		 699 tmp = readl(port_mmio + PORT_IRQ_STAT);
700 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
701 if (tmp)
702 writel(tmp, port_mmio + PORT_IRQ_STAT);
703
704 writel(1 << i, mmio + HOST_IRQ_STAT);
d91542c1
TH		 705 }
706
707 tmp = readl(mmio + HOST_CTL);
708 VPRINTK("HOST_CTL 0x%x\n", tmp);
709 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
710 tmp = readl(mmio + HOST_CTL);
711 VPRINTK("HOST_CTL 0x%x\n", tmp);
712}
713
422b7595 714static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 715{
716 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
717 struct ata_taskfile tf;
422b7595
TH		 718 u32 tmp;
719
720 tmp = readl(port_mmio + PORT_SIG);
721 tf.lbah = (tmp >> 24) & 0xff;
722 tf.lbam = (tmp >> 16) & 0xff;
723 tf.lbal = (tmp >> 8) & 0xff;
724 tf.nsect = (tmp) & 0xff;
725
726 return ata_dev_classify(&tf);
727}
728
12fad3f9
TH		 729static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
730 u32 opts)
cc9278ed 731{
12fad3f9
TH		 732 dma_addr_t cmd_tbl_dma;
733
734 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
735
736 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
737 pp->cmd_slot[tag].status = 0;
738 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
739 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 740}
741
bf2af2a2 742static int ahci_clo(struct ata_port *ap)
4658f79b 743{
bf2af2a2 744 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
cca3974e 745 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2
BJ		 746 u32 tmp;
747
748 if (!(hpriv->cap & HOST_CAP_CLO))
749 return -EOPNOTSUPP;
750
751 tmp = readl(port_mmio + PORT_CMD);
752 tmp |= PORT_CMD_CLO;
753 writel(tmp, port_mmio + PORT_CMD);
754
755 tmp = ata_wait_register(port_mmio + PORT_CMD,
756 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
757 if (tmp & PORT_CMD_CLO)
758 return -EIO;
759
760 return 0;
761}
762
763static int ahci_softreset(struct ata_port *ap, unsigned int *class)
764{
4658f79b 765 struct ahci_port_priv *pp = ap->private_data;
cca3974e 766 void __iomem *mmio = ap->host->mmio_base;
4658f79b
TH		 767 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
768 const u32 cmd_fis_len = 5; /* five dwords */
769 const char *reason = NULL;
770 struct ata_taskfile tf;
75fe1806 771 u32 tmp;
4658f79b
TH		 772 u8 *fis;
773 int rc;
774
775 DPRINTK("ENTER\n");
776
81952c54 777 if (ata_port_offline(ap)) {
c2a65852
TH		 778 DPRINTK("PHY reports no device\n");
779 *class = ATA_DEV_NONE;
780 return 0;
781 }
782
4658f79b 783 /* prepare for SRST (AHCI-1.1 10.4.1) */
5457f219 784 rc = ahci_stop_engine(port_mmio);
4658f79b
TH		 785 if (rc) {
786 reason = "failed to stop engine";
787 goto fail_restart;
788 }
789
790 /* check BUSY/DRQ, perform Command List Override if necessary */
1244a19c 791 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
bf2af2a2 792 rc = ahci_clo(ap);
4658f79b 793
bf2af2a2
BJ		 794 if (rc == -EOPNOTSUPP) {
795 reason = "port busy but CLO unavailable";
796 goto fail_restart;
797 } else if (rc) {
798 reason = "port busy but CLO failed";
4658f79b
TH		 799 goto fail_restart;
800 }
801 }
802
803 /* restart engine */
5457f219 804 ahci_start_engine(port_mmio);
4658f79b 805
3373efd8 806 ata_tf_init(ap->device, &tf);
4658f79b
TH		 807 fis = pp->cmd_tbl;
808
809 /* issue the first D2H Register FIS */
12fad3f9
TH		 810 ahci_fill_cmd_slot(pp, 0,
811 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
4658f79b
TH		 812
813 tf.ctl |= ATA_SRST;
814 ata_tf_to_fis(&tf, fis, 0);
815 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
816
817 writel(1, port_mmio + PORT_CMD_ISSUE);
4658f79b 818
75fe1806
TH		 819 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
820 if (tmp & 0x1) {
4658f79b
TH		 821 rc = -EIO;
822 reason = "1st FIS failed";
823 goto fail;
824 }
825
826 /* spec says at least 5us, but be generous and sleep for 1ms */
827 msleep(1);
828
829 /* issue the second D2H Register FIS */
12fad3f9 830 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
4658f79b
TH		 831
832 tf.ctl &= ~ATA_SRST;
833 ata_tf_to_fis(&tf, fis, 0);
834 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
835
836 writel(1, port_mmio + PORT_CMD_ISSUE);
837 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
838
839 /* spec mandates ">= 2ms" before checking status.
840 * We wait 150ms, because that was the magic delay used for
841 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
842 * between when the ATA command register is written, and then
843 * status is checked. Because waiting for "a while" before
844 * checking status is fine, post SRST, we perform this magic
845 * delay here as well.
846 */
847 msleep(150);
848
849 *class = ATA_DEV_NONE;
81952c54 850 if (ata_port_online(ap)) {
4658f79b
TH		 851 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
852 rc = -EIO;
853 reason = "device not ready";
854 goto fail;
855 }
856 *class = ahci_dev_classify(ap);
857 }
858
859 DPRINTK("EXIT, class=%u\n", *class);
860 return 0;
861
862 fail_restart:
5457f219 863 ahci_start_engine(port_mmio);
4658f79b 864 fail:
f15a1daf 865 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 866 return rc;
867}
868
2bf2cb26 869static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
422b7595 870{
4296971d
TH		 871 struct ahci_port_priv *pp = ap->private_data;
872 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
873 struct ata_taskfile tf;
cca3974e 874 void __iomem *mmio = ap->host->mmio_base;
5457f219 875 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
4bd00f6a
TH		 876 int rc;
877
878 DPRINTK("ENTER\n");
1da177e4 879
5457f219 880 ahci_stop_engine(port_mmio);
4296971d
TH		 881
882 /* clear D2H reception area to properly wait for D2H FIS */
883 ata_tf_init(ap->device, &tf);
884 tf.command = 0xff;
885 ata_tf_to_fis(&tf, d2h_fis, 0);
886
2bf2cb26 887 rc = sata_std_hardreset(ap, class);
4296971d 888
5457f219 889 ahci_start_engine(port_mmio);
1da177e4 890
81952c54 891 if (rc == 0 && ata_port_online(ap))
4bd00f6a
TH		 892 *class = ahci_dev_classify(ap);
893 if (*class == ATA_DEV_UNKNOWN)
894 *class = ATA_DEV_NONE;
1da177e4 895
4bd00f6a
TH		 896 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
897 return rc;
898}
899
ad616ffb
TH		 900static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
901{
902 void __iomem *mmio = ap->host->mmio_base;
903 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
904 int rc;
905
906 DPRINTK("ENTER\n");
907
908 ahci_stop_engine(port_mmio);
909
910 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
911
912 /* vt8251 needs SError cleared for the port to operate */
913 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
914
915 ahci_start_engine(port_mmio);
916
917 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
918
919 /* vt8251 doesn't clear BSY on signature FIS reception,
920 * request follow-up softreset.
921 */
922 return rc ?: -EAGAIN;
923}
924
4bd00f6a
TH		 925static void ahci_postreset(struct ata_port *ap, unsigned int *class)
926{
927 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
928 u32 new_tmp, tmp;
929
930 ata_std_postreset(ap, class);
02eaa666
JG		 931
932 /* Make sure port's ATAPI bit is set appropriately */
933 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 934 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 935 new_tmp |= PORT_CMD_ATAPI;
936 else
937 new_tmp &= ~PORT_CMD_ATAPI;
938 if (new_tmp != tmp) {
939 writel(new_tmp, port_mmio + PORT_CMD);
940 readl(port_mmio + PORT_CMD); /* flush */
941 }
1da177e4
LT		 942}
943
944static u8 ahci_check_status(struct ata_port *ap)
945{
1e4f2a96 946 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 947
948 return readl(mmio + PORT_TFDATA) & 0xFF;
949}
950
1da177e4
LT		 951static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
952{
953 struct ahci_port_priv *pp = ap->private_data;
954 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
955
956 ata_tf_from_fis(d2h_fis, tf);
957}
958
12fad3f9 959static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 960{
cedc9a47
JG		 961 struct scatterlist *sg;
962 struct ahci_sg *ahci_sg;
828d09de 963 unsigned int n_sg = 0;
1da177e4
LT		 964
965 VPRINTK("ENTER\n");
966
967 /*
968 * Next, the S/G list.
969 */
12fad3f9 970 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
cedc9a47
JG		 971 ata_for_each_sg(sg, qc) {
972 dma_addr_t addr = sg_dma_address(sg);
973 u32 sg_len = sg_dma_len(sg);
974
975 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
976 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
977 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 978
cedc9a47 979 ahci_sg++;
828d09de 980 n_sg++;
1da177e4 981 }
828d09de
JG		 982
983 return n_sg;
1da177e4
LT		 984}
985
986static void ahci_qc_prep(struct ata_queued_cmd *qc)
987{
a0ea7328
JG		 988 struct ata_port *ap = qc->ap;
989 struct ahci_port_priv *pp = ap->private_data;
cc9278ed 990 int is_atapi = is_atapi_taskfile(&qc->tf);
12fad3f9 991 void *cmd_tbl;
1da177e4
LT		 992 u32 opts;
993 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 994 unsigned int n_elem;
1da177e4 995
1da177e4
LT		 996 /*
997 * Fill in command table information. First, the header,
998 * a SATA Register - Host to Device command FIS.
999 */
12fad3f9
TH		 1000 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1001
1002 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
cc9278ed 1003 if (is_atapi) {
12fad3f9
TH		 1004 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1005 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1006 }
1da177e4 1007
cc9278ed
TH		 1008 n_elem = 0;
1009 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1010 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1011
cc9278ed
TH		 1012 /*
1013 * Fill in command slot information.
1014 */
1015 opts = cmd_fis_len | n_elem << 16;
1016 if (qc->tf.flags & ATA_TFLAG_WRITE)
1017 opts |= AHCI_CMD_WRITE;
1018 if (is_atapi)
4b10e559 1019 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1020
12fad3f9 1021 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1022}
1023
78cd52d0 1024static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1025{
78cd52d0
TH		 1026 struct ahci_port_priv *pp = ap->private_data;
1027 struct ata_eh_info *ehi = &ap->eh_info;
1028 unsigned int err_mask = 0, action = 0;
1029 struct ata_queued_cmd *qc;
1030 u32 serror;
1da177e4 1031
78cd52d0 1032 ata_ehi_clear_desc(ehi);
1da177e4 1033
78cd52d0
TH		 1034 /* AHCI needs SError cleared; otherwise, it might lock up */
1035 serror = ahci_scr_read(ap, SCR_ERROR);
1036 ahci_scr_write(ap, SCR_ERROR, serror);
1da177e4 1037
78cd52d0
TH		 1038 /* analyze @irq_stat */
1039 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1040
41669553
TH		 1041 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1042 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1043 irq_stat &= ~PORT_IRQ_IF_ERR;
1044
78cd52d0
TH		 1045 if (irq_stat & PORT_IRQ_TF_ERR)
1046 err_mask |= AC_ERR_DEV;
1047
1048 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1049 err_mask |= AC_ERR_HOST_BUS;
1050 action |= ATA_EH_SOFTRESET;
1da177e4
LT		 1051 }
1052
78cd52d0
TH		 1053 if (irq_stat & PORT_IRQ_IF_ERR) {
1054 err_mask |= AC_ERR_ATA_BUS;
1055 action |= ATA_EH_SOFTRESET;
1056 ata_ehi_push_desc(ehi, ", interface fatal error");
1057 }
1da177e4 1058
78cd52d0 1059 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
4296971d 1060 ata_ehi_hotplugged(ehi);
78cd52d0
TH		 1061 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1062 "connection status changed" : "PHY RDY changed");
1063 }
1064
1065 if (irq_stat & PORT_IRQ_UNK_FIS) {
1066 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1da177e4 1067
78cd52d0
TH		 1068 err_mask |= AC_ERR_HSM;
1069 action |= ATA_EH_SOFTRESET;
1070 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1071 unk[0], unk[1], unk[2], unk[3]);
1072 }
1da177e4 1073
78cd52d0
TH		 1074 /* okay, let's hand over to EH */
1075 ehi->serror |= serror;
1076 ehi->action |= action;
b8f6153e 1077
1da177e4 1078 qc = ata_qc_from_tag(ap, ap->active_tag);
78cd52d0
TH		 1079 if (qc)
1080 qc->err_mask |= err_mask;
1081 else
1082 ehi->err_mask |= err_mask;
a72ec4ce 1083
78cd52d0
TH		 1084 if (irq_stat & PORT_IRQ_FREEZE)
1085 ata_port_freeze(ap);
1086 else
1087 ata_port_abort(ap);
1da177e4
LT		 1088}
1089
78cd52d0 1090static void ahci_host_intr(struct ata_port *ap)
1da177e4 1091{
cca3974e 1092 void __iomem *mmio = ap->host->mmio_base;
ea6ba10b 1093 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
12fad3f9
TH		 1094 struct ata_eh_info *ehi = &ap->eh_info;
1095 u32 status, qc_active;
1096 int rc;
1da177e4
LT		 1097
1098 status = readl(port_mmio + PORT_IRQ_STAT);
1099 writel(status, port_mmio + PORT_IRQ_STAT);
1100
78cd52d0
TH		 1101 if (unlikely(status & PORT_IRQ_ERROR)) {
1102 ahci_error_intr(ap, status);
1103 return;
1da177e4
LT		 1104 }
1105
12fad3f9
TH		 1106 if (ap->sactive)
1107 qc_active = readl(port_mmio + PORT_SCR_ACT);
1108 else
1109 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1110
1111 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1112 if (rc > 0)
1113 return;
1114 if (rc < 0) {
1115 ehi->err_mask |= AC_ERR_HSM;
1116 ehi->action |= ATA_EH_SOFTRESET;
1117 ata_port_freeze(ap);
1118 return;
1da177e4
LT		 1119 }
1120
2a3917a8
TH		 1121 /* hmmm... a spurious interupt */
1122
12fad3f9 1123 /* some devices send D2H reg with I bit set during NCQ command phase */
12a87d36 1124 if (ap->sactive && (status & PORT_IRQ_D2H_REG_FIS))
12fad3f9
TH		 1125 return;
1126
2a3917a8 1127 /* ignore interim PIO setup fis interrupts */
9bec2e38 1128 if (ata_tag_valid(ap->active_tag) && (status & PORT_IRQ_PIOS_FIS))
f1d39b29 1129 return;
2a3917a8 1130
78cd52d0
TH		 1131 if (ata_ratelimit())
1132 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
12fad3f9
TH		 1133 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
1134 status, ap->active_tag, ap->sactive);
1da177e4
LT		 1135}
1136
1137static void ahci_irq_clear(struct ata_port *ap)
1138{
1139 /* TODO */
1140}
1141
7d12e780 1142static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1143{
cca3974e 1144 struct ata_host *host = dev_instance;
1da177e4
LT		 1145 struct ahci_host_priv *hpriv;
1146 unsigned int i, handled = 0;
ea6ba10b 1147 void __iomem *mmio;
1da177e4
LT		 1148 u32 irq_stat, irq_ack = 0;
1149
1150 VPRINTK("ENTER\n");
1151
cca3974e
JG		 1152 hpriv = host->private_data;
1153 mmio = host->mmio_base;
1da177e4
LT		 1154
1155 /* sigh. 0xffffffff is a valid return from h/w */
1156 irq_stat = readl(mmio + HOST_IRQ_STAT);
1157 irq_stat &= hpriv->port_map;
1158 if (!irq_stat)
1159 return IRQ_NONE;
1160
cca3974e 1161 spin_lock(&host->lock);
1da177e4 1162
cca3974e 1163 for (i = 0; i < host->n_ports; i++) {
1da177e4 1164 struct ata_port *ap;
1da177e4 1165
67846b30
JG		 1166 if (!(irq_stat & (1 << i)))
1167 continue;
1168
cca3974e 1169 ap = host->ports[i];
67846b30 1170 if (ap) {
78cd52d0 1171 ahci_host_intr(ap);
67846b30
JG		 1172 VPRINTK("port %u\n", i);
1173 } else {
1174 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1175 if (ata_ratelimit())
cca3974e 1176 dev_printk(KERN_WARNING, host->dev,
a9524a76 1177 "interrupt on disabled port %u\n", i);
1da177e4 1178 }
67846b30
JG		 1179
1180 irq_ack |= (1 << i);
1da177e4
LT		 1181 }
1182
1183 if (irq_ack) {
1184 writel(irq_ack, mmio + HOST_IRQ_STAT);
1185 handled = 1;
1186 }
1187
cca3974e 1188 spin_unlock(&host->lock);
1da177e4
LT		 1189
1190 VPRINTK("EXIT\n");
1191
1192 return IRQ_RETVAL(handled);
1193}
1194
9a3d9eb0 1195static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1196{
1197 struct ata_port *ap = qc->ap;
ea6ba10b 1198 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 1199
12fad3f9
TH		 1200 if (qc->tf.protocol == ATA_PROT_NCQ)
1201 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1202 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1203 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1204
1205 return 0;
1206}
1207
78cd52d0
TH		 1208static void ahci_freeze(struct ata_port *ap)
1209{
cca3974e 1210 void __iomem *mmio = ap->host->mmio_base;
78cd52d0
TH		 1211 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1212
1213 /* turn IRQ off */
1214 writel(0, port_mmio + PORT_IRQ_MASK);
1215}
1216
1217static void ahci_thaw(struct ata_port *ap)
1218{
cca3974e 1219 void __iomem *mmio = ap->host->mmio_base;
78cd52d0
TH		 1220 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1221 u32 tmp;
1222
1223 /* clear IRQ */
1224 tmp = readl(port_mmio + PORT_IRQ_STAT);
1225 writel(tmp, port_mmio + PORT_IRQ_STAT);
1226 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
1227
1228 /* turn IRQ back on */
1229 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1230}
1231
1232static void ahci_error_handler(struct ata_port *ap)
1233{
cca3974e 1234 void __iomem *mmio = ap->host->mmio_base;
5457f219 1235 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1236
b51e9e5d 1237 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1238 /* restart engine */
5457f219 1239 ahci_stop_engine(port_mmio);
1240 ahci_start_engine(port_mmio);
78cd52d0
TH		 1241 }
1242
1243 /* perform recovery */
4aeb0e32 1244 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
f5914a46 1245 ahci_postreset);
78cd52d0
TH		 1246}
1247
ad616ffb
TH		 1248static void ahci_vt8251_error_handler(struct ata_port *ap)
1249{
1250 void __iomem *mmio = ap->host->mmio_base;
1251 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1252
1253 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1254 /* restart engine */
1255 ahci_stop_engine(port_mmio);
1256 ahci_start_engine(port_mmio);
1257 }
1258
1259 /* perform recovery */
1260 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1261 ahci_postreset);
1262}
1263
78cd52d0
TH		 1264static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1265{
1266 struct ata_port *ap = qc->ap;
cca3974e 1267 void __iomem *mmio = ap->host->mmio_base;
5457f219 1268 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
78cd52d0
TH		 1269
1270 if (qc->flags & ATA_QCFLAG_FAILED)
1271 qc->err_mask |= AC_ERR_OTHER;
1272
1273 if (qc->err_mask) {
1274 /* make DMA engine forget about the failed command */
5457f219 1275 ahci_stop_engine(port_mmio);
1276 ahci_start_engine(port_mmio);
78cd52d0
TH		 1277 }
1278}
1279
c1332875
TH		 1280static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1281{
cca3974e 1282 struct ahci_host_priv *hpriv = ap->host->private_data;
c1332875 1283 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1284 void __iomem *mmio = ap->host->mmio_base;
c1332875
TH		 1285 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1286 const char *emsg = NULL;
1287 int rc;
1288
1289 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1290 if (rc) {
1291 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1292 ahci_init_port(port_mmio, hpriv->cap,
1293 pp->cmd_slot_dma, pp->rx_fis_dma);
1294 }
1295
1296 return rc;
1297}
1298
1299static int ahci_port_resume(struct ata_port *ap)
1300{
1301 struct ahci_port_priv *pp = ap->private_data;
cca3974e
JG		 1302 struct ahci_host_priv *hpriv = ap->host->private_data;
1303 void __iomem *mmio = ap->host->mmio_base;
c1332875
TH		 1304 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1305
1306 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1307
1308 return 0;
1309}
1310
1311static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1312{
cca3974e
JG		 1313 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1314 void __iomem *mmio = host->mmio_base;
c1332875
TH		 1315 u32 ctl;
1316
1317 if (mesg.event == PM_EVENT_SUSPEND) {
1318 /* AHCI spec rev1.1 section 8.3.3:
1319 * Software must disable interrupts prior to requesting a
1320 * transition of the HBA to D3 state.
1321 */
1322 ctl = readl(mmio + HOST_CTL);
1323 ctl &= ~HOST_IRQ_EN;
1324 writel(ctl, mmio + HOST_CTL);
1325 readl(mmio + HOST_CTL); /* flush */
1326 }
1327
1328 return ata_pci_device_suspend(pdev, mesg);
1329}
1330
1331static int ahci_pci_device_resume(struct pci_dev *pdev)
1332{
cca3974e
JG		 1333 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1334 struct ahci_host_priv *hpriv = host->private_data;
1335 void __iomem *mmio = host->mmio_base;
c1332875
TH		 1336 int rc;
1337
1338 ata_pci_device_do_resume(pdev);
1339
1340 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1341 rc = ahci_reset_controller(mmio, pdev);
1342 if (rc)
1343 return rc;
1344
cca3974e 1345 ahci_init_controller(mmio, pdev, host->n_ports, hpriv->cap);
c1332875
TH		 1346 }
1347
cca3974e 1348 ata_host_resume(host);
c1332875
TH		 1349
1350 return 0;
1351}
1352
254950cd
TH		 1353static int ahci_port_start(struct ata_port *ap)
1354{
cca3974e
JG		 1355 struct device *dev = ap->host->dev;
1356 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1357 struct ahci_port_priv *pp;
cca3974e 1358 void __iomem *mmio = ap->host->mmio_base;
254950cd
TH		 1359 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1360 void *mem;
1361 dma_addr_t mem_dma;
1362 int rc;
1363
1364 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
1365 if (!pp)
1366 return -ENOMEM;
1367 memset(pp, 0, sizeof(*pp));
1368
1369 rc = ata_pad_alloc(ap, dev);
1370 if (rc) {
1371 kfree(pp);
1372 return rc;
1373 }
1374
1375 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1376 if (!mem) {
1377 ata_pad_free(ap, dev);
1378 kfree(pp);
1379 return -ENOMEM;
1380 }
1381 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1382
1383 /*
1384 * First item in chunk of DMA memory: 32-slot command table,
1385 * 32 bytes each in size
1386 */
1387 pp->cmd_slot = mem;
1388 pp->cmd_slot_dma = mem_dma;
1389
1390 mem += AHCI_CMD_SLOT_SZ;
1391 mem_dma += AHCI_CMD_SLOT_SZ;
1392
1393 /*
1394 * Second item: Received-FIS area
1395 */
1396 pp->rx_fis = mem;
1397 pp->rx_fis_dma = mem_dma;
1398
1399 mem += AHCI_RX_FIS_SZ;
1400 mem_dma += AHCI_RX_FIS_SZ;
1401
1402 /*
1403 * Third item: data area for storing a single command
1404 * and its scatter-gather table
1405 */
1406 pp->cmd_tbl = mem;
1407 pp->cmd_tbl_dma = mem_dma;
1408
1409 ap->private_data = pp;
1410
0be0aa98
TH		 1411 /* initialize port */
1412 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
254950cd
TH		 1413
1414 return 0;
1415}
1416
1417static void ahci_port_stop(struct ata_port *ap)
1418{
cca3974e
JG		 1419 struct device *dev = ap->host->dev;
1420 struct ahci_host_priv *hpriv = ap->host->private_data;
254950cd 1421 struct ahci_port_priv *pp = ap->private_data;
cca3974e 1422 void __iomem *mmio = ap->host->mmio_base;
254950cd 1423 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
0be0aa98
TH		 1424 const char *emsg = NULL;
1425 int rc;
254950cd 1426
0be0aa98
TH		 1427 /* de-initialize port */
1428 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1429 if (rc)
1430 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 1431
1432 ap->private_data = NULL;
1433 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1434 pp->cmd_slot, pp->cmd_slot_dma);
1435 ata_pad_free(ap, dev);
1436 kfree(pp);
1437}
1438
1da177e4
LT		 1439static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1440 unsigned int port_idx)
1441{
1442 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1443 base = ahci_port_base_ul(base, port_idx);
1444 VPRINTK("base now==0x%lx\n", base);
1445
1446 port->cmd_addr = base;
1447 port->scr_addr = base + PORT_SCR;
1448
1449 VPRINTK("EXIT\n");
1450}
1451
1452static int ahci_host_init(struct ata_probe_ent *probe_ent)
1453{
1454 struct ahci_host_priv *hpriv = probe_ent->private_data;
1455 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1456 void __iomem *mmio = probe_ent->mmio_base;
0be0aa98 1457 unsigned int i, using_dac;
1da177e4 1458 int rc;
1da177e4 1459
d91542c1
TH		 1460 rc = ahci_reset_controller(mmio, pdev);
1461 if (rc)
1462 return rc;
1da177e4
LT		 1463
1464 hpriv->cap = readl(mmio + HOST_CAP);
1465 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1466 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1467
1468 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1469 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1470
1471 using_dac = hpriv->cap & HOST_CAP_64;
1472 if (using_dac &&
1473 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1474 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1475 if (rc) {
1476 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1477 if (rc) {
a9524a76
JG		 1478 dev_printk(KERN_ERR, &pdev->dev,
1479 "64-bit DMA enable failed\n");
1da177e4
LT		 1480 return rc;
1481 }
1482 }
1da177e4
LT		 1483 } else {
1484 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1485 if (rc) {
a9524a76
JG		 1486 dev_printk(KERN_ERR, &pdev->dev,
1487 "32-bit DMA enable failed\n");
1da177e4
LT		 1488 return rc;
1489 }
1490 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1491 if (rc) {
a9524a76
JG		 1492 dev_printk(KERN_ERR, &pdev->dev,
1493 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 1494 return rc;
1495 }
1496 }
1497
d91542c1
TH		 1498 for (i = 0; i < probe_ent->n_ports; i++)
1499 ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i);
1da177e4 1500
d91542c1 1501 ahci_init_controller(mmio, pdev, probe_ent->n_ports, hpriv->cap);
1da177e4
LT		 1502
1503 pci_set_master(pdev);
1504
1505 return 0;
1506}
1507
1da177e4
LT		 1508static void ahci_print_info(struct ata_probe_ent *probe_ent)
1509{
1510 struct ahci_host_priv *hpriv = probe_ent->private_data;
1511 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 1512 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 1513 u32 vers, cap, impl, speed;
1514 const char *speed_s;
1515 u16 cc;
1516 const char *scc_s;
1517
1518 vers = readl(mmio + HOST_VERSION);
1519 cap = hpriv->cap;
1520 impl = hpriv->port_map;
1521
1522 speed = (cap >> 20) & 0xf;
1523 if (speed == 1)
1524 speed_s = "1.5";
1525 else if (speed == 2)
1526 speed_s = "3";
1527 else
1528 speed_s = "?";
1529
1530 pci_read_config_word(pdev, 0x0a, &cc);
1531 if (cc == 0x0101)
1532 scc_s = "IDE";
1533 else if (cc == 0x0106)
1534 scc_s = "SATA";
1535 else if (cc == 0x0104)
1536 scc_s = "RAID";
1537 else
1538 scc_s = "unknown";
1539
a9524a76
JG		 1540 dev_printk(KERN_INFO, &pdev->dev,
1541 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1542 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1543 ,
1da177e4
LT		 1544
1545 (vers >> 24) & 0xff,
1546 (vers >> 16) & 0xff,
1547 (vers >> 8) & 0xff,
1548 vers & 0xff,
1549
1550 ((cap >> 8) & 0x1f) + 1,
1551 (cap & 0x1f) + 1,
1552 speed_s,
1553 impl,
1554 scc_s);
1555
a9524a76
JG		 1556 dev_printk(KERN_INFO, &pdev->dev,
1557 "flags: "
1da177e4
LT		 1558 "%s%s%s%s%s%s"
1559 "%s%s%s%s%s%s%s\n"
1560 ,
1da177e4
LT		 1561
1562 cap & (1 << 31) ? "64bit " : "",
1563 cap & (1 << 30) ? "ncq " : "",
1564 cap & (1 << 28) ? "ilck " : "",
1565 cap & (1 << 27) ? "stag " : "",
1566 cap & (1 << 26) ? "pm " : "",
1567 cap & (1 << 25) ? "led " : "",
1568
1569 cap & (1 << 24) ? "clo " : "",
1570 cap & (1 << 19) ? "nz " : "",
1571 cap & (1 << 18) ? "only " : "",
1572 cap & (1 << 17) ? "pmp " : "",
1573 cap & (1 << 15) ? "pio " : "",
1574 cap & (1 << 14) ? "slum " : "",
1575 cap & (1 << 13) ? "part " : ""
1576 );
1577}
1578
1579static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1580{
1581 static int printed_version;
1582 struct ata_probe_ent *probe_ent = NULL;
1583 struct ahci_host_priv *hpriv;
1584 unsigned long base;
ea6ba10b 1585 void __iomem *mmio_base;
1da177e4 1586 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1587 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1588 int rc;
1589
1590 VPRINTK("ENTER\n");
1591
12fad3f9
TH		 1592 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1593
1da177e4 1594 if (!printed_version++)
a9524a76 1595 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1596
9545b578
AC		 1597 /* JMicron-specific fixup: make sure we're in AHCI mode */
1598 /* This is protected from races with ata_jmicron by the pci probe
1599 locking */
1600 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1601 /* AHCI enable, AHCI on function 0 */
1602 pci_write_config_byte(pdev, 0x41, 0xa1);
1603 /* Function 1 is the PATA controller */
1604 if (PCI_FUNC(pdev->devfn))
1605 return -ENODEV;
1606 }
1607
1da177e4
LT		 1608 rc = pci_enable_device(pdev);
1609 if (rc)
1610 return rc;
1611
1612 rc = pci_request_regions(pdev, DRV_NAME);
1613 if (rc) {
1614 pci_dev_busy = 1;
1615 goto err_out;
1616 }
1617
907f4678
JG		 1618 if (pci_enable_msi(pdev) == 0)
1619 have_msi = 1;
1620 else {
1621 pci_intx(pdev, 1);
1622 have_msi = 0;
1623 }
1da177e4
LT		 1624
1625 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1626 if (probe_ent == NULL) {
1627 rc = -ENOMEM;
907f4678 1628 goto err_out_msi;
1da177e4
LT		 1629 }
1630
1631 memset(probe_ent, 0, sizeof(*probe_ent));
1632 probe_ent->dev = pci_dev_to_dev(pdev);
1633 INIT_LIST_HEAD(&probe_ent->node);
1634
374b1873 1635 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1636 if (mmio_base == NULL) {
1637 rc = -ENOMEM;
1638 goto err_out_free_ent;
1639 }
1640 base = (unsigned long) mmio_base;
1641
1642 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1643 if (!hpriv) {
1644 rc = -ENOMEM;
1645 goto err_out_iounmap;
1646 }
1647 memset(hpriv, 0, sizeof(*hpriv));
1648
1649 probe_ent->sht = ahci_port_info[board_idx].sht;
cca3974e 1650 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1da177e4
LT		 1651 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1652 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1653 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1654
1655 probe_ent->irq = pdev->irq;
1d6f359a 1656 probe_ent->irq_flags = IRQF_SHARED;
1da177e4
LT		 1657 probe_ent->mmio_base = mmio_base;
1658 probe_ent->private_data = hpriv;
1659
4b0060f4
JG		 1660 if (have_msi)
1661 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1662
1da177e4
LT		 1663 /* initialize adapter */
1664 rc = ahci_host_init(probe_ent);
1665 if (rc)
1666 goto err_out_hpriv;
1667
cca3974e 1668 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
71f0737b 1669 (hpriv->cap & HOST_CAP_NCQ))
cca3974e 1670 probe_ent->port_flags |= ATA_FLAG_NCQ;
12fad3f9 1671
1da177e4
LT		 1672 ahci_print_info(probe_ent);
1673
1674 /* FIXME: check ata_device_add return value */
1675 ata_device_add(probe_ent);
1676 kfree(probe_ent);
1677
1678 return 0;
1679
1680err_out_hpriv:
1681 kfree(hpriv);
1682err_out_iounmap:
374b1873 1683 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1684err_out_free_ent:
1685 kfree(probe_ent);
907f4678
JG		 1686err_out_msi:
1687 if (have_msi)
1688 pci_disable_msi(pdev);
1689 else
1690 pci_intx(pdev, 0);
1da177e4
LT		 1691 pci_release_regions(pdev);
1692err_out:
1693 if (!pci_dev_busy)
1694 pci_disable_device(pdev);
1695 return rc;
1696}
1697
907f4678
JG		 1698static void ahci_remove_one (struct pci_dev *pdev)
1699{
1700 struct device *dev = pci_dev_to_dev(pdev);
cca3974e
JG		 1701 struct ata_host *host = dev_get_drvdata(dev);
1702 struct ahci_host_priv *hpriv = host->private_data;
907f4678
JG		 1703 unsigned int i;
1704 int have_msi;
1705
cca3974e
JG		 1706 for (i = 0; i < host->n_ports; i++)
1707 ata_port_detach(host->ports[i]);
907f4678 1708
4b0060f4 1709 have_msi = hpriv->flags & AHCI_FLAG_MSI;
cca3974e 1710 free_irq(host->irq, host);
907f4678 1711
cca3974e
JG		 1712 for (i = 0; i < host->n_ports; i++) {
1713 struct ata_port *ap = host->ports[i];
907f4678 1714
cca3974e
JG		 1715 ata_scsi_release(ap->scsi_host);
1716 scsi_host_put(ap->scsi_host);
907f4678
JG		 1717 }
1718
e005f01d 1719 kfree(hpriv);
cca3974e
JG		 1720 pci_iounmap(pdev, host->mmio_base);
1721 kfree(host);
ead5de99 1722
907f4678
JG		 1723 if (have_msi)
1724 pci_disable_msi(pdev);
1725 else
1726 pci_intx(pdev, 0);
1727 pci_release_regions(pdev);
907f4678
JG		 1728 pci_disable_device(pdev);
1729 dev_set_drvdata(dev, NULL);
1730}
1da177e4
LT		 1731
1732static int __init ahci_init(void)
1733{
b7887196 1734 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1735}
1736
1da177e4
LT		 1737static void __exit ahci_exit(void)
1738{
1739 pci_unregister_driver(&ahci_pci_driver);
1740}
1741
1742
1743MODULE_AUTHOR("Jeff Garzik");
1744MODULE_DESCRIPTION("AHCI SATA low-level driver");
1745MODULE_LICENSE("GPL");
1746MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1747MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1748
1749module_init(ahci_init);
1750module_exit(ahci_exit);
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