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ata: Convert ata_<foo>_printk(KERN_<LEVEL> to ata_<foo>_<level>
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
5f173107 63 board_ahci_yes_fbs,
1da177e4 64
441577ef
TH		 65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
83f2b963
TH		 67 board_ahci_mcp77,
68 board_ahci_mcp89,
441577ef
TH		 69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 78 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 79};
80
2dcb407e 81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
bd17243a
SH		 82static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
438ac6d5 88#ifdef CONFIG_PM
c1332875
TH		 89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 91#endif
ad616ffb 92
fad16e7a
TH		 93static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
029cfd6b
TH		 97static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
a1efdaba 99 .hardreset = ahci_vt8251_hardreset,
029cfd6b 100};
edc93052 101
029cfd6b
TH		 102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
a1efdaba 104 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 105};
106
bd17243a
SH		 107static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111};
112
417a1a6d
TH		 113#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
98ac62de 115static const struct ata_port_info ahci_port_info[] = {
441577ef 116 /* by features */
4da646b7 117 [board_ahci] =
1da177e4 118 {
1188c0d8 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
1da177e4
LT		 122 .port_ops = &ahci_ops,
123 },
441577ef 124 [board_ahci_ign_iferr] =
bf2af2a2 125 {
441577ef 126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 127 .flags = AHCI_FLAG_COMMON,
14bdef98 128 .pio_mask = ATA_PIO4,
469248ab 129 .udma_mask = ATA_UDMA6,
441577ef 130 .port_ops = &ahci_ops,
bf2af2a2 131 },
441577ef 132 [board_ahci_nosntf] =
41669553 133 {
441577ef 134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 135 .flags = AHCI_FLAG_COMMON,
14bdef98 136 .pio_mask = ATA_PIO4,
469248ab 137 .udma_mask = ATA_UDMA6,
41669553
TH		 138 .port_ops = &ahci_ops,
139 },
5f173107
TH		 140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
441577ef
TH		 148 /* by chipsets */
149 [board_ahci_mcp65] =
55a61604 150 {
83f2b963
TH		 151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
ae01b249 153 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 169 .flags = AHCI_FLAG_COMMON,
14bdef98 170 .pio_mask = ATA_PIO4,
469248ab 171 .udma_mask = ATA_UDMA6,
441577ef 172 .port_ops = &ahci_ops,
55a61604 173 },
4da646b7 174 [board_ahci_mv] =
cd70c266 175 {
417a1a6d 176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 179 .pio_mask = ATA_PIO4,
cd70c266
JG		 180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
441577ef 183 [board_ahci_sb600] =
e39fc8c9 184 {
441577ef
TH		 185 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
186 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 188 .flags = AHCI_FLAG_COMMON,
14bdef98 189 .pio_mask = ATA_PIO4,
e39fc8c9 190 .udma_mask = ATA_UDMA6,
bd17243a 191 .port_ops = &ahci_sb600_ops,
e39fc8c9 192 },
441577ef 193 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 194 {
441577ef 195 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
441577ef 199 .port_ops = &ahci_sb600_ops,
aa431dd3 200 },
441577ef 201 [board_ahci_vt8251] =
1b677afd 202 {
441577ef 203 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 204 .flags = AHCI_FLAG_COMMON,
205 .pio_mask = ATA_PIO4,
206 .udma_mask = ATA_UDMA6,
441577ef 207 .port_ops = &ahci_vt8251_ops,
1b677afd 208 },
1da177e4
LT		 209};
210
3b7d697d 211static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 212 /* Intel */
54bb3a94
JG		 213 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
214 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
215 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
216 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
217 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 218 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 219 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
220 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 223 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 224 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 225 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
227 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
239 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 240 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
241 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 242 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 243 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 244 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 245 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
246 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 247 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 248 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 249 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 250 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 251 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 252 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 253 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 259 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
260 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
261 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 262 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 263 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 264 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
265 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
266 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
fe7fa31a 270
e34bb370
TH		 271 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
272 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
273 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 274
275 /* ATI */
c65ec1c2 276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 283
e2dd90b1 284 /* AMD */
5deab536 285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
289
fe7fa31a 290 /* VIA */
54bb3a94 291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 293
294 /* NVIDIA */
e297d99e
TH		 295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 379
95916edd 380 /* SiS */
20e2de4a
TH		 381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 384
cd70c266
JG		 385 /* Marvell */
386 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 387 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 388 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 389 .class = PCI_CLASS_STORAGE_SATA_AHCI,
390 .class_mask = 0xffffff,
5f173107 391 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 392 { PCI_DEVICE(0x1b4b, 0x9125),
393 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
50be5e36
TH		 394 { PCI_DEVICE(0x1b4b, 0x91a3),
395 .driver_data = board_ahci_yes_fbs },
cd70c266 396
c77a036b
MN		 397 /* Promise */
398 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
399
415ae2b5
JG		 400 /* Generic, PCI class code for AHCI */
401 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 402 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 403
1da177e4
LT		 404 { } /* terminate list */
405};
406
407
408static struct pci_driver ahci_pci_driver = {
409 .name = DRV_NAME,
410 .id_table = ahci_pci_tbl,
411 .probe = ahci_init_one,
24dc5f33 412 .remove = ata_pci_remove_one,
438ac6d5 413#ifdef CONFIG_PM
c1332875 414 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 415 .resume = ahci_pci_device_resume,
416#endif
417};
1da177e4 418
365cfa1e
AV		 419#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
420static int marvell_enable;
421#else
422static int marvell_enable = 1;
423#endif
424module_param(marvell_enable, int, 0644);
425MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 426
1da177e4 427
365cfa1e
AV		 428static void ahci_pci_save_initial_config(struct pci_dev *pdev,
429 struct ahci_host_priv *hpriv)
430{
431 unsigned int force_port_map = 0;
432 unsigned int mask_port_map = 0;
67846b30 433
365cfa1e
AV		 434 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
435 dev_info(&pdev->dev, "JMB361 has only one port\n");
436 force_port_map = 1;
1da177e4
LT		 437 }
438
365cfa1e
AV		 439 /*
440 * Temporary Marvell 6145 hack: PATA port presence
441 * is asserted through the standard AHCI port
442 * presence register, as bit 4 (counting from 0)
d28f87aa 443 */
365cfa1e
AV		 444 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
445 if (pdev->device == 0x6121)
446 mask_port_map = 0x3;
447 else
448 mask_port_map = 0xf;
449 dev_info(&pdev->dev,
450 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
451 }
1da177e4 452
365cfa1e
AV		 453 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
454 mask_port_map);
1da177e4
LT		 455}
456
365cfa1e 457static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 458{
365cfa1e 459 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 460
365cfa1e 461 ahci_reset_controller(host);
1da177e4 462
365cfa1e
AV		 463 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
464 struct ahci_host_priv *hpriv = host->private_data;
465 u16 tmp16;
d6ef3153 466
365cfa1e
AV		 467 /* configure PCS */
468 pci_read_config_word(pdev, 0x92, &tmp16);
469 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
470 tmp16 |= hpriv->port_map;
471 pci_write_config_word(pdev, 0x92, tmp16);
472 }
d6ef3153
SH		 473 }
474
1da177e4
LT		 475 return 0;
476}
477
365cfa1e 478static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 479{
365cfa1e
AV		 480 struct ahci_host_priv *hpriv = host->private_data;
481 struct pci_dev *pdev = to_pci_dev(host->dev);
482 void __iomem *port_mmio;
78cd52d0 483 u32 tmp;
365cfa1e 484 int mv;
78cd52d0 485
365cfa1e
AV		 486 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
487 if (pdev->device == 0x6121)
488 mv = 2;
489 else
490 mv = 4;
491 port_mmio = __ahci_port_base(host, mv);
78cd52d0 492
365cfa1e 493 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 494
365cfa1e
AV		 495 /* clear port IRQ */
496 tmp = readl(port_mmio + PORT_IRQ_STAT);
497 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
498 if (tmp)
499 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 500 }
501
365cfa1e 502 ahci_init_controller(host);
edc93052
TH		 503}
504
365cfa1e 505static int ahci_sb600_check_ready(struct ata_link *link)
78cd52d0 506{
365cfa1e
AV		 507 void __iomem *port_mmio = ahci_port_base(link->ap);
508 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
509 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
510
511 /*
512 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
513 * which can save timeout delay.
514 */
515 if (irq_status & PORT_IRQ_BAD_PMP)
516 return -EIO;
78cd52d0 517
365cfa1e 518 return ata_check_ready(status);
78cd52d0
TH		 519}
520
365cfa1e
AV		 521static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
522 unsigned long deadline)
d6ef3153 523{
365cfa1e 524 struct ata_port *ap = link->ap;
d6ef3153 525 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 526 int pmp = sata_srst_pmp(link);
d6ef3153 527 int rc;
365cfa1e 528 u32 irq_sts;
d6ef3153 529
365cfa1e 530 DPRINTK("ENTER\n");
d6ef3153 531
365cfa1e
AV		 532 rc = ahci_do_softreset(link, class, pmp, deadline,
533 ahci_sb600_check_ready);
d6ef3153 534
365cfa1e
AV		 535 /*
536 * Soft reset fails on some ATI chips with IPMS set when PMP
537 * is enabled but SATA HDD/ODD is connected to SATA port,
538 * do soft reset again to port 0.
539 */
540 if (rc == -EIO) {
541 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
542 if (irq_sts & PORT_IRQ_BAD_PMP) {
a9a79dfe
JP		 543 ata_link_warn(link,
544 "applying SB600 PMP SRST workaround and retrying\n");
365cfa1e
AV		 545 rc = ahci_do_softreset(link, class, 0, deadline,
546 ahci_check_ready);
547 }
548 }
d6ef3153 549
365cfa1e 550 return rc;
d6ef3153
SH		 551}
552
365cfa1e
AV		 553static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
554 unsigned long deadline)
d6ef3153 555{
365cfa1e
AV		 556 struct ata_port *ap = link->ap;
557 bool online;
d6ef3153
SH		 558 int rc;
559
365cfa1e 560 DPRINTK("ENTER\n");
d6ef3153 561
365cfa1e 562 ahci_stop_engine(ap);
d6ef3153 563
365cfa1e
AV		 564 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
565 deadline, &online, NULL);
d6ef3153
SH		 566
567 ahci_start_engine(ap);
d6ef3153 568
365cfa1e 569 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 570
365cfa1e
AV		 571 /* vt8251 doesn't clear BSY on signature FIS reception,
572 * request follow-up softreset.
573 */
574 return online ? -EAGAIN : rc;
7d50b60b
TH		 575}
576
365cfa1e
AV		 577static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
578 unsigned long deadline)
7d50b60b 579{
365cfa1e 580 struct ata_port *ap = link->ap;
1c954a4d 581 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 582 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
583 struct ata_taskfile tf;
584 bool online;
585 int rc;
7d50b60b 586
365cfa1e 587 ahci_stop_engine(ap);
028a2596 588
365cfa1e
AV		 589 /* clear D2H reception area to properly wait for D2H FIS */
590 ata_tf_init(link->device, &tf);
591 tf.command = 0x80;
592 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 593
365cfa1e
AV		 594 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
595 deadline, &online, NULL);
028a2596 596
365cfa1e 597 ahci_start_engine(ap);
c1332875 598
365cfa1e
AV		 599 /* The pseudo configuration device on SIMG4726 attached to
600 * ASUS P5W-DH Deluxe doesn't send signature FIS after
601 * hardreset if no device is attached to the first downstream
602 * port && the pseudo device locks up on SRST w/ PMP==0. To
603 * work around this, wait for !BSY only briefly. If BSY isn't
604 * cleared, perform CLO and proceed to IDENTIFY (achieved by
605 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
606 *
607 * Wait for two seconds. Devices attached to downstream port
608 * which can't process the following IDENTIFY after this will
609 * have to be reset again. For most cases, this should
610 * suffice while making probing snappish enough.
611 */
612 if (online) {
613 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
614 ahci_check_ready);
615 if (rc)
616 ahci_kick_engine(ap);
c1332875 617 }
c1332875
TH		 618 return rc;
619}
620
365cfa1e 621#ifdef CONFIG_PM
c1332875
TH		 622static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
623{
cca3974e 624 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 625 struct ahci_host_priv *hpriv = host->private_data;
d8993349 626 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 627 u32 ctl;
628
9b10ae86
TH		 629 if (mesg.event & PM_EVENT_SUSPEND &&
630 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 631 dev_err(&pdev->dev,
632 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 633 return -EIO;
634 }
635
3a2d5b70 636 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 637 /* AHCI spec rev1.1 section 8.3.3:
638 * Software must disable interrupts prior to requesting a
639 * transition of the HBA to D3 state.
640 */
641 ctl = readl(mmio + HOST_CTL);
642 ctl &= ~HOST_IRQ_EN;
643 writel(ctl, mmio + HOST_CTL);
644 readl(mmio + HOST_CTL); /* flush */
645 }
646
647 return ata_pci_device_suspend(pdev, mesg);
648}
649
650static int ahci_pci_device_resume(struct pci_dev *pdev)
651{
cca3974e 652 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 653 int rc;
654
553c4aa6
TH		 655 rc = ata_pci_device_do_resume(pdev);
656 if (rc)
657 return rc;
c1332875
TH		 658
659 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 660 rc = ahci_pci_reset_controller(host);
c1332875
TH		 661 if (rc)
662 return rc;
663
781d6550 664 ahci_pci_init_controller(host);
c1332875
TH		 665 }
666
cca3974e 667 ata_host_resume(host);
c1332875
TH		 668
669 return 0;
670}
438ac6d5 671#endif
c1332875 672
4447d351 673static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 674{
1da177e4 675 int rc;
1da177e4 676
1da177e4 677 if (using_dac &&
6a35528a
YH		 678 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
679 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 680 if (rc) {
284901a9 681 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 682 if (rc) {
a44fec1f
JP		 683 dev_err(&pdev->dev,
684 "64-bit DMA enable failed\n");
1da177e4
LT		 685 return rc;
686 }
687 }
1da177e4 688 } else {
284901a9 689 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 690 if (rc) {
a44fec1f 691 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 692 return rc;
693 }
284901a9 694 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 695 if (rc) {
a44fec1f
JP		 696 dev_err(&pdev->dev,
697 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 698 return rc;
699 }
700 }
1da177e4
LT		 701 return 0;
702}
703
439fcaec
AV		 704static void ahci_pci_print_info(struct ata_host *host)
705{
706 struct pci_dev *pdev = to_pci_dev(host->dev);
707 u16 cc;
708 const char *scc_s;
709
710 pci_read_config_word(pdev, 0x0a, &cc);
711 if (cc == PCI_CLASS_STORAGE_IDE)
712 scc_s = "IDE";
713 else if (cc == PCI_CLASS_STORAGE_SATA)
714 scc_s = "SATA";
715 else if (cc == PCI_CLASS_STORAGE_RAID)
716 scc_s = "RAID";
717 else
718 scc_s = "unknown";
719
720 ahci_print_info(host, scc_s);
721}
722
edc93052
TH		 723/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
724 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
725 * support PMP and the 4726 either directly exports the device
726 * attached to the first downstream port or acts as a hardware storage
727 * controller and emulate a single ATA device (can be RAID 0/1 or some
728 * other configuration).
729 *
730 * When there's no device attached to the first downstream port of the
731 * 4726, "Config Disk" appears, which is a pseudo ATA device to
732 * configure the 4726. However, ATA emulation of the device is very
733 * lame. It doesn't send signature D2H Reg FIS after the initial
734 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
735 *
736 * The following function works around the problem by always using
737 * hardreset on the port and not depending on receiving signature FIS
738 * afterward. If signature FIS isn't received soon, ATA class is
739 * assumed without follow-up softreset.
740 */
741static void ahci_p5wdh_workaround(struct ata_host *host)
742{
743 static struct dmi_system_id sysids[] = {
744 {
745 .ident = "P5W DH Deluxe",
746 .matches = {
747 DMI_MATCH(DMI_SYS_VENDOR,
748 "ASUSTEK COMPUTER INC"),
749 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
750 },
751 },
752 { }
753 };
754 struct pci_dev *pdev = to_pci_dev(host->dev);
755
756 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
757 dmi_check_system(sysids)) {
758 struct ata_port *ap = host->ports[1];
759
a44fec1f
JP		 760 dev_info(&pdev->dev,
761 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 762
763 ap->ops = &ahci_p5wdh_ops;
764 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
765 }
766}
767
2fcad9d2
TH		 768/* only some SB600 ahci controllers can do 64bit DMA */
769static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 770{
771 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 772 /*
773 * The oldest version known to be broken is 0901 and
774 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 775 * Enable 64bit DMA on 1501 and anything newer.
776 *
03d783bf
TH		 777 * Please read bko#9412 for more info.
778 */
58a09b38
SH		 779 {
780 .ident = "ASUS M2A-VM",
781 .matches = {
782 DMI_MATCH(DMI_BOARD_VENDOR,
783 "ASUSTeK Computer INC."),
784 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
785 },
03d783bf 786 .driver_data = "20071026", /* yyyymmdd */
58a09b38 787 },
e65cc194
MN		 788 /*
789 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
790 * support 64bit DMA.
791 *
792 * BIOS versions earlier than 1.5 had the Manufacturer DMI
793 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
794 * This spelling mistake was fixed in BIOS version 1.5, so
795 * 1.5 and later have the Manufacturer as
796 * "MICRO-STAR INTERNATIONAL CO.,LTD".
797 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
798 *
799 * BIOS versions earlier than 1.9 had a Board Product Name
800 * DMI field of "MS-7376". This was changed to be
801 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
802 * match on DMI_BOARD_NAME of "MS-7376".
803 */
804 {
805 .ident = "MSI K9A2 Platinum",
806 .matches = {
807 DMI_MATCH(DMI_BOARD_VENDOR,
808 "MICRO-STAR INTER"),
809 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
810 },
811 },
58a09b38
SH		 812 { }
813 };
03d783bf 814 const struct dmi_system_id *match;
2fcad9d2
TH		 815 int year, month, date;
816 char buf[9];
58a09b38 817
03d783bf 818 match = dmi_first_match(sysids);
58a09b38 819 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 820 !match)
58a09b38
SH		 821 return false;
822
e65cc194
MN		 823 if (!match->driver_data)
824 goto enable_64bit;
825
2fcad9d2
TH		 826 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
827 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 828
e65cc194
MN		 829 if (strcmp(buf, match->driver_data) >= 0)
830 goto enable_64bit;
831 else {
a44fec1f
JP		 832 dev_warn(&pdev->dev,
833 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
834 match->ident);
2fcad9d2
TH		 835 return false;
836 }
e65cc194
MN		 837
838enable_64bit:
a44fec1f 839 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 840 return true;
58a09b38
SH		 841}
842
1fd68434
RW		 843static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
844{
845 static const struct dmi_system_id broken_systems[] = {
846 {
847 .ident = "HP Compaq nx6310",
848 .matches = {
849 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
850 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
851 },
852 /* PCI slot number of the controller */
853 .driver_data = (void *)0x1FUL,
854 },
d2f9c061
MR		 855 {
856 .ident = "HP Compaq 6720s",
857 .matches = {
858 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
859 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
860 },
861 /* PCI slot number of the controller */
862 .driver_data = (void *)0x1FUL,
863 },
1fd68434
RW		 864
865 { } /* terminate list */
866 };
867 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
868
869 if (dmi) {
870 unsigned long slot = (unsigned long)dmi->driver_data;
871 /* apply the quirk only to on-board controllers */
872 return slot == PCI_SLOT(pdev->devfn);
873 }
874
875 return false;
876}
877
9b10ae86
TH		 878static bool ahci_broken_suspend(struct pci_dev *pdev)
879{
880 static const struct dmi_system_id sysids[] = {
881 /*
882 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
883 * to the harddisk doesn't become online after
884 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 885 *
886 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
887 *
888 * Use dates instead of versions to match as HP is
889 * apparently recycling both product and version
890 * strings.
891 *
892 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 893 */
894 {
895 .ident = "dv4",
896 .matches = {
897 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
898 DMI_MATCH(DMI_PRODUCT_NAME,
899 "HP Pavilion dv4 Notebook PC"),
900 },
9deb3431 901 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 902 },
903 {
904 .ident = "dv5",
905 .matches = {
906 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
907 DMI_MATCH(DMI_PRODUCT_NAME,
908 "HP Pavilion dv5 Notebook PC"),
909 },
9deb3431 910 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 911 },
912 {
913 .ident = "dv6",
914 .matches = {
915 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
916 DMI_MATCH(DMI_PRODUCT_NAME,
917 "HP Pavilion dv6 Notebook PC"),
918 },
9deb3431 919 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 920 },
921 {
922 .ident = "HDX18",
923 .matches = {
924 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
925 DMI_MATCH(DMI_PRODUCT_NAME,
926 "HP HDX18 Notebook PC"),
927 },
9deb3431 928 .driver_data = "20090430", /* F.23 */
9b10ae86 929 },
cedc9bf9
TH		 930 /*
931 * Acer eMachines G725 has the same problem. BIOS
932 * V1.03 is known to be broken. V3.04 is known to
25985edc 933 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 934 * that we don't have much idea about. For now,
935 * blacklist anything older than V3.04.
9deb3431
TH		 936 *
937 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 938 */
939 {
940 .ident = "G725",
941 .matches = {
942 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
943 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
944 },
9deb3431 945 .driver_data = "20091216", /* V3.04 */
cedc9bf9 946 },
9b10ae86
TH		 947 { } /* terminate list */
948 };
949 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 950 int year, month, date;
951 char buf[9];
9b10ae86
TH		 952
953 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
954 return false;
955
9deb3431
TH		 956 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
957 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 958
9deb3431 959 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 960}
961
5594639a
TH		 962static bool ahci_broken_online(struct pci_dev *pdev)
963{
964#define ENCODE_BUSDEVFN(bus, slot, func) \
965 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
966 static const struct dmi_system_id sysids[] = {
967 /*
968 * There are several gigabyte boards which use
969 * SIMG5723s configured as hardware RAID. Certain
970 * 5723 firmware revisions shipped there keep the link
971 * online but fail to answer properly to SRST or
972 * IDENTIFY when no device is attached downstream
973 * causing libata to retry quite a few times leading
974 * to excessive detection delay.
975 *
976 * As these firmwares respond to the second reset try
977 * with invalid device signature, considering unknown
978 * sig as offline works around the problem acceptably.
979 */
980 {
981 .ident = "EP45-DQ6",
982 .matches = {
983 DMI_MATCH(DMI_BOARD_VENDOR,
984 "Gigabyte Technology Co., Ltd."),
985 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
986 },
987 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
988 },
989 {
990 .ident = "EP45-DS5",
991 .matches = {
992 DMI_MATCH(DMI_BOARD_VENDOR,
993 "Gigabyte Technology Co., Ltd."),
994 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
995 },
996 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
997 },
998 { } /* terminate list */
999 };
1000#undef ENCODE_BUSDEVFN
1001 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1002 unsigned int val;
1003
1004 if (!dmi)
1005 return false;
1006
1007 val = (unsigned long)dmi->driver_data;
1008
1009 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1010}
1011
8e513217 1012#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1013static void ahci_gtf_filter_workaround(struct ata_host *host)
1014{
1015 static const struct dmi_system_id sysids[] = {
1016 /*
1017 * Aspire 3810T issues a bunch of SATA enable commands
1018 * via _GTF including an invalid one and one which is
1019 * rejected by the device. Among the successful ones
1020 * is FPDMA non-zero offset enable which when enabled
1021 * only on the drive side leads to NCQ command
1022 * failures. Filter it out.
1023 */
1024 {
1025 .ident = "Aspire 3810T",
1026 .matches = {
1027 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1028 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1029 },
1030 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1031 },
1032 { }
1033 };
1034 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1035 unsigned int filter;
1036 int i;
1037
1038 if (!dmi)
1039 return;
1040
1041 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1042 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1043 filter, dmi->ident);
f80ae7e4
TH		 1044
1045 for (i = 0; i < host->n_ports; i++) {
1046 struct ata_port *ap = host->ports[i];
1047 struct ata_link *link;
1048 struct ata_device *dev;
1049
1050 ata_for_each_link(link, ap, EDGE)
1051 ata_for_each_dev(dev, link, ALL)
1052 dev->gtf_filter |= filter;
1053 }
1054}
8e513217
MT		 1055#else
1056static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1057{}
1058#endif
f80ae7e4 1059
24dc5f33 1060static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1061{
1062 static int printed_version;
e297d99e
TH		 1063 unsigned int board_id = ent->driver_data;
1064 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1065 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1066 struct device *dev = &pdev->dev;
1da177e4 1067 struct ahci_host_priv *hpriv;
4447d351 1068 struct ata_host *host;
837f5f8f 1069 int n_ports, i, rc;
1da177e4
LT		 1070
1071 VPRINTK("ENTER\n");
1072
b429dd59 1073 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1074
1da177e4 1075 if (!printed_version++)
a9524a76 1076 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1077
5b66c829
AC		 1078 /* The AHCI driver can only drive the SATA ports, the PATA driver
1079 can drive them all so if both drivers are selected make sure
1080 AHCI stays out of the way */
1081 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1082 return -ENODEV;
1083
c6353b45
TH		 1084 /*
1085 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1086 * ahci, use ata_generic instead.
1087 */
1088 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1089 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1090 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1091 pdev->subsystem_device == 0xcb89)
1092 return -ENODEV;
1093
7a02267e
MN		 1094 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1095 * At the moment, we can only use the AHCI mode. Let the users know
1096 * that for SAS drives they're out of luck.
1097 */
1098 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1099 dev_info(&pdev->dev,
1100 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1101
4447d351 1102 /* acquire resources */
24dc5f33 1103 rc = pcim_enable_device(pdev);
1da177e4
LT		 1104 if (rc)
1105 return rc;
1106
dea55137
TH		 1107 /* AHCI controllers often implement SFF compatible interface.
1108 * Grab all PCI BARs just in case.
1109 */
1110 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1111 if (rc == -EBUSY)
24dc5f33 1112 pcim_pin_device(pdev);
0d5ff566 1113 if (rc)
24dc5f33 1114 return rc;
1da177e4 1115
c4f7792c
TH		 1116 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1117 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1118 u8 map;
1119
1120 /* ICH6s share the same PCI ID for both piix and ahci
1121 * modes. Enabling ahci mode while MAP indicates
1122 * combined mode is a bad idea. Yield to ata_piix.
1123 */
1124 pci_read_config_byte(pdev, ICH_MAP, &map);
1125 if (map & 0x3) {
a44fec1f
JP		 1126 dev_info(&pdev->dev,
1127 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1128 return -ENODEV;
1129 }
1130 }
1131
24dc5f33
TH		 1132 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1133 if (!hpriv)
1134 return -ENOMEM;
417a1a6d
TH		 1135 hpriv->flags |= (unsigned long)pi.private_data;
1136
e297d99e
TH		 1137 /* MCP65 revision A1 and A2 can't do MSI */
1138 if (board_id == board_ahci_mcp65 &&
1139 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1140 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1141
e427fe04
SH		 1142 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1143 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1144 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1145
2fcad9d2
TH		 1146 /* only some SB600s can do 64bit DMA */
1147 if (ahci_sb600_enable_64bit(pdev))
1148 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1149
31b239ad
TH		 1150 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1151 pci_intx(pdev, 1);
1da177e4 1152
d8993349
AV		 1153 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1154
4447d351 1155 /* save initial config */
394d6e53 1156 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1157
4447d351 1158 /* prepare host */
453d3131
RH		 1159 if (hpriv->cap & HOST_CAP_NCQ) {
1160 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1161 /*
1162 * Auto-activate optimization is supposed to be
1163 * supported on all AHCI controllers indicating NCQ
1164 * capability, but it seems to be broken on some
1165 * chipsets including NVIDIAs.
1166 */
1167 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1168 pi.flags |= ATA_FLAG_FPDMA_AA;
1169 }
1da177e4 1170
7d50b60b
TH		 1171 if (hpriv->cap & HOST_CAP_PMP)
1172 pi.flags |= ATA_FLAG_PMP;
1173
0cbb0e77 1174 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1175
1fd68434
RW		 1176 if (ahci_broken_system_poweroff(pdev)) {
1177 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1178 dev_info(&pdev->dev,
1179 "quirky BIOS, skipping spindown on poweroff\n");
1180 }
1181
9b10ae86
TH		 1182 if (ahci_broken_suspend(pdev)) {
1183 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1184 dev_warn(&pdev->dev,
1185 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1186 }
1187
5594639a
TH		 1188 if (ahci_broken_online(pdev)) {
1189 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1190 dev_info(&pdev->dev,
1191 "online status unreliable, applying workaround\n");
1192 }
1193
837f5f8f
TH		 1194 /* CAP.NP sometimes indicate the index of the last enabled
1195 * port, at other times, that of the last possible port, so
1196 * determining the maximum port number requires looking at
1197 * both CAP.NP and port_map.
1198 */
1199 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1200
1201 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1202 if (!host)
1203 return -ENOMEM;
4447d351
TH		 1204 host->private_data = hpriv;
1205
f3d7f23f 1206 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1207 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1208 else
1209 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1210
18f7ba4c
KCA		 1211 if (pi.flags & ATA_FLAG_EM)
1212 ahci_reset_em(host);
1213
4447d351 1214 for (i = 0; i < host->n_ports; i++) {
dab632e8 1215 struct ata_port *ap = host->ports[i];
4447d351 1216
cbcdd875
TH		 1217 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1218 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1219 0x100 + ap->port_no * 0x80, "port");
1220
18f7ba4c
KCA		 1221 /* set enclosure management message type */
1222 if (ap->flags & ATA_FLAG_EM)
008dbd61 1223 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1224
1225
dab632e8 1226 /* disabled/not-implemented port */
350756f6 1227 if (!(hpriv->port_map & (1 << i)))
dab632e8 1228 ap->ops = &ata_dummy_port_ops;
4447d351 1229 }
d447df14 1230
edc93052
TH		 1231 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1232 ahci_p5wdh_workaround(host);
1233
f80ae7e4
TH		 1234 /* apply gtf filter quirk */
1235 ahci_gtf_filter_workaround(host);
1236
4447d351
TH		 1237 /* initialize adapter */
1238 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1239 if (rc)
24dc5f33 1240 return rc;
1da177e4 1241
3303040d 1242 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1243 if (rc)
1244 return rc;
1da177e4 1245
781d6550 1246 ahci_pci_init_controller(host);
439fcaec 1247 ahci_pci_print_info(host);
1da177e4 1248
4447d351
TH		 1249 pci_set_master(pdev);
1250 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1251 &ahci_sht);
907f4678 1252}
1da177e4
LT		 1253
1254static int __init ahci_init(void)
1255{
b7887196 1256 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1257}
1258
1da177e4
LT		 1259static void __exit ahci_exit(void)
1260{
1261 pci_unregister_driver(&ahci_pci_driver);
1262}
1263
1264
1265MODULE_AUTHOR("Jeff Garzik");
1266MODULE_DESCRIPTION("AHCI SATA low-level driver");
1267MODULE_LICENSE("GPL");
1268MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1269MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1270
1271module_init(ahci_init);
1272module_exit(ahci_exit);
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