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[libata] Prevent interface errors with Seagate FreeAgent GoFlex
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1
AR		 55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
5f173107 64 board_ahci_yes_fbs,
1da177e4 65
441577ef
TH		 66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
83f2b963
TH		 68 board_ahci_mcp77,
69 board_ahci_mcp89,
441577ef
TH		 70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 79 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 80};
81
2dcb407e 82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
438ac6d5 87#ifdef CONFIG_PM
c1332875
TH		 88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 90#endif
ad616ffb 91
fad16e7a
TH		 92static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94};
95
029cfd6b
TH		 96static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
a1efdaba 98 .hardreset = ahci_vt8251_hardreset,
029cfd6b 99};
edc93052 100
029cfd6b
TH		 101static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
a1efdaba 103 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 104};
105
98ac62de 106static const struct ata_port_info ahci_port_info[] = {
441577ef 107 /* by features */
4da646b7 108 [board_ahci] =
1da177e4 109 {
1188c0d8 110 .flags = AHCI_FLAG_COMMON,
14bdef98 111 .pio_mask = ATA_PIO4,
469248ab 112 .udma_mask = ATA_UDMA6,
1da177e4
LT		 113 .port_ops = &ahci_ops,
114 },
441577ef 115 [board_ahci_ign_iferr] =
bf2af2a2 116 {
441577ef 117 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 118 .flags = AHCI_FLAG_COMMON,
14bdef98 119 .pio_mask = ATA_PIO4,
469248ab 120 .udma_mask = ATA_UDMA6,
441577ef 121 .port_ops = &ahci_ops,
bf2af2a2 122 },
441577ef 123 [board_ahci_nosntf] =
41669553 124 {
441577ef 125 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 126 .flags = AHCI_FLAG_COMMON,
14bdef98 127 .pio_mask = ATA_PIO4,
469248ab 128 .udma_mask = ATA_UDMA6,
41669553
TH		 129 .port_ops = &ahci_ops,
130 },
5f173107
TH		 131 [board_ahci_yes_fbs] =
132 {
133 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
441577ef
TH		 139 /* by chipsets */
140 [board_ahci_mcp65] =
55a61604 141 {
83f2b963
TH		 142 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
143 AHCI_HFLAG_YES_NCQ),
ae01b249 144 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_mcp77] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
156 },
157 [board_ahci_mcp89] =
158 {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 160 .flags = AHCI_FLAG_COMMON,
14bdef98 161 .pio_mask = ATA_PIO4,
469248ab 162 .udma_mask = ATA_UDMA6,
441577ef 163 .port_ops = &ahci_ops,
55a61604 164 },
4da646b7 165 [board_ahci_mv] =
cd70c266 166 {
417a1a6d 167 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 168 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 169 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 170 .pio_mask = ATA_PIO4,
cd70c266
JG		 171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
441577ef 174 [board_ahci_sb600] =
e39fc8c9 175 {
441577ef
TH		 176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
177 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
178 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 179 .flags = AHCI_FLAG_COMMON,
14bdef98 180 .pio_mask = ATA_PIO4,
e39fc8c9 181 .udma_mask = ATA_UDMA6,
345347c5 182 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 183 },
441577ef 184 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 185 {
441577ef 186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
345347c5 190 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 191 },
441577ef 192 [board_ahci_vt8251] =
1b677afd 193 {
441577ef 194 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 195 .flags = AHCI_FLAG_COMMON,
196 .pio_mask = ATA_PIO4,
197 .udma_mask = ATA_UDMA6,
441577ef 198 .port_ops = &ahci_vt8251_ops,
1b677afd 199 },
1da177e4
LT		 200};
201
3b7d697d 202static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 203 /* Intel */
54bb3a94
JG		 204 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
205 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
206 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
207 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
208 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 209 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 210 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 214 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 215 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 216 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 231 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
232 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 233 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 234 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 235 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 236 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
237 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 238 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 239 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 240 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 241 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 242 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 243 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 244 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 250 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
251 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
252 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 253 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 254 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 255 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 261 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 262 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
264 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
fe7fa31a 270
e34bb370
TH		 271 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
272 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
273 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 274
275 /* ATI */
c65ec1c2 276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 283
e2dd90b1 284 /* AMD */
5deab536 285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
289
fe7fa31a 290 /* VIA */
54bb3a94 291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 293
294 /* NVIDIA */
e297d99e
TH		 295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 379
95916edd 380 /* SiS */
20e2de4a
TH		 381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 384
318893e1
AR		 385 /* ST Microelectronics */
386 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
387
cd70c266
JG		 388 /* Marvell */
389 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 390 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 391 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 392 .class = PCI_CLASS_STORAGE_SATA_AHCI,
393 .class_mask = 0xffffff,
5f173107 394 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 395 { PCI_DEVICE(0x1b4b, 0x9125),
396 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
642d8925
MJ		 397 { PCI_DEVICE(0x1b4b, 0x917a),
398 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
50be5e36
TH		 399 { PCI_DEVICE(0x1b4b, 0x91a3),
400 .driver_data = board_ahci_yes_fbs },
cd70c266 401
c77a036b
MN		 402 /* Promise */
403 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
404
c9703765
KYL		 405 /* Asmedia */
406 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
407
415ae2b5
JG		 408 /* Generic, PCI class code for AHCI */
409 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 410 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 411
1da177e4
LT		 412 { } /* terminate list */
413};
414
415
416static struct pci_driver ahci_pci_driver = {
417 .name = DRV_NAME,
418 .id_table = ahci_pci_tbl,
419 .probe = ahci_init_one,
24dc5f33 420 .remove = ata_pci_remove_one,
438ac6d5 421#ifdef CONFIG_PM
c1332875 422 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 423 .resume = ahci_pci_device_resume,
424#endif
425};
1da177e4 426
365cfa1e
AV		 427#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
428static int marvell_enable;
429#else
430static int marvell_enable = 1;
431#endif
432module_param(marvell_enable, int, 0644);
433MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 434
1da177e4 435
365cfa1e
AV		 436static void ahci_pci_save_initial_config(struct pci_dev *pdev,
437 struct ahci_host_priv *hpriv)
438{
439 unsigned int force_port_map = 0;
440 unsigned int mask_port_map = 0;
67846b30 441
365cfa1e
AV		 442 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
443 dev_info(&pdev->dev, "JMB361 has only one port\n");
444 force_port_map = 1;
1da177e4
LT		 445 }
446
365cfa1e
AV		 447 /*
448 * Temporary Marvell 6145 hack: PATA port presence
449 * is asserted through the standard AHCI port
450 * presence register, as bit 4 (counting from 0)
d28f87aa 451 */
365cfa1e
AV		 452 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
453 if (pdev->device == 0x6121)
454 mask_port_map = 0x3;
455 else
456 mask_port_map = 0xf;
457 dev_info(&pdev->dev,
458 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
459 }
1da177e4 460
365cfa1e
AV		 461 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
462 mask_port_map);
1da177e4
LT		 463}
464
365cfa1e 465static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 466{
365cfa1e 467 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 468
365cfa1e 469 ahci_reset_controller(host);
1da177e4 470
365cfa1e
AV		 471 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
472 struct ahci_host_priv *hpriv = host->private_data;
473 u16 tmp16;
d6ef3153 474
365cfa1e
AV		 475 /* configure PCS */
476 pci_read_config_word(pdev, 0x92, &tmp16);
477 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
478 tmp16 |= hpriv->port_map;
479 pci_write_config_word(pdev, 0x92, tmp16);
480 }
d6ef3153
SH		 481 }
482
1da177e4
LT		 483 return 0;
484}
485
365cfa1e 486static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 487{
365cfa1e
AV		 488 struct ahci_host_priv *hpriv = host->private_data;
489 struct pci_dev *pdev = to_pci_dev(host->dev);
490 void __iomem *port_mmio;
78cd52d0 491 u32 tmp;
365cfa1e 492 int mv;
78cd52d0 493
365cfa1e
AV		 494 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
495 if (pdev->device == 0x6121)
496 mv = 2;
497 else
498 mv = 4;
499 port_mmio = __ahci_port_base(host, mv);
78cd52d0 500
365cfa1e 501 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 502
365cfa1e
AV		 503 /* clear port IRQ */
504 tmp = readl(port_mmio + PORT_IRQ_STAT);
505 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
506 if (tmp)
507 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 508 }
509
365cfa1e 510 ahci_init_controller(host);
edc93052
TH		 511}
512
365cfa1e
AV		 513static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
514 unsigned long deadline)
d6ef3153 515{
365cfa1e
AV		 516 struct ata_port *ap = link->ap;
517 bool online;
d6ef3153
SH		 518 int rc;
519
365cfa1e 520 DPRINTK("ENTER\n");
d6ef3153 521
365cfa1e 522 ahci_stop_engine(ap);
d6ef3153 523
365cfa1e
AV		 524 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
525 deadline, &online, NULL);
d6ef3153
SH		 526
527 ahci_start_engine(ap);
d6ef3153 528
365cfa1e 529 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 530
365cfa1e
AV		 531 /* vt8251 doesn't clear BSY on signature FIS reception,
532 * request follow-up softreset.
533 */
534 return online ? -EAGAIN : rc;
7d50b60b
TH		 535}
536
365cfa1e
AV		 537static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
538 unsigned long deadline)
7d50b60b 539{
365cfa1e 540 struct ata_port *ap = link->ap;
1c954a4d 541 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 542 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
543 struct ata_taskfile tf;
544 bool online;
545 int rc;
7d50b60b 546
365cfa1e 547 ahci_stop_engine(ap);
028a2596 548
365cfa1e
AV		 549 /* clear D2H reception area to properly wait for D2H FIS */
550 ata_tf_init(link->device, &tf);
551 tf.command = 0x80;
552 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 553
365cfa1e
AV		 554 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
555 deadline, &online, NULL);
028a2596 556
365cfa1e 557 ahci_start_engine(ap);
c1332875 558
365cfa1e
AV		 559 /* The pseudo configuration device on SIMG4726 attached to
560 * ASUS P5W-DH Deluxe doesn't send signature FIS after
561 * hardreset if no device is attached to the first downstream
562 * port && the pseudo device locks up on SRST w/ PMP==0. To
563 * work around this, wait for !BSY only briefly. If BSY isn't
564 * cleared, perform CLO and proceed to IDENTIFY (achieved by
565 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
566 *
567 * Wait for two seconds. Devices attached to downstream port
568 * which can't process the following IDENTIFY after this will
569 * have to be reset again. For most cases, this should
570 * suffice while making probing snappish enough.
571 */
572 if (online) {
573 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
574 ahci_check_ready);
575 if (rc)
576 ahci_kick_engine(ap);
c1332875 577 }
c1332875
TH		 578 return rc;
579}
580
365cfa1e 581#ifdef CONFIG_PM
c1332875
TH		 582static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
583{
cca3974e 584 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 585 struct ahci_host_priv *hpriv = host->private_data;
d8993349 586 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 587 u32 ctl;
588
9b10ae86
TH		 589 if (mesg.event & PM_EVENT_SUSPEND &&
590 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 591 dev_err(&pdev->dev,
592 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 593 return -EIO;
594 }
595
3a2d5b70 596 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 597 /* AHCI spec rev1.1 section 8.3.3:
598 * Software must disable interrupts prior to requesting a
599 * transition of the HBA to D3 state.
600 */
601 ctl = readl(mmio + HOST_CTL);
602 ctl &= ~HOST_IRQ_EN;
603 writel(ctl, mmio + HOST_CTL);
604 readl(mmio + HOST_CTL); /* flush */
605 }
606
607 return ata_pci_device_suspend(pdev, mesg);
608}
609
610static int ahci_pci_device_resume(struct pci_dev *pdev)
611{
cca3974e 612 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 613 int rc;
614
553c4aa6
TH		 615 rc = ata_pci_device_do_resume(pdev);
616 if (rc)
617 return rc;
c1332875
TH		 618
619 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 620 rc = ahci_pci_reset_controller(host);
c1332875
TH		 621 if (rc)
622 return rc;
623
781d6550 624 ahci_pci_init_controller(host);
c1332875
TH		 625 }
626
cca3974e 627 ata_host_resume(host);
c1332875
TH		 628
629 return 0;
630}
438ac6d5 631#endif
c1332875 632
4447d351 633static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 634{
1da177e4 635 int rc;
1da177e4 636
318893e1
AR		 637 /*
638 * If the device fixup already set the dma_mask to some non-standard
639 * value, don't extend it here. This happens on STA2X11, for example.
640 */
641 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
642 return 0;
643
1da177e4 644 if (using_dac &&
6a35528a
YH		 645 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
646 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 647 if (rc) {
284901a9 648 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 649 if (rc) {
a44fec1f
JP		 650 dev_err(&pdev->dev,
651 "64-bit DMA enable failed\n");
1da177e4
LT		 652 return rc;
653 }
654 }
1da177e4 655 } else {
284901a9 656 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 657 if (rc) {
a44fec1f 658 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 659 return rc;
660 }
284901a9 661 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 662 if (rc) {
a44fec1f
JP		 663 dev_err(&pdev->dev,
664 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 665 return rc;
666 }
667 }
1da177e4
LT		 668 return 0;
669}
670
439fcaec
AV		 671static void ahci_pci_print_info(struct ata_host *host)
672{
673 struct pci_dev *pdev = to_pci_dev(host->dev);
674 u16 cc;
675 const char *scc_s;
676
677 pci_read_config_word(pdev, 0x0a, &cc);
678 if (cc == PCI_CLASS_STORAGE_IDE)
679 scc_s = "IDE";
680 else if (cc == PCI_CLASS_STORAGE_SATA)
681 scc_s = "SATA";
682 else if (cc == PCI_CLASS_STORAGE_RAID)
683 scc_s = "RAID";
684 else
685 scc_s = "unknown";
686
687 ahci_print_info(host, scc_s);
688}
689
edc93052
TH		 690/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
691 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
692 * support PMP and the 4726 either directly exports the device
693 * attached to the first downstream port or acts as a hardware storage
694 * controller and emulate a single ATA device (can be RAID 0/1 or some
695 * other configuration).
696 *
697 * When there's no device attached to the first downstream port of the
698 * 4726, "Config Disk" appears, which is a pseudo ATA device to
699 * configure the 4726. However, ATA emulation of the device is very
700 * lame. It doesn't send signature D2H Reg FIS after the initial
701 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
702 *
703 * The following function works around the problem by always using
704 * hardreset on the port and not depending on receiving signature FIS
705 * afterward. If signature FIS isn't received soon, ATA class is
706 * assumed without follow-up softreset.
707 */
708static void ahci_p5wdh_workaround(struct ata_host *host)
709{
710 static struct dmi_system_id sysids[] = {
711 {
712 .ident = "P5W DH Deluxe",
713 .matches = {
714 DMI_MATCH(DMI_SYS_VENDOR,
715 "ASUSTEK COMPUTER INC"),
716 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
717 },
718 },
719 { }
720 };
721 struct pci_dev *pdev = to_pci_dev(host->dev);
722
723 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
724 dmi_check_system(sysids)) {
725 struct ata_port *ap = host->ports[1];
726
a44fec1f
JP		 727 dev_info(&pdev->dev,
728 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 729
730 ap->ops = &ahci_p5wdh_ops;
731 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
732 }
733}
734
2fcad9d2
TH		 735/* only some SB600 ahci controllers can do 64bit DMA */
736static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 737{
738 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 739 /*
740 * The oldest version known to be broken is 0901 and
741 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 742 * Enable 64bit DMA on 1501 and anything newer.
743 *
03d783bf
TH		 744 * Please read bko#9412 for more info.
745 */
58a09b38
SH		 746 {
747 .ident = "ASUS M2A-VM",
748 .matches = {
749 DMI_MATCH(DMI_BOARD_VENDOR,
750 "ASUSTeK Computer INC."),
751 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
752 },
03d783bf 753 .driver_data = "20071026", /* yyyymmdd */
58a09b38 754 },
e65cc194
MN		 755 /*
756 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
757 * support 64bit DMA.
758 *
759 * BIOS versions earlier than 1.5 had the Manufacturer DMI
760 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
761 * This spelling mistake was fixed in BIOS version 1.5, so
762 * 1.5 and later have the Manufacturer as
763 * "MICRO-STAR INTERNATIONAL CO.,LTD".
764 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
765 *
766 * BIOS versions earlier than 1.9 had a Board Product Name
767 * DMI field of "MS-7376". This was changed to be
768 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
769 * match on DMI_BOARD_NAME of "MS-7376".
770 */
771 {
772 .ident = "MSI K9A2 Platinum",
773 .matches = {
774 DMI_MATCH(DMI_BOARD_VENDOR,
775 "MICRO-STAR INTER"),
776 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
777 },
778 },
3c4aa91f
MN		 779 /*
780 * All BIOS versions for the Asus M3A support 64bit DMA.
781 * (all release versions from 0301 to 1206 were tested)
782 */
783 {
784 .ident = "ASUS M3A",
785 .matches = {
786 DMI_MATCH(DMI_BOARD_VENDOR,
787 "ASUSTeK Computer INC."),
788 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
789 },
790 },
58a09b38
SH		 791 { }
792 };
03d783bf 793 const struct dmi_system_id *match;
2fcad9d2
TH		 794 int year, month, date;
795 char buf[9];
58a09b38 796
03d783bf 797 match = dmi_first_match(sysids);
58a09b38 798 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 799 !match)
58a09b38
SH		 800 return false;
801
e65cc194
MN		 802 if (!match->driver_data)
803 goto enable_64bit;
804
2fcad9d2
TH		 805 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
806 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 807
e65cc194
MN		 808 if (strcmp(buf, match->driver_data) >= 0)
809 goto enable_64bit;
810 else {
a44fec1f
JP		 811 dev_warn(&pdev->dev,
812 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
813 match->ident);
2fcad9d2
TH		 814 return false;
815 }
e65cc194
MN		 816
817enable_64bit:
a44fec1f 818 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 819 return true;
58a09b38
SH		 820}
821
1fd68434
RW		 822static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
823{
824 static const struct dmi_system_id broken_systems[] = {
825 {
826 .ident = "HP Compaq nx6310",
827 .matches = {
828 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
829 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
830 },
831 /* PCI slot number of the controller */
832 .driver_data = (void *)0x1FUL,
833 },
d2f9c061
MR		 834 {
835 .ident = "HP Compaq 6720s",
836 .matches = {
837 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
838 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
839 },
840 /* PCI slot number of the controller */
841 .driver_data = (void *)0x1FUL,
842 },
1fd68434
RW		 843
844 { } /* terminate list */
845 };
846 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
847
848 if (dmi) {
849 unsigned long slot = (unsigned long)dmi->driver_data;
850 /* apply the quirk only to on-board controllers */
851 return slot == PCI_SLOT(pdev->devfn);
852 }
853
854 return false;
855}
856
9b10ae86
TH		 857static bool ahci_broken_suspend(struct pci_dev *pdev)
858{
859 static const struct dmi_system_id sysids[] = {
860 /*
861 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
862 * to the harddisk doesn't become online after
863 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 864 *
865 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
866 *
867 * Use dates instead of versions to match as HP is
868 * apparently recycling both product and version
869 * strings.
870 *
871 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 872 */
873 {
874 .ident = "dv4",
875 .matches = {
876 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
877 DMI_MATCH(DMI_PRODUCT_NAME,
878 "HP Pavilion dv4 Notebook PC"),
879 },
9deb3431 880 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 881 },
882 {
883 .ident = "dv5",
884 .matches = {
885 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
886 DMI_MATCH(DMI_PRODUCT_NAME,
887 "HP Pavilion dv5 Notebook PC"),
888 },
9deb3431 889 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 890 },
891 {
892 .ident = "dv6",
893 .matches = {
894 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
895 DMI_MATCH(DMI_PRODUCT_NAME,
896 "HP Pavilion dv6 Notebook PC"),
897 },
9deb3431 898 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 899 },
900 {
901 .ident = "HDX18",
902 .matches = {
903 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
904 DMI_MATCH(DMI_PRODUCT_NAME,
905 "HP HDX18 Notebook PC"),
906 },
9deb3431 907 .driver_data = "20090430", /* F.23 */
9b10ae86 908 },
cedc9bf9
TH		 909 /*
910 * Acer eMachines G725 has the same problem. BIOS
911 * V1.03 is known to be broken. V3.04 is known to
25985edc 912 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 913 * that we don't have much idea about. For now,
914 * blacklist anything older than V3.04.
9deb3431
TH		 915 *
916 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 917 */
918 {
919 .ident = "G725",
920 .matches = {
921 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
922 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
923 },
9deb3431 924 .driver_data = "20091216", /* V3.04 */
cedc9bf9 925 },
9b10ae86
TH		 926 { } /* terminate list */
927 };
928 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 929 int year, month, date;
930 char buf[9];
9b10ae86
TH		 931
932 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
933 return false;
934
9deb3431
TH		 935 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
936 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 937
9deb3431 938 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 939}
940
5594639a
TH		 941static bool ahci_broken_online(struct pci_dev *pdev)
942{
943#define ENCODE_BUSDEVFN(bus, slot, func) \
944 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
945 static const struct dmi_system_id sysids[] = {
946 /*
947 * There are several gigabyte boards which use
948 * SIMG5723s configured as hardware RAID. Certain
949 * 5723 firmware revisions shipped there keep the link
950 * online but fail to answer properly to SRST or
951 * IDENTIFY when no device is attached downstream
952 * causing libata to retry quite a few times leading
953 * to excessive detection delay.
954 *
955 * As these firmwares respond to the second reset try
956 * with invalid device signature, considering unknown
957 * sig as offline works around the problem acceptably.
958 */
959 {
960 .ident = "EP45-DQ6",
961 .matches = {
962 DMI_MATCH(DMI_BOARD_VENDOR,
963 "Gigabyte Technology Co., Ltd."),
964 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
965 },
966 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
967 },
968 {
969 .ident = "EP45-DS5",
970 .matches = {
971 DMI_MATCH(DMI_BOARD_VENDOR,
972 "Gigabyte Technology Co., Ltd."),
973 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
974 },
975 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
976 },
977 { } /* terminate list */
978 };
979#undef ENCODE_BUSDEVFN
980 const struct dmi_system_id *dmi = dmi_first_match(sysids);
981 unsigned int val;
982
983 if (!dmi)
984 return false;
985
986 val = (unsigned long)dmi->driver_data;
987
988 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
989}
990
8e513217 991#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 992static void ahci_gtf_filter_workaround(struct ata_host *host)
993{
994 static const struct dmi_system_id sysids[] = {
995 /*
996 * Aspire 3810T issues a bunch of SATA enable commands
997 * via _GTF including an invalid one and one which is
998 * rejected by the device. Among the successful ones
999 * is FPDMA non-zero offset enable which when enabled
1000 * only on the drive side leads to NCQ command
1001 * failures. Filter it out.
1002 */
1003 {
1004 .ident = "Aspire 3810T",
1005 .matches = {
1006 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1007 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1008 },
1009 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1010 },
1011 { }
1012 };
1013 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1014 unsigned int filter;
1015 int i;
1016
1017 if (!dmi)
1018 return;
1019
1020 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1021 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1022 filter, dmi->ident);
f80ae7e4
TH		 1023
1024 for (i = 0; i < host->n_ports; i++) {
1025 struct ata_port *ap = host->ports[i];
1026 struct ata_link *link;
1027 struct ata_device *dev;
1028
1029 ata_for_each_link(link, ap, EDGE)
1030 ata_for_each_dev(dev, link, ALL)
1031 dev->gtf_filter |= filter;
1032 }
1033}
8e513217
MT		 1034#else
1035static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1036{}
1037#endif
f80ae7e4 1038
24dc5f33 1039static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1040{
e297d99e
TH		 1041 unsigned int board_id = ent->driver_data;
1042 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1043 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1044 struct device *dev = &pdev->dev;
1da177e4 1045 struct ahci_host_priv *hpriv;
4447d351 1046 struct ata_host *host;
837f5f8f 1047 int n_ports, i, rc;
318893e1 1048 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1049
1050 VPRINTK("ENTER\n");
1051
b429dd59 1052 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1053
06296a1e 1054 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1055
5b66c829
AC		 1056 /* The AHCI driver can only drive the SATA ports, the PATA driver
1057 can drive them all so if both drivers are selected make sure
1058 AHCI stays out of the way */
1059 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1060 return -ENODEV;
1061
c6353b45
TH		 1062 /*
1063 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1064 * ahci, use ata_generic instead.
1065 */
1066 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1067 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1068 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1069 pdev->subsystem_device == 0xcb89)
1070 return -ENODEV;
1071
7a02267e
MN		 1072 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1073 * At the moment, we can only use the AHCI mode. Let the users know
1074 * that for SAS drives they're out of luck.
1075 */
1076 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1077 dev_info(&pdev->dev,
1078 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1079
318893e1
AR		 1080 /* The Connext uses non-standard BAR */
1081 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1082 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1083
4447d351 1084 /* acquire resources */
24dc5f33 1085 rc = pcim_enable_device(pdev);
1da177e4
LT		 1086 if (rc)
1087 return rc;
1088
dea55137
TH		 1089 /* AHCI controllers often implement SFF compatible interface.
1090 * Grab all PCI BARs just in case.
1091 */
318893e1 1092 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1093 if (rc == -EBUSY)
24dc5f33 1094 pcim_pin_device(pdev);
0d5ff566 1095 if (rc)
24dc5f33 1096 return rc;
1da177e4 1097
c4f7792c
TH		 1098 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1099 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1100 u8 map;
1101
1102 /* ICH6s share the same PCI ID for both piix and ahci
1103 * modes. Enabling ahci mode while MAP indicates
1104 * combined mode is a bad idea. Yield to ata_piix.
1105 */
1106 pci_read_config_byte(pdev, ICH_MAP, &map);
1107 if (map & 0x3) {
a44fec1f
JP		 1108 dev_info(&pdev->dev,
1109 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1110 return -ENODEV;
1111 }
1112 }
1113
24dc5f33
TH		 1114 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1115 if (!hpriv)
1116 return -ENOMEM;
417a1a6d
TH		 1117 hpriv->flags |= (unsigned long)pi.private_data;
1118
e297d99e
TH		 1119 /* MCP65 revision A1 and A2 can't do MSI */
1120 if (board_id == board_ahci_mcp65 &&
1121 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1122 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1123
e427fe04
SH		 1124 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1125 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1126 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1127
2fcad9d2
TH		 1128 /* only some SB600s can do 64bit DMA */
1129 if (ahci_sb600_enable_64bit(pdev))
1130 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1131
31b239ad
TH		 1132 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1133 pci_intx(pdev, 1);
1da177e4 1134
318893e1 1135 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1136
4447d351 1137 /* save initial config */
394d6e53 1138 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1139
4447d351 1140 /* prepare host */
453d3131
RH		 1141 if (hpriv->cap & HOST_CAP_NCQ) {
1142 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1143 /*
1144 * Auto-activate optimization is supposed to be
1145 * supported on all AHCI controllers indicating NCQ
1146 * capability, but it seems to be broken on some
1147 * chipsets including NVIDIAs.
1148 */
1149 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1150 pi.flags |= ATA_FLAG_FPDMA_AA;
1151 }
1da177e4 1152
7d50b60b
TH		 1153 if (hpriv->cap & HOST_CAP_PMP)
1154 pi.flags |= ATA_FLAG_PMP;
1155
0cbb0e77 1156 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1157
1fd68434
RW		 1158 if (ahci_broken_system_poweroff(pdev)) {
1159 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1160 dev_info(&pdev->dev,
1161 "quirky BIOS, skipping spindown on poweroff\n");
1162 }
1163
9b10ae86
TH		 1164 if (ahci_broken_suspend(pdev)) {
1165 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1166 dev_warn(&pdev->dev,
1167 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1168 }
1169
5594639a
TH		 1170 if (ahci_broken_online(pdev)) {
1171 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1172 dev_info(&pdev->dev,
1173 "online status unreliable, applying workaround\n");
1174 }
1175
837f5f8f
TH		 1176 /* CAP.NP sometimes indicate the index of the last enabled
1177 * port, at other times, that of the last possible port, so
1178 * determining the maximum port number requires looking at
1179 * both CAP.NP and port_map.
1180 */
1181 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1182
1183 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1184 if (!host)
1185 return -ENOMEM;
4447d351
TH		 1186 host->private_data = hpriv;
1187
f3d7f23f 1188 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1189 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1190 else
1191 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1192
18f7ba4c
KCA		 1193 if (pi.flags & ATA_FLAG_EM)
1194 ahci_reset_em(host);
1195
4447d351 1196 for (i = 0; i < host->n_ports; i++) {
dab632e8 1197 struct ata_port *ap = host->ports[i];
4447d351 1198
318893e1
AR		 1199 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1200 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1201 0x100 + ap->port_no * 0x80, "port");
1202
18f7ba4c
KCA		 1203 /* set enclosure management message type */
1204 if (ap->flags & ATA_FLAG_EM)
008dbd61 1205 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1206
1207
dab632e8 1208 /* disabled/not-implemented port */
350756f6 1209 if (!(hpriv->port_map & (1 << i)))
dab632e8 1210 ap->ops = &ata_dummy_port_ops;
4447d351 1211 }
d447df14 1212
edc93052
TH		 1213 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1214 ahci_p5wdh_workaround(host);
1215
f80ae7e4
TH		 1216 /* apply gtf filter quirk */
1217 ahci_gtf_filter_workaround(host);
1218
4447d351
TH		 1219 /* initialize adapter */
1220 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1221 if (rc)
24dc5f33 1222 return rc;
1da177e4 1223
3303040d 1224 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1225 if (rc)
1226 return rc;
1da177e4 1227
781d6550 1228 ahci_pci_init_controller(host);
439fcaec 1229 ahci_pci_print_info(host);
1da177e4 1230
4447d351
TH		 1231 pci_set_master(pdev);
1232 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1233 &ahci_sht);
907f4678 1234}
1da177e4
LT		 1235
1236static int __init ahci_init(void)
1237{
b7887196 1238 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1239}
1240
1da177e4
LT		 1241static void __exit ahci_exit(void)
1242{
1243 pci_unregister_driver(&ahci_pci_driver);
1244}
1245
1246
1247MODULE_AUTHOR("Jeff Garzik");
1248MODULE_DESCRIPTION("AHCI SATA low-level driver");
1249MODULE_LICENSE("GPL");
1250MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1251MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1252
1253module_init(ahci_init);
1254module_exit(ahci_exit);
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