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ahci: Implement SATA AHCI FIS-based switching support
[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
87943acf
DM		 52/* Enclosure Management Control */
53#define EM_CTRL_MSG_TYPE 0x000f0000
54
55/* Enclosure Management LED Message Type */
56#define EM_MSG_LED_HBA_PORT 0x0000000f
57#define EM_MSG_LED_PMP_SLOT 0x0000ff00
58#define EM_MSG_LED_VALUE 0xffff0000
59#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60#define EM_MSG_LED_VALUE_OFF 0xfff80000
61#define EM_MSG_LED_VALUE_ON 0x00010000
62
a22e6444 63static int ahci_skip_host_reset;
f3d7f23f
AV		 64static int ahci_ignore_sss;
65
a22e6444
TH		 66module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68
f3d7f23f
AV		 69module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71
31556594
KCA		 72static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy);
74static void ahci_disable_alpm(struct ata_port *ap);
18f7ba4c
KCA		 75static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size);
78static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size);
1da177e4
LT		 80
81enum {
82 AHCI_PCI_BAR = 5,
648a88be 83 AHCI_MAX_PORTS = 32,
1da177e4
LT		 84 AHCI_MAX_SG = 168, /* hardware max is 64K */
85 AHCI_DMA_BOUNDARY = 0xffffffff,
12fad3f9 86 AHCI_MAX_CMDS = 32,
dd410ff1 87 AHCI_CMD_SZ = 32,
12fad3f9 88 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 89 AHCI_RX_FIS_SZ = 256,
a0ea7328 90 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 91 AHCI_CMD_TBL_HDR_SZ = 0x80,
92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4 95 AHCI_RX_FIS_SZ,
d6ef3153
SH		 96 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
97 AHCI_CMD_TBL_AR_SZ +
98 (AHCI_RX_FIS_SZ * 16),
1da177e4
LT		 99 AHCI_IRQ_ON_SG = (1 << 31),
100 AHCI_CMD_ATAPI = (1 << 5),
101 AHCI_CMD_WRITE = (1 << 6),
4b10e559 102 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 103 AHCI_CMD_RESET = (1 << 8),
104 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 105
106 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 107 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 108 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 109
110 board_ahci = 0,
7a234aff
TH		 111 board_ahci_vt8251 = 1,
112 board_ahci_ign_iferr = 2,
113 board_ahci_sb600 = 3,
114 board_ahci_mv = 4,
e427fe04 115 board_ahci_sb700 = 5, /* for SB700 and SB800 */
e297d99e 116 board_ahci_mcp65 = 6,
9a3b103c 117 board_ahci_nopmp = 7,
aa431dd3 118 board_ahci_yesncq = 8,
1b677afd 119 board_ahci_nosntf = 9,
1da177e4
LT		 120
121 /* global controller registers */
122 HOST_CAP = 0x00, /* host capabilities */
123 HOST_CTL = 0x04, /* global host control */
124 HOST_IRQ_STAT = 0x08, /* interrupt status */
125 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
126 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
18f7ba4c
KCA		 127 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
128 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
4c521c8e 129 HOST_CAP2 = 0x24, /* host capabilities, extended */
1da177e4
LT		 130
131 /* HOST_CTL bits */
132 HOST_RESET = (1 << 0), /* reset controller; self-clear */
133 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
134 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
135
136 /* HOST_CAP bits */
4c521c8e 137 HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
18f7ba4c 138 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
4c521c8e
RH		 139 HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
140 HOST_CAP_PART = (1 << 13), /* Partial state capable */
141 HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
142 HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
143 HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
7d50b60b 144 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
4c521c8e 145 HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
22b49985 146 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
4c521c8e 147 HOST_CAP_LED = (1 << 25), /* Supports activity LED */
31556594 148 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 149 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
4c521c8e 150 HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
203ef6c4 151 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 152 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 153 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4 154
4c521c8e
RH		 155 /* HOST_CAP2 bits */
156 HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
157 HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
158 HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
159
1da177e4
LT		 160 /* registers for each SATA port */
161 PORT_LST_ADDR = 0x00, /* command list DMA addr */
162 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
163 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
164 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
165 PORT_IRQ_STAT = 0x10, /* interrupt status */
166 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
167 PORT_CMD = 0x18, /* port command */
168 PORT_TFDATA = 0x20, /* taskfile data */
169 PORT_SIG = 0x24, /* device TF signature */
170 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 171 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
172 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
173 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
174 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 175 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
d6ef3153 176 PORT_FBS = 0x40, /* FIS-based Switching */
1da177e4
LT		 177
178 /* PORT_IRQ_{STAT,MASK} bits */
179 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
180 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
181 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
182 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
183 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
184 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
185 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
186 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
187
188 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
189 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
190 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
191 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
192 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
193 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
194 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
195 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
196 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
197
78cd52d0
TH		 198 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
199 PORT_IRQ_IF_ERR |
200 PORT_IRQ_CONNECT |
4296971d 201 PORT_IRQ_PHYRDY |
7d50b60b
TH		 202 PORT_IRQ_UNK_FIS |
203 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 204 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
205 PORT_IRQ_TF_ERR |
206 PORT_IRQ_HBUS_DATA_ERR,
207 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
208 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
209 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 210
211 /* PORT_CMD bits */
31556594
KCA		 212 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
213 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 214 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
d6ef3153 215 PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
7d50b60b 216 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 217 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
218 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
219 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 220 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 221 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
222 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
223 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
224
0be0aa98 225 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 226 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
227 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
228 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 229
d6ef3153
SH		 230 PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
231 PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
232 PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
233 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
234 PORT_FBS_SDE = (1 << 2), /* FBS single device error */
235 PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
236 PORT_FBS_EN = (1 << 0), /* Enable FBS */
237
417a1a6d
TH		 238 /* hpriv->flags bits */
239 AHCI_HFLAG_NO_NCQ = (1 << 0),
240 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
241 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
242 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
243 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
244 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 245 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 246 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
a878539e 247 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
e297d99e 248 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
9b10ae86 249 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
5594639a
TH		 250 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
251 link offline */
1b677afd 252 AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
417a1a6d 253
bf2af2a2 254 /* ap->flags bits */
1188c0d8
TH		 255
256 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
257 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 258 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
259 ATA_FLAG_IPM,
c4f7792c
TH		 260
261 ICH_MAP = 0x90, /* ICH MAP register */
18f7ba4c 262
d50ce07d
TH		 263 /* em constants */
264 EM_MAX_SLOTS = 8,
265 EM_MAX_RETRY = 5,
266
18f7ba4c
KCA		 267 /* em_ctl bits */
268 EM_CTL_RST = (1 << 9), /* Reset */
269 EM_CTL_TM = (1 << 8), /* Transmit Message */
270 EM_CTL_ALHD = (1 << 26), /* Activity LED */
1da177e4
LT		 271};
272
273struct ahci_cmd_hdr {
4ca4e439
AV		 274 __le32 opts;
275 __le32 status;
276 __le32 tbl_addr;
277 __le32 tbl_addr_hi;
278 __le32 reserved[4];
1da177e4
LT		 279};
280
281struct ahci_sg {
4ca4e439
AV		 282 __le32 addr;
283 __le32 addr_hi;
284 __le32 reserved;
285 __le32 flags_size;
1da177e4
LT		 286};
287
18f7ba4c
KCA		 288struct ahci_em_priv {
289 enum sw_activity blink_policy;
290 struct timer_list timer;
291 unsigned long saved_activity;
292 unsigned long activity;
293 unsigned long led_state;
294};
295
1da177e4 296struct ahci_host_priv {
417a1a6d 297 unsigned int flags; /* AHCI_HFLAG_* */
d447df14 298 u32 cap; /* cap to use */
4c521c8e 299 u32 cap2; /* cap2 to use */
d447df14
TH		 300 u32 port_map; /* port map to use */
301 u32 saved_cap; /* saved initial cap */
4c521c8e 302 u32 saved_cap2; /* saved initial cap2 */
d447df14 303 u32 saved_port_map; /* saved initial port_map */
18f7ba4c 304 u32 em_loc; /* enclosure management location */
1da177e4
LT		 305};
306
307struct ahci_port_priv {
7d50b60b 308 struct ata_link *active_link;
1da177e4
LT		 309 struct ahci_cmd_hdr *cmd_slot;
310 dma_addr_t cmd_slot_dma;
311 void *cmd_tbl;
312 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 313 void *rx_fis;
314 dma_addr_t rx_fis_dma;
0291f95f 315 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 316 unsigned int ncq_saw_d2h:1;
317 unsigned int ncq_saw_dmas:1;
afb2d552 318 unsigned int ncq_saw_sdb:1;
a7384925 319 u32 intr_mask; /* interrupts to enable */
d6ef3153
SH		 320 bool fbs_supported; /* set iff FBS is supported */
321 bool fbs_enabled; /* set iff FBS is enabled */
322 int fbs_last_dev; /* save FBS.DEV of last FIS */
d50ce07d
TH		 323 /* enclosure management info per PM slot */
324 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
1da177e4
LT		 325};
326
82ef04fb
TH		 327static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
328static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
2dcb407e 329static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 330static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
4c9bf4e7 331static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
1da177e4
LT		 332static int ahci_port_start(struct ata_port *ap);
333static void ahci_port_stop(struct ata_port *ap);
d6ef3153 334static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
1da177e4 335static void ahci_qc_prep(struct ata_queued_cmd *qc);
78cd52d0
TH		 336static void ahci_freeze(struct ata_port *ap);
337static void ahci_thaw(struct ata_port *ap);
d6ef3153
SH		 338static void ahci_enable_fbs(struct ata_port *ap);
339static void ahci_disable_fbs(struct ata_port *ap);
7d50b60b
TH		 340static void ahci_pmp_attach(struct ata_port *ap);
341static void ahci_pmp_detach(struct ata_port *ap);
a1efdaba
TH		 342static int ahci_softreset(struct ata_link *link, unsigned int *class,
343 unsigned long deadline);
bd17243a
SH		 344static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
345 unsigned long deadline);
a1efdaba
TH		 346static int ahci_hardreset(struct ata_link *link, unsigned int *class,
347 unsigned long deadline);
348static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
349 unsigned long deadline);
350static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
351 unsigned long deadline);
352static void ahci_postreset(struct ata_link *link, unsigned int *class);
78cd52d0
TH		 353static void ahci_error_handler(struct ata_port *ap);
354static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 355static int ahci_port_resume(struct ata_port *ap);
a878539e 356static void ahci_dev_config(struct ata_device *dev);
dab632e8
JG		 357static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
358 u32 opts);
438ac6d5 359#ifdef CONFIG_PM
c1332875 360static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 361static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
362static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 363#endif
18f7ba4c
KCA		 364static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
365static ssize_t ahci_activity_store(struct ata_device *dev,
366 enum sw_activity val);
367static void ahci_init_sw_activity(struct ata_link *link);
1da177e4 368
77cdec1a
MG		 369static ssize_t ahci_show_host_caps(struct device *dev,
370 struct device_attribute *attr, char *buf);
4c521c8e
RH		 371static ssize_t ahci_show_host_cap2(struct device *dev,
372 struct device_attribute *attr, char *buf);
77cdec1a
MG		 373static ssize_t ahci_show_host_version(struct device *dev,
374 struct device_attribute *attr, char *buf);
375static ssize_t ahci_show_port_cmd(struct device *dev,
376 struct device_attribute *attr, char *buf);
377
378DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
4c521c8e 379DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
77cdec1a
MG		 380DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
381DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
382
ee959b00
TJ		 383static struct device_attribute *ahci_shost_attrs[] = {
384 &dev_attr_link_power_management_policy,
18f7ba4c
KCA		 385 &dev_attr_em_message_type,
386 &dev_attr_em_message,
77cdec1a 387 &dev_attr_ahci_host_caps,
4c521c8e 388 &dev_attr_ahci_host_cap2,
77cdec1a
MG		 389 &dev_attr_ahci_host_version,
390 &dev_attr_ahci_port_cmd,
18f7ba4c
KCA		 391 NULL
392};
393
394static struct device_attribute *ahci_sdev_attrs[] = {
395 &dev_attr_sw_activity,
45fabbb7 396 &dev_attr_unload_heads,
31556594
KCA		 397 NULL
398};
399
193515d5 400static struct scsi_host_template ahci_sht = {
68d1d07b 401 ATA_NCQ_SHT(DRV_NAME),
12fad3f9 402 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4 403 .sg_tablesize = AHCI_MAX_SG,
1da177e4 404 .dma_boundary = AHCI_DMA_BOUNDARY,
31556594 405 .shost_attrs = ahci_shost_attrs,
18f7ba4c 406 .sdev_attrs = ahci_sdev_attrs,
1da177e4
LT		 407};
408
029cfd6b
TH		 409static struct ata_port_operations ahci_ops = {
410 .inherits = &sata_pmp_port_ops,
411
d6ef3153 412 .qc_defer = ahci_pmp_qc_defer,
1da177e4
LT		 413 .qc_prep = ahci_qc_prep,
414 .qc_issue = ahci_qc_issue,
4c9bf4e7 415 .qc_fill_rtf = ahci_qc_fill_rtf,
1da177e4 416
78cd52d0
TH		 417 .freeze = ahci_freeze,
418 .thaw = ahci_thaw,
a1efdaba
TH		 419 .softreset = ahci_softreset,
420 .hardreset = ahci_hardreset,
421 .postreset = ahci_postreset,
071f44b1 422 .pmp_softreset = ahci_softreset,
78cd52d0
TH		 423 .error_handler = ahci_error_handler,
424 .post_internal_cmd = ahci_post_internal_cmd,
6bd99b4e
TH		 425 .dev_config = ahci_dev_config,
426
ad616ffb
TH		 427 .scr_read = ahci_scr_read,
428 .scr_write = ahci_scr_write,
7d50b60b
TH		 429 .pmp_attach = ahci_pmp_attach,
430 .pmp_detach = ahci_pmp_detach,
7d50b60b 431
029cfd6b
TH		 432 .enable_pm = ahci_enable_alpm,
433 .disable_pm = ahci_disable_alpm,
18f7ba4c
KCA		 434 .em_show = ahci_led_show,
435 .em_store = ahci_led_store,
436 .sw_activity_show = ahci_activity_show,
437 .sw_activity_store = ahci_activity_store,
438ac6d5 438#ifdef CONFIG_PM
ad616ffb
TH		 439 .port_suspend = ahci_port_suspend,
440 .port_resume = ahci_port_resume,
438ac6d5 441#endif
ad616ffb
TH		 442 .port_start = ahci_port_start,
443 .port_stop = ahci_port_stop,
444};
445
029cfd6b
TH		 446static struct ata_port_operations ahci_vt8251_ops = {
447 .inherits = &ahci_ops,
a1efdaba 448 .hardreset = ahci_vt8251_hardreset,
029cfd6b 449};
edc93052 450
029cfd6b
TH		 451static struct ata_port_operations ahci_p5wdh_ops = {
452 .inherits = &ahci_ops,
a1efdaba 453 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 454};
455
bd17243a
SH		 456static struct ata_port_operations ahci_sb600_ops = {
457 .inherits = &ahci_ops,
458 .softreset = ahci_sb600_softreset,
459 .pmp_softreset = ahci_sb600_softreset,
460};
461
417a1a6d
TH		 462#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
463
98ac62de 464static const struct ata_port_info ahci_port_info[] = {
4da646b7 465 [board_ahci] =
1da177e4 466 {
1188c0d8 467 .flags = AHCI_FLAG_COMMON,
14bdef98 468 .pio_mask = ATA_PIO4,
469248ab 469 .udma_mask = ATA_UDMA6,
1da177e4
LT		 470 .port_ops = &ahci_ops,
471 },
4da646b7 472 [board_ahci_vt8251] =
bf2af2a2 473 {
6949b914 474 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 475 .flags = AHCI_FLAG_COMMON,
14bdef98 476 .pio_mask = ATA_PIO4,
469248ab 477 .udma_mask = ATA_UDMA6,
ad616ffb 478 .port_ops = &ahci_vt8251_ops,
bf2af2a2 479 },
4da646b7 480 [board_ahci_ign_iferr] =
41669553 481 {
417a1a6d
TH		 482 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
483 .flags = AHCI_FLAG_COMMON,
14bdef98 484 .pio_mask = ATA_PIO4,
469248ab 485 .udma_mask = ATA_UDMA6,
41669553
TH		 486 .port_ops = &ahci_ops,
487 },
4da646b7 488 [board_ahci_sb600] =
55a61604 489 {
417a1a6d 490 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
2fcad9d2
TH		 491 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
492 AHCI_HFLAG_32BIT_ONLY),
417a1a6d 493 .flags = AHCI_FLAG_COMMON,
14bdef98 494 .pio_mask = ATA_PIO4,
469248ab 495 .udma_mask = ATA_UDMA6,
bd17243a 496 .port_ops = &ahci_sb600_ops,
55a61604 497 },
4da646b7 498 [board_ahci_mv] =
cd70c266 499 {
417a1a6d 500 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 501 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
cd70c266 502 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 503 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
14bdef98 504 .pio_mask = ATA_PIO4,
cd70c266
JG		 505 .udma_mask = ATA_UDMA6,
506 .port_ops = &ahci_ops,
507 },
4da646b7 508 [board_ahci_sb700] = /* for SB700 and SB800 */
e39fc8c9 509 {
bd17243a 510 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
e39fc8c9 511 .flags = AHCI_FLAG_COMMON,
14bdef98 512 .pio_mask = ATA_PIO4,
e39fc8c9 513 .udma_mask = ATA_UDMA6,
bd17243a 514 .port_ops = &ahci_sb600_ops,
e39fc8c9 515 },
4da646b7 516 [board_ahci_mcp65] =
e297d99e
TH		 517 {
518 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
519 .flags = AHCI_FLAG_COMMON,
14bdef98 520 .pio_mask = ATA_PIO4,
e297d99e
TH		 521 .udma_mask = ATA_UDMA6,
522 .port_ops = &ahci_ops,
523 },
4da646b7 524 [board_ahci_nopmp] =
9a3b103c
TH		 525 {
526 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
527 .flags = AHCI_FLAG_COMMON,
14bdef98 528 .pio_mask = ATA_PIO4,
9a3b103c
TH		 529 .udma_mask = ATA_UDMA6,
530 .port_ops = &ahci_ops,
531 },
1b677afd 532 [board_ahci_yesncq] =
aa431dd3
TH		 533 {
534 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
535 .flags = AHCI_FLAG_COMMON,
536 .pio_mask = ATA_PIO4,
537 .udma_mask = ATA_UDMA6,
538 .port_ops = &ahci_ops,
539 },
1b677afd
SL		 540 [board_ahci_nosntf] =
541 {
542 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
543 .flags = AHCI_FLAG_COMMON,
544 .pio_mask = ATA_PIO4,
545 .udma_mask = ATA_UDMA6,
546 .port_ops = &ahci_ops,
547 },
1da177e4
LT		 548};
549
3b7d697d 550static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 551 /* Intel */
54bb3a94
JG		 552 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
553 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
554 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
555 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
556 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 557 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 558 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
559 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
560 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
561 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 562 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 563 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 564 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
565 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
566 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
567 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
568 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
569 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
570 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
571 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
572 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
573 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
574 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
575 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
576 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
577 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
578 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 579 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
580 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 581 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 582 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 583 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 584 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
585 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 586 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 587 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 588 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 589 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 590 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 591 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
fe7fa31a 592
e34bb370
TH		 593 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
594 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
595 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 596
597 /* ATI */
c65ec1c2 598 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 599 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
600 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
601 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
602 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
603 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
604 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 605
e2dd90b1 606 /* AMD */
5deab536 607 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 608 /* AMD is using RAID class only for ahci controllers */
609 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
610 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
611
fe7fa31a 612 /* VIA */
54bb3a94 613 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 614 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 615
616 /* NVIDIA */
e297d99e
TH		 617 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
618 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
619 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
620 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
621 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
622 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
623 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
624 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
aa431dd3
TH		 625 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
626 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
627 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
628 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
629 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
630 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
631 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
632 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
633 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
634 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
635 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
636 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
726206f8 637 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_yesncq }, /* Linux ID */
aa431dd3
TH		 638 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
639 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
640 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
641 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
642 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
643 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
644 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
645 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
646 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
647 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
648 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
649 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
0522b286
PC		 650 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
651 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
652 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
653 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
654 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
655 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
656 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
657 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
658 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
659 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
660 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
661 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 662 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
663 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
664 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
665 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 666 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
667 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
668 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
669 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
670 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
671 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
672 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
673 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
7adbe46b 674 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
675 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
676 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
677 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
678 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
679 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
680 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
681 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
682 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
683 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
684 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
685 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
fe7fa31a 686
95916edd 687 /* SiS */
20e2de4a
TH		 688 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
689 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
690 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 691
cd70c266
JG		 692 /* Marvell */
693 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 694 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 695
c77a036b
MN		 696 /* Promise */
697 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
698
415ae2b5
JG		 699 /* Generic, PCI class code for AHCI */
700 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 701 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 702
1da177e4
LT		 703 { } /* terminate list */
704};
705
706
707static struct pci_driver ahci_pci_driver = {
708 .name = DRV_NAME,
709 .id_table = ahci_pci_tbl,
710 .probe = ahci_init_one,
24dc5f33 711 .remove = ata_pci_remove_one,
438ac6d5 712#ifdef CONFIG_PM
c1332875
TH		 713 .suspend = ahci_pci_device_suspend,
714 .resume = ahci_pci_device_resume,
438ac6d5 715#endif
1da177e4
LT		 716};
717
18f7ba4c
KCA		 718static int ahci_em_messages = 1;
719module_param(ahci_em_messages, int, 0444);
720/* add other LED protocol types when they become supported */
721MODULE_PARM_DESC(ahci_em_messages,
722 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
1da177e4 723
5b66c829
AC		 724#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
725static int marvell_enable;
726#else
727static int marvell_enable = 1;
728#endif
729module_param(marvell_enable, int, 0644);
730MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
731
732
98fa4b60
TH		 733static inline int ahci_nr_ports(u32 cap)
734{
735 return (cap & 0x1f) + 1;
736}
737
dab632e8
JG		 738static inline void __iomem *__ahci_port_base(struct ata_host *host,
739 unsigned int port_no)
1da177e4 740{
dab632e8 741 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 742
dab632e8
JG		 743 return mmio + 0x100 + (port_no * 0x80);
744}
745
746static inline void __iomem *ahci_port_base(struct ata_port *ap)
747{
748 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 749}
750
b710a1f4
TH		 751static void ahci_enable_ahci(void __iomem *mmio)
752{
15fe982e 753 int i;
b710a1f4
TH		 754 u32 tmp;
755
756 /* turn on AHCI_EN */
757 tmp = readl(mmio + HOST_CTL);
15fe982e
TH		 758 if (tmp & HOST_AHCI_EN)
759 return;
760
761 /* Some controllers need AHCI_EN to be written multiple times.
762 * Try a few times before giving up.
763 */
764 for (i = 0; i < 5; i++) {
b710a1f4
TH		 765 tmp |= HOST_AHCI_EN;
766 writel(tmp, mmio + HOST_CTL);
767 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
15fe982e
TH		 768 if (tmp & HOST_AHCI_EN)
769 return;
770 msleep(10);
b710a1f4 771 }
15fe982e
TH		 772
773 WARN_ON(1);
b710a1f4
TH		 774}
775
77cdec1a
MG		 776static ssize_t ahci_show_host_caps(struct device *dev,
777 struct device_attribute *attr, char *buf)
778{
779 struct Scsi_Host *shost = class_to_shost(dev);
780 struct ata_port *ap = ata_shost_to_port(shost);
781 struct ahci_host_priv *hpriv = ap->host->private_data;
782
783 return sprintf(buf, "%x\n", hpriv->cap);
784}
785
4c521c8e
RH		 786static ssize_t ahci_show_host_cap2(struct device *dev,
787 struct device_attribute *attr, char *buf)
788{
789 struct Scsi_Host *shost = class_to_shost(dev);
790 struct ata_port *ap = ata_shost_to_port(shost);
791 struct ahci_host_priv *hpriv = ap->host->private_data;
792
793 return sprintf(buf, "%x\n", hpriv->cap2);
794}
795
77cdec1a
MG		 796static ssize_t ahci_show_host_version(struct device *dev,
797 struct device_attribute *attr, char *buf)
798{
799 struct Scsi_Host *shost = class_to_shost(dev);
800 struct ata_port *ap = ata_shost_to_port(shost);
801 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
802
803 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
804}
805
806static ssize_t ahci_show_port_cmd(struct device *dev,
807 struct device_attribute *attr, char *buf)
808{
809 struct Scsi_Host *shost = class_to_shost(dev);
810 struct ata_port *ap = ata_shost_to_port(shost);
811 void __iomem *port_mmio = ahci_port_base(ap);
812
813 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
814}
815
d447df14
TH		 816/**
817 * ahci_save_initial_config - Save and fixup initial config values
4447d351 818 * @pdev: target PCI device
4447d351 819 * @hpriv: host private area to store config values
d447df14
TH		 820 *
821 * Some registers containing configuration info might be setup by
822 * BIOS and might be cleared on reset. This function saves the
823 * initial values of those registers into @hpriv such that they
824 * can be restored after controller reset.
825 *
826 * If inconsistent, config values are fixed up by this function.
827 *
828 * LOCKING:
829 * None.
830 */
4447d351 831static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 832 struct ahci_host_priv *hpriv)
d447df14 833{
4447d351 834 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
4c521c8e 835 u32 cap, cap2, vers, port_map;
17199b18 836 int i;
c40e7cb8 837 int mv;
d447df14 838
b710a1f4
TH		 839 /* make sure AHCI mode is enabled before accessing CAP */
840 ahci_enable_ahci(mmio);
841
d447df14
TH		 842 /* Values prefixed with saved_ are written back to host after
843 * reset. Values without are used for driver operation.
844 */
845 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
846 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
847
4c521c8e
RH		 848 /* CAP2 register is only defined for AHCI 1.2 and later */
849 vers = readl(mmio + HOST_VERSION);
850 if ((vers >> 16) > 1 ||
851 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
852 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
853 else
854 hpriv->saved_cap2 = cap2 = 0;
855
274c1fde 856 /* some chips have errata preventing 64bit use */
417a1a6d 857 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 858 dev_printk(KERN_INFO, &pdev->dev,
859 "controller can't do 64bit DMA, forcing 32bit\n");
860 cap &= ~HOST_CAP_64;
861 }
862
417a1a6d 863 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 864 dev_printk(KERN_INFO, &pdev->dev,
865 "controller can't do NCQ, turning off CAP_NCQ\n");
866 cap &= ~HOST_CAP_NCQ;
867 }
868
e297d99e
TH		 869 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
870 dev_printk(KERN_INFO, &pdev->dev,
871 "controller can do NCQ, turning on CAP_NCQ\n");
872 cap |= HOST_CAP_NCQ;
873 }
874
258cd846 875 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
6949b914
TH		 876 dev_printk(KERN_INFO, &pdev->dev,
877 "controller can't do PMP, turning off CAP_PMP\n");
878 cap &= ~HOST_CAP_PMP;
879 }
880
1b677afd
SL		 881 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
882 dev_printk(KERN_INFO, &pdev->dev,
883 "controller can't do SNTF, turning off CAP_SNTF\n");
884 cap &= ~HOST_CAP_SNTF;
885 }
886
d799e083
TH		 887 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
888 port_map != 1) {
889 dev_printk(KERN_INFO, &pdev->dev,
890 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
891 port_map, 1);
892 port_map = 1;
893 }
894
cd70c266
JG		 895 /*
896 * Temporary Marvell 6145 hack: PATA port presence
897 * is asserted through the standard AHCI port
898 * presence register, as bit 4 (counting from 0)
899 */
417a1a6d 900 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 901 if (pdev->device == 0x6121)
902 mv = 0x3;
903 else
904 mv = 0xf;
cd70c266
JG		 905 dev_printk(KERN_ERR, &pdev->dev,
906 "MV_AHCI HACK: port_map %x -> %x\n",
c40e7cb8
JAR		 907 port_map,
908 port_map & mv);
5b66c829
AC		 909 dev_printk(KERN_ERR, &pdev->dev,
910 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
cd70c266 911
c40e7cb8 912 port_map &= mv;
cd70c266
JG		 913 }
914
17199b18 915 /* cross check port_map and cap.n_ports */
7a234aff 916 if (port_map) {
837f5f8f 917 int map_ports = 0;
17199b18 918
837f5f8f
TH		 919 for (i = 0; i < AHCI_MAX_PORTS; i++)
920 if (port_map & (1 << i))
921 map_ports++;
17199b18 922
837f5f8f
TH		 923 /* If PI has more ports than n_ports, whine, clear
924 * port_map and let it be generated from n_ports.
17199b18 925 */
837f5f8f 926 if (map_ports > ahci_nr_ports(cap)) {
4447d351 927 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 928 "implemented port map (0x%x) contains more "
929 "ports than nr_ports (%u), using nr_ports\n",
930 port_map, ahci_nr_ports(cap));
7a234aff
TH		 931 port_map = 0;
932 }
933 }
934
935 /* fabricate port_map from cap.nr_ports */
936 if (!port_map) {
17199b18 937 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 938 dev_printk(KERN_WARNING, &pdev->dev,
939 "forcing PORTS_IMPL to 0x%x\n", port_map);
940
941 /* write the fixed up value to the PI register */
942 hpriv->saved_port_map = port_map;
17199b18
TH		 943 }
944
d447df14
TH		 945 /* record values to use during operation */
946 hpriv->cap = cap;
4c521c8e 947 hpriv->cap2 = cap2;
d447df14
TH		 948 hpriv->port_map = port_map;
949}
950
951/**
952 * ahci_restore_initial_config - Restore initial config
4447d351 953 * @host: target ATA host
d447df14
TH		 954 *
955 * Restore initial config stored by ahci_save_initial_config().
956 *
957 * LOCKING:
958 * None.
959 */
4447d351 960static void ahci_restore_initial_config(struct ata_host *host)
d447df14 961{
4447d351
TH		 962 struct ahci_host_priv *hpriv = host->private_data;
963 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
964
d447df14 965 writel(hpriv->saved_cap, mmio + HOST_CAP);
4c521c8e
RH		 966 if (hpriv->saved_cap2)
967 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
d447df14
TH		 968 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
969 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
970}
971
203ef6c4 972static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 973{
203ef6c4
TH		 974 static const int offset[] = {
975 [SCR_STATUS] = PORT_SCR_STAT,
976 [SCR_CONTROL] = PORT_SCR_CTL,
977 [SCR_ERROR] = PORT_SCR_ERR,
978 [SCR_ACTIVE] = PORT_SCR_ACT,
979 [SCR_NOTIFICATION] = PORT_SCR_NTF,
980 };
981 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 982
203ef6c4
TH		 983 if (sc_reg < ARRAY_SIZE(offset) &&
984 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
985 return offset[sc_reg];
da3dbb17 986 return 0;
1da177e4
LT		 987}
988
82ef04fb 989static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
1da177e4 990{
82ef04fb
TH		 991 void __iomem *port_mmio = ahci_port_base(link->ap);
992 int offset = ahci_scr_offset(link->ap, sc_reg);
203ef6c4
TH		 993
994 if (offset) {
995 *val = readl(port_mmio + offset);
996 return 0;
1da177e4 997 }
203ef6c4
TH		 998 return -EINVAL;
999}
1da177e4 1000
82ef04fb 1001static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
203ef6c4 1002{
82ef04fb
TH		 1003 void __iomem *port_mmio = ahci_port_base(link->ap);
1004 int offset = ahci_scr_offset(link->ap, sc_reg);
203ef6c4
TH		 1005
1006 if (offset) {
1007 writel(val, port_mmio + offset);
1008 return 0;
1009 }
1010 return -EINVAL;
1da177e4
LT		 1011}
1012
4447d351 1013static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 1014{
4447d351 1015 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 1016 u32 tmp;
1017
d8fcd116 1018 /* start DMA */
9f592056 1019 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 1020 tmp |= PORT_CMD_START;
1021 writel(tmp, port_mmio + PORT_CMD);
1022 readl(port_mmio + PORT_CMD); /* flush */
1023}
1024
4447d351 1025static int ahci_stop_engine(struct ata_port *ap)
254950cd 1026{
4447d351 1027 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 1028 u32 tmp;
1029
1030 tmp = readl(port_mmio + PORT_CMD);
1031
d8fcd116 1032 /* check if the HBA is idle */
254950cd
TH		 1033 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
1034 return 0;
1035
d8fcd116 1036 /* setting HBA to idle */
254950cd
TH		 1037 tmp &= ~PORT_CMD_START;
1038 writel(tmp, port_mmio + PORT_CMD);
1039
d8fcd116 1040 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 1041 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 1042 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 1043 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 1044 return -EIO;
1045
1046 return 0;
1047}
1048
4447d351 1049static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 1050{
4447d351
TH		 1051 void __iomem *port_mmio = ahci_port_base(ap);
1052 struct ahci_host_priv *hpriv = ap->host->private_data;
1053 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 1054 u32 tmp;
1055
1056 /* set FIS registers */
4447d351
TH		 1057 if (hpriv->cap & HOST_CAP_64)
1058 writel((pp->cmd_slot_dma >> 16) >> 16,
1059 port_mmio + PORT_LST_ADDR_HI);
1060 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 1061
4447d351
TH		 1062 if (hpriv->cap & HOST_CAP_64)
1063 writel((pp->rx_fis_dma >> 16) >> 16,
1064 port_mmio + PORT_FIS_ADDR_HI);
1065 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 1066
1067 /* enable FIS reception */
1068 tmp = readl(port_mmio + PORT_CMD);
1069 tmp |= PORT_CMD_FIS_RX;
1070 writel(tmp, port_mmio + PORT_CMD);
1071
1072 /* flush */
1073 readl(port_mmio + PORT_CMD);
1074}
1075
4447d351 1076static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 1077{
4447d351 1078 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1079 u32 tmp;
1080
1081 /* disable FIS reception */
1082 tmp = readl(port_mmio + PORT_CMD);
1083 tmp &= ~PORT_CMD_FIS_RX;
1084 writel(tmp, port_mmio + PORT_CMD);
1085
1086 /* wait for completion, spec says 500ms, give it 1000 */
1087 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
1088 PORT_CMD_FIS_ON, 10, 1000);
1089 if (tmp & PORT_CMD_FIS_ON)
1090 return -EBUSY;
1091
1092 return 0;
1093}
1094
4447d351 1095static void ahci_power_up(struct ata_port *ap)
0be0aa98 1096{
4447d351
TH		 1097 struct ahci_host_priv *hpriv = ap->host->private_data;
1098 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1099 u32 cmd;
1100
1101 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1102
1103 /* spin up device */
4447d351 1104 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 1105 cmd |= PORT_CMD_SPIN_UP;
1106 writel(cmd, port_mmio + PORT_CMD);
1107 }
1108
1109 /* wake up link */
1110 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
1111}
1112
31556594
KCA		 1113static void ahci_disable_alpm(struct ata_port *ap)
1114{
1115 struct ahci_host_priv *hpriv = ap->host->private_data;
1116 void __iomem *port_mmio = ahci_port_base(ap);
1117 u32 cmd;
1118 struct ahci_port_priv *pp = ap->private_data;
1119
1120 /* IPM bits should be disabled by libata-core */
1121 /* get the existing command bits */
1122 cmd = readl(port_mmio + PORT_CMD);
1123
1124 /* disable ALPM and ASP */
1125 cmd &= ~PORT_CMD_ASP;
1126 cmd &= ~PORT_CMD_ALPE;
1127
1128 /* force the interface back to active */
1129 cmd |= PORT_CMD_ICC_ACTIVE;
1130
1131 /* write out new cmd value */
1132 writel(cmd, port_mmio + PORT_CMD);
1133 cmd = readl(port_mmio + PORT_CMD);
1134
1135 /* wait 10ms to be sure we've come out of any low power state */
1136 msleep(10);
1137
1138 /* clear out any PhyRdy stuff from interrupt status */
1139 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1140
1141 /* go ahead and clean out PhyRdy Change from Serror too */
82ef04fb 1142 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
31556594
KCA		 1143
1144 /*
1145 * Clear flag to indicate that we should ignore all PhyRdy
1146 * state changes
1147 */
1148 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1149
1150 /*
1151 * Enable interrupts on Phy Ready.
1152 */
1153 pp->intr_mask |= PORT_IRQ_PHYRDY;
1154 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1155
1156 /*
1157 * don't change the link pm policy - we can be called
1158 * just to turn of link pm temporarily
1159 */
1160}
1161
1162static int ahci_enable_alpm(struct ata_port *ap,
1163 enum link_pm policy)
1164{
1165 struct ahci_host_priv *hpriv = ap->host->private_data;
1166 void __iomem *port_mmio = ahci_port_base(ap);
1167 u32 cmd;
1168 struct ahci_port_priv *pp = ap->private_data;
1169 u32 asp;
1170
1171 /* Make sure the host is capable of link power management */
1172 if (!(hpriv->cap & HOST_CAP_ALPM))
1173 return -EINVAL;
1174
1175 switch (policy) {
1176 case MAX_PERFORMANCE:
1177 case NOT_AVAILABLE:
1178 /*
1179 * if we came here with NOT_AVAILABLE,
1180 * it just means this is the first time we
1181 * have tried to enable - default to max performance,
1182 * and let the user go to lower power modes on request.
1183 */
1184 ahci_disable_alpm(ap);
1185 return 0;
1186 case MIN_POWER:
1187 /* configure HBA to enter SLUMBER */
1188 asp = PORT_CMD_ASP;
1189 break;
1190 case MEDIUM_POWER:
1191 /* configure HBA to enter PARTIAL */
1192 asp = 0;
1193 break;
1194 default:
1195 return -EINVAL;
1196 }
1197
1198 /*
1199 * Disable interrupts on Phy Ready. This keeps us from
1200 * getting woken up due to spurious phy ready interrupts
1201 * TBD - Hot plug should be done via polling now, is
1202 * that even supported?
1203 */
1204 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1205 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1206
1207 /*
1208 * Set a flag to indicate that we should ignore all PhyRdy
1209 * state changes since these can happen now whenever we
1210 * change link state
1211 */
1212 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1213
1214 /* get the existing command bits */
1215 cmd = readl(port_mmio + PORT_CMD);
1216
1217 /*
1218 * Set ASP based on Policy
1219 */
1220 cmd |= asp;
1221
1222 /*
1223 * Setting this bit will instruct the HBA to aggressively
1224 * enter a lower power link state when it's appropriate and
1225 * based on the value set above for ASP
1226 */
1227 cmd |= PORT_CMD_ALPE;
1228
1229 /* write out new cmd value */
1230 writel(cmd, port_mmio + PORT_CMD);
1231 cmd = readl(port_mmio + PORT_CMD);
1232
1233 /* IPM bits should be set by libata-core */
1234 return 0;
1235}
1236
438ac6d5 1237#ifdef CONFIG_PM
4447d351 1238static void ahci_power_down(struct ata_port *ap)
0be0aa98 1239{
4447d351
TH		 1240 struct ahci_host_priv *hpriv = ap->host->private_data;
1241 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1242 u32 cmd, scontrol;
1243
4447d351 1244 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1245 return;
0be0aa98 1246
07c53dac
TH		 1247 /* put device into listen mode, first set PxSCTL.DET to 0 */
1248 scontrol = readl(port_mmio + PORT_SCR_CTL);
1249 scontrol &= ~0xf;
1250 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1251
07c53dac
TH		 1252 /* then set PxCMD.SUD to 0 */
1253 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1254 cmd &= ~PORT_CMD_SPIN_UP;
1255 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1256}
438ac6d5 1257#endif
0be0aa98 1258
df69c9c5 1259static void ahci_start_port(struct ata_port *ap)
0be0aa98 1260{
18f7ba4c
KCA		 1261 struct ahci_port_priv *pp = ap->private_data;
1262 struct ata_link *link;
1263 struct ahci_em_priv *emp;
4c1e9aa4
DM		 1264 ssize_t rc;
1265 int i;
18f7ba4c 1266
0be0aa98 1267 /* enable FIS reception */
4447d351 1268 ahci_start_fis_rx(ap);
0be0aa98
TH		 1269
1270 /* enable DMA */
4447d351 1271 ahci_start_engine(ap);
18f7ba4c
KCA		 1272
1273 /* turn on LEDs */
1274 if (ap->flags & ATA_FLAG_EM) {
1eca4365 1275 ata_for_each_link(link, ap, EDGE) {
18f7ba4c 1276 emp = &pp->em_priv[link->pmp];
4c1e9aa4
DM		 1277
1278 /* EM Transmit bit maybe busy during init */
d50ce07d 1279 for (i = 0; i < EM_MAX_RETRY; i++) {
4c1e9aa4
DM		 1280 rc = ahci_transmit_led_message(ap,
1281 emp->led_state,
1282 4);
1283 if (rc == -EBUSY)
d50ce07d 1284 msleep(1);
4c1e9aa4
DM		 1285 else
1286 break;
1287 }
18f7ba4c
KCA		 1288 }
1289 }
1290
1291 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1eca4365 1292 ata_for_each_link(link, ap, EDGE)
18f7ba4c
KCA		 1293 ahci_init_sw_activity(link);
1294
0be0aa98
TH		 1295}
1296
4447d351 1297static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1298{
1299 int rc;
1300
1301 /* disable DMA */
4447d351 1302 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1303 if (rc) {
1304 *emsg = "failed to stop engine";
1305 return rc;
1306 }
1307
1308 /* disable FIS reception */
4447d351 1309 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1310 if (rc) {
1311 *emsg = "failed stop FIS RX";
1312 return rc;
1313 }
1314
0be0aa98
TH		 1315 return 0;
1316}
1317
4447d351 1318static int ahci_reset_controller(struct ata_host *host)
d91542c1 1319{
4447d351 1320 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1321 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1322 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1323 u32 tmp;
d91542c1 1324
3cc3eb11
JG		 1325 /* we must be in AHCI mode, before using anything
1326 * AHCI-specific, such as HOST_RESET.
1327 */
b710a1f4 1328 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1329
1330 /* global controller reset */
a22e6444
TH		 1331 if (!ahci_skip_host_reset) {
1332 tmp = readl(mmio + HOST_CTL);
1333 if ((tmp & HOST_RESET) == 0) {
1334 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1335 readl(mmio + HOST_CTL); /* flush */
1336 }
d91542c1 1337
24920c8a
ZR		 1338 /*
1339 * to perform host reset, OS should set HOST_RESET
1340 * and poll until this bit is read to be "0".
1341 * reset must complete within 1 second, or
a22e6444
TH		 1342 * the hardware should be considered fried.
1343 */
24920c8a
ZR		 1344 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1345 HOST_RESET, 10, 1000);
d91542c1 1346
a22e6444
TH		 1347 if (tmp & HOST_RESET) {
1348 dev_printk(KERN_ERR, host->dev,
1349 "controller reset failed (0x%x)\n", tmp);
1350 return -EIO;
1351 }
d91542c1 1352
a22e6444
TH		 1353 /* turn on AHCI mode */
1354 ahci_enable_ahci(mmio);
98fa4b60 1355
a22e6444
TH		 1356 /* Some registers might be cleared on reset. Restore
1357 * initial values.
1358 */
1359 ahci_restore_initial_config(host);
1360 } else
1361 dev_printk(KERN_INFO, host->dev,
1362 "skipping global host reset\n");
d91542c1
TH		 1363
1364 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1365 u16 tmp16;
1366
1367 /* configure PCS */
1368 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1369 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1370 tmp16 |= hpriv->port_map;
1371 pci_write_config_word(pdev, 0x92, tmp16);
1372 }
d91542c1
TH		 1373 }
1374
1375 return 0;
1376}
1377
18f7ba4c
KCA		 1378static void ahci_sw_activity(struct ata_link *link)
1379{
1380 struct ata_port *ap = link->ap;
1381 struct ahci_port_priv *pp = ap->private_data;
1382 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1383
1384 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1385 return;
1386
1387 emp->activity++;
1388 if (!timer_pending(&emp->timer))
1389 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1390}
1391
1392static void ahci_sw_activity_blink(unsigned long arg)
1393{
1394 struct ata_link *link = (struct ata_link *)arg;
1395 struct ata_port *ap = link->ap;
1396 struct ahci_port_priv *pp = ap->private_data;
1397 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1398 unsigned long led_message = emp->led_state;
1399 u32 activity_led_state;
eb40963c 1400 unsigned long flags;
18f7ba4c 1401
87943acf 1402 led_message &= EM_MSG_LED_VALUE;
18f7ba4c
KCA		 1403 led_message |= ap->port_no | (link->pmp << 8);
1404
1405 /* check to see if we've had activity. If so,
1406 * toggle state of LED and reset timer. If not,
1407 * turn LED to desired idle state.
1408 */
eb40963c 1409 spin_lock_irqsave(ap->lock, flags);
18f7ba4c
KCA		 1410 if (emp->saved_activity != emp->activity) {
1411 emp->saved_activity = emp->activity;
1412 /* get the current LED state */
87943acf 1413 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
18f7ba4c
KCA		 1414
1415 if (activity_led_state)
1416 activity_led_state = 0;
1417 else
1418 activity_led_state = 1;
1419
1420 /* clear old state */
87943acf 1421 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
18f7ba4c
KCA		 1422
1423 /* toggle state */
1424 led_message |= (activity_led_state << 16);
1425 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1426 } else {
1427 /* switch to idle */
87943acf 1428 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
18f7ba4c
KCA		 1429 if (emp->blink_policy == BLINK_OFF)
1430 led_message |= (1 << 16);
1431 }
eb40963c 1432 spin_unlock_irqrestore(ap->lock, flags);
18f7ba4c
KCA		 1433 ahci_transmit_led_message(ap, led_message, 4);
1434}
1435
1436static void ahci_init_sw_activity(struct ata_link *link)
1437{
1438 struct ata_port *ap = link->ap;
1439 struct ahci_port_priv *pp = ap->private_data;
1440 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1441
1442 /* init activity stats, setup timer */
1443 emp->saved_activity = emp->activity = 0;
1444 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1445
1446 /* check our blink policy and set flag for link if it's enabled */
1447 if (emp->blink_policy)
1448 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1449}
1450
1451static int ahci_reset_em(struct ata_host *host)
1452{
1453 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1454 u32 em_ctl;
1455
1456 em_ctl = readl(mmio + HOST_EM_CTL);
1457 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1458 return -EINVAL;
1459
1460 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1461 return 0;
1462}
1463
1464static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1465 ssize_t size)
1466{
1467 struct ahci_host_priv *hpriv = ap->host->private_data;
1468 struct ahci_port_priv *pp = ap->private_data;
1469 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1470 u32 em_ctl;
1471 u32 message[] = {0, 0};
93082f0b 1472 unsigned long flags;
18f7ba4c
KCA		 1473 int pmp;
1474 struct ahci_em_priv *emp;
1475
1476 /* get the slot number from the message */
87943acf 1477 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
d50ce07d 1478 if (pmp < EM_MAX_SLOTS)
18f7ba4c
KCA		 1479 emp = &pp->em_priv[pmp];
1480 else
1481 return -EINVAL;
1482
1483 spin_lock_irqsave(ap->lock, flags);
1484
1485 /*
1486 * if we are still busy transmitting a previous message,
1487 * do not allow
1488 */
1489 em_ctl = readl(mmio + HOST_EM_CTL);
1490 if (em_ctl & EM_CTL_TM) {
1491 spin_unlock_irqrestore(ap->lock, flags);
4c1e9aa4 1492 return -EBUSY;
18f7ba4c
KCA		 1493 }
1494
1495 /*
1496 * create message header - this is all zero except for
1497 * the message size, which is 4 bytes.
1498 */
1499 message[0] |= (4 << 8);
1500
1501 /* ignore 0:4 of byte zero, fill in port info yourself */
87943acf 1502 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
18f7ba4c
KCA		 1503
1504 /* write message to EM_LOC */
1505 writel(message[0], mmio + hpriv->em_loc);
1506 writel(message[1], mmio + hpriv->em_loc+4);
1507
1508 /* save off new led state for port/slot */
208f2a88 1509 emp->led_state = state;
18f7ba4c
KCA		 1510
1511 /*
1512 * tell hardware to transmit the message
1513 */
1514 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1515
1516 spin_unlock_irqrestore(ap->lock, flags);
1517 return size;
1518}
1519
1520static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1521{
1522 struct ahci_port_priv *pp = ap->private_data;
1523 struct ata_link *link;
1524 struct ahci_em_priv *emp;
1525 int rc = 0;
1526
1eca4365 1527 ata_for_each_link(link, ap, EDGE) {
18f7ba4c
KCA		 1528 emp = &pp->em_priv[link->pmp];
1529 rc += sprintf(buf, "%lx\n", emp->led_state);
1530 }
1531 return rc;
1532}
1533
1534static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1535 size_t size)
1536{
1537 int state;
1538 int pmp;
1539 struct ahci_port_priv *pp = ap->private_data;
1540 struct ahci_em_priv *emp;
1541
1542 state = simple_strtoul(buf, NULL, 0);
1543
1544 /* get the slot number from the message */
87943acf 1545 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
d50ce07d 1546 if (pmp < EM_MAX_SLOTS)
18f7ba4c
KCA		 1547 emp = &pp->em_priv[pmp];
1548 else
1549 return -EINVAL;
1550
1551 /* mask off the activity bits if we are in sw_activity
1552 * mode, user should turn off sw_activity before setting
1553 * activity led through em_message
1554 */
1555 if (emp->blink_policy)
87943acf 1556 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
18f7ba4c
KCA		 1557
1558 return ahci_transmit_led_message(ap, state, size);
1559}
1560
1561static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1562{
1563 struct ata_link *link = dev->link;
1564 struct ata_port *ap = link->ap;
1565 struct ahci_port_priv *pp = ap->private_data;
1566 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1567 u32 port_led_state = emp->led_state;
1568
1569 /* save the desired Activity LED behavior */
1570 if (val == OFF) {
1571 /* clear LFLAG */
1572 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1573
1574 /* set the LED to OFF */
87943acf 1575 port_led_state &= EM_MSG_LED_VALUE_OFF;
18f7ba4c
KCA		 1576 port_led_state |= (ap->port_no | (link->pmp << 8));
1577 ahci_transmit_led_message(ap, port_led_state, 4);
1578 } else {
1579 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1580 if (val == BLINK_OFF) {
1581 /* set LED to ON for idle */
87943acf 1582 port_led_state &= EM_MSG_LED_VALUE_OFF;
18f7ba4c 1583 port_led_state |= (ap->port_no | (link->pmp << 8));
87943acf 1584 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
18f7ba4c
KCA		 1585 ahci_transmit_led_message(ap, port_led_state, 4);
1586 }
1587 }
1588 emp->blink_policy = val;
1589 return 0;
1590}
1591
1592static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1593{
1594 struct ata_link *link = dev->link;
1595 struct ata_port *ap = link->ap;
1596 struct ahci_port_priv *pp = ap->private_data;
1597 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1598
1599 /* display the saved value of activity behavior for this
1600 * disk.
1601 */
1602 return sprintf(buf, "%d\n", emp->blink_policy);
1603}
1604
2bcd866b
JG		 1605static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1606 int port_no, void __iomem *mmio,
1607 void __iomem *port_mmio)
1608{
1609 const char *emsg = NULL;
1610 int rc;
1611 u32 tmp;
1612
1613 /* make sure port is not active */
1614 rc = ahci_deinit_port(ap, &emsg);
1615 if (rc)
1616 dev_printk(KERN_WARNING, &pdev->dev,
1617 "%s (%d)\n", emsg, rc);
1618
1619 /* clear SError */
1620 tmp = readl(port_mmio + PORT_SCR_ERR);
1621 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1622 writel(tmp, port_mmio + PORT_SCR_ERR);
1623
1624 /* clear port IRQ */
1625 tmp = readl(port_mmio + PORT_IRQ_STAT);
1626 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1627 if (tmp)
1628 writel(tmp, port_mmio + PORT_IRQ_STAT);
1629
1630 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1631}
1632
4447d351 1633static void ahci_init_controller(struct ata_host *host)
d91542c1 1634{
417a1a6d 1635 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1636 struct pci_dev *pdev = to_pci_dev(host->dev);
1637 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1638 int i;
cd70c266 1639 void __iomem *port_mmio;
d91542c1 1640 u32 tmp;
c40e7cb8 1641 int mv;
d91542c1 1642
417a1a6d 1643 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 1644 if (pdev->device == 0x6121)
1645 mv = 2;
1646 else
1647 mv = 4;
1648 port_mmio = __ahci_port_base(host, mv);
cd70c266
JG		 1649
1650 writel(0, port_mmio + PORT_IRQ_MASK);
1651
1652 /* clear port IRQ */
1653 tmp = readl(port_mmio + PORT_IRQ_STAT);
1654 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1655 if (tmp)
1656 writel(tmp, port_mmio + PORT_IRQ_STAT);
1657 }
1658
4447d351
TH		 1659 for (i = 0; i < host->n_ports; i++) {
1660 struct ata_port *ap = host->ports[i];
d91542c1 1661
cd70c266 1662 port_mmio = ahci_port_base(ap);
4447d351 1663 if (ata_port_is_dummy(ap))
d91542c1 1664 continue;
d91542c1 1665
2bcd866b 1666 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1667 }
1668
1669 tmp = readl(mmio + HOST_CTL);
1670 VPRINTK("HOST_CTL 0x%x\n", tmp);
1671 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1672 tmp = readl(mmio + HOST_CTL);
1673 VPRINTK("HOST_CTL 0x%x\n", tmp);
1674}
1675
a878539e
JG		 1676static void ahci_dev_config(struct ata_device *dev)
1677{
1678 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1679
4cde32fc 1680 if (hpriv->flags & AHCI_HFLAG_SECT255) {
a878539e 1681 dev->max_sectors = 255;
4cde32fc
JG		 1682 ata_dev_printk(dev, KERN_INFO,
1683 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1684 }
a878539e
JG		 1685}
1686
422b7595 1687static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1688{
4447d351 1689 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1690 struct ata_taskfile tf;
422b7595
TH		 1691 u32 tmp;
1692
1693 tmp = readl(port_mmio + PORT_SIG);
1694 tf.lbah = (tmp >> 24) & 0xff;
1695 tf.lbam = (tmp >> 16) & 0xff;
1696 tf.lbal = (tmp >> 8) & 0xff;
1697 tf.nsect = (tmp) & 0xff;
1698
1699 return ata_dev_classify(&tf);
1700}
1701
12fad3f9
TH		 1702static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1703 u32 opts)
cc9278ed 1704{
12fad3f9
TH		 1705 dma_addr_t cmd_tbl_dma;
1706
1707 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1708
1709 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1710 pp->cmd_slot[tag].status = 0;
1711 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1712 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1713}
1714
78d5ae39 1715static int ahci_kick_engine(struct ata_port *ap)
4658f79b 1716{
350756f6 1717 void __iomem *port_mmio = ahci_port_base(ap);
cca3974e 1718 struct ahci_host_priv *hpriv = ap->host->private_data;
520d06f9 1719 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
bf2af2a2 1720 u32 tmp;
d2e75dff 1721 int busy, rc;
bf2af2a2 1722
d2e75dff
TH		 1723 /* stop engine */
1724 rc = ahci_stop_engine(ap);
1725 if (rc)
1726 goto out_restart;
1727
78d5ae39
SH		 1728 /* need to do CLO?
1729 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1730 */
1731 busy = status & (ATA_BUSY | ATA_DRQ);
1732 if (!busy && !sata_pmp_attached(ap)) {
d2e75dff
TH		 1733 rc = 0;
1734 goto out_restart;
1735 }
1736
1737 if (!(hpriv->cap & HOST_CAP_CLO)) {
1738 rc = -EOPNOTSUPP;
1739 goto out_restart;
1740 }
bf2af2a2 1741
d2e75dff 1742 /* perform CLO */
bf2af2a2
BJ		 1743 tmp = readl(port_mmio + PORT_CMD);
1744 tmp |= PORT_CMD_CLO;
1745 writel(tmp, port_mmio + PORT_CMD);
1746
d2e75dff 1747 rc = 0;
bf2af2a2
BJ		 1748 tmp = ata_wait_register(port_mmio + PORT_CMD,
1749 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1750 if (tmp & PORT_CMD_CLO)
d2e75dff 1751 rc = -EIO;
bf2af2a2 1752
d2e75dff
TH		 1753 /* restart engine */
1754 out_restart:
1755 ahci_start_engine(ap);
1756 return rc;
bf2af2a2
BJ		 1757}
1758
91c4a2e0
TH		 1759static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1760 struct ata_taskfile *tf, int is_cmd, u16 flags,
1761 unsigned long timeout_msec)
bf2af2a2 1762{
91c4a2e0 1763 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1764 struct ahci_port_priv *pp = ap->private_data;
4447d351 1765 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1766 u8 *fis = pp->cmd_tbl;
1767 u32 tmp;
1768
1769 /* prep the command */
1770 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1771 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1772
1773 /* issue & wait */
1774 writel(1, port_mmio + PORT_CMD_ISSUE);
1775
1776 if (timeout_msec) {
1777 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1778 1, timeout_msec);
1779 if (tmp & 0x1) {
78d5ae39 1780 ahci_kick_engine(ap);
91c4a2e0
TH		 1781 return -EBUSY;
1782 }
1783 } else
1784 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1785
1786 return 0;
1787}
1788
bd17243a
SH		 1789static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1790 int pmp, unsigned long deadline,
1791 int (*check_ready)(struct ata_link *link))
91c4a2e0 1792{
cc0680a5 1793 struct ata_port *ap = link->ap;
5594639a 1794 struct ahci_host_priv *hpriv = ap->host->private_data;
4658f79b 1795 const char *reason = NULL;
2cbb79eb 1796 unsigned long now, msecs;
4658f79b 1797 struct ata_taskfile tf;
4658f79b
TH		 1798 int rc;
1799
1800 DPRINTK("ENTER\n");
1801
1802 /* prepare for SRST (AHCI-1.1 10.4.1) */
78d5ae39 1803 rc = ahci_kick_engine(ap);
994056d7 1804 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1805 ata_link_printk(link, KERN_WARNING,
994056d7 1806 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1807
cc0680a5 1808 ata_tf_init(link->device, &tf);
4658f79b
TH		 1809
1810 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1811 msecs = 0;
1812 now = jiffies;
1813 if (time_after(now, deadline))
1814 msecs = jiffies_to_msecs(deadline - now);
1815
4658f79b 1816 tf.ctl |= ATA_SRST;
a9cf5e85 1817 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1818 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1819 rc = -EIO;
1820 reason = "1st FIS failed";
1821 goto fail;
1822 }
1823
1824 /* spec says at least 5us, but be generous and sleep for 1ms */
1825 msleep(1);
1826
1827 /* issue the second D2H Register FIS */
4658f79b 1828 tf.ctl &= ~ATA_SRST;
a9cf5e85 1829 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1830
705e76be 1831 /* wait for link to become ready */
bd17243a 1832 rc = ata_wait_after_reset(link, deadline, check_ready);
5594639a
TH		 1833 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1834 /*
1835 * Workaround for cases where link online status can't
1836 * be trusted. Treat device readiness timeout as link
1837 * offline.
1838 */
1839 ata_link_printk(link, KERN_INFO,
1840 "device not ready, treating as offline\n");
1841 *class = ATA_DEV_NONE;
1842 } else if (rc) {
1843 /* link occupied, -ENODEV too is an error */
9b89391c
TH		 1844 reason = "device not ready";
1845 goto fail;
5594639a
TH		 1846 } else
1847 *class = ahci_dev_classify(ap);
4658f79b
TH		 1848
1849 DPRINTK("EXIT, class=%u\n", *class);
1850 return 0;
1851
4658f79b 1852 fail:
cc0680a5 1853 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1854 return rc;
1855}
1856
bd17243a
SH		 1857static int ahci_check_ready(struct ata_link *link)
1858{
1859 void __iomem *port_mmio = ahci_port_base(link->ap);
1860 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1861
1862 return ata_check_ready(status);
1863}
1864
1865static int ahci_softreset(struct ata_link *link, unsigned int *class,
1866 unsigned long deadline)
1867{
1868 int pmp = sata_srst_pmp(link);
1869
1870 DPRINTK("ENTER\n");
1871
1872 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1873}
1874
1875static int ahci_sb600_check_ready(struct ata_link *link)
1876{
1877 void __iomem *port_mmio = ahci_port_base(link->ap);
1878 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1879 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1880
1881 /*
1882 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1883 * which can save timeout delay.
1884 */
1885 if (irq_status & PORT_IRQ_BAD_PMP)
1886 return -EIO;
1887
1888 return ata_check_ready(status);
1889}
1890
1891static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1892 unsigned long deadline)
1893{
1894 struct ata_port *ap = link->ap;
1895 void __iomem *port_mmio = ahci_port_base(ap);
1896 int pmp = sata_srst_pmp(link);
1897 int rc;
1898 u32 irq_sts;
1899
1900 DPRINTK("ENTER\n");
1901
1902 rc = ahci_do_softreset(link, class, pmp, deadline,
1903 ahci_sb600_check_ready);
1904
1905 /*
1906 * Soft reset fails on some ATI chips with IPMS set when PMP
1907 * is enabled but SATA HDD/ODD is connected to SATA port,
1908 * do soft reset again to port 0.
1909 */
1910 if (rc == -EIO) {
1911 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1912 if (irq_sts & PORT_IRQ_BAD_PMP) {
1913 ata_link_printk(link, KERN_WARNING,
b6931c1f
SH		 1914 "applying SB600 PMP SRST workaround "
1915 "and retrying\n");
bd17243a
SH		 1916 rc = ahci_do_softreset(link, class, 0, deadline,
1917 ahci_check_ready);
1918 }
1919 }
1920
1921 return rc;
1922}
1923
cc0680a5 1924static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1925 unsigned long deadline)
422b7595 1926{
9dadd45b 1927 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
cc0680a5 1928 struct ata_port *ap = link->ap;
4296971d
TH		 1929 struct ahci_port_priv *pp = ap->private_data;
1930 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1931 struct ata_taskfile tf;
9dadd45b 1932 bool online;
4bd00f6a
TH		 1933 int rc;
1934
1935 DPRINTK("ENTER\n");
1da177e4 1936
4447d351 1937 ahci_stop_engine(ap);
4296971d
TH		 1938
1939 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1940 ata_tf_init(link->device, &tf);
dfd7a3db 1941 tf.command = 0x80;
9977126c 1942 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1943
9dadd45b
TH		 1944 rc = sata_link_hardreset(link, timing, deadline, &online,
1945 ahci_check_ready);
4296971d 1946
4447d351 1947 ahci_start_engine(ap);
1da177e4 1948
9dadd45b 1949 if (online)
4bd00f6a 1950 *class = ahci_dev_classify(ap);
1da177e4 1951
4bd00f6a
TH		 1952 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1953 return rc;
1954}
1955
cc0680a5 1956static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1957 unsigned long deadline)
ad616ffb 1958{
cc0680a5 1959 struct ata_port *ap = link->ap;
9dadd45b 1960 bool online;
ad616ffb
TH		 1961 int rc;
1962
1963 DPRINTK("ENTER\n");
1964
4447d351 1965 ahci_stop_engine(ap);
ad616ffb 1966
cc0680a5 1967 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1968 deadline, &online, NULL);
ad616ffb 1969
4447d351 1970 ahci_start_engine(ap);
ad616ffb
TH		 1971
1972 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1973
1974 /* vt8251 doesn't clear BSY on signature FIS reception,
1975 * request follow-up softreset.
1976 */
9dadd45b 1977 return online ? -EAGAIN : rc;
ad616ffb
TH		 1978}
1979
edc93052
TH		 1980static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1981 unsigned long deadline)
1982{
1983 struct ata_port *ap = link->ap;
1984 struct ahci_port_priv *pp = ap->private_data;
1985 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1986 struct ata_taskfile tf;
9dadd45b 1987 bool online;
edc93052
TH		 1988 int rc;
1989
1990 ahci_stop_engine(ap);
1991
1992 /* clear D2H reception area to properly wait for D2H FIS */
1993 ata_tf_init(link->device, &tf);
1994 tf.command = 0x80;
1995 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1996
1997 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1998 deadline, &online, NULL);
edc93052
TH		 1999
2000 ahci_start_engine(ap);
2001
edc93052
TH		 2002 /* The pseudo configuration device on SIMG4726 attached to
2003 * ASUS P5W-DH Deluxe doesn't send signature FIS after
2004 * hardreset if no device is attached to the first downstream
2005 * port && the pseudo device locks up on SRST w/ PMP==0. To
2006 * work around this, wait for !BSY only briefly. If BSY isn't
2007 * cleared, perform CLO and proceed to IDENTIFY (achieved by
2008 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
2009 *
2010 * Wait for two seconds. Devices attached to downstream port
2011 * which can't process the following IDENTIFY after this will
2012 * have to be reset again. For most cases, this should
2013 * suffice while making probing snappish enough.
2014 */
9dadd45b
TH		 2015 if (online) {
2016 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
2017 ahci_check_ready);
2018 if (rc)
78d5ae39 2019 ahci_kick_engine(ap);
9dadd45b 2020 }
9dadd45b 2021 return rc;
edc93052
TH		 2022}
2023
cc0680a5 2024static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 2025{
cc0680a5 2026 struct ata_port *ap = link->ap;
4447d351 2027 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 2028 u32 new_tmp, tmp;
2029
203c75b8 2030 ata_std_postreset(link, class);
02eaa666
JG		 2031
2032 /* Make sure port's ATAPI bit is set appropriately */
2033 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 2034 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 2035 new_tmp |= PORT_CMD_ATAPI;
2036 else
2037 new_tmp &= ~PORT_CMD_ATAPI;
2038 if (new_tmp != tmp) {
2039 writel(new_tmp, port_mmio + PORT_CMD);
2040 readl(port_mmio + PORT_CMD); /* flush */
2041 }
1da177e4
LT		 2042}
2043
12fad3f9 2044static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 2045{
cedc9a47 2046 struct scatterlist *sg;
ff2aeb1e
TH		 2047 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
2048 unsigned int si;
1da177e4
LT		 2049
2050 VPRINTK("ENTER\n");
2051
2052 /*
2053 * Next, the S/G list.
2054 */
ff2aeb1e 2055 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 2056 dma_addr_t addr = sg_dma_address(sg);
2057 u32 sg_len = sg_dma_len(sg);
2058
ff2aeb1e
TH		 2059 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
2060 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
2061 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 2062 }
828d09de 2063
ff2aeb1e 2064 return si;
1da177e4
LT		 2065}
2066
d6ef3153
SH		 2067static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
2068{
2069 struct ata_port *ap = qc->ap;
2070 struct ahci_port_priv *pp = ap->private_data;
2071
2072 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
2073 return ata_std_qc_defer(qc);
2074 else
2075 return sata_pmp_qc_defer_cmd_switch(qc);
2076}
2077
1da177e4
LT		 2078static void ahci_qc_prep(struct ata_queued_cmd *qc)
2079{
a0ea7328
JG		 2080 struct ata_port *ap = qc->ap;
2081 struct ahci_port_priv *pp = ap->private_data;
405e66b3 2082 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 2083 void *cmd_tbl;
1da177e4
LT		 2084 u32 opts;
2085 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 2086 unsigned int n_elem;
1da177e4 2087
1da177e4
LT		 2088 /*
2089 * Fill in command table information. First, the header,
2090 * a SATA Register - Host to Device command FIS.
2091 */
12fad3f9
TH		 2092 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
2093
7d50b60b 2094 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 2095 if (is_atapi) {
12fad3f9
TH		 2096 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
2097 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 2098 }
1da177e4 2099
cc9278ed
TH		 2100 n_elem = 0;
2101 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 2102 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 2103
cc9278ed
TH		 2104 /*
2105 * Fill in command slot information.
2106 */
7d50b60b 2107 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 2108 if (qc->tf.flags & ATA_TFLAG_WRITE)
2109 opts |= AHCI_CMD_WRITE;
2110 if (is_atapi)
4b10e559 2111 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 2112
12fad3f9 2113 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 2114}
2115
d6ef3153
SH		 2116static void ahci_fbs_dec_intr(struct ata_port *ap)
2117{
2118 struct ahci_port_priv *pp = ap->private_data;
2119 void __iomem *port_mmio = ahci_port_base(ap);
2120 u32 fbs = readl(port_mmio + PORT_FBS);
2121 int retries = 3;
2122
2123 DPRINTK("ENTER\n");
2124 BUG_ON(!pp->fbs_enabled);
2125
2126 /* time to wait for DEC is not specified by AHCI spec,
2127 * add a retry loop for safety.
2128 */
2129 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
2130 fbs = readl(port_mmio + PORT_FBS);
2131 while ((fbs & PORT_FBS_DEC) && retries--) {
2132 udelay(1);
2133 fbs = readl(port_mmio + PORT_FBS);
2134 }
2135
2136 if (fbs & PORT_FBS_DEC)
2137 dev_printk(KERN_ERR, ap->host->dev,
2138 "failed to clear device error\n");
2139}
2140
78cd52d0 2141static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 2142{
417a1a6d 2143 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 2144 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2145 struct ata_eh_info *host_ehi = &ap->link.eh_info;
2146 struct ata_link *link = NULL;
2147 struct ata_queued_cmd *active_qc;
2148 struct ata_eh_info *active_ehi;
d6ef3153 2149 bool fbs_need_dec = false;
78cd52d0 2150 u32 serror;
1da177e4 2151
d6ef3153
SH		 2152 /* determine active link with error */
2153 if (pp->fbs_enabled) {
2154 void __iomem *port_mmio = ahci_port_base(ap);
2155 u32 fbs = readl(port_mmio + PORT_FBS);
2156 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
2157
2158 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
2159 ata_link_online(&ap->pmp_link[pmp])) {
2160 link = &ap->pmp_link[pmp];
2161 fbs_need_dec = true;
2162 }
2163
2164 } else
2165 ata_for_each_link(link, ap, EDGE)
2166 if (ata_link_active(link))
2167 break;
2168
7d50b60b
TH		 2169 if (!link)
2170 link = &ap->link;
2171
2172 active_qc = ata_qc_from_tag(ap, link->active_tag);
2173 active_ehi = &link->eh_info;
2174
2175 /* record irq stat */
2176 ata_ehi_clear_desc(host_ehi);
2177 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 2178
78cd52d0 2179 /* AHCI needs SError cleared; otherwise, it might lock up */
82ef04fb
TH		 2180 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2181 ahci_scr_write(&ap->link, SCR_ERROR, serror);
7d50b60b 2182 host_ehi->serror |= serror;
78cd52d0 2183
41669553 2184 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 2185 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 2186 irq_stat &= ~PORT_IRQ_IF_ERR;
2187
55a61604 2188 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 2189 /* If qc is active, charge it; otherwise, the active
2190 * link. There's no active qc on NCQ errors. It will
2191 * be determined by EH by reading log page 10h.
2192 */
2193 if (active_qc)
2194 active_qc->err_mask |= AC_ERR_DEV;
2195 else
2196 active_ehi->err_mask |= AC_ERR_DEV;
2197
417a1a6d 2198 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 2199 host_ehi->serror &= ~SERR_INTERNAL;
2200 }
2201
2202 if (irq_stat & PORT_IRQ_UNK_FIS) {
2203 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2204
2205 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 2206 active_ehi->action |= ATA_EH_RESET;
7d50b60b
TH		 2207 ata_ehi_push_desc(active_ehi,
2208 "unknown FIS %08x %08x %08x %08x" ,
2209 unk[0], unk[1], unk[2], unk[3]);
2210 }
2211
071f44b1 2212 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
7d50b60b 2213 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 2214 active_ehi->action |= ATA_EH_RESET;
7d50b60b 2215 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 2216 }
78cd52d0
TH		 2217
2218 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b 2219 host_ehi->err_mask |= AC_ERR_HOST_BUS;
cf480626 2220 host_ehi->action |= ATA_EH_RESET;
7d50b60b 2221 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 2222 }
2223
78cd52d0 2224 if (irq_stat & PORT_IRQ_IF_ERR) {
d6ef3153
SH		 2225 if (fbs_need_dec)
2226 active_ehi->err_mask |= AC_ERR_DEV;
2227 else {
2228 host_ehi->err_mask |= AC_ERR_ATA_BUS;
2229 host_ehi->action |= ATA_EH_RESET;
2230 }
2231
7d50b60b 2232 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 2233 }
1da177e4 2234
78cd52d0 2235 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 2236 ata_ehi_hotplugged(host_ehi);
2237 ata_ehi_push_desc(host_ehi, "%s",
2238 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 2239 "connection status changed" : "PHY RDY changed");
2240 }
2241
78cd52d0 2242 /* okay, let's hand over to EH */
a72ec4ce 2243
78cd52d0
TH		 2244 if (irq_stat & PORT_IRQ_FREEZE)
2245 ata_port_freeze(ap);
d6ef3153
SH		 2246 else if (fbs_need_dec) {
2247 ata_link_abort(link);
2248 ahci_fbs_dec_intr(ap);
2249 } else
78cd52d0 2250 ata_port_abort(ap);
1da177e4
LT		 2251}
2252
df69c9c5 2253static void ahci_port_intr(struct ata_port *ap)
1da177e4 2254{
350756f6 2255 void __iomem *port_mmio = ahci_port_base(ap);
9af5c9c9 2256 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 2257 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 2258 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 2259 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 2260 u32 status, qc_active;
459ad688 2261 int rc;
1da177e4
LT		 2262
2263 status = readl(port_mmio + PORT_IRQ_STAT);
2264 writel(status, port_mmio + PORT_IRQ_STAT);
2265
b06ce3e5
TH		 2266 /* ignore BAD_PMP while resetting */
2267 if (unlikely(resetting))
2268 status &= ~PORT_IRQ_BAD_PMP;
2269
31556594
KCA		 2270 /* If we are getting PhyRdy, this is
2271 * just a power state change, we should
2272 * clear out this, plus the PhyRdy/Comm
2273 * Wake bits from Serror
2274 */
2275 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2276 (status & PORT_IRQ_PHYRDY)) {
2277 status &= ~PORT_IRQ_PHYRDY;
82ef04fb 2278 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
31556594
KCA		 2279 }
2280
78cd52d0
TH		 2281 if (unlikely(status & PORT_IRQ_ERROR)) {
2282 ahci_error_intr(ap, status);
2283 return;
1da177e4
LT		 2284 }
2285
2f294968 2286 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 2287 /* If SNotification is available, leave notification
2288 * handling to sata_async_notification(). If not,
2289 * emulate it by snooping SDB FIS RX area.
2290 *
2291 * Snooping FIS RX area is probably cheaper than
2292 * poking SNotification but some constrollers which
2293 * implement SNotification, ICH9 for example, don't
2294 * store AN SDB FIS into receive area.
2f294968 2295 */
5f226c6b 2296 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 2297 sata_async_notification(ap);
5f226c6b
TH		 2298 else {
2299 /* If the 'N' bit in word 0 of the FIS is set,
2300 * we just received asynchronous notification.
2301 * Tell libata about it.
d6ef3153
SH		 2302 *
2303 * Lack of SNotification should not appear in
2304 * ahci 1.2, so the workaround is unnecessary
2305 * when FBS is enabled.
5f226c6b 2306 */
d6ef3153
SH		 2307 if (pp->fbs_enabled)
2308 WARN_ON_ONCE(1);
2309 else {
2310 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2311 u32 f0 = le32_to_cpu(f[0]);
2312 if (f0 & (1 << 15))
2313 sata_async_notification(ap);
2314 }
5f226c6b 2315 }
2f294968
KCA		 2316 }
2317
7d50b60b
TH		 2318 /* pp->active_link is valid iff any command is in flight */
2319 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 2320 qc_active = readl(port_mmio + PORT_SCR_ACT);
2321 else
2322 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2323
79f97dad 2324 rc = ata_qc_complete_multiple(ap, qc_active);
b06ce3e5 2325
459ad688
TH		 2326 /* while resetting, invalid completions are expected */
2327 if (unlikely(rc < 0 && !resetting)) {
12fad3f9 2328 ehi->err_mask |= AC_ERR_HSM;
cf480626 2329 ehi->action |= ATA_EH_RESET;
12fad3f9 2330 ata_port_freeze(ap);
1da177e4 2331 }
1da177e4
LT		 2332}
2333
7d12e780 2334static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 2335{
cca3974e 2336 struct ata_host *host = dev_instance;
1da177e4
LT		 2337 struct ahci_host_priv *hpriv;
2338 unsigned int i, handled = 0;
ea6ba10b 2339 void __iomem *mmio;
d28f87aa 2340 u32 irq_stat, irq_masked;
1da177e4
LT		 2341
2342 VPRINTK("ENTER\n");
2343
cca3974e 2344 hpriv = host->private_data;
0d5ff566 2345 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2346
2347 /* sigh. 0xffffffff is a valid return from h/w */
2348 irq_stat = readl(mmio + HOST_IRQ_STAT);
1da177e4
LT		 2349 if (!irq_stat)
2350 return IRQ_NONE;
2351
d28f87aa
TH		 2352 irq_masked = irq_stat & hpriv->port_map;
2353
2dcb407e 2354 spin_lock(&host->lock);
1da177e4 2355
2dcb407e 2356 for (i = 0; i < host->n_ports; i++) {
1da177e4 2357 struct ata_port *ap;
1da177e4 2358
d28f87aa 2359 if (!(irq_masked & (1 << i)))
67846b30
JG		 2360 continue;
2361
cca3974e 2362 ap = host->ports[i];
67846b30 2363 if (ap) {
df69c9c5 2364 ahci_port_intr(ap);
67846b30
JG		 2365 VPRINTK("port %u\n", i);
2366 } else {
2367 VPRINTK("port %u (no irq)\n", i);
6971ed1f 2368 if (ata_ratelimit())
cca3974e 2369 dev_printk(KERN_WARNING, host->dev,
a9524a76 2370 "interrupt on disabled port %u\n", i);
1da177e4 2371 }
67846b30 2372
1da177e4
LT		 2373 handled = 1;
2374 }
2375
d28f87aa
TH		 2376 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2377 * it should be cleared after all the port events are cleared;
2378 * otherwise, it will raise a spurious interrupt after each
2379 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2380 * information.
2381 *
2382 * Also, use the unmasked value to clear interrupt as spurious
2383 * pending event on a dummy port might cause screaming IRQ.
2384 */
ea0c62f7
TH		 2385 writel(irq_stat, mmio + HOST_IRQ_STAT);
2386
cca3974e 2387 spin_unlock(&host->lock);
1da177e4
LT		 2388
2389 VPRINTK("EXIT\n");
2390
2391 return IRQ_RETVAL(handled);
2392}
2393
9a3d9eb0 2394static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 2395{
2396 struct ata_port *ap = qc->ap;
4447d351 2397 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 2398 struct ahci_port_priv *pp = ap->private_data;
2399
2400 /* Keep track of the currently active link. It will be used
2401 * in completion path to determine whether NCQ phase is in
2402 * progress.
2403 */
2404 pp->active_link = qc->dev->link;
1da177e4 2405
12fad3f9
TH		 2406 if (qc->tf.protocol == ATA_PROT_NCQ)
2407 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
d6ef3153
SH		 2408
2409 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2410 u32 fbs = readl(port_mmio + PORT_FBS);
2411 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2412 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2413 writel(fbs, port_mmio + PORT_FBS);
2414 pp->fbs_last_dev = qc->dev->link->pmp;
2415 }
2416
12fad3f9 2417 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4 2418
18f7ba4c
KCA		 2419 ahci_sw_activity(qc->dev->link);
2420
1da177e4
LT		 2421 return 0;
2422}
2423
4c9bf4e7
TH		 2424static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2425{
2426 struct ahci_port_priv *pp = qc->ap->private_data;
2427 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2428
d6ef3153
SH		 2429 if (pp->fbs_enabled)
2430 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2431
4c9bf4e7
TH		 2432 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2433 return true;
2434}
2435
78cd52d0
TH		 2436static void ahci_freeze(struct ata_port *ap)
2437{
4447d351 2438 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 2439
2440 /* turn IRQ off */
2441 writel(0, port_mmio + PORT_IRQ_MASK);
2442}
2443
2444static void ahci_thaw(struct ata_port *ap)
2445{
0d5ff566 2446 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 2447 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 2448 u32 tmp;
a7384925 2449 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 2450
2451 /* clear IRQ */
2452 tmp = readl(port_mmio + PORT_IRQ_STAT);
2453 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 2454 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 2455
1c954a4d
TH		 2456 /* turn IRQ back on */
2457 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 2458}
2459
2460static void ahci_error_handler(struct ata_port *ap)
2461{
b51e9e5d 2462 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 2463 /* restart engine */
4447d351
TH		 2464 ahci_stop_engine(ap);
2465 ahci_start_engine(ap);
78cd52d0
TH		 2466 }
2467
a1efdaba 2468 sata_pmp_error_handler(ap);
edc93052
TH		 2469}
2470
78cd52d0
TH		 2471static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2472{
2473 struct ata_port *ap = qc->ap;
2474
d2e75dff
TH		 2475 /* make DMA engine forget about the failed command */
2476 if (qc->flags & ATA_QCFLAG_FAILED)
78d5ae39 2477 ahci_kick_engine(ap);
78cd52d0
TH		 2478}
2479
d6ef3153
SH		 2480static void ahci_enable_fbs(struct ata_port *ap)
2481{
2482 struct ahci_port_priv *pp = ap->private_data;
2483 void __iomem *port_mmio = ahci_port_base(ap);
2484 u32 fbs;
2485 int rc;
2486
2487 if (!pp->fbs_supported)
2488 return;
2489
2490 fbs = readl(port_mmio + PORT_FBS);
2491 if (fbs & PORT_FBS_EN) {
2492 pp->fbs_enabled = true;
2493 pp->fbs_last_dev = -1; /* initialization */
2494 return;
2495 }
2496
2497 rc = ahci_stop_engine(ap);
2498 if (rc)
2499 return;
2500
2501 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2502 fbs = readl(port_mmio + PORT_FBS);
2503 if (fbs & PORT_FBS_EN) {
2504 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
2505 pp->fbs_enabled = true;
2506 pp->fbs_last_dev = -1; /* initialization */
2507 } else
2508 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
2509
2510 ahci_start_engine(ap);
2511}
2512
2513static void ahci_disable_fbs(struct ata_port *ap)
2514{
2515 struct ahci_port_priv *pp = ap->private_data;
2516 void __iomem *port_mmio = ahci_port_base(ap);
2517 u32 fbs;
2518 int rc;
2519
2520 if (!pp->fbs_supported)
2521 return;
2522
2523 fbs = readl(port_mmio + PORT_FBS);
2524 if ((fbs & PORT_FBS_EN) == 0) {
2525 pp->fbs_enabled = false;
2526 return;
2527 }
2528
2529 rc = ahci_stop_engine(ap);
2530 if (rc)
2531 return;
2532
2533 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2534 fbs = readl(port_mmio + PORT_FBS);
2535 if (fbs & PORT_FBS_EN)
2536 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
2537 else {
2538 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
2539 pp->fbs_enabled = false;
2540 }
2541
2542 ahci_start_engine(ap);
2543}
2544
7d50b60b
TH		 2545static void ahci_pmp_attach(struct ata_port *ap)
2546{
2547 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2548 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2549 u32 cmd;
2550
2551 cmd = readl(port_mmio + PORT_CMD);
2552 cmd |= PORT_CMD_PMP;
2553 writel(cmd, port_mmio + PORT_CMD);
1c954a4d 2554
d6ef3153
SH		 2555 ahci_enable_fbs(ap);
2556
1c954a4d
TH		 2557 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2558 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2559}
2560
2561static void ahci_pmp_detach(struct ata_port *ap)
2562{
2563 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2564 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2565 u32 cmd;
2566
d6ef3153
SH		 2567 ahci_disable_fbs(ap);
2568
7d50b60b
TH		 2569 cmd = readl(port_mmio + PORT_CMD);
2570 cmd &= ~PORT_CMD_PMP;
2571 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2572
2573 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2574 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2575}
2576
028a2596
AD		 2577static int ahci_port_resume(struct ata_port *ap)
2578{
2579 ahci_power_up(ap);
2580 ahci_start_port(ap);
2581
071f44b1 2582 if (sata_pmp_attached(ap))
7d50b60b
TH		 2583 ahci_pmp_attach(ap);
2584 else
2585 ahci_pmp_detach(ap);
2586
028a2596
AD		 2587 return 0;
2588}
2589
438ac6d5 2590#ifdef CONFIG_PM
c1332875
TH		 2591static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2592{
c1332875
TH		 2593 const char *emsg = NULL;
2594 int rc;
2595
4447d351 2596 rc = ahci_deinit_port(ap, &emsg);
8e16f941 2597 if (rc == 0)
4447d351 2598 ahci_power_down(ap);
8e16f941 2599 else {
c1332875 2600 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 2601 ahci_start_port(ap);
c1332875
TH		 2602 }
2603
2604 return rc;
2605}
2606
c1332875
TH		 2607static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2608{
cca3974e 2609 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 2610 struct ahci_host_priv *hpriv = host->private_data;
0d5ff566 2611 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 2612 u32 ctl;
2613
9b10ae86
TH		 2614 if (mesg.event & PM_EVENT_SUSPEND &&
2615 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2616 dev_printk(KERN_ERR, &pdev->dev,
2617 "BIOS update required for suspend/resume\n");
2618 return -EIO;
2619 }
2620
3a2d5b70 2621 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 2622 /* AHCI spec rev1.1 section 8.3.3:
2623 * Software must disable interrupts prior to requesting a
2624 * transition of the HBA to D3 state.
2625 */
2626 ctl = readl(mmio + HOST_CTL);
2627 ctl &= ~HOST_IRQ_EN;
2628 writel(ctl, mmio + HOST_CTL);
2629 readl(mmio + HOST_CTL); /* flush */
2630 }
2631
2632 return ata_pci_device_suspend(pdev, mesg);
2633}
2634
2635static int ahci_pci_device_resume(struct pci_dev *pdev)
2636{
cca3974e 2637 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 2638 int rc;
2639
553c4aa6
TH		 2640 rc = ata_pci_device_do_resume(pdev);
2641 if (rc)
2642 return rc;
c1332875
TH		 2643
2644 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 2645 rc = ahci_reset_controller(host);
c1332875
TH		 2646 if (rc)
2647 return rc;
2648
4447d351 2649 ahci_init_controller(host);
c1332875
TH		 2650 }
2651
cca3974e 2652 ata_host_resume(host);
c1332875
TH		 2653
2654 return 0;
2655}
438ac6d5 2656#endif
c1332875 2657
254950cd
TH		 2658static int ahci_port_start(struct ata_port *ap)
2659{
d6ef3153 2660 struct ahci_host_priv *hpriv = ap->host->private_data;
cca3974e 2661 struct device *dev = ap->host->dev;
254950cd 2662 struct ahci_port_priv *pp;
254950cd
TH		 2663 void *mem;
2664 dma_addr_t mem_dma;
d6ef3153 2665 size_t dma_sz, rx_fis_sz;
254950cd 2666
24dc5f33 2667 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2668 if (!pp)
2669 return -ENOMEM;
254950cd 2670
d6ef3153
SH		 2671 /* check FBS capability */
2672 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2673 void __iomem *port_mmio = ahci_port_base(ap);
2674 u32 cmd = readl(port_mmio + PORT_CMD);
2675 if (cmd & PORT_CMD_FBSCP)
2676 pp->fbs_supported = true;
2677 else
2678 dev_printk(KERN_WARNING, dev,
2679 "The port is not capable of FBS\n");
2680 }
2681
2682 if (pp->fbs_supported) {
2683 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2684 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2685 } else {
2686 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2687 rx_fis_sz = AHCI_RX_FIS_SZ;
2688 }
2689
2690 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
24dc5f33 2691 if (!mem)
254950cd 2692 return -ENOMEM;
d6ef3153 2693 memset(mem, 0, dma_sz);
254950cd
TH		 2694
2695 /*
2696 * First item in chunk of DMA memory: 32-slot command table,
2697 * 32 bytes each in size
2698 */
2699 pp->cmd_slot = mem;
2700 pp->cmd_slot_dma = mem_dma;
2701
2702 mem += AHCI_CMD_SLOT_SZ;
2703 mem_dma += AHCI_CMD_SLOT_SZ;
2704
2705 /*
2706 * Second item: Received-FIS area
2707 */
2708 pp->rx_fis = mem;
2709 pp->rx_fis_dma = mem_dma;
2710
d6ef3153
SH		 2711 mem += rx_fis_sz;
2712 mem_dma += rx_fis_sz;
254950cd
TH		 2713
2714 /*
2715 * Third item: data area for storing a single command
2716 * and its scatter-gather table
2717 */
2718 pp->cmd_tbl = mem;
2719 pp->cmd_tbl_dma = mem_dma;
2720
a7384925 2721 /*
2dcb407e
JG		 2722 * Save off initial list of interrupts to be enabled.
2723 * This could be changed later
2724 */
a7384925
KCA		 2725 pp->intr_mask = DEF_PORT_IRQ;
2726
254950cd
TH		 2727 ap->private_data = pp;
2728
df69c9c5
JG		 2729 /* engage engines, captain */
2730 return ahci_port_resume(ap);
254950cd
TH		 2731}
2732
2733static void ahci_port_stop(struct ata_port *ap)
2734{
0be0aa98
TH		 2735 const char *emsg = NULL;
2736 int rc;
254950cd 2737
0be0aa98 2738 /* de-initialize port */
4447d351 2739 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2740 if (rc)
2741 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2742}
2743
4447d351 2744static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2745{
1da177e4 2746 int rc;
1da177e4 2747
1da177e4 2748 if (using_dac &&
6a35528a
YH		 2749 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2750 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 2751 if (rc) {
284901a9 2752 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2753 if (rc) {
a9524a76
JG		 2754 dev_printk(KERN_ERR, &pdev->dev,
2755 "64-bit DMA enable failed\n");
1da177e4
LT		 2756 return rc;
2757 }
2758 }
1da177e4 2759 } else {
284901a9 2760 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2761 if (rc) {
a9524a76
JG		 2762 dev_printk(KERN_ERR, &pdev->dev,
2763 "32-bit DMA enable failed\n");
1da177e4
LT		 2764 return rc;
2765 }
284901a9 2766 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2767 if (rc) {
a9524a76
JG		 2768 dev_printk(KERN_ERR, &pdev->dev,
2769 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2770 return rc;
2771 }
2772 }
1da177e4
LT		 2773 return 0;
2774}
2775
4447d351 2776static void ahci_print_info(struct ata_host *host)
1da177e4 2777{
4447d351
TH		 2778 struct ahci_host_priv *hpriv = host->private_data;
2779 struct pci_dev *pdev = to_pci_dev(host->dev);
2780 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4c521c8e 2781 u32 vers, cap, cap2, impl, speed;
1da177e4
LT		 2782 const char *speed_s;
2783 u16 cc;
2784 const char *scc_s;
2785
2786 vers = readl(mmio + HOST_VERSION);
2787 cap = hpriv->cap;
4c521c8e 2788 cap2 = hpriv->cap2;
1da177e4
LT		 2789 impl = hpriv->port_map;
2790
2791 speed = (cap >> 20) & 0xf;
2792 if (speed == 1)
2793 speed_s = "1.5";
2794 else if (speed == 2)
2795 speed_s = "3";
8522ee25
SH		 2796 else if (speed == 3)
2797 speed_s = "6";
1da177e4
LT		 2798 else
2799 speed_s = "?";
2800
2801 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2802 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2803 scc_s = "IDE";
c9f89475 2804 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2805 scc_s = "SATA";
c9f89475 2806 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2807 scc_s = "RAID";
2808 else
2809 scc_s = "unknown";
2810
a9524a76
JG		 2811 dev_printk(KERN_INFO, &pdev->dev,
2812 "AHCI %02x%02x.%02x%02x "
1da177e4 2813 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2814 ,
1da177e4 2815
2dcb407e
JG		 2816 (vers >> 24) & 0xff,
2817 (vers >> 16) & 0xff,
2818 (vers >> 8) & 0xff,
2819 vers & 0xff,
1da177e4
LT		 2820
2821 ((cap >> 8) & 0x1f) + 1,
2822 (cap & 0x1f) + 1,
2823 speed_s,
2824 impl,
2825 scc_s);
2826
a9524a76
JG		 2827 dev_printk(KERN_INFO, &pdev->dev,
2828 "flags: "
203ef6c4 2829 "%s%s%s%s%s%s%s"
18f7ba4c 2830 "%s%s%s%s%s%s%s"
4c521c8e 2831 "%s%s%s%s%s%s\n"
2dcb407e 2832 ,
1da177e4 2833
4c521c8e
RH		 2834 cap & HOST_CAP_64 ? "64bit " : "",
2835 cap & HOST_CAP_NCQ ? "ncq " : "",
2836 cap & HOST_CAP_SNTF ? "sntf " : "",
2837 cap & HOST_CAP_MPS ? "ilck " : "",
2838 cap & HOST_CAP_SSS ? "stag " : "",
2839 cap & HOST_CAP_ALPM ? "pm " : "",
2840 cap & HOST_CAP_LED ? "led " : "",
2841 cap & HOST_CAP_CLO ? "clo " : "",
2842 cap & HOST_CAP_ONLY ? "only " : "",
2843 cap & HOST_CAP_PMP ? "pmp " : "",
2844 cap & HOST_CAP_FBS ? "fbs " : "",
2845 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2846 cap & HOST_CAP_SSC ? "slum " : "",
2847 cap & HOST_CAP_PART ? "part " : "",
2848 cap & HOST_CAP_CCC ? "ccc " : "",
2849 cap & HOST_CAP_EMS ? "ems " : "",
2850 cap & HOST_CAP_SXS ? "sxs " : "",
2851 cap2 & HOST_CAP2_APST ? "apst " : "",
2852 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2853 cap2 & HOST_CAP2_BOH ? "boh " : ""
1da177e4
LT		 2854 );
2855}
2856
edc93052
TH		 2857/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2858 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2859 * support PMP and the 4726 either directly exports the device
2860 * attached to the first downstream port or acts as a hardware storage
2861 * controller and emulate a single ATA device (can be RAID 0/1 or some
2862 * other configuration).
2863 *
2864 * When there's no device attached to the first downstream port of the
2865 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2866 * configure the 4726. However, ATA emulation of the device is very
2867 * lame. It doesn't send signature D2H Reg FIS after the initial
2868 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2869 *
2870 * The following function works around the problem by always using
2871 * hardreset on the port and not depending on receiving signature FIS
2872 * afterward. If signature FIS isn't received soon, ATA class is
2873 * assumed without follow-up softreset.
2874 */
2875static void ahci_p5wdh_workaround(struct ata_host *host)
2876{
2877 static struct dmi_system_id sysids[] = {
2878 {
2879 .ident = "P5W DH Deluxe",
2880 .matches = {
2881 DMI_MATCH(DMI_SYS_VENDOR,
2882 "ASUSTEK COMPUTER INC"),
2883 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2884 },
2885 },
2886 { }
2887 };
2888 struct pci_dev *pdev = to_pci_dev(host->dev);
2889
2890 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2891 dmi_check_system(sysids)) {
2892 struct ata_port *ap = host->ports[1];
2893
2894 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2895 "Deluxe on-board SIMG4726 workaround\n");
2896
2897 ap->ops = &ahci_p5wdh_ops;
2898 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2899 }
2900}
2901
2fcad9d2
TH		 2902/* only some SB600 ahci controllers can do 64bit DMA */
2903static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 2904{
2905 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 2906 /*
2907 * The oldest version known to be broken is 0901 and
2908 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 2909 * Enable 64bit DMA on 1501 and anything newer.
2910 *
03d783bf
TH		 2911 * Please read bko#9412 for more info.
2912 */
58a09b38
SH		 2913 {
2914 .ident = "ASUS M2A-VM",
2915 .matches = {
2916 DMI_MATCH(DMI_BOARD_VENDOR,
2917 "ASUSTeK Computer INC."),
2918 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2919 },
03d783bf 2920 .driver_data = "20071026", /* yyyymmdd */
58a09b38 2921 },
e65cc194
MN		 2922 /*
2923 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
2924 * support 64bit DMA.
2925 *
2926 * BIOS versions earlier than 1.5 had the Manufacturer DMI
2927 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
2928 * This spelling mistake was fixed in BIOS version 1.5, so
2929 * 1.5 and later have the Manufacturer as
2930 * "MICRO-STAR INTERNATIONAL CO.,LTD".
2931 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
2932 *
2933 * BIOS versions earlier than 1.9 had a Board Product Name
2934 * DMI field of "MS-7376". This was changed to be
2935 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
2936 * match on DMI_BOARD_NAME of "MS-7376".
2937 */
2938 {
2939 .ident = "MSI K9A2 Platinum",
2940 .matches = {
2941 DMI_MATCH(DMI_BOARD_VENDOR,
2942 "MICRO-STAR INTER"),
2943 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
2944 },
2945 },
58a09b38
SH		 2946 { }
2947 };
03d783bf 2948 const struct dmi_system_id *match;
2fcad9d2
TH		 2949 int year, month, date;
2950 char buf[9];
58a09b38 2951
03d783bf 2952 match = dmi_first_match(sysids);
58a09b38 2953 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 2954 !match)
58a09b38
SH		 2955 return false;
2956
e65cc194
MN		 2957 if (!match->driver_data)
2958 goto enable_64bit;
2959
2fcad9d2
TH		 2960 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2961 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 2962
e65cc194
MN		 2963 if (strcmp(buf, match->driver_data) >= 0)
2964 goto enable_64bit;
2965 else {
03d783bf
TH		 2966 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
2967 "forcing 32bit DMA, update BIOS\n", match->ident);
2fcad9d2
TH		 2968 return false;
2969 }
e65cc194
MN		 2970
2971enable_64bit:
2972 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
2973 match->ident);
2974 return true;
58a09b38
SH		 2975}
2976
1fd68434
RW		 2977static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2978{
2979 static const struct dmi_system_id broken_systems[] = {
2980 {
2981 .ident = "HP Compaq nx6310",
2982 .matches = {
2983 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2984 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2985 },
2986 /* PCI slot number of the controller */
2987 .driver_data = (void *)0x1FUL,
2988 },
d2f9c061
MR		 2989 {
2990 .ident = "HP Compaq 6720s",
2991 .matches = {
2992 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2993 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2994 },
2995 /* PCI slot number of the controller */
2996 .driver_data = (void *)0x1FUL,
2997 },
1fd68434
RW		 2998
2999 { } /* terminate list */
3000 };
3001 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
3002
3003 if (dmi) {
3004 unsigned long slot = (unsigned long)dmi->driver_data;
3005 /* apply the quirk only to on-board controllers */
3006 return slot == PCI_SLOT(pdev->devfn);
3007 }
3008
3009 return false;
3010}
3011
9b10ae86
TH		 3012static bool ahci_broken_suspend(struct pci_dev *pdev)
3013{
3014 static const struct dmi_system_id sysids[] = {
3015 /*
3016 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
3017 * to the harddisk doesn't become online after
3018 * resuming from STR. Warn and fail suspend.
3019 */
3020 {
3021 .ident = "dv4",
3022 .matches = {
3023 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3024 DMI_MATCH(DMI_PRODUCT_NAME,
3025 "HP Pavilion dv4 Notebook PC"),
3026 },
3027 .driver_data = "F.30", /* cutoff BIOS version */
3028 },
3029 {
3030 .ident = "dv5",
3031 .matches = {
3032 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3033 DMI_MATCH(DMI_PRODUCT_NAME,
3034 "HP Pavilion dv5 Notebook PC"),
3035 },
3036 .driver_data = "F.16", /* cutoff BIOS version */
3037 },
3038 {
3039 .ident = "dv6",
3040 .matches = {
3041 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3042 DMI_MATCH(DMI_PRODUCT_NAME,
3043 "HP Pavilion dv6 Notebook PC"),
3044 },
3045 .driver_data = "F.21", /* cutoff BIOS version */
3046 },
3047 {
3048 .ident = "HDX18",
3049 .matches = {
3050 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3051 DMI_MATCH(DMI_PRODUCT_NAME,
3052 "HP HDX18 Notebook PC"),
3053 },
3054 .driver_data = "F.23", /* cutoff BIOS version */
3055 },
cedc9bf9
TH		 3056 /*
3057 * Acer eMachines G725 has the same problem. BIOS
3058 * V1.03 is known to be broken. V3.04 is known to
3059 * work. Inbetween, there are V1.06, V2.06 and V3.03
3060 * that we don't have much idea about. For now,
3061 * blacklist anything older than V3.04.
3062 */
3063 {
3064 .ident = "G725",
3065 .matches = {
3066 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
3067 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
3068 },
3069 .driver_data = "V3.04", /* cutoff BIOS version */
3070 },
9b10ae86
TH		 3071 { } /* terminate list */
3072 };
3073 const struct dmi_system_id *dmi = dmi_first_match(sysids);
3074 const char *ver;
3075
3076 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
3077 return false;
3078
3079 ver = dmi_get_system_info(DMI_BIOS_VERSION);
3080
3081 return !ver || strcmp(ver, dmi->driver_data) < 0;
3082}
3083
5594639a
TH		 3084static bool ahci_broken_online(struct pci_dev *pdev)
3085{
3086#define ENCODE_BUSDEVFN(bus, slot, func) \
3087 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
3088 static const struct dmi_system_id sysids[] = {
3089 /*
3090 * There are several gigabyte boards which use
3091 * SIMG5723s configured as hardware RAID. Certain
3092 * 5723 firmware revisions shipped there keep the link
3093 * online but fail to answer properly to SRST or
3094 * IDENTIFY when no device is attached downstream
3095 * causing libata to retry quite a few times leading
3096 * to excessive detection delay.
3097 *
3098 * As these firmwares respond to the second reset try
3099 * with invalid device signature, considering unknown
3100 * sig as offline works around the problem acceptably.
3101 */
3102 {
3103 .ident = "EP45-DQ6",
3104 .matches = {
3105 DMI_MATCH(DMI_BOARD_VENDOR,
3106 "Gigabyte Technology Co., Ltd."),
3107 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
3108 },
3109 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
3110 },
3111 {
3112 .ident = "EP45-DS5",
3113 .matches = {
3114 DMI_MATCH(DMI_BOARD_VENDOR,
3115 "Gigabyte Technology Co., Ltd."),
3116 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
3117 },
3118 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
3119 },
3120 { } /* terminate list */
3121 };
3122#undef ENCODE_BUSDEVFN
3123 const struct dmi_system_id *dmi = dmi_first_match(sysids);
3124 unsigned int val;
3125
3126 if (!dmi)
3127 return false;
3128
3129 val = (unsigned long)dmi->driver_data;
3130
3131 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
3132}
3133
8e513217 3134#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 3135static void ahci_gtf_filter_workaround(struct ata_host *host)
3136{
3137 static const struct dmi_system_id sysids[] = {
3138 /*
3139 * Aspire 3810T issues a bunch of SATA enable commands
3140 * via _GTF including an invalid one and one which is
3141 * rejected by the device. Among the successful ones
3142 * is FPDMA non-zero offset enable which when enabled
3143 * only on the drive side leads to NCQ command
3144 * failures. Filter it out.
3145 */
3146 {
3147 .ident = "Aspire 3810T",
3148 .matches = {
3149 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
3150 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
3151 },
3152 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
3153 },
3154 { }
3155 };
3156 const struct dmi_system_id *dmi = dmi_first_match(sysids);
3157 unsigned int filter;
3158 int i;
3159
3160 if (!dmi)
3161 return;
3162
3163 filter = (unsigned long)dmi->driver_data;
3164 dev_printk(KERN_INFO, host->dev,
3165 "applying extra ACPI _GTF filter 0x%x for %s\n",
3166 filter, dmi->ident);
3167
3168 for (i = 0; i < host->n_ports; i++) {
3169 struct ata_port *ap = host->ports[i];
3170 struct ata_link *link;
3171 struct ata_device *dev;
3172
3173 ata_for_each_link(link, ap, EDGE)
3174 ata_for_each_dev(dev, link, ALL)
3175 dev->gtf_filter |= filter;
3176 }
3177}
8e513217
MT		 3178#else
3179static inline void ahci_gtf_filter_workaround(struct ata_host *host)
3180{}
3181#endif
f80ae7e4 3182
24dc5f33 3183static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 3184{
3185 static int printed_version;
e297d99e
TH		 3186 unsigned int board_id = ent->driver_data;
3187 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 3188 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 3189 struct device *dev = &pdev->dev;
1da177e4 3190 struct ahci_host_priv *hpriv;
4447d351 3191 struct ata_host *host;
837f5f8f 3192 int n_ports, i, rc;
1da177e4
LT		 3193
3194 VPRINTK("ENTER\n");
3195
12fad3f9
TH		 3196 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
3197
1da177e4 3198 if (!printed_version++)
a9524a76 3199 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 3200
5b66c829
AC		 3201 /* The AHCI driver can only drive the SATA ports, the PATA driver
3202 can drive them all so if both drivers are selected make sure
3203 AHCI stays out of the way */
3204 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
3205 return -ENODEV;
3206
7a02267e
MN		 3207 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
3208 * At the moment, we can only use the AHCI mode. Let the users know
3209 * that for SAS drives they're out of luck.
3210 */
3211 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
3212 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
3213 "can only drive SATA devices with this driver\n");
3214
4447d351 3215 /* acquire resources */
24dc5f33 3216 rc = pcim_enable_device(pdev);
1da177e4
LT		 3217 if (rc)
3218 return rc;
3219
dea55137
TH		 3220 /* AHCI controllers often implement SFF compatible interface.
3221 * Grab all PCI BARs just in case.
3222 */
3223 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 3224 if (rc == -EBUSY)
24dc5f33 3225 pcim_pin_device(pdev);
0d5ff566 3226 if (rc)
24dc5f33 3227 return rc;
1da177e4 3228
c4f7792c
TH		 3229 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
3230 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
3231 u8 map;
3232
3233 /* ICH6s share the same PCI ID for both piix and ahci
3234 * modes. Enabling ahci mode while MAP indicates
3235 * combined mode is a bad idea. Yield to ata_piix.
3236 */
3237 pci_read_config_byte(pdev, ICH_MAP, &map);
3238 if (map & 0x3) {
3239 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
3240 "combined mode, can't enable AHCI mode\n");
3241 return -ENODEV;
3242 }
3243 }
3244
24dc5f33
TH		 3245 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
3246 if (!hpriv)
3247 return -ENOMEM;
417a1a6d
TH		 3248 hpriv->flags |= (unsigned long)pi.private_data;
3249
e297d99e
TH		 3250 /* MCP65 revision A1 and A2 can't do MSI */
3251 if (board_id == board_ahci_mcp65 &&
3252 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
3253 hpriv->flags |= AHCI_HFLAG_NO_MSI;
3254
e427fe04
SH		 3255 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
3256 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
3257 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
3258
2fcad9d2
TH		 3259 /* only some SB600s can do 64bit DMA */
3260 if (ahci_sb600_enable_64bit(pdev))
3261 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 3262
31b239ad
TH		 3263 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
3264 pci_intx(pdev, 1);
1da177e4 3265
4447d351 3266 /* save initial config */
417a1a6d 3267 ahci_save_initial_config(pdev, hpriv);
1da177e4 3268
4447d351 3269 /* prepare host */
453d3131
RH		 3270 if (hpriv->cap & HOST_CAP_NCQ) {
3271 pi.flags |= ATA_FLAG_NCQ;
3272 /* Auto-activate optimization is supposed to be supported on
3273 all AHCI controllers indicating NCQ support, but it seems
3274 to be broken at least on some NVIDIA MCP79 chipsets.
3275 Until we get info on which NVIDIA chipsets don't have this
3276 issue, if any, disable AA on all NVIDIA AHCIs. */
3277 if (pdev->vendor != PCI_VENDOR_ID_NVIDIA)
3278 pi.flags |= ATA_FLAG_FPDMA_AA;
3279 }
1da177e4 3280
7d50b60b
TH		 3281 if (hpriv->cap & HOST_CAP_PMP)
3282 pi.flags |= ATA_FLAG_PMP;
3283
18f7ba4c
KCA		 3284 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
3285 u8 messages;
3286 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
3287 u32 em_loc = readl(mmio + HOST_EM_LOC);
3288 u32 em_ctl = readl(mmio + HOST_EM_CTL);
3289
87943acf 3290 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
18f7ba4c
KCA		 3291
3292 /* we only support LED message type right now */
3293 if ((messages & 0x01) && (ahci_em_messages == 1)) {
3294 /* store em_loc */
3295 hpriv->em_loc = ((em_loc >> 16) * 4);
3296 pi.flags |= ATA_FLAG_EM;
3297 if (!(em_ctl & EM_CTL_ALHD))
3298 pi.flags |= ATA_FLAG_SW_ACTIVITY;
3299 }
3300 }
3301
1fd68434
RW		 3302 if (ahci_broken_system_poweroff(pdev)) {
3303 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
3304 dev_info(&pdev->dev,
3305 "quirky BIOS, skipping spindown on poweroff\n");
3306 }
3307
9b10ae86
TH		 3308 if (ahci_broken_suspend(pdev)) {
3309 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
3310 dev_printk(KERN_WARNING, &pdev->dev,
3311 "BIOS update required for suspend/resume\n");
3312 }
3313
5594639a
TH		 3314 if (ahci_broken_online(pdev)) {
3315 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
3316 dev_info(&pdev->dev,
3317 "online status unreliable, applying workaround\n");
3318 }
3319
837f5f8f
TH		 3320 /* CAP.NP sometimes indicate the index of the last enabled
3321 * port, at other times, that of the last possible port, so
3322 * determining the maximum port number requires looking at
3323 * both CAP.NP and port_map.
3324 */
3325 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
3326
3327 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 3328 if (!host)
3329 return -ENOMEM;
3330 host->iomap = pcim_iomap_table(pdev);
3331 host->private_data = hpriv;
3332
f3d7f23f 3333 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 3334 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 3335 else
3336 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 3337
18f7ba4c
KCA		 3338 if (pi.flags & ATA_FLAG_EM)
3339 ahci_reset_em(host);
3340
4447d351 3341 for (i = 0; i < host->n_ports; i++) {
dab632e8 3342 struct ata_port *ap = host->ports[i];
4447d351 3343
cbcdd875
TH		 3344 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
3345 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
3346 0x100 + ap->port_no * 0x80, "port");
3347
31556594
KCA		 3348 /* set initial link pm policy */
3349 ap->pm_policy = NOT_AVAILABLE;
3350
18f7ba4c
KCA		 3351 /* set enclosure management message type */
3352 if (ap->flags & ATA_FLAG_EM)
3353 ap->em_message_type = ahci_em_messages;
3354
3355
dab632e8 3356 /* disabled/not-implemented port */
350756f6 3357 if (!(hpriv->port_map & (1 << i)))
dab632e8 3358 ap->ops = &ata_dummy_port_ops;
4447d351 3359 }
d447df14 3360
edc93052
TH		 3361 /* apply workaround for ASUS P5W DH Deluxe mainboard */
3362 ahci_p5wdh_workaround(host);
3363
f80ae7e4
TH		 3364 /* apply gtf filter quirk */
3365 ahci_gtf_filter_workaround(host);
3366
4447d351
TH		 3367 /* initialize adapter */
3368 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 3369 if (rc)
24dc5f33 3370 return rc;
1da177e4 3371
4447d351
TH		 3372 rc = ahci_reset_controller(host);
3373 if (rc)
3374 return rc;
1da177e4 3375
4447d351
TH		 3376 ahci_init_controller(host);
3377 ahci_print_info(host);
1da177e4 3378
4447d351
TH		 3379 pci_set_master(pdev);
3380 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
3381 &ahci_sht);
907f4678 3382}
1da177e4
LT		 3383
3384static int __init ahci_init(void)
3385{
b7887196 3386 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 3387}
3388
1da177e4
LT		 3389static void __exit ahci_exit(void)
3390{
3391 pci_unregister_driver(&ahci_pci_driver);
3392}
3393
3394
3395MODULE_AUTHOR("Jeff Garzik");
3396MODULE_DESCRIPTION("AHCI SATA low-level driver");
3397MODULE_LICENSE("GPL");
3398MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 3399MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 3400
3401module_init(ahci_init);
3402module_exit(ahci_exit);
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