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ata: ahci_tegra: Read calibration fuse
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
365cfa1e 48#include "ahci.h"
1da177e4
LT		 49
50#define DRV_NAME "ahci"
7d50b60b 51#define DRV_VERSION "3.0"
1da177e4 52
1da177e4 53enum {
318893e1 54 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 55 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
67809f85 63 board_ahci_noncq,
441577ef 64 board_ahci_nosntf,
5f173107 65 board_ahci_yes_fbs,
1da177e4 66
441577ef
TH		 67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
83f2b963
TH		 69 board_ahci_mcp77,
70 board_ahci_mcp89,
441577ef
TH		 71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
cb85696d
JL		 86static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 88static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
438ac6d5 90#ifdef CONFIG_PM
c1332875
TH		 91static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 93#endif
ad616ffb 94
fad16e7a
TH		 95static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97};
98
029cfd6b
TH		 99static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
a1efdaba 101 .hardreset = ahci_vt8251_hardreset,
029cfd6b 102};
edc93052 103
029cfd6b
TH		 104static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
a1efdaba 106 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 107};
108
98ac62de 109static const struct ata_port_info ahci_port_info[] = {
441577ef 110 /* by features */
facb8fa6 111 [board_ahci] = {
1188c0d8 112 .flags = AHCI_FLAG_COMMON,
14bdef98 113 .pio_mask = ATA_PIO4,
469248ab 114 .udma_mask = ATA_UDMA6,
1da177e4
LT		 115 .port_ops = &ahci_ops,
116 },
facb8fa6 117 [board_ahci_ign_iferr] = {
441577ef 118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
441577ef 122 .port_ops = &ahci_ops,
bf2af2a2 123 },
67809f85
LK		 124 [board_ahci_noncq] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
facb8fa6 131 [board_ahci_nosntf] = {
441577ef 132 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 133 .flags = AHCI_FLAG_COMMON,
14bdef98 134 .pio_mask = ATA_PIO4,
469248ab 135 .udma_mask = ATA_UDMA6,
41669553
TH		 136 .port_ops = &ahci_ops,
137 },
facb8fa6 138 [board_ahci_yes_fbs] = {
5f173107
TH		 139 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
441577ef 145 /* by chipsets */
facb8fa6 146 [board_ahci_mcp65] = {
83f2b963
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
ae01b249 149 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
facb8fa6 154 [board_ahci_mcp77] = {
83f2b963
TH		 155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
facb8fa6 161 [board_ahci_mcp89] = {
83f2b963 162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 163 .flags = AHCI_FLAG_COMMON,
14bdef98 164 .pio_mask = ATA_PIO4,
469248ab 165 .udma_mask = ATA_UDMA6,
441577ef 166 .port_ops = &ahci_ops,
55a61604 167 },
facb8fa6 168 [board_ahci_mv] = {
417a1a6d 169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 172 .pio_mask = ATA_PIO4,
cd70c266
JG		 173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
facb8fa6 176 [board_ahci_sb600] = {
441577ef
TH		 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 180 .flags = AHCI_FLAG_COMMON,
14bdef98 181 .pio_mask = ATA_PIO4,
e39fc8c9 182 .udma_mask = ATA_UDMA6,
345347c5 183 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 184 },
facb8fa6 185 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
345347c5 190 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 191 },
facb8fa6 192 [board_ahci_vt8251] = {
441577ef 193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
441577ef 197 .port_ops = &ahci_vt8251_ops,
1b677afd 198 },
1da177e4
LT		 199};
200
3b7d697d 201static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 202 /* Intel */
54bb3a94
JG		 203 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
204 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
205 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
206 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
207 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 208 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 209 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 213 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 214 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 215 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 230 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 232 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 233 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 234 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 235 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 237 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 238 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 239 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 240 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 241 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 242 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 243 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 249 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
250 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 252 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 253 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 254 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 260 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 261 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 269 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 277 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 293 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 295 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
296 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
300 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 303 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 304 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
fe7fa31a 308
e34bb370
TH		 309 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
310 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
311 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 312 /* JMicron 362B and 362C have an AHCI function with IDE class code */
313 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
314 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 315
316 /* ATI */
c65ec1c2 317 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 318 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
319 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
320 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
321 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
322 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
323 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 324
e2dd90b1 325 /* AMD */
5deab536 326 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 327 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 328 /* AMD is using RAID class only for ahci controllers */
329 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
330 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
331
fe7fa31a 332 /* VIA */
54bb3a94 333 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 334 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 335
336 /* NVIDIA */
e297d99e
TH		 337 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
338 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
339 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
340 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
341 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
342 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
343 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
344 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 345 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
349 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
350 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
351 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
352 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
377 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
378 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
379 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
380 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
389 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
390 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
391 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
401 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
402 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
403 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
404 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
412 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
413 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
414 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
415 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
416 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 421
95916edd 422 /* SiS */
20e2de4a
TH		 423 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
424 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
425 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 426
318893e1
AR		 427 /* ST Microelectronics */
428 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
429
cd70c266
JG		 430 /* Marvell */
431 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 432 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 433 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 434 .class = PCI_CLASS_STORAGE_SATA_AHCI,
435 .class_mask = 0xffffff,
5f173107 436 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 437 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 438 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 439 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
440 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
441 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 442 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 443 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35
GS		 444 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
445 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 446 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 447 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 448 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
449 .driver_data = board_ahci_yes_fbs },
69fd3157 450 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 451 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 452 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
453 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 454 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
455 .driver_data = board_ahci_yes_fbs },
cd70c266 456
c77a036b
MN		 457 /* Promise */
458 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 459 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 460
c9703765 461 /* Asmedia */
7b4f6eca
AC		 462 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
463 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
464 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
465 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 466
67809f85
LK		 467 /*
468 * Samsung SSDs found on some macbooks. NCQ times out.
469 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
470 */
471 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
472
7f9c9f8e
HD		 473 /* Enmotus */
474 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
475
415ae2b5
JG		 476 /* Generic, PCI class code for AHCI */
477 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 478 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 479
1da177e4
LT		 480 { } /* terminate list */
481};
482
483
484static struct pci_driver ahci_pci_driver = {
485 .name = DRV_NAME,
486 .id_table = ahci_pci_tbl,
487 .probe = ahci_init_one,
24dc5f33 488 .remove = ata_pci_remove_one,
438ac6d5 489#ifdef CONFIG_PM
c1332875 490 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 491 .resume = ahci_pci_device_resume,
492#endif
493};
1da177e4 494
365cfa1e
AV		 495#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
496static int marvell_enable;
497#else
498static int marvell_enable = 1;
499#endif
500module_param(marvell_enable, int, 0644);
501MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 502
1da177e4 503
365cfa1e
AV		 504static void ahci_pci_save_initial_config(struct pci_dev *pdev,
505 struct ahci_host_priv *hpriv)
506{
507 unsigned int force_port_map = 0;
508 unsigned int mask_port_map = 0;
67846b30 509
365cfa1e
AV		 510 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
511 dev_info(&pdev->dev, "JMB361 has only one port\n");
512 force_port_map = 1;
1da177e4
LT		 513 }
514
365cfa1e
AV		 515 /*
516 * Temporary Marvell 6145 hack: PATA port presence
517 * is asserted through the standard AHCI port
518 * presence register, as bit 4 (counting from 0)
d28f87aa 519 */
365cfa1e
AV		 520 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
521 if (pdev->device == 0x6121)
522 mask_port_map = 0x3;
523 else
524 mask_port_map = 0xf;
525 dev_info(&pdev->dev,
526 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
527 }
1da177e4 528
725c7b57 529 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 530}
531
365cfa1e 532static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 533{
365cfa1e 534 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 535
365cfa1e 536 ahci_reset_controller(host);
1da177e4 537
365cfa1e
AV		 538 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
539 struct ahci_host_priv *hpriv = host->private_data;
540 u16 tmp16;
d6ef3153 541
365cfa1e
AV		 542 /* configure PCS */
543 pci_read_config_word(pdev, 0x92, &tmp16);
544 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
545 tmp16 |= hpriv->port_map;
546 pci_write_config_word(pdev, 0x92, tmp16);
547 }
d6ef3153
SH		 548 }
549
1da177e4
LT		 550 return 0;
551}
552
365cfa1e 553static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 554{
365cfa1e
AV		 555 struct ahci_host_priv *hpriv = host->private_data;
556 struct pci_dev *pdev = to_pci_dev(host->dev);
557 void __iomem *port_mmio;
78cd52d0 558 u32 tmp;
365cfa1e 559 int mv;
78cd52d0 560
365cfa1e
AV		 561 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
562 if (pdev->device == 0x6121)
563 mv = 2;
564 else
565 mv = 4;
566 port_mmio = __ahci_port_base(host, mv);
78cd52d0 567
365cfa1e 568 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 569
365cfa1e
AV		 570 /* clear port IRQ */
571 tmp = readl(port_mmio + PORT_IRQ_STAT);
572 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
573 if (tmp)
574 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 575 }
576
365cfa1e 577 ahci_init_controller(host);
edc93052
TH		 578}
579
365cfa1e
AV		 580static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
581 unsigned long deadline)
d6ef3153 582{
365cfa1e 583 struct ata_port *ap = link->ap;
039ece38 584 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 585 bool online;
d6ef3153
SH		 586 int rc;
587
365cfa1e 588 DPRINTK("ENTER\n");
d6ef3153 589
365cfa1e 590 ahci_stop_engine(ap);
d6ef3153 591
365cfa1e
AV		 592 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
593 deadline, &online, NULL);
d6ef3153 594
039ece38 595 hpriv->start_engine(ap);
d6ef3153 596
365cfa1e 597 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 598
365cfa1e
AV		 599 /* vt8251 doesn't clear BSY on signature FIS reception,
600 * request follow-up softreset.
601 */
602 return online ? -EAGAIN : rc;
7d50b60b
TH		 603}
604
365cfa1e
AV		 605static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
606 unsigned long deadline)
7d50b60b 607{
365cfa1e 608 struct ata_port *ap = link->ap;
1c954a4d 609 struct ahci_port_priv *pp = ap->private_data;
039ece38 610 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 611 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
612 struct ata_taskfile tf;
613 bool online;
614 int rc;
7d50b60b 615
365cfa1e 616 ahci_stop_engine(ap);
028a2596 617
365cfa1e
AV		 618 /* clear D2H reception area to properly wait for D2H FIS */
619 ata_tf_init(link->device, &tf);
9bbb1b0e 620 tf.command = ATA_BUSY;
365cfa1e 621 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 622
365cfa1e
AV		 623 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
624 deadline, &online, NULL);
028a2596 625
039ece38 626 hpriv->start_engine(ap);
c1332875 627
365cfa1e
AV		 628 /* The pseudo configuration device on SIMG4726 attached to
629 * ASUS P5W-DH Deluxe doesn't send signature FIS after
630 * hardreset if no device is attached to the first downstream
631 * port && the pseudo device locks up on SRST w/ PMP==0. To
632 * work around this, wait for !BSY only briefly. If BSY isn't
633 * cleared, perform CLO and proceed to IDENTIFY (achieved by
634 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
635 *
636 * Wait for two seconds. Devices attached to downstream port
637 * which can't process the following IDENTIFY after this will
638 * have to be reset again. For most cases, this should
639 * suffice while making probing snappish enough.
640 */
641 if (online) {
642 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
643 ahci_check_ready);
644 if (rc)
645 ahci_kick_engine(ap);
c1332875 646 }
c1332875
TH		 647 return rc;
648}
649
365cfa1e 650#ifdef CONFIG_PM
c1332875
TH		 651static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
652{
0a86e1c8 653 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 654 struct ahci_host_priv *hpriv = host->private_data;
d8993349 655 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 656 u32 ctl;
657
9b10ae86
TH		 658 if (mesg.event & PM_EVENT_SUSPEND &&
659 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 660 dev_err(&pdev->dev,
661 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 662 return -EIO;
663 }
664
3a2d5b70 665 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 666 /* AHCI spec rev1.1 section 8.3.3:
667 * Software must disable interrupts prior to requesting a
668 * transition of the HBA to D3 state.
669 */
670 ctl = readl(mmio + HOST_CTL);
671 ctl &= ~HOST_IRQ_EN;
672 writel(ctl, mmio + HOST_CTL);
673 readl(mmio + HOST_CTL); /* flush */
674 }
675
676 return ata_pci_device_suspend(pdev, mesg);
677}
678
679static int ahci_pci_device_resume(struct pci_dev *pdev)
680{
0a86e1c8 681 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 682 int rc;
683
553c4aa6
TH		 684 rc = ata_pci_device_do_resume(pdev);
685 if (rc)
686 return rc;
c1332875 687
cb85696d
JL		 688 /* Apple BIOS helpfully mangles the registers on resume */
689 if (is_mcp89_apple(pdev))
690 ahci_mcp89_apple_enable(pdev);
691
c1332875 692 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 693 rc = ahci_pci_reset_controller(host);
c1332875
TH		 694 if (rc)
695 return rc;
696
781d6550 697 ahci_pci_init_controller(host);
c1332875
TH		 698 }
699
cca3974e 700 ata_host_resume(host);
c1332875
TH		 701
702 return 0;
703}
438ac6d5 704#endif
c1332875 705
4447d351 706static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 707{
1da177e4 708 int rc;
1da177e4 709
318893e1
AR		 710 /*
711 * If the device fixup already set the dma_mask to some non-standard
712 * value, don't extend it here. This happens on STA2X11, for example.
713 */
714 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
715 return 0;
716
1da177e4 717 if (using_dac &&
6a35528a
YH		 718 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
719 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 720 if (rc) {
284901a9 721 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 722 if (rc) {
a44fec1f
JP		 723 dev_err(&pdev->dev,
724 "64-bit DMA enable failed\n");
1da177e4
LT		 725 return rc;
726 }
727 }
1da177e4 728 } else {
284901a9 729 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 730 if (rc) {
a44fec1f 731 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 732 return rc;
733 }
284901a9 734 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 735 if (rc) {
a44fec1f
JP		 736 dev_err(&pdev->dev,
737 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 738 return rc;
739 }
740 }
1da177e4
LT		 741 return 0;
742}
743
439fcaec
AV		 744static void ahci_pci_print_info(struct ata_host *host)
745{
746 struct pci_dev *pdev = to_pci_dev(host->dev);
747 u16 cc;
748 const char *scc_s;
749
750 pci_read_config_word(pdev, 0x0a, &cc);
751 if (cc == PCI_CLASS_STORAGE_IDE)
752 scc_s = "IDE";
753 else if (cc == PCI_CLASS_STORAGE_SATA)
754 scc_s = "SATA";
755 else if (cc == PCI_CLASS_STORAGE_RAID)
756 scc_s = "RAID";
757 else
758 scc_s = "unknown";
759
760 ahci_print_info(host, scc_s);
761}
762
edc93052
TH		 763/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
764 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
765 * support PMP and the 4726 either directly exports the device
766 * attached to the first downstream port or acts as a hardware storage
767 * controller and emulate a single ATA device (can be RAID 0/1 or some
768 * other configuration).
769 *
770 * When there's no device attached to the first downstream port of the
771 * 4726, "Config Disk" appears, which is a pseudo ATA device to
772 * configure the 4726. However, ATA emulation of the device is very
773 * lame. It doesn't send signature D2H Reg FIS after the initial
774 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
775 *
776 * The following function works around the problem by always using
777 * hardreset on the port and not depending on receiving signature FIS
778 * afterward. If signature FIS isn't received soon, ATA class is
779 * assumed without follow-up softreset.
780 */
781static void ahci_p5wdh_workaround(struct ata_host *host)
782{
783 static struct dmi_system_id sysids[] = {
784 {
785 .ident = "P5W DH Deluxe",
786 .matches = {
787 DMI_MATCH(DMI_SYS_VENDOR,
788 "ASUSTEK COMPUTER INC"),
789 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
790 },
791 },
792 { }
793 };
794 struct pci_dev *pdev = to_pci_dev(host->dev);
795
796 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
797 dmi_check_system(sysids)) {
798 struct ata_port *ap = host->ports[1];
799
a44fec1f
JP		 800 dev_info(&pdev->dev,
801 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 802
803 ap->ops = &ahci_p5wdh_ops;
804 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
805 }
806}
807
cb85696d
JL		 808/*
809 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
810 * booting in BIOS compatibility mode. We restore the registers but not ID.
811 */
812static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
813{
814 u32 val;
815
816 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
817
818 pci_read_config_dword(pdev, 0xf8, &val);
819 val |= 1 << 0x1b;
820 /* the following changes the device ID, but appears not to affect function */
821 /* val = (val & ~0xf0000000) | 0x80000000; */
822 pci_write_config_dword(pdev, 0xf8, val);
823
824 pci_read_config_dword(pdev, 0x54c, &val);
825 val |= 1 << 0xc;
826 pci_write_config_dword(pdev, 0x54c, val);
827
828 pci_read_config_dword(pdev, 0x4a4, &val);
829 val &= 0xff;
830 val |= 0x01060100;
831 pci_write_config_dword(pdev, 0x4a4, val);
832
833 pci_read_config_dword(pdev, 0x54c, &val);
834 val &= ~(1 << 0xc);
835 pci_write_config_dword(pdev, 0x54c, val);
836
837 pci_read_config_dword(pdev, 0xf8, &val);
838 val &= ~(1 << 0x1b);
839 pci_write_config_dword(pdev, 0xf8, val);
840}
841
842static bool is_mcp89_apple(struct pci_dev *pdev)
843{
844 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
845 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
846 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
847 pdev->subsystem_device == 0xcb89;
848}
849
2fcad9d2
TH		 850/* only some SB600 ahci controllers can do 64bit DMA */
851static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 852{
853 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 854 /*
855 * The oldest version known to be broken is 0901 and
856 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 857 * Enable 64bit DMA on 1501 and anything newer.
858 *
03d783bf
TH		 859 * Please read bko#9412 for more info.
860 */
58a09b38
SH		 861 {
862 .ident = "ASUS M2A-VM",
863 .matches = {
864 DMI_MATCH(DMI_BOARD_VENDOR,
865 "ASUSTeK Computer INC."),
866 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
867 },
03d783bf 868 .driver_data = "20071026", /* yyyymmdd */
58a09b38 869 },
e65cc194
MN		 870 /*
871 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
872 * support 64bit DMA.
873 *
874 * BIOS versions earlier than 1.5 had the Manufacturer DMI
875 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
876 * This spelling mistake was fixed in BIOS version 1.5, so
877 * 1.5 and later have the Manufacturer as
878 * "MICRO-STAR INTERNATIONAL CO.,LTD".
879 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
880 *
881 * BIOS versions earlier than 1.9 had a Board Product Name
882 * DMI field of "MS-7376". This was changed to be
883 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
884 * match on DMI_BOARD_NAME of "MS-7376".
885 */
886 {
887 .ident = "MSI K9A2 Platinum",
888 .matches = {
889 DMI_MATCH(DMI_BOARD_VENDOR,
890 "MICRO-STAR INTER"),
891 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
892 },
893 },
ff0173c1
MN		 894 /*
895 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
896 * 64bit DMA.
897 *
898 * This board also had the typo mentioned above in the
899 * Manufacturer DMI field (fixed in BIOS version 1.5), so
900 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
901 */
902 {
903 .ident = "MSI K9AGM2",
904 .matches = {
905 DMI_MATCH(DMI_BOARD_VENDOR,
906 "MICRO-STAR INTER"),
907 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
908 },
909 },
3c4aa91f
MN		 910 /*
911 * All BIOS versions for the Asus M3A support 64bit DMA.
912 * (all release versions from 0301 to 1206 were tested)
913 */
914 {
915 .ident = "ASUS M3A",
916 .matches = {
917 DMI_MATCH(DMI_BOARD_VENDOR,
918 "ASUSTeK Computer INC."),
919 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
920 },
921 },
58a09b38
SH		 922 { }
923 };
03d783bf 924 const struct dmi_system_id *match;
2fcad9d2
TH		 925 int year, month, date;
926 char buf[9];
58a09b38 927
03d783bf 928 match = dmi_first_match(sysids);
58a09b38 929 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 930 !match)
58a09b38
SH		 931 return false;
932
e65cc194
MN		 933 if (!match->driver_data)
934 goto enable_64bit;
935
2fcad9d2
TH		 936 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
937 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 938
e65cc194
MN		 939 if (strcmp(buf, match->driver_data) >= 0)
940 goto enable_64bit;
941 else {
a44fec1f
JP		 942 dev_warn(&pdev->dev,
943 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
944 match->ident);
2fcad9d2
TH		 945 return false;
946 }
e65cc194
MN		 947
948enable_64bit:
a44fec1f 949 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 950 return true;
58a09b38
SH		 951}
952
1fd68434
RW		 953static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
954{
955 static const struct dmi_system_id broken_systems[] = {
956 {
957 .ident = "HP Compaq nx6310",
958 .matches = {
959 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
960 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
961 },
962 /* PCI slot number of the controller */
963 .driver_data = (void *)0x1FUL,
964 },
d2f9c061
MR		 965 {
966 .ident = "HP Compaq 6720s",
967 .matches = {
968 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
969 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
970 },
971 /* PCI slot number of the controller */
972 .driver_data = (void *)0x1FUL,
973 },
1fd68434
RW		 974
975 { } /* terminate list */
976 };
977 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
978
979 if (dmi) {
980 unsigned long slot = (unsigned long)dmi->driver_data;
981 /* apply the quirk only to on-board controllers */
982 return slot == PCI_SLOT(pdev->devfn);
983 }
984
985 return false;
986}
987
9b10ae86
TH		 988static bool ahci_broken_suspend(struct pci_dev *pdev)
989{
990 static const struct dmi_system_id sysids[] = {
991 /*
992 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
993 * to the harddisk doesn't become online after
994 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 995 *
996 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
997 *
998 * Use dates instead of versions to match as HP is
999 * apparently recycling both product and version
1000 * strings.
1001 *
1002 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1003 */
1004 {
1005 .ident = "dv4",
1006 .matches = {
1007 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1008 DMI_MATCH(DMI_PRODUCT_NAME,
1009 "HP Pavilion dv4 Notebook PC"),
1010 },
9deb3431 1011 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1012 },
1013 {
1014 .ident = "dv5",
1015 .matches = {
1016 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1017 DMI_MATCH(DMI_PRODUCT_NAME,
1018 "HP Pavilion dv5 Notebook PC"),
1019 },
9deb3431 1020 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1021 },
1022 {
1023 .ident = "dv6",
1024 .matches = {
1025 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1026 DMI_MATCH(DMI_PRODUCT_NAME,
1027 "HP Pavilion dv6 Notebook PC"),
1028 },
9deb3431 1029 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1030 },
1031 {
1032 .ident = "HDX18",
1033 .matches = {
1034 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1035 DMI_MATCH(DMI_PRODUCT_NAME,
1036 "HP HDX18 Notebook PC"),
1037 },
9deb3431 1038 .driver_data = "20090430", /* F.23 */
9b10ae86 1039 },
cedc9bf9
TH		 1040 /*
1041 * Acer eMachines G725 has the same problem. BIOS
1042 * V1.03 is known to be broken. V3.04 is known to
25985edc 1043 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1044 * that we don't have much idea about. For now,
1045 * blacklist anything older than V3.04.
9deb3431
TH		 1046 *
1047 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1048 */
1049 {
1050 .ident = "G725",
1051 .matches = {
1052 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1053 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1054 },
9deb3431 1055 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1056 },
9b10ae86
TH		 1057 { } /* terminate list */
1058 };
1059 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1060 int year, month, date;
1061 char buf[9];
9b10ae86
TH		 1062
1063 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1064 return false;
1065
9deb3431
TH		 1066 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1067 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1068
9deb3431 1069 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1070}
1071
5594639a
TH		 1072static bool ahci_broken_online(struct pci_dev *pdev)
1073{
1074#define ENCODE_BUSDEVFN(bus, slot, func) \
1075 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1076 static const struct dmi_system_id sysids[] = {
1077 /*
1078 * There are several gigabyte boards which use
1079 * SIMG5723s configured as hardware RAID. Certain
1080 * 5723 firmware revisions shipped there keep the link
1081 * online but fail to answer properly to SRST or
1082 * IDENTIFY when no device is attached downstream
1083 * causing libata to retry quite a few times leading
1084 * to excessive detection delay.
1085 *
1086 * As these firmwares respond to the second reset try
1087 * with invalid device signature, considering unknown
1088 * sig as offline works around the problem acceptably.
1089 */
1090 {
1091 .ident = "EP45-DQ6",
1092 .matches = {
1093 DMI_MATCH(DMI_BOARD_VENDOR,
1094 "Gigabyte Technology Co., Ltd."),
1095 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1096 },
1097 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1098 },
1099 {
1100 .ident = "EP45-DS5",
1101 .matches = {
1102 DMI_MATCH(DMI_BOARD_VENDOR,
1103 "Gigabyte Technology Co., Ltd."),
1104 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1105 },
1106 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1107 },
1108 { } /* terminate list */
1109 };
1110#undef ENCODE_BUSDEVFN
1111 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1112 unsigned int val;
1113
1114 if (!dmi)
1115 return false;
1116
1117 val = (unsigned long)dmi->driver_data;
1118
1119 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1120}
1121
0cf4a7d6
JP		 1122static bool ahci_broken_devslp(struct pci_dev *pdev)
1123{
1124 /* device with broken DEVSLP but still showing SDS capability */
1125 static const struct pci_device_id ids[] = {
1126 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1127 {}
1128 };
1129
1130 return pci_match_id(ids, pdev);
1131}
1132
8e513217 1133#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1134static void ahci_gtf_filter_workaround(struct ata_host *host)
1135{
1136 static const struct dmi_system_id sysids[] = {
1137 /*
1138 * Aspire 3810T issues a bunch of SATA enable commands
1139 * via _GTF including an invalid one and one which is
1140 * rejected by the device. Among the successful ones
1141 * is FPDMA non-zero offset enable which when enabled
1142 * only on the drive side leads to NCQ command
1143 * failures. Filter it out.
1144 */
1145 {
1146 .ident = "Aspire 3810T",
1147 .matches = {
1148 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1149 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1150 },
1151 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1152 },
1153 { }
1154 };
1155 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1156 unsigned int filter;
1157 int i;
1158
1159 if (!dmi)
1160 return;
1161
1162 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1163 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1164 filter, dmi->ident);
f80ae7e4
TH		 1165
1166 for (i = 0; i < host->n_ports; i++) {
1167 struct ata_port *ap = host->ports[i];
1168 struct ata_link *link;
1169 struct ata_device *dev;
1170
1171 ata_for_each_link(link, ap, EDGE)
1172 ata_for_each_dev(dev, link, ALL)
1173 dev->gtf_filter |= filter;
1174 }
1175}
8e513217
MT		 1176#else
1177static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1178{}
1179#endif
f80ae7e4 1180
e1ba8459 1181static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
ab0f9e78 1182 struct ahci_host_priv *hpriv)
5ca72c4f 1183{
ccf8f53c 1184 int rc, nvec;
5ca72c4f 1185
7b92b4f6
AG		 1186 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1187 goto intx;
1188
fc061d96
AG		 1189 nvec = pci_msi_vec_count(pdev);
1190 if (nvec < 0)
7b92b4f6
AG		 1191 goto intx;
1192
1193 /*
1194 * If number of MSIs is less than number of ports then Sharing Last
1195 * Message mode could be enforced. In this case assume that advantage
1196 * of multipe MSIs is negated and use single MSI mode instead.
1197 */
fc061d96 1198 if (nvec < n_ports)
7b92b4f6
AG		 1199 goto single_msi;
1200
ccf8f53c
AG		 1201 rc = pci_enable_msi_exact(pdev, nvec);
1202 if (rc == -ENOSPC)
fc40363b 1203 goto single_msi;
ccf8f53c 1204 else if (rc < 0)
fc061d96 1205 goto intx;
5ca72c4f 1206
ab0f9e78
AG		 1207 /* fallback to single MSI mode if the controller enforced MRSM mode */
1208 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1209 pci_disable_msi(pdev);
1210 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1211 goto single_msi;
1212 }
1213
7b92b4f6
AG		 1214 return nvec;
1215
1216single_msi:
fc061d96 1217 if (pci_enable_msi(pdev))
7b92b4f6
AG		 1218 goto intx;
1219 return 1;
1220
1221intx:
5ca72c4f
AG		 1222 pci_intx(pdev, 1);
1223 return 0;
1224}
1225
1226/**
1227 * ahci_host_activate - start AHCI host, request IRQs and register it
1228 * @host: target ATA host
1229 * @irq: base IRQ number to request
1230 * @n_msis: number of MSIs allocated for this host
1231 * @irq_handler: irq_handler used when requesting IRQs
1232 * @irq_flags: irq_flags used when requesting IRQs
1233 *
1234 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1235 * when multiple MSIs were allocated. That is one MSI per port, starting
1236 * from @irq.
1237 *
1238 * LOCKING:
1239 * Inherited from calling layer (may sleep).
1240 *
1241 * RETURNS:
1242 * 0 on success, -errno otherwise.
1243 */
1244int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1245{
1246 int i, rc;
1247
1248 /* Sharing Last Message among several ports is not supported */
1249 if (n_msis < host->n_ports)
1250 return -EINVAL;
1251
1252 rc = ata_host_start(host);
1253 if (rc)
1254 return rc;
1255
1256 for (i = 0; i < host->n_ports; i++) {
b29900e6
AG		 1257 struct ahci_port_priv *pp = host->ports[i]->private_data;
1258
2cf532f5
AG		 1259 /* Do not receive interrupts sent by dummy ports */
1260 if (!pp) {
1261 disable_irq(irq + i);
1262 continue;
1263 }
1264
1265 rc = devm_request_threaded_irq(host->dev, irq + i,
1266 ahci_hw_interrupt,
1267 ahci_thread_fn, IRQF_SHARED,
1268 pp->irq_desc, host->ports[i]);
5ca72c4f
AG		 1269 if (rc)
1270 goto out_free_irqs;
1271 }
1272
1273 for (i = 0; i < host->n_ports; i++)
1274 ata_port_desc(host->ports[i], "irq %d", irq + i);
1275
1276 rc = ata_host_register(host, &ahci_sht);
1277 if (rc)
1278 goto out_free_all_irqs;
1279
1280 return 0;
1281
1282out_free_all_irqs:
1283 i = host->n_ports;
1284out_free_irqs:
1285 for (i--; i >= 0; i--)
1286 devm_free_irq(host->dev, irq + i, host->ports[i]);
1287
1288 return rc;
1289}
1290
24dc5f33 1291static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1292{
e297d99e
TH		 1293 unsigned int board_id = ent->driver_data;
1294 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1295 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1296 struct device *dev = &pdev->dev;
1da177e4 1297 struct ahci_host_priv *hpriv;
4447d351 1298 struct ata_host *host;
5ca72c4f 1299 int n_ports, n_msis, i, rc;
318893e1 1300 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1301
1302 VPRINTK("ENTER\n");
1303
b429dd59 1304 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1305
06296a1e 1306 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1307
5b66c829
AC		 1308 /* The AHCI driver can only drive the SATA ports, the PATA driver
1309 can drive them all so if both drivers are selected make sure
1310 AHCI stays out of the way */
1311 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1312 return -ENODEV;
1313
cb85696d
JL		 1314 /* Apple BIOS on MCP89 prevents us using AHCI */
1315 if (is_mcp89_apple(pdev))
1316 ahci_mcp89_apple_enable(pdev);
c6353b45 1317
7a02267e
MN		 1318 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1319 * At the moment, we can only use the AHCI mode. Let the users know
1320 * that for SAS drives they're out of luck.
1321 */
1322 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1323 dev_info(&pdev->dev,
1324 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1325
7f9c9f8e 1326 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1327 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1328 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1329 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1330 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1331
4447d351 1332 /* acquire resources */
24dc5f33 1333 rc = pcim_enable_device(pdev);
1da177e4
LT		 1334 if (rc)
1335 return rc;
1336
c4f7792c
TH		 1337 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1338 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1339 u8 map;
1340
1341 /* ICH6s share the same PCI ID for both piix and ahci
1342 * modes. Enabling ahci mode while MAP indicates
1343 * combined mode is a bad idea. Yield to ata_piix.
1344 */
1345 pci_read_config_byte(pdev, ICH_MAP, &map);
1346 if (map & 0x3) {
a44fec1f
JP		 1347 dev_info(&pdev->dev,
1348 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1349 return -ENODEV;
1350 }
1351 }
1352
6fec8871
PB		 1353 /* AHCI controllers often implement SFF compatible interface.
1354 * Grab all PCI BARs just in case.
1355 */
1356 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1357 if (rc == -EBUSY)
1358 pcim_pin_device(pdev);
1359 if (rc)
1360 return rc;
1361
24dc5f33
TH		 1362 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1363 if (!hpriv)
1364 return -ENOMEM;
417a1a6d
TH		 1365 hpriv->flags |= (unsigned long)pi.private_data;
1366
e297d99e
TH		 1367 /* MCP65 revision A1 and A2 can't do MSI */
1368 if (board_id == board_ahci_mcp65 &&
1369 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1370 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1371
e427fe04
SH		 1372 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1373 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1374 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1375
2fcad9d2
TH		 1376 /* only some SB600s can do 64bit DMA */
1377 if (ahci_sb600_enable_64bit(pdev))
1378 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1379
318893e1 1380 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1381
0cf4a7d6
JP		 1382 /* must set flag prior to save config in order to take effect */
1383 if (ahci_broken_devslp(pdev))
1384 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1385
4447d351 1386 /* save initial config */
394d6e53 1387 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1388
4447d351 1389 /* prepare host */
453d3131
RH		 1390 if (hpriv->cap & HOST_CAP_NCQ) {
1391 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1392 /*
1393 * Auto-activate optimization is supposed to be
1394 * supported on all AHCI controllers indicating NCQ
1395 * capability, but it seems to be broken on some
1396 * chipsets including NVIDIAs.
1397 */
1398 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1399 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1400
1401 /*
1402 * All AHCI controllers should be forward-compatible
1403 * with the new auxiliary field. This code should be
1404 * conditionalized if any buggy AHCI controllers are
1405 * encountered.
1406 */
1407 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1408 }
1da177e4 1409
7d50b60b
TH		 1410 if (hpriv->cap & HOST_CAP_PMP)
1411 pi.flags |= ATA_FLAG_PMP;
1412
0cbb0e77 1413 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1414
1fd68434
RW		 1415 if (ahci_broken_system_poweroff(pdev)) {
1416 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1417 dev_info(&pdev->dev,
1418 "quirky BIOS, skipping spindown on poweroff\n");
1419 }
1420
9b10ae86
TH		 1421 if (ahci_broken_suspend(pdev)) {
1422 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1423 dev_warn(&pdev->dev,
1424 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1425 }
1426
5594639a
TH		 1427 if (ahci_broken_online(pdev)) {
1428 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1429 dev_info(&pdev->dev,
1430 "online status unreliable, applying workaround\n");
1431 }
1432
837f5f8f
TH		 1433 /* CAP.NP sometimes indicate the index of the last enabled
1434 * port, at other times, that of the last possible port, so
1435 * determining the maximum port number requires looking at
1436 * both CAP.NP and port_map.
1437 */
1438 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1439
7b92b4f6
AG		 1440 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1441 if (n_msis > 1)
1442 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1443
837f5f8f 1444 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1445 if (!host)
1446 return -ENOMEM;
4447d351
TH		 1447 host->private_data = hpriv;
1448
f3d7f23f 1449 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1450 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1451 else
d2782d96 1452 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1453
18f7ba4c
KCA		 1454 if (pi.flags & ATA_FLAG_EM)
1455 ahci_reset_em(host);
1456
4447d351 1457 for (i = 0; i < host->n_ports; i++) {
dab632e8 1458 struct ata_port *ap = host->ports[i];
4447d351 1459
318893e1
AR		 1460 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1461 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1462 0x100 + ap->port_no * 0x80, "port");
1463
18f7ba4c
KCA		 1464 /* set enclosure management message type */
1465 if (ap->flags & ATA_FLAG_EM)
008dbd61 1466 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1467
1468
dab632e8 1469 /* disabled/not-implemented port */
350756f6 1470 if (!(hpriv->port_map & (1 << i)))
dab632e8 1471 ap->ops = &ata_dummy_port_ops;
4447d351 1472 }
d447df14 1473
edc93052
TH		 1474 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1475 ahci_p5wdh_workaround(host);
1476
f80ae7e4
TH		 1477 /* apply gtf filter quirk */
1478 ahci_gtf_filter_workaround(host);
1479
4447d351
TH		 1480 /* initialize adapter */
1481 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1482 if (rc)
24dc5f33 1483 return rc;
1da177e4 1484
3303040d 1485 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1486 if (rc)
1487 return rc;
1da177e4 1488
781d6550 1489 ahci_pci_init_controller(host);
439fcaec 1490 ahci_pci_print_info(host);
1da177e4 1491
4447d351 1492 pci_set_master(pdev);
5ca72c4f
AG		 1493
1494 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1495 return ahci_host_activate(host, pdev->irq, n_msis);
1496
4447d351
TH		 1497 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1498 &ahci_sht);
907f4678 1499}
1da177e4 1500
2fc75da0 1501module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1502
1503MODULE_AUTHOR("Jeff Garzik");
1504MODULE_DESCRIPTION("AHCI SATA low-level driver");
1505MODULE_LICENSE("GPL");
1506MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1507MODULE_VERSION(DRV_VERSION);
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