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ata: Disabling the async PM for JMicron chip 363/361
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
1da177e4
LT		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
87507cfd 41#include <linux/dma-mapping.h>
a9524a76 42#include <linux/device.h>
edc93052 43#include <linux/dmi.h>
5a0e3ad6 44#include <linux/gfp.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
365cfa1e 48#include "ahci.h"
1da177e4
LT		 49
50#define DRV_NAME "ahci"
7d50b60b 51#define DRV_VERSION "3.0"
1da177e4 52
1da177e4 53enum {
318893e1 54 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 55 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
67809f85 63 board_ahci_noncq,
441577ef 64 board_ahci_nosntf,
5f173107 65 board_ahci_yes_fbs,
1da177e4 66
441577ef
TH		 67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
83f2b963
TH		 69 board_ahci_mcp77,
70 board_ahci_mcp89,
441577ef
TH		 71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
cb85696d
JL		 86static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87static bool is_mcp89_apple(struct pci_dev *pdev);
a1efdaba
TH		 88static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
438ac6d5 90#ifdef CONFIG_PM
c1332875
TH		 91static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 93#endif
ad616ffb 94
fad16e7a
TH		 95static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97};
98
029cfd6b
TH		 99static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
a1efdaba 101 .hardreset = ahci_vt8251_hardreset,
029cfd6b 102};
edc93052 103
029cfd6b
TH		 104static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
a1efdaba 106 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 107};
108
98ac62de 109static const struct ata_port_info ahci_port_info[] = {
441577ef 110 /* by features */
facb8fa6 111 [board_ahci] = {
1188c0d8 112 .flags = AHCI_FLAG_COMMON,
14bdef98 113 .pio_mask = ATA_PIO4,
469248ab 114 .udma_mask = ATA_UDMA6,
1da177e4
LT		 115 .port_ops = &ahci_ops,
116 },
facb8fa6 117 [board_ahci_ign_iferr] = {
441577ef 118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 119 .flags = AHCI_FLAG_COMMON,
14bdef98 120 .pio_mask = ATA_PIO4,
469248ab 121 .udma_mask = ATA_UDMA6,
441577ef 122 .port_ops = &ahci_ops,
bf2af2a2 123 },
67809f85
LK		 124 [board_ahci_noncq] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
facb8fa6 131 [board_ahci_nosntf] = {
441577ef 132 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 133 .flags = AHCI_FLAG_COMMON,
14bdef98 134 .pio_mask = ATA_PIO4,
469248ab 135 .udma_mask = ATA_UDMA6,
41669553
TH		 136 .port_ops = &ahci_ops,
137 },
facb8fa6 138 [board_ahci_yes_fbs] = {
5f173107
TH		 139 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
441577ef 145 /* by chipsets */
facb8fa6 146 [board_ahci_mcp65] = {
83f2b963
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
ae01b249 149 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
facb8fa6 154 [board_ahci_mcp77] = {
83f2b963
TH		 155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
156 .flags = AHCI_FLAG_COMMON,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
facb8fa6 161 [board_ahci_mcp89] = {
83f2b963 162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 163 .flags = AHCI_FLAG_COMMON,
14bdef98 164 .pio_mask = ATA_PIO4,
469248ab 165 .udma_mask = ATA_UDMA6,
441577ef 166 .port_ops = &ahci_ops,
55a61604 167 },
facb8fa6 168 [board_ahci_mv] = {
417a1a6d 169 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 170 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 171 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 172 .pio_mask = ATA_PIO4,
cd70c266
JG		 173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
175 },
facb8fa6 176 [board_ahci_sb600] = {
441577ef
TH		 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 180 .flags = AHCI_FLAG_COMMON,
14bdef98 181 .pio_mask = ATA_PIO4,
e39fc8c9 182 .udma_mask = ATA_UDMA6,
345347c5 183 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 184 },
facb8fa6 185 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
345347c5 190 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 191 },
facb8fa6 192 [board_ahci_vt8251] = {
441577ef 193 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
441577ef 197 .port_ops = &ahci_vt8251_ops,
1b677afd 198 },
1da177e4
LT		 199};
200
3b7d697d 201static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 202 /* Intel */
54bb3a94
JG		 203 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
204 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
205 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
206 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
207 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 208 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 209 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
211 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 213 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 214 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 215 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
217 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
218 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 230 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
231 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 232 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 233 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 234 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 235 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
236 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 237 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 238 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 239 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 240 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 241 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 242 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 243 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
244 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
247 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 249 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
250 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
251 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 252 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 253 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 254 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
255 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
257 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
258 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 260 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 261 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
264 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
266 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
267 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 269 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
270 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
271 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
272 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
273 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
274 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
275 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
276 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 277 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
279 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
285 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
287 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 293 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 295 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
296 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
297 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
298 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
299 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
300 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 303 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
9f961a5f
JR		 304 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
305 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
306 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
307 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
1b071a09
JR		 308 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
309 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
310 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
311 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
312 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
313 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
314 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
315 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
fe7fa31a 316
e34bb370
TH		 317 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
318 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
319 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 320 /* JMicron 362B and 362C have an AHCI function with IDE class code */
321 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
322 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 323
324 /* ATI */
c65ec1c2 325 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 326 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
327 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
328 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
329 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
330 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
331 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 332
e2dd90b1 333 /* AMD */
5deab536 334 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 335 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 336 /* AMD is using RAID class only for ahci controllers */
337 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
338 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
339
fe7fa31a 340 /* VIA */
54bb3a94 341 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 342 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 343
344 /* NVIDIA */
e297d99e
TH		 345 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
346 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
347 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
348 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
349 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
350 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
351 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
352 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 353 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
358 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
359 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
360 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
361 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
365 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
375 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
376 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
377 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
378 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
386 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
387 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
388 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
389 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
390 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
391 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
392 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
398 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
399 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
400 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
401 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
402 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
403 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
404 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
405 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
410 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
411 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
412 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
413 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
414 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
415 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
416 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
417 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
421 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
423 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
425 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
426 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
427 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
428 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 429
95916edd 430 /* SiS */
20e2de4a
TH		 431 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
432 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
433 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 434
318893e1
AR		 435 /* ST Microelectronics */
436 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
437
cd70c266
JG		 438 /* Marvell */
439 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 440 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 441 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 442 .class = PCI_CLASS_STORAGE_SATA_AHCI,
443 .class_mask = 0xffffff,
5f173107 444 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 445 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 446 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
e098f5cb
SG		 447 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
448 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
449 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
69fd3157 450 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 451 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35
GS		 452 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
453 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 454 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 455 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
754a292f
AS		 456 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
457 .driver_data = board_ahci_yes_fbs },
69fd3157 458 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 459 .driver_data = board_ahci_yes_fbs },
6d5278a6
SB		 460 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
461 .driver_data = board_ahci_yes_fbs },
d2518365
JC		 462 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
463 .driver_data = board_ahci_yes_fbs },
cd70c266 464
c77a036b
MN		 465 /* Promise */
466 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
b32bfc06 467 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
c77a036b 468
c9703765 469 /* Asmedia */
7b4f6eca
AC		 470 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
471 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
472 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
473 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 474
67809f85
LK		 475 /*
476 * Samsung SSDs found on some macbooks. NCQ times out.
477 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
478 */
479 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
480
7f9c9f8e
HD		 481 /* Enmotus */
482 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
483
415ae2b5
JG		 484 /* Generic, PCI class code for AHCI */
485 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 486 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 487
1da177e4
LT		 488 { } /* terminate list */
489};
490
491
492static struct pci_driver ahci_pci_driver = {
493 .name = DRV_NAME,
494 .id_table = ahci_pci_tbl,
495 .probe = ahci_init_one,
24dc5f33 496 .remove = ata_pci_remove_one,
438ac6d5 497#ifdef CONFIG_PM
c1332875 498 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 499 .resume = ahci_pci_device_resume,
500#endif
501};
1da177e4 502
365cfa1e
AV		 503#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
504static int marvell_enable;
505#else
506static int marvell_enable = 1;
507#endif
508module_param(marvell_enable, int, 0644);
509MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 510
1da177e4 511
365cfa1e
AV		 512static void ahci_pci_save_initial_config(struct pci_dev *pdev,
513 struct ahci_host_priv *hpriv)
514{
515 unsigned int force_port_map = 0;
516 unsigned int mask_port_map = 0;
67846b30 517
365cfa1e
AV		 518 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
519 dev_info(&pdev->dev, "JMB361 has only one port\n");
520 force_port_map = 1;
1da177e4
LT		 521 }
522
365cfa1e
AV		 523 /*
524 * Temporary Marvell 6145 hack: PATA port presence
525 * is asserted through the standard AHCI port
526 * presence register, as bit 4 (counting from 0)
d28f87aa 527 */
365cfa1e
AV		 528 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
529 if (pdev->device == 0x6121)
530 mask_port_map = 0x3;
531 else
532 mask_port_map = 0xf;
533 dev_info(&pdev->dev,
534 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
535 }
1da177e4 536
725c7b57 537 ahci_save_initial_config(&pdev->dev, hpriv);
1da177e4
LT		 538}
539
365cfa1e 540static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 541{
365cfa1e 542 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 543
365cfa1e 544 ahci_reset_controller(host);
1da177e4 545
365cfa1e
AV		 546 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
547 struct ahci_host_priv *hpriv = host->private_data;
548 u16 tmp16;
d6ef3153 549
365cfa1e
AV		 550 /* configure PCS */
551 pci_read_config_word(pdev, 0x92, &tmp16);
552 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
553 tmp16 |= hpriv->port_map;
554 pci_write_config_word(pdev, 0x92, tmp16);
555 }
d6ef3153
SH		 556 }
557
1da177e4
LT		 558 return 0;
559}
560
365cfa1e 561static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 562{
365cfa1e
AV		 563 struct ahci_host_priv *hpriv = host->private_data;
564 struct pci_dev *pdev = to_pci_dev(host->dev);
565 void __iomem *port_mmio;
78cd52d0 566 u32 tmp;
365cfa1e 567 int mv;
78cd52d0 568
365cfa1e
AV		 569 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
570 if (pdev->device == 0x6121)
571 mv = 2;
572 else
573 mv = 4;
574 port_mmio = __ahci_port_base(host, mv);
78cd52d0 575
365cfa1e 576 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 577
365cfa1e
AV		 578 /* clear port IRQ */
579 tmp = readl(port_mmio + PORT_IRQ_STAT);
580 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
581 if (tmp)
582 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 583 }
584
365cfa1e 585 ahci_init_controller(host);
edc93052
TH		 586}
587
365cfa1e
AV		 588static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
589 unsigned long deadline)
d6ef3153 590{
365cfa1e 591 struct ata_port *ap = link->ap;
039ece38 592 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 593 bool online;
d6ef3153
SH		 594 int rc;
595
365cfa1e 596 DPRINTK("ENTER\n");
d6ef3153 597
365cfa1e 598 ahci_stop_engine(ap);
d6ef3153 599
365cfa1e
AV		 600 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
601 deadline, &online, NULL);
d6ef3153 602
039ece38 603 hpriv->start_engine(ap);
d6ef3153 604
365cfa1e 605 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 606
365cfa1e
AV		 607 /* vt8251 doesn't clear BSY on signature FIS reception,
608 * request follow-up softreset.
609 */
610 return online ? -EAGAIN : rc;
7d50b60b
TH		 611}
612
365cfa1e
AV		 613static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
614 unsigned long deadline)
7d50b60b 615{
365cfa1e 616 struct ata_port *ap = link->ap;
1c954a4d 617 struct ahci_port_priv *pp = ap->private_data;
039ece38 618 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 619 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
620 struct ata_taskfile tf;
621 bool online;
622 int rc;
7d50b60b 623
365cfa1e 624 ahci_stop_engine(ap);
028a2596 625
365cfa1e
AV		 626 /* clear D2H reception area to properly wait for D2H FIS */
627 ata_tf_init(link->device, &tf);
9bbb1b0e 628 tf.command = ATA_BUSY;
365cfa1e 629 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 630
365cfa1e
AV		 631 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
632 deadline, &online, NULL);
028a2596 633
039ece38 634 hpriv->start_engine(ap);
c1332875 635
365cfa1e
AV		 636 /* The pseudo configuration device on SIMG4726 attached to
637 * ASUS P5W-DH Deluxe doesn't send signature FIS after
638 * hardreset if no device is attached to the first downstream
639 * port && the pseudo device locks up on SRST w/ PMP==0. To
640 * work around this, wait for !BSY only briefly. If BSY isn't
641 * cleared, perform CLO and proceed to IDENTIFY (achieved by
642 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
643 *
644 * Wait for two seconds. Devices attached to downstream port
645 * which can't process the following IDENTIFY after this will
646 * have to be reset again. For most cases, this should
647 * suffice while making probing snappish enough.
648 */
649 if (online) {
650 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
651 ahci_check_ready);
652 if (rc)
653 ahci_kick_engine(ap);
c1332875 654 }
c1332875
TH		 655 return rc;
656}
657
365cfa1e 658#ifdef CONFIG_PM
c1332875
TH		 659static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
660{
0a86e1c8 661 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 662 struct ahci_host_priv *hpriv = host->private_data;
d8993349 663 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 664 u32 ctl;
665
9b10ae86
TH		 666 if (mesg.event & PM_EVENT_SUSPEND &&
667 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 668 dev_err(&pdev->dev,
669 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 670 return -EIO;
671 }
672
3a2d5b70 673 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 674 /* AHCI spec rev1.1 section 8.3.3:
675 * Software must disable interrupts prior to requesting a
676 * transition of the HBA to D3 state.
677 */
678 ctl = readl(mmio + HOST_CTL);
679 ctl &= ~HOST_IRQ_EN;
680 writel(ctl, mmio + HOST_CTL);
681 readl(mmio + HOST_CTL); /* flush */
682 }
683
684 return ata_pci_device_suspend(pdev, mesg);
685}
686
687static int ahci_pci_device_resume(struct pci_dev *pdev)
688{
0a86e1c8 689 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 690 int rc;
691
553c4aa6
TH		 692 rc = ata_pci_device_do_resume(pdev);
693 if (rc)
694 return rc;
c1332875 695
cb85696d
JL		 696 /* Apple BIOS helpfully mangles the registers on resume */
697 if (is_mcp89_apple(pdev))
698 ahci_mcp89_apple_enable(pdev);
699
c1332875 700 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 701 rc = ahci_pci_reset_controller(host);
c1332875
TH		 702 if (rc)
703 return rc;
704
781d6550 705 ahci_pci_init_controller(host);
c1332875
TH		 706 }
707
cca3974e 708 ata_host_resume(host);
c1332875
TH		 709
710 return 0;
711}
438ac6d5 712#endif
c1332875 713
4447d351 714static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 715{
1da177e4 716 int rc;
1da177e4 717
318893e1
AR		 718 /*
719 * If the device fixup already set the dma_mask to some non-standard
720 * value, don't extend it here. This happens on STA2X11, for example.
721 */
722 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
723 return 0;
724
1da177e4 725 if (using_dac &&
6a35528a
YH		 726 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
727 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 728 if (rc) {
284901a9 729 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 730 if (rc) {
a44fec1f
JP		 731 dev_err(&pdev->dev,
732 "64-bit DMA enable failed\n");
1da177e4
LT		 733 return rc;
734 }
735 }
1da177e4 736 } else {
284901a9 737 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 738 if (rc) {
a44fec1f 739 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 740 return rc;
741 }
284901a9 742 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 743 if (rc) {
a44fec1f
JP		 744 dev_err(&pdev->dev,
745 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 746 return rc;
747 }
748 }
1da177e4
LT		 749 return 0;
750}
751
439fcaec
AV		 752static void ahci_pci_print_info(struct ata_host *host)
753{
754 struct pci_dev *pdev = to_pci_dev(host->dev);
755 u16 cc;
756 const char *scc_s;
757
758 pci_read_config_word(pdev, 0x0a, &cc);
759 if (cc == PCI_CLASS_STORAGE_IDE)
760 scc_s = "IDE";
761 else if (cc == PCI_CLASS_STORAGE_SATA)
762 scc_s = "SATA";
763 else if (cc == PCI_CLASS_STORAGE_RAID)
764 scc_s = "RAID";
765 else
766 scc_s = "unknown";
767
768 ahci_print_info(host, scc_s);
769}
770
edc93052
TH		 771/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
772 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
773 * support PMP and the 4726 either directly exports the device
774 * attached to the first downstream port or acts as a hardware storage
775 * controller and emulate a single ATA device (can be RAID 0/1 or some
776 * other configuration).
777 *
778 * When there's no device attached to the first downstream port of the
779 * 4726, "Config Disk" appears, which is a pseudo ATA device to
780 * configure the 4726. However, ATA emulation of the device is very
781 * lame. It doesn't send signature D2H Reg FIS after the initial
782 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
783 *
784 * The following function works around the problem by always using
785 * hardreset on the port and not depending on receiving signature FIS
786 * afterward. If signature FIS isn't received soon, ATA class is
787 * assumed without follow-up softreset.
788 */
789static void ahci_p5wdh_workaround(struct ata_host *host)
790{
791 static struct dmi_system_id sysids[] = {
792 {
793 .ident = "P5W DH Deluxe",
794 .matches = {
795 DMI_MATCH(DMI_SYS_VENDOR,
796 "ASUSTEK COMPUTER INC"),
797 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
798 },
799 },
800 { }
801 };
802 struct pci_dev *pdev = to_pci_dev(host->dev);
803
804 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
805 dmi_check_system(sysids)) {
806 struct ata_port *ap = host->ports[1];
807
a44fec1f
JP		 808 dev_info(&pdev->dev,
809 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 810
811 ap->ops = &ahci_p5wdh_ops;
812 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
813 }
814}
815
cb85696d
JL		 816/*
817 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
818 * booting in BIOS compatibility mode. We restore the registers but not ID.
819 */
820static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
821{
822 u32 val;
823
824 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
825
826 pci_read_config_dword(pdev, 0xf8, &val);
827 val |= 1 << 0x1b;
828 /* the following changes the device ID, but appears not to affect function */
829 /* val = (val & ~0xf0000000) | 0x80000000; */
830 pci_write_config_dword(pdev, 0xf8, val);
831
832 pci_read_config_dword(pdev, 0x54c, &val);
833 val |= 1 << 0xc;
834 pci_write_config_dword(pdev, 0x54c, val);
835
836 pci_read_config_dword(pdev, 0x4a4, &val);
837 val &= 0xff;
838 val |= 0x01060100;
839 pci_write_config_dword(pdev, 0x4a4, val);
840
841 pci_read_config_dword(pdev, 0x54c, &val);
842 val &= ~(1 << 0xc);
843 pci_write_config_dword(pdev, 0x54c, val);
844
845 pci_read_config_dword(pdev, 0xf8, &val);
846 val &= ~(1 << 0x1b);
847 pci_write_config_dword(pdev, 0xf8, val);
848}
849
850static bool is_mcp89_apple(struct pci_dev *pdev)
851{
852 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
853 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
854 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
855 pdev->subsystem_device == 0xcb89;
856}
857
2fcad9d2
TH		 858/* only some SB600 ahci controllers can do 64bit DMA */
859static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 860{
861 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 862 /*
863 * The oldest version known to be broken is 0901 and
864 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 865 * Enable 64bit DMA on 1501 and anything newer.
866 *
03d783bf
TH		 867 * Please read bko#9412 for more info.
868 */
58a09b38
SH		 869 {
870 .ident = "ASUS M2A-VM",
871 .matches = {
872 DMI_MATCH(DMI_BOARD_VENDOR,
873 "ASUSTeK Computer INC."),
874 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
875 },
03d783bf 876 .driver_data = "20071026", /* yyyymmdd */
58a09b38 877 },
e65cc194
MN		 878 /*
879 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
880 * support 64bit DMA.
881 *
882 * BIOS versions earlier than 1.5 had the Manufacturer DMI
883 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
884 * This spelling mistake was fixed in BIOS version 1.5, so
885 * 1.5 and later have the Manufacturer as
886 * "MICRO-STAR INTERNATIONAL CO.,LTD".
887 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
888 *
889 * BIOS versions earlier than 1.9 had a Board Product Name
890 * DMI field of "MS-7376". This was changed to be
891 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
892 * match on DMI_BOARD_NAME of "MS-7376".
893 */
894 {
895 .ident = "MSI K9A2 Platinum",
896 .matches = {
897 DMI_MATCH(DMI_BOARD_VENDOR,
898 "MICRO-STAR INTER"),
899 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
900 },
901 },
ff0173c1
MN		 902 /*
903 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
904 * 64bit DMA.
905 *
906 * This board also had the typo mentioned above in the
907 * Manufacturer DMI field (fixed in BIOS version 1.5), so
908 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
909 */
910 {
911 .ident = "MSI K9AGM2",
912 .matches = {
913 DMI_MATCH(DMI_BOARD_VENDOR,
914 "MICRO-STAR INTER"),
915 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
916 },
917 },
3c4aa91f
MN		 918 /*
919 * All BIOS versions for the Asus M3A support 64bit DMA.
920 * (all release versions from 0301 to 1206 were tested)
921 */
922 {
923 .ident = "ASUS M3A",
924 .matches = {
925 DMI_MATCH(DMI_BOARD_VENDOR,
926 "ASUSTeK Computer INC."),
927 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
928 },
929 },
58a09b38
SH		 930 { }
931 };
03d783bf 932 const struct dmi_system_id *match;
2fcad9d2
TH		 933 int year, month, date;
934 char buf[9];
58a09b38 935
03d783bf 936 match = dmi_first_match(sysids);
58a09b38 937 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 938 !match)
58a09b38
SH		 939 return false;
940
e65cc194
MN		 941 if (!match->driver_data)
942 goto enable_64bit;
943
2fcad9d2
TH		 944 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
945 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 946
e65cc194
MN		 947 if (strcmp(buf, match->driver_data) >= 0)
948 goto enable_64bit;
949 else {
a44fec1f
JP		 950 dev_warn(&pdev->dev,
951 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
952 match->ident);
2fcad9d2
TH		 953 return false;
954 }
e65cc194
MN		 955
956enable_64bit:
a44fec1f 957 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 958 return true;
58a09b38
SH		 959}
960
1fd68434
RW		 961static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
962{
963 static const struct dmi_system_id broken_systems[] = {
964 {
965 .ident = "HP Compaq nx6310",
966 .matches = {
967 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
968 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
969 },
970 /* PCI slot number of the controller */
971 .driver_data = (void *)0x1FUL,
972 },
d2f9c061
MR		 973 {
974 .ident = "HP Compaq 6720s",
975 .matches = {
976 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
977 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
978 },
979 /* PCI slot number of the controller */
980 .driver_data = (void *)0x1FUL,
981 },
1fd68434
RW		 982
983 { } /* terminate list */
984 };
985 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
986
987 if (dmi) {
988 unsigned long slot = (unsigned long)dmi->driver_data;
989 /* apply the quirk only to on-board controllers */
990 return slot == PCI_SLOT(pdev->devfn);
991 }
992
993 return false;
994}
995
9b10ae86
TH		 996static bool ahci_broken_suspend(struct pci_dev *pdev)
997{
998 static const struct dmi_system_id sysids[] = {
999 /*
1000 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1001 * to the harddisk doesn't become online after
1002 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 1003 *
1004 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1005 *
1006 * Use dates instead of versions to match as HP is
1007 * apparently recycling both product and version
1008 * strings.
1009 *
1010 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 1011 */
1012 {
1013 .ident = "dv4",
1014 .matches = {
1015 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1016 DMI_MATCH(DMI_PRODUCT_NAME,
1017 "HP Pavilion dv4 Notebook PC"),
1018 },
9deb3431 1019 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 1020 },
1021 {
1022 .ident = "dv5",
1023 .matches = {
1024 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1025 DMI_MATCH(DMI_PRODUCT_NAME,
1026 "HP Pavilion dv5 Notebook PC"),
1027 },
9deb3431 1028 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 1029 },
1030 {
1031 .ident = "dv6",
1032 .matches = {
1033 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1034 DMI_MATCH(DMI_PRODUCT_NAME,
1035 "HP Pavilion dv6 Notebook PC"),
1036 },
9deb3431 1037 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 1038 },
1039 {
1040 .ident = "HDX18",
1041 .matches = {
1042 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1043 DMI_MATCH(DMI_PRODUCT_NAME,
1044 "HP HDX18 Notebook PC"),
1045 },
9deb3431 1046 .driver_data = "20090430", /* F.23 */
9b10ae86 1047 },
cedc9bf9
TH		 1048 /*
1049 * Acer eMachines G725 has the same problem. BIOS
1050 * V1.03 is known to be broken. V3.04 is known to
25985edc 1051 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 1052 * that we don't have much idea about. For now,
1053 * blacklist anything older than V3.04.
9deb3431
TH		 1054 *
1055 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 1056 */
1057 {
1058 .ident = "G725",
1059 .matches = {
1060 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1061 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1062 },
9deb3431 1063 .driver_data = "20091216", /* V3.04 */
cedc9bf9 1064 },
9b10ae86
TH		 1065 { } /* terminate list */
1066 };
1067 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 1068 int year, month, date;
1069 char buf[9];
9b10ae86
TH		 1070
1071 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1072 return false;
1073
9deb3431
TH		 1074 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1075 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 1076
9deb3431 1077 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 1078}
1079
5594639a
TH		 1080static bool ahci_broken_online(struct pci_dev *pdev)
1081{
1082#define ENCODE_BUSDEVFN(bus, slot, func) \
1083 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1084 static const struct dmi_system_id sysids[] = {
1085 /*
1086 * There are several gigabyte boards which use
1087 * SIMG5723s configured as hardware RAID. Certain
1088 * 5723 firmware revisions shipped there keep the link
1089 * online but fail to answer properly to SRST or
1090 * IDENTIFY when no device is attached downstream
1091 * causing libata to retry quite a few times leading
1092 * to excessive detection delay.
1093 *
1094 * As these firmwares respond to the second reset try
1095 * with invalid device signature, considering unknown
1096 * sig as offline works around the problem acceptably.
1097 */
1098 {
1099 .ident = "EP45-DQ6",
1100 .matches = {
1101 DMI_MATCH(DMI_BOARD_VENDOR,
1102 "Gigabyte Technology Co., Ltd."),
1103 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1104 },
1105 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1106 },
1107 {
1108 .ident = "EP45-DS5",
1109 .matches = {
1110 DMI_MATCH(DMI_BOARD_VENDOR,
1111 "Gigabyte Technology Co., Ltd."),
1112 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1113 },
1114 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1115 },
1116 { } /* terminate list */
1117 };
1118#undef ENCODE_BUSDEVFN
1119 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1120 unsigned int val;
1121
1122 if (!dmi)
1123 return false;
1124
1125 val = (unsigned long)dmi->driver_data;
1126
1127 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1128}
1129
0cf4a7d6
JP		 1130static bool ahci_broken_devslp(struct pci_dev *pdev)
1131{
1132 /* device with broken DEVSLP but still showing SDS capability */
1133 static const struct pci_device_id ids[] = {
1134 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1135 {}
1136 };
1137
1138 return pci_match_id(ids, pdev);
1139}
1140
8e513217 1141#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1142static void ahci_gtf_filter_workaround(struct ata_host *host)
1143{
1144 static const struct dmi_system_id sysids[] = {
1145 /*
1146 * Aspire 3810T issues a bunch of SATA enable commands
1147 * via _GTF including an invalid one and one which is
1148 * rejected by the device. Among the successful ones
1149 * is FPDMA non-zero offset enable which when enabled
1150 * only on the drive side leads to NCQ command
1151 * failures. Filter it out.
1152 */
1153 {
1154 .ident = "Aspire 3810T",
1155 .matches = {
1156 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1157 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1158 },
1159 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1160 },
1161 { }
1162 };
1163 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1164 unsigned int filter;
1165 int i;
1166
1167 if (!dmi)
1168 return;
1169
1170 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1171 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1172 filter, dmi->ident);
f80ae7e4
TH		 1173
1174 for (i = 0; i < host->n_ports; i++) {
1175 struct ata_port *ap = host->ports[i];
1176 struct ata_link *link;
1177 struct ata_device *dev;
1178
1179 ata_for_each_link(link, ap, EDGE)
1180 ata_for_each_dev(dev, link, ALL)
1181 dev->gtf_filter |= filter;
1182 }
1183}
8e513217
MT		 1184#else
1185static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1186{}
1187#endif
f80ae7e4 1188
e1ba8459 1189static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
ab0f9e78 1190 struct ahci_host_priv *hpriv)
5ca72c4f 1191{
ccf8f53c 1192 int rc, nvec;
5ca72c4f 1193
7b92b4f6
AG		 1194 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1195 goto intx;
1196
fc061d96
AG		 1197 nvec = pci_msi_vec_count(pdev);
1198 if (nvec < 0)
7b92b4f6
AG		 1199 goto intx;
1200
1201 /*
1202 * If number of MSIs is less than number of ports then Sharing Last
1203 * Message mode could be enforced. In this case assume that advantage
1204 * of multipe MSIs is negated and use single MSI mode instead.
1205 */
fc061d96 1206 if (nvec < n_ports)
7b92b4f6
AG		 1207 goto single_msi;
1208
ccf8f53c
AG		 1209 rc = pci_enable_msi_exact(pdev, nvec);
1210 if (rc == -ENOSPC)
fc40363b 1211 goto single_msi;
ccf8f53c 1212 else if (rc < 0)
fc061d96 1213 goto intx;
5ca72c4f 1214
ab0f9e78
AG		 1215 /* fallback to single MSI mode if the controller enforced MRSM mode */
1216 if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1217 pci_disable_msi(pdev);
1218 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1219 goto single_msi;
1220 }
1221
7b92b4f6
AG		 1222 return nvec;
1223
1224single_msi:
fc061d96 1225 if (pci_enable_msi(pdev))
7b92b4f6
AG		 1226 goto intx;
1227 return 1;
1228
1229intx:
5ca72c4f
AG		 1230 pci_intx(pdev, 1);
1231 return 0;
1232}
1233
1234/**
1235 * ahci_host_activate - start AHCI host, request IRQs and register it
1236 * @host: target ATA host
1237 * @irq: base IRQ number to request
1238 * @n_msis: number of MSIs allocated for this host
1239 * @irq_handler: irq_handler used when requesting IRQs
1240 * @irq_flags: irq_flags used when requesting IRQs
1241 *
1242 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1243 * when multiple MSIs were allocated. That is one MSI per port, starting
1244 * from @irq.
1245 *
1246 * LOCKING:
1247 * Inherited from calling layer (may sleep).
1248 *
1249 * RETURNS:
1250 * 0 on success, -errno otherwise.
1251 */
1252int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1253{
1254 int i, rc;
1255
1256 /* Sharing Last Message among several ports is not supported */
1257 if (n_msis < host->n_ports)
1258 return -EINVAL;
1259
1260 rc = ata_host_start(host);
1261 if (rc)
1262 return rc;
1263
1264 for (i = 0; i < host->n_ports; i++) {
b29900e6
AG		 1265 struct ahci_port_priv *pp = host->ports[i]->private_data;
1266
2cf532f5
AG		 1267 /* Do not receive interrupts sent by dummy ports */
1268 if (!pp) {
1269 disable_irq(irq + i);
1270 continue;
1271 }
1272
1273 rc = devm_request_threaded_irq(host->dev, irq + i,
1274 ahci_hw_interrupt,
1275 ahci_thread_fn, IRQF_SHARED,
1276 pp->irq_desc, host->ports[i]);
5ca72c4f
AG		 1277 if (rc)
1278 goto out_free_irqs;
1279 }
1280
1281 for (i = 0; i < host->n_ports; i++)
1282 ata_port_desc(host->ports[i], "irq %d", irq + i);
1283
1284 rc = ata_host_register(host, &ahci_sht);
1285 if (rc)
1286 goto out_free_all_irqs;
1287
1288 return 0;
1289
1290out_free_all_irqs:
1291 i = host->n_ports;
1292out_free_irqs:
1293 for (i--; i >= 0; i--)
1294 devm_free_irq(host->dev, irq + i, host->ports[i]);
1295
1296 return rc;
1297}
1298
24dc5f33 1299static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1300{
e297d99e
TH		 1301 unsigned int board_id = ent->driver_data;
1302 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1303 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1304 struct device *dev = &pdev->dev;
1da177e4 1305 struct ahci_host_priv *hpriv;
4447d351 1306 struct ata_host *host;
5ca72c4f 1307 int n_ports, n_msis, i, rc;
318893e1 1308 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1309
1310 VPRINTK("ENTER\n");
1311
b429dd59 1312 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1313
06296a1e 1314 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1315
5b66c829
AC		 1316 /* The AHCI driver can only drive the SATA ports, the PATA driver
1317 can drive them all so if both drivers are selected make sure
1318 AHCI stays out of the way */
1319 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1320 return -ENODEV;
1321
cb85696d
JL		 1322 /* Apple BIOS on MCP89 prevents us using AHCI */
1323 if (is_mcp89_apple(pdev))
1324 ahci_mcp89_apple_enable(pdev);
c6353b45 1325
7a02267e
MN		 1326 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1327 * At the moment, we can only use the AHCI mode. Let the users know
1328 * that for SAS drives they're out of luck.
1329 */
1330 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1331 dev_info(&pdev->dev,
1332 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1333
7f9c9f8e 1334 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1335 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1336 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1337 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1338 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1339
e6b7e41c
CL		 1340 /*
1341 * The JMicron chip 361/363 contains one SATA controller and one
1342 * PATA controller,for powering on these both controllers, we must
1343 * follow the sequence one by one, otherwise one of them can not be
1344 * powered on successfully, so here we disable the async suspend
1345 * method for these chips.
1346 */
1347 if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1348 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1349 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1350 device_disable_async_suspend(&pdev->dev);
1351
4447d351 1352 /* acquire resources */
24dc5f33 1353 rc = pcim_enable_device(pdev);
1da177e4
LT		 1354 if (rc)
1355 return rc;
1356
c4f7792c
TH		 1357 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1358 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1359 u8 map;
1360
1361 /* ICH6s share the same PCI ID for both piix and ahci
1362 * modes. Enabling ahci mode while MAP indicates
1363 * combined mode is a bad idea. Yield to ata_piix.
1364 */
1365 pci_read_config_byte(pdev, ICH_MAP, &map);
1366 if (map & 0x3) {
a44fec1f
JP		 1367 dev_info(&pdev->dev,
1368 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1369 return -ENODEV;
1370 }
1371 }
1372
6fec8871
PB		 1373 /* AHCI controllers often implement SFF compatible interface.
1374 * Grab all PCI BARs just in case.
1375 */
1376 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1377 if (rc == -EBUSY)
1378 pcim_pin_device(pdev);
1379 if (rc)
1380 return rc;
1381
24dc5f33
TH		 1382 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1383 if (!hpriv)
1384 return -ENOMEM;
417a1a6d
TH		 1385 hpriv->flags |= (unsigned long)pi.private_data;
1386
e297d99e
TH		 1387 /* MCP65 revision A1 and A2 can't do MSI */
1388 if (board_id == board_ahci_mcp65 &&
1389 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1390 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1391
e427fe04
SH		 1392 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1393 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1394 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1395
2fcad9d2
TH		 1396 /* only some SB600s can do 64bit DMA */
1397 if (ahci_sb600_enable_64bit(pdev))
1398 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1399
318893e1 1400 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1401
0cf4a7d6
JP		 1402 /* must set flag prior to save config in order to take effect */
1403 if (ahci_broken_devslp(pdev))
1404 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1405
4447d351 1406 /* save initial config */
394d6e53 1407 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1408
4447d351 1409 /* prepare host */
453d3131
RH		 1410 if (hpriv->cap & HOST_CAP_NCQ) {
1411 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1412 /*
1413 * Auto-activate optimization is supposed to be
1414 * supported on all AHCI controllers indicating NCQ
1415 * capability, but it seems to be broken on some
1416 * chipsets including NVIDIAs.
1417 */
1418 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1419 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1420
1421 /*
1422 * All AHCI controllers should be forward-compatible
1423 * with the new auxiliary field. This code should be
1424 * conditionalized if any buggy AHCI controllers are
1425 * encountered.
1426 */
1427 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1428 }
1da177e4 1429
7d50b60b
TH		 1430 if (hpriv->cap & HOST_CAP_PMP)
1431 pi.flags |= ATA_FLAG_PMP;
1432
0cbb0e77 1433 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1434
1fd68434
RW		 1435 if (ahci_broken_system_poweroff(pdev)) {
1436 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1437 dev_info(&pdev->dev,
1438 "quirky BIOS, skipping spindown on poweroff\n");
1439 }
1440
9b10ae86
TH		 1441 if (ahci_broken_suspend(pdev)) {
1442 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1443 dev_warn(&pdev->dev,
1444 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1445 }
1446
5594639a
TH		 1447 if (ahci_broken_online(pdev)) {
1448 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1449 dev_info(&pdev->dev,
1450 "online status unreliable, applying workaround\n");
1451 }
1452
837f5f8f
TH		 1453 /* CAP.NP sometimes indicate the index of the last enabled
1454 * port, at other times, that of the last possible port, so
1455 * determining the maximum port number requires looking at
1456 * both CAP.NP and port_map.
1457 */
1458 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1459
7b92b4f6
AG		 1460 n_msis = ahci_init_interrupts(pdev, n_ports, hpriv);
1461 if (n_msis > 1)
1462 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1463
837f5f8f 1464 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1465 if (!host)
1466 return -ENOMEM;
4447d351
TH		 1467 host->private_data = hpriv;
1468
f3d7f23f 1469 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1470 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f 1471 else
d2782d96 1472 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
886ad09f 1473
18f7ba4c
KCA		 1474 if (pi.flags & ATA_FLAG_EM)
1475 ahci_reset_em(host);
1476
4447d351 1477 for (i = 0; i < host->n_ports; i++) {
dab632e8 1478 struct ata_port *ap = host->ports[i];
4447d351 1479
318893e1
AR		 1480 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1481 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1482 0x100 + ap->port_no * 0x80, "port");
1483
18f7ba4c
KCA		 1484 /* set enclosure management message type */
1485 if (ap->flags & ATA_FLAG_EM)
008dbd61 1486 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1487
1488
dab632e8 1489 /* disabled/not-implemented port */
350756f6 1490 if (!(hpriv->port_map & (1 << i)))
dab632e8 1491 ap->ops = &ata_dummy_port_ops;
4447d351 1492 }
d447df14 1493
edc93052
TH		 1494 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1495 ahci_p5wdh_workaround(host);
1496
f80ae7e4
TH		 1497 /* apply gtf filter quirk */
1498 ahci_gtf_filter_workaround(host);
1499
4447d351
TH		 1500 /* initialize adapter */
1501 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1502 if (rc)
24dc5f33 1503 return rc;
1da177e4 1504
3303040d 1505 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1506 if (rc)
1507 return rc;
1da177e4 1508
781d6550 1509 ahci_pci_init_controller(host);
439fcaec 1510 ahci_pci_print_info(host);
1da177e4 1511
4447d351 1512 pci_set_master(pdev);
5ca72c4f
AG		 1513
1514 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1515 return ahci_host_activate(host, pdev->irq, n_msis);
1516
4447d351
TH		 1517 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1518 &ahci_sht);
907f4678 1519}
1da177e4 1520
2fc75da0 1521module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1522
1523MODULE_AUTHOR("Jeff Garzik");
1524MODULE_DESCRIPTION("AHCI SATA low-level driver");
1525MODULE_LICENSE("GPL");
1526MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1527MODULE_VERSION(DRV_VERSION);
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