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pata_isapnp: Don't use invalid I/O ports
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
af36d7f0
JG		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1 55 AHCI_PCI_BAR_STA2X11 = 0,
7f9c9f8e 56 AHCI_PCI_BAR_ENMOTUS = 2,
318893e1 57 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 58};
59
60enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
5f173107 65 board_ahci_yes_fbs,
1da177e4 66
441577ef
TH		 67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
83f2b963
TH		 69 board_ahci_mcp77,
70 board_ahci_mcp89,
441577ef
TH		 71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 80 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 81};
82
2dcb407e 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
438ac6d5 88#ifdef CONFIG_PM
c1332875
TH		 89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 91#endif
ad616ffb 92
fad16e7a
TH		 93static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95};
96
029cfd6b
TH		 97static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
a1efdaba 99 .hardreset = ahci_vt8251_hardreset,
029cfd6b 100};
edc93052 101
029cfd6b
TH		 102static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
a1efdaba 104 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 105};
106
98ac62de 107static const struct ata_port_info ahci_port_info[] = {
441577ef 108 /* by features */
facb8fa6 109 [board_ahci] = {
1188c0d8 110 .flags = AHCI_FLAG_COMMON,
14bdef98 111 .pio_mask = ATA_PIO4,
469248ab 112 .udma_mask = ATA_UDMA6,
1da177e4
LT		 113 .port_ops = &ahci_ops,
114 },
facb8fa6 115 [board_ahci_ign_iferr] = {
441577ef 116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 117 .flags = AHCI_FLAG_COMMON,
14bdef98 118 .pio_mask = ATA_PIO4,
469248ab 119 .udma_mask = ATA_UDMA6,
441577ef 120 .port_ops = &ahci_ops,
bf2af2a2 121 },
facb8fa6 122 [board_ahci_nosntf] = {
441577ef 123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 124 .flags = AHCI_FLAG_COMMON,
14bdef98 125 .pio_mask = ATA_PIO4,
469248ab 126 .udma_mask = ATA_UDMA6,
41669553
TH		 127 .port_ops = &ahci_ops,
128 },
facb8fa6 129 [board_ahci_yes_fbs] = {
5f173107
TH		 130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
441577ef 136 /* by chipsets */
facb8fa6 137 [board_ahci_mcp65] = {
83f2b963
TH		 138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
ae01b249 140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
facb8fa6 145 [board_ahci_mcp77] = {
83f2b963
TH		 146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
facb8fa6 152 [board_ahci_mcp89] = {
83f2b963 153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 154 .flags = AHCI_FLAG_COMMON,
14bdef98 155 .pio_mask = ATA_PIO4,
469248ab 156 .udma_mask = ATA_UDMA6,
441577ef 157 .port_ops = &ahci_ops,
55a61604 158 },
facb8fa6 159 [board_ahci_mv] = {
417a1a6d 160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 163 .pio_mask = ATA_PIO4,
cd70c266
JG		 164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
facb8fa6 167 [board_ahci_sb600] = {
441577ef
TH		 168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 171 .flags = AHCI_FLAG_COMMON,
14bdef98 172 .pio_mask = ATA_PIO4,
e39fc8c9 173 .udma_mask = ATA_UDMA6,
345347c5 174 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 175 },
facb8fa6 176 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
345347c5 181 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 182 },
facb8fa6 183 [board_ahci_vt8251] = {
441577ef 184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
441577ef 188 .port_ops = &ahci_vt8251_ops,
1b677afd 189 },
1da177e4
LT		 190};
191
3b7d697d 192static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 193 /* Intel */
54bb3a94
JG		 194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
29e674dd
SH		 268 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
269 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
271 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
efda332c
JR		 284 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
285 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
151743fd
JR		 286 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
287 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
288 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
289 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
291 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
292 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
1cfc7df3 294 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
fe7fa31a 295
e34bb370
TH		 296 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
297 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
298 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 299 /* JMicron 362B and 362C have an AHCI function with IDE class code */
300 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
301 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 302
303 /* ATI */
c65ec1c2 304 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 305 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
306 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
307 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
308 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
309 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
310 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 311
e2dd90b1 312 /* AMD */
5deab536 313 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
fafe5c3d 314 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
e2dd90b1
SH		 315 /* AMD is using RAID class only for ahci controllers */
316 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
317 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
318
fe7fa31a 319 /* VIA */
54bb3a94 320 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 321 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 322
323 /* NVIDIA */
e297d99e
TH		 324 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
325 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
326 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
327 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
328 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
329 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
330 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
331 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 332 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
333 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
334 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
335 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
336 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
337 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
345 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
346 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
347 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
348 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
349 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
350 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
361 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
362 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
363 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
364 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
365 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
366 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
371 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
372 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
373 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
374 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
375 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
376 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
377 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
383 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
384 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
385 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
386 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
387 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
388 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
389 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
390 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
395 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
396 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
397 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
398 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
399 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
400 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
401 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
402 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
406 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
407 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 408
95916edd 409 /* SiS */
20e2de4a
TH		 410 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
411 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
412 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 413
318893e1
AR		 414 /* ST Microelectronics */
415 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
416
cd70c266
JG		 417 /* Marvell */
418 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 419 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
69fd3157 420 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
10aca06c
AH		 421 .class = PCI_CLASS_STORAGE_SATA_AHCI,
422 .class_mask = 0xffffff,
5f173107 423 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
69fd3157 424 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
467b41c6 425 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
69fd3157 426 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
642d8925 427 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
fcce9a35
GS		 428 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
429 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
69fd3157 430 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
17c60c6b 431 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
69fd3157 432 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
50be5e36 433 .driver_data = board_ahci_yes_fbs },
cd70c266 434
c77a036b
MN		 435 /* Promise */
436 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
437
c9703765 438 /* Asmedia */
7b4f6eca
AC		 439 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
440 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
441 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
442 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 443
7f9c9f8e
HD		 444 /* Enmotus */
445 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
446
415ae2b5
JG		 447 /* Generic, PCI class code for AHCI */
448 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 449 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 450
1da177e4
LT		 451 { } /* terminate list */
452};
453
454
455static struct pci_driver ahci_pci_driver = {
456 .name = DRV_NAME,
457 .id_table = ahci_pci_tbl,
458 .probe = ahci_init_one,
24dc5f33 459 .remove = ata_pci_remove_one,
438ac6d5 460#ifdef CONFIG_PM
c1332875 461 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 462 .resume = ahci_pci_device_resume,
463#endif
464};
1da177e4 465
365cfa1e
AV		 466#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
467static int marvell_enable;
468#else
469static int marvell_enable = 1;
470#endif
471module_param(marvell_enable, int, 0644);
472MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 473
1da177e4 474
365cfa1e
AV		 475static void ahci_pci_save_initial_config(struct pci_dev *pdev,
476 struct ahci_host_priv *hpriv)
477{
478 unsigned int force_port_map = 0;
479 unsigned int mask_port_map = 0;
67846b30 480
365cfa1e
AV		 481 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
482 dev_info(&pdev->dev, "JMB361 has only one port\n");
483 force_port_map = 1;
1da177e4
LT		 484 }
485
365cfa1e
AV		 486 /*
487 * Temporary Marvell 6145 hack: PATA port presence
488 * is asserted through the standard AHCI port
489 * presence register, as bit 4 (counting from 0)
d28f87aa 490 */
365cfa1e
AV		 491 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
492 if (pdev->device == 0x6121)
493 mask_port_map = 0x3;
494 else
495 mask_port_map = 0xf;
496 dev_info(&pdev->dev,
497 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
498 }
1da177e4 499
365cfa1e
AV		 500 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
501 mask_port_map);
1da177e4
LT		 502}
503
365cfa1e 504static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 505{
365cfa1e 506 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 507
365cfa1e 508 ahci_reset_controller(host);
1da177e4 509
365cfa1e
AV		 510 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
511 struct ahci_host_priv *hpriv = host->private_data;
512 u16 tmp16;
d6ef3153 513
365cfa1e
AV		 514 /* configure PCS */
515 pci_read_config_word(pdev, 0x92, &tmp16);
516 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
517 tmp16 |= hpriv->port_map;
518 pci_write_config_word(pdev, 0x92, tmp16);
519 }
d6ef3153
SH		 520 }
521
1da177e4
LT		 522 return 0;
523}
524
365cfa1e 525static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 526{
365cfa1e
AV		 527 struct ahci_host_priv *hpriv = host->private_data;
528 struct pci_dev *pdev = to_pci_dev(host->dev);
529 void __iomem *port_mmio;
78cd52d0 530 u32 tmp;
365cfa1e 531 int mv;
78cd52d0 532
365cfa1e
AV		 533 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
534 if (pdev->device == 0x6121)
535 mv = 2;
536 else
537 mv = 4;
538 port_mmio = __ahci_port_base(host, mv);
78cd52d0 539
365cfa1e 540 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 541
365cfa1e
AV		 542 /* clear port IRQ */
543 tmp = readl(port_mmio + PORT_IRQ_STAT);
544 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
545 if (tmp)
546 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 547 }
548
365cfa1e 549 ahci_init_controller(host);
edc93052
TH		 550}
551
365cfa1e
AV		 552static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
553 unsigned long deadline)
d6ef3153 554{
365cfa1e
AV		 555 struct ata_port *ap = link->ap;
556 bool online;
d6ef3153
SH		 557 int rc;
558
365cfa1e 559 DPRINTK("ENTER\n");
d6ef3153 560
365cfa1e 561 ahci_stop_engine(ap);
d6ef3153 562
365cfa1e
AV		 563 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
564 deadline, &online, NULL);
d6ef3153
SH		 565
566 ahci_start_engine(ap);
d6ef3153 567
365cfa1e 568 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 569
365cfa1e
AV		 570 /* vt8251 doesn't clear BSY on signature FIS reception,
571 * request follow-up softreset.
572 */
573 return online ? -EAGAIN : rc;
7d50b60b
TH		 574}
575
365cfa1e
AV		 576static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
577 unsigned long deadline)
7d50b60b 578{
365cfa1e 579 struct ata_port *ap = link->ap;
1c954a4d 580 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 581 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
582 struct ata_taskfile tf;
583 bool online;
584 int rc;
7d50b60b 585
365cfa1e 586 ahci_stop_engine(ap);
028a2596 587
365cfa1e
AV		 588 /* clear D2H reception area to properly wait for D2H FIS */
589 ata_tf_init(link->device, &tf);
9bbb1b0e 590 tf.command = ATA_BUSY;
365cfa1e 591 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 592
365cfa1e
AV		 593 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
594 deadline, &online, NULL);
028a2596 595
365cfa1e 596 ahci_start_engine(ap);
c1332875 597
365cfa1e
AV		 598 /* The pseudo configuration device on SIMG4726 attached to
599 * ASUS P5W-DH Deluxe doesn't send signature FIS after
600 * hardreset if no device is attached to the first downstream
601 * port && the pseudo device locks up on SRST w/ PMP==0. To
602 * work around this, wait for !BSY only briefly. If BSY isn't
603 * cleared, perform CLO and proceed to IDENTIFY (achieved by
604 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
605 *
606 * Wait for two seconds. Devices attached to downstream port
607 * which can't process the following IDENTIFY after this will
608 * have to be reset again. For most cases, this should
609 * suffice while making probing snappish enough.
610 */
611 if (online) {
612 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
613 ahci_check_ready);
614 if (rc)
615 ahci_kick_engine(ap);
c1332875 616 }
c1332875
TH		 617 return rc;
618}
619
365cfa1e 620#ifdef CONFIG_PM
c1332875
TH		 621static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
622{
0a86e1c8 623 struct ata_host *host = pci_get_drvdata(pdev);
9b10ae86 624 struct ahci_host_priv *hpriv = host->private_data;
d8993349 625 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 626 u32 ctl;
627
9b10ae86
TH		 628 if (mesg.event & PM_EVENT_SUSPEND &&
629 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 630 dev_err(&pdev->dev,
631 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 632 return -EIO;
633 }
634
3a2d5b70 635 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 636 /* AHCI spec rev1.1 section 8.3.3:
637 * Software must disable interrupts prior to requesting a
638 * transition of the HBA to D3 state.
639 */
640 ctl = readl(mmio + HOST_CTL);
641 ctl &= ~HOST_IRQ_EN;
642 writel(ctl, mmio + HOST_CTL);
643 readl(mmio + HOST_CTL); /* flush */
644 }
645
646 return ata_pci_device_suspend(pdev, mesg);
647}
648
649static int ahci_pci_device_resume(struct pci_dev *pdev)
650{
0a86e1c8 651 struct ata_host *host = pci_get_drvdata(pdev);
c1332875
TH		 652 int rc;
653
553c4aa6
TH		 654 rc = ata_pci_device_do_resume(pdev);
655 if (rc)
656 return rc;
c1332875
TH		 657
658 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 659 rc = ahci_pci_reset_controller(host);
c1332875
TH		 660 if (rc)
661 return rc;
662
781d6550 663 ahci_pci_init_controller(host);
c1332875
TH		 664 }
665
cca3974e 666 ata_host_resume(host);
c1332875
TH		 667
668 return 0;
669}
438ac6d5 670#endif
c1332875 671
4447d351 672static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 673{
1da177e4 674 int rc;
1da177e4 675
318893e1
AR		 676 /*
677 * If the device fixup already set the dma_mask to some non-standard
678 * value, don't extend it here. This happens on STA2X11, for example.
679 */
680 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
681 return 0;
682
1da177e4 683 if (using_dac &&
6a35528a
YH		 684 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
685 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 686 if (rc) {
284901a9 687 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 688 if (rc) {
a44fec1f
JP		 689 dev_err(&pdev->dev,
690 "64-bit DMA enable failed\n");
1da177e4
LT		 691 return rc;
692 }
693 }
1da177e4 694 } else {
284901a9 695 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 696 if (rc) {
a44fec1f 697 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 698 return rc;
699 }
284901a9 700 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 701 if (rc) {
a44fec1f
JP		 702 dev_err(&pdev->dev,
703 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 704 return rc;
705 }
706 }
1da177e4
LT		 707 return 0;
708}
709
439fcaec
AV		 710static void ahci_pci_print_info(struct ata_host *host)
711{
712 struct pci_dev *pdev = to_pci_dev(host->dev);
713 u16 cc;
714 const char *scc_s;
715
716 pci_read_config_word(pdev, 0x0a, &cc);
717 if (cc == PCI_CLASS_STORAGE_IDE)
718 scc_s = "IDE";
719 else if (cc == PCI_CLASS_STORAGE_SATA)
720 scc_s = "SATA";
721 else if (cc == PCI_CLASS_STORAGE_RAID)
722 scc_s = "RAID";
723 else
724 scc_s = "unknown";
725
726 ahci_print_info(host, scc_s);
727}
728
edc93052
TH		 729/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
730 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
731 * support PMP and the 4726 either directly exports the device
732 * attached to the first downstream port or acts as a hardware storage
733 * controller and emulate a single ATA device (can be RAID 0/1 or some
734 * other configuration).
735 *
736 * When there's no device attached to the first downstream port of the
737 * 4726, "Config Disk" appears, which is a pseudo ATA device to
738 * configure the 4726. However, ATA emulation of the device is very
739 * lame. It doesn't send signature D2H Reg FIS after the initial
740 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
741 *
742 * The following function works around the problem by always using
743 * hardreset on the port and not depending on receiving signature FIS
744 * afterward. If signature FIS isn't received soon, ATA class is
745 * assumed without follow-up softreset.
746 */
747static void ahci_p5wdh_workaround(struct ata_host *host)
748{
749 static struct dmi_system_id sysids[] = {
750 {
751 .ident = "P5W DH Deluxe",
752 .matches = {
753 DMI_MATCH(DMI_SYS_VENDOR,
754 "ASUSTEK COMPUTER INC"),
755 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
756 },
757 },
758 { }
759 };
760 struct pci_dev *pdev = to_pci_dev(host->dev);
761
762 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
763 dmi_check_system(sysids)) {
764 struct ata_port *ap = host->ports[1];
765
a44fec1f
JP		 766 dev_info(&pdev->dev,
767 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 768
769 ap->ops = &ahci_p5wdh_ops;
770 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
771 }
772}
773
2fcad9d2
TH		 774/* only some SB600 ahci controllers can do 64bit DMA */
775static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 776{
777 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 778 /*
779 * The oldest version known to be broken is 0901 and
780 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 781 * Enable 64bit DMA on 1501 and anything newer.
782 *
03d783bf
TH		 783 * Please read bko#9412 for more info.
784 */
58a09b38
SH		 785 {
786 .ident = "ASUS M2A-VM",
787 .matches = {
788 DMI_MATCH(DMI_BOARD_VENDOR,
789 "ASUSTeK Computer INC."),
790 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
791 },
03d783bf 792 .driver_data = "20071026", /* yyyymmdd */
58a09b38 793 },
e65cc194
MN		 794 /*
795 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
796 * support 64bit DMA.
797 *
798 * BIOS versions earlier than 1.5 had the Manufacturer DMI
799 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
800 * This spelling mistake was fixed in BIOS version 1.5, so
801 * 1.5 and later have the Manufacturer as
802 * "MICRO-STAR INTERNATIONAL CO.,LTD".
803 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
804 *
805 * BIOS versions earlier than 1.9 had a Board Product Name
806 * DMI field of "MS-7376". This was changed to be
807 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
808 * match on DMI_BOARD_NAME of "MS-7376".
809 */
810 {
811 .ident = "MSI K9A2 Platinum",
812 .matches = {
813 DMI_MATCH(DMI_BOARD_VENDOR,
814 "MICRO-STAR INTER"),
815 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
816 },
817 },
ff0173c1
MN		 818 /*
819 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
820 * 64bit DMA.
821 *
822 * This board also had the typo mentioned above in the
823 * Manufacturer DMI field (fixed in BIOS version 1.5), so
824 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
825 */
826 {
827 .ident = "MSI K9AGM2",
828 .matches = {
829 DMI_MATCH(DMI_BOARD_VENDOR,
830 "MICRO-STAR INTER"),
831 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
832 },
833 },
3c4aa91f
MN		 834 /*
835 * All BIOS versions for the Asus M3A support 64bit DMA.
836 * (all release versions from 0301 to 1206 were tested)
837 */
838 {
839 .ident = "ASUS M3A",
840 .matches = {
841 DMI_MATCH(DMI_BOARD_VENDOR,
842 "ASUSTeK Computer INC."),
843 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
844 },
845 },
58a09b38
SH		 846 { }
847 };
03d783bf 848 const struct dmi_system_id *match;
2fcad9d2
TH		 849 int year, month, date;
850 char buf[9];
58a09b38 851
03d783bf 852 match = dmi_first_match(sysids);
58a09b38 853 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 854 !match)
58a09b38
SH		 855 return false;
856
e65cc194
MN		 857 if (!match->driver_data)
858 goto enable_64bit;
859
2fcad9d2
TH		 860 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
861 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 862
e65cc194
MN		 863 if (strcmp(buf, match->driver_data) >= 0)
864 goto enable_64bit;
865 else {
a44fec1f
JP		 866 dev_warn(&pdev->dev,
867 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
868 match->ident);
2fcad9d2
TH		 869 return false;
870 }
e65cc194
MN		 871
872enable_64bit:
a44fec1f 873 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 874 return true;
58a09b38
SH		 875}
876
1fd68434
RW		 877static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
878{
879 static const struct dmi_system_id broken_systems[] = {
880 {
881 .ident = "HP Compaq nx6310",
882 .matches = {
883 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
884 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
885 },
886 /* PCI slot number of the controller */
887 .driver_data = (void *)0x1FUL,
888 },
d2f9c061
MR		 889 {
890 .ident = "HP Compaq 6720s",
891 .matches = {
892 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
893 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
894 },
895 /* PCI slot number of the controller */
896 .driver_data = (void *)0x1FUL,
897 },
1fd68434
RW		 898
899 { } /* terminate list */
900 };
901 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
902
903 if (dmi) {
904 unsigned long slot = (unsigned long)dmi->driver_data;
905 /* apply the quirk only to on-board controllers */
906 return slot == PCI_SLOT(pdev->devfn);
907 }
908
909 return false;
910}
911
9b10ae86
TH		 912static bool ahci_broken_suspend(struct pci_dev *pdev)
913{
914 static const struct dmi_system_id sysids[] = {
915 /*
916 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
917 * to the harddisk doesn't become online after
918 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 919 *
920 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
921 *
922 * Use dates instead of versions to match as HP is
923 * apparently recycling both product and version
924 * strings.
925 *
926 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 927 */
928 {
929 .ident = "dv4",
930 .matches = {
931 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
932 DMI_MATCH(DMI_PRODUCT_NAME,
933 "HP Pavilion dv4 Notebook PC"),
934 },
9deb3431 935 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 936 },
937 {
938 .ident = "dv5",
939 .matches = {
940 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
941 DMI_MATCH(DMI_PRODUCT_NAME,
942 "HP Pavilion dv5 Notebook PC"),
943 },
9deb3431 944 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 945 },
946 {
947 .ident = "dv6",
948 .matches = {
949 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
950 DMI_MATCH(DMI_PRODUCT_NAME,
951 "HP Pavilion dv6 Notebook PC"),
952 },
9deb3431 953 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 954 },
955 {
956 .ident = "HDX18",
957 .matches = {
958 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
959 DMI_MATCH(DMI_PRODUCT_NAME,
960 "HP HDX18 Notebook PC"),
961 },
9deb3431 962 .driver_data = "20090430", /* F.23 */
9b10ae86 963 },
cedc9bf9
TH		 964 /*
965 * Acer eMachines G725 has the same problem. BIOS
966 * V1.03 is known to be broken. V3.04 is known to
25985edc 967 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 968 * that we don't have much idea about. For now,
969 * blacklist anything older than V3.04.
9deb3431
TH		 970 *
971 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 972 */
973 {
974 .ident = "G725",
975 .matches = {
976 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
977 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
978 },
9deb3431 979 .driver_data = "20091216", /* V3.04 */
cedc9bf9 980 },
9b10ae86
TH		 981 { } /* terminate list */
982 };
983 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 984 int year, month, date;
985 char buf[9];
9b10ae86
TH		 986
987 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
988 return false;
989
9deb3431
TH		 990 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
991 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 992
9deb3431 993 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 994}
995
5594639a
TH		 996static bool ahci_broken_online(struct pci_dev *pdev)
997{
998#define ENCODE_BUSDEVFN(bus, slot, func) \
999 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1000 static const struct dmi_system_id sysids[] = {
1001 /*
1002 * There are several gigabyte boards which use
1003 * SIMG5723s configured as hardware RAID. Certain
1004 * 5723 firmware revisions shipped there keep the link
1005 * online but fail to answer properly to SRST or
1006 * IDENTIFY when no device is attached downstream
1007 * causing libata to retry quite a few times leading
1008 * to excessive detection delay.
1009 *
1010 * As these firmwares respond to the second reset try
1011 * with invalid device signature, considering unknown
1012 * sig as offline works around the problem acceptably.
1013 */
1014 {
1015 .ident = "EP45-DQ6",
1016 .matches = {
1017 DMI_MATCH(DMI_BOARD_VENDOR,
1018 "Gigabyte Technology Co., Ltd."),
1019 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1020 },
1021 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1022 },
1023 {
1024 .ident = "EP45-DS5",
1025 .matches = {
1026 DMI_MATCH(DMI_BOARD_VENDOR,
1027 "Gigabyte Technology Co., Ltd."),
1028 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1029 },
1030 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1031 },
1032 { } /* terminate list */
1033 };
1034#undef ENCODE_BUSDEVFN
1035 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1036 unsigned int val;
1037
1038 if (!dmi)
1039 return false;
1040
1041 val = (unsigned long)dmi->driver_data;
1042
1043 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1044}
1045
8e513217 1046#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1047static void ahci_gtf_filter_workaround(struct ata_host *host)
1048{
1049 static const struct dmi_system_id sysids[] = {
1050 /*
1051 * Aspire 3810T issues a bunch of SATA enable commands
1052 * via _GTF including an invalid one and one which is
1053 * rejected by the device. Among the successful ones
1054 * is FPDMA non-zero offset enable which when enabled
1055 * only on the drive side leads to NCQ command
1056 * failures. Filter it out.
1057 */
1058 {
1059 .ident = "Aspire 3810T",
1060 .matches = {
1061 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1062 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1063 },
1064 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1065 },
1066 { }
1067 };
1068 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1069 unsigned int filter;
1070 int i;
1071
1072 if (!dmi)
1073 return;
1074
1075 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1076 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1077 filter, dmi->ident);
f80ae7e4
TH		 1078
1079 for (i = 0; i < host->n_ports; i++) {
1080 struct ata_port *ap = host->ports[i];
1081 struct ata_link *link;
1082 struct ata_device *dev;
1083
1084 ata_for_each_link(link, ap, EDGE)
1085 ata_for_each_dev(dev, link, ALL)
1086 dev->gtf_filter |= filter;
1087 }
1088}
8e513217
MT		 1089#else
1090static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1091{}
1092#endif
f80ae7e4 1093
5ca72c4f
AG		 1094int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1095{
1096 int rc;
1097 unsigned int maxvec;
1098
1099 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1100 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1101 if (rc > 0) {
1102 if ((rc == maxvec) || (rc == 1))
1103 return rc;
1104 /*
1105 * Assume that advantage of multipe MSIs is negated,
1106 * so fallback to single MSI mode to save resources
1107 */
1108 pci_disable_msi(pdev);
1109 if (!pci_enable_msi(pdev))
1110 return 1;
1111 }
1112 }
1113
1114 pci_intx(pdev, 1);
1115 return 0;
1116}
1117
1118/**
1119 * ahci_host_activate - start AHCI host, request IRQs and register it
1120 * @host: target ATA host
1121 * @irq: base IRQ number to request
1122 * @n_msis: number of MSIs allocated for this host
1123 * @irq_handler: irq_handler used when requesting IRQs
1124 * @irq_flags: irq_flags used when requesting IRQs
1125 *
1126 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1127 * when multiple MSIs were allocated. That is one MSI per port, starting
1128 * from @irq.
1129 *
1130 * LOCKING:
1131 * Inherited from calling layer (may sleep).
1132 *
1133 * RETURNS:
1134 * 0 on success, -errno otherwise.
1135 */
1136int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1137{
1138 int i, rc;
1139
1140 /* Sharing Last Message among several ports is not supported */
1141 if (n_msis < host->n_ports)
1142 return -EINVAL;
1143
1144 rc = ata_host_start(host);
1145 if (rc)
1146 return rc;
1147
1148 for (i = 0; i < host->n_ports; i++) {
c91bc6cc 1149 const char* desc;
b29900e6
AG		 1150 struct ahci_port_priv *pp = host->ports[i]->private_data;
1151
c91bc6cc
XF		 1152 /* pp is NULL for dummy ports */
1153 if (pp)
1154 desc = pp->irq_desc;
1155 else
1156 desc = dev_driver_string(host->dev);
1157
5ca72c4f
AG		 1158 rc = devm_request_threaded_irq(host->dev,
1159 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
c91bc6cc 1160 desc, host->ports[i]);
5ca72c4f
AG		 1161 if (rc)
1162 goto out_free_irqs;
1163 }
1164
1165 for (i = 0; i < host->n_ports; i++)
1166 ata_port_desc(host->ports[i], "irq %d", irq + i);
1167
1168 rc = ata_host_register(host, &ahci_sht);
1169 if (rc)
1170 goto out_free_all_irqs;
1171
1172 return 0;
1173
1174out_free_all_irqs:
1175 i = host->n_ports;
1176out_free_irqs:
1177 for (i--; i >= 0; i--)
1178 devm_free_irq(host->dev, irq + i, host->ports[i]);
1179
1180 return rc;
1181}
1182
24dc5f33 1183static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1184{
e297d99e
TH		 1185 unsigned int board_id = ent->driver_data;
1186 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1187 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1188 struct device *dev = &pdev->dev;
1da177e4 1189 struct ahci_host_priv *hpriv;
4447d351 1190 struct ata_host *host;
5ca72c4f 1191 int n_ports, n_msis, i, rc;
318893e1 1192 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1193
1194 VPRINTK("ENTER\n");
1195
b429dd59 1196 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1197
06296a1e 1198 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1199
5b66c829
AC		 1200 /* The AHCI driver can only drive the SATA ports, the PATA driver
1201 can drive them all so if both drivers are selected make sure
1202 AHCI stays out of the way */
1203 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1204 return -ENODEV;
1205
c6353b45
TH		 1206 /*
1207 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1208 * ahci, use ata_generic instead.
1209 */
1210 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1211 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1212 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1213 pdev->subsystem_device == 0xcb89)
1214 return -ENODEV;
1215
7a02267e
MN		 1216 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1217 * At the moment, we can only use the AHCI mode. Let the users know
1218 * that for SAS drives they're out of luck.
1219 */
1220 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1221 dev_info(&pdev->dev,
1222 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1223
7f9c9f8e 1224 /* Both Connext and Enmotus devices use non-standard BARs */
318893e1
AR		 1225 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1226 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
7f9c9f8e
HD		 1227 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1228 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
318893e1 1229
4447d351 1230 /* acquire resources */
24dc5f33 1231 rc = pcim_enable_device(pdev);
1da177e4
LT		 1232 if (rc)
1233 return rc;
1234
dea55137
TH		 1235 /* AHCI controllers often implement SFF compatible interface.
1236 * Grab all PCI BARs just in case.
1237 */
318893e1 1238 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1239 if (rc == -EBUSY)
24dc5f33 1240 pcim_pin_device(pdev);
0d5ff566 1241 if (rc)
24dc5f33 1242 return rc;
1da177e4 1243
c4f7792c
TH		 1244 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1245 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1246 u8 map;
1247
1248 /* ICH6s share the same PCI ID for both piix and ahci
1249 * modes. Enabling ahci mode while MAP indicates
1250 * combined mode is a bad idea. Yield to ata_piix.
1251 */
1252 pci_read_config_byte(pdev, ICH_MAP, &map);
1253 if (map & 0x3) {
a44fec1f
JP		 1254 dev_info(&pdev->dev,
1255 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1256 return -ENODEV;
1257 }
1258 }
1259
24dc5f33
TH		 1260 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1261 if (!hpriv)
1262 return -ENOMEM;
417a1a6d
TH		 1263 hpriv->flags |= (unsigned long)pi.private_data;
1264
e297d99e
TH		 1265 /* MCP65 revision A1 and A2 can't do MSI */
1266 if (board_id == board_ahci_mcp65 &&
1267 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1268 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1269
e427fe04
SH		 1270 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1271 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1272 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1273
2fcad9d2
TH		 1274 /* only some SB600s can do 64bit DMA */
1275 if (ahci_sb600_enable_64bit(pdev))
1276 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1277
318893e1 1278 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1279
5ca72c4f
AG		 1280 n_msis = ahci_init_interrupts(pdev, hpriv);
1281 if (n_msis > 1)
1282 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1283
4447d351 1284 /* save initial config */
394d6e53 1285 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1286
4447d351 1287 /* prepare host */
453d3131
RH		 1288 if (hpriv->cap & HOST_CAP_NCQ) {
1289 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1290 /*
1291 * Auto-activate optimization is supposed to be
1292 * supported on all AHCI controllers indicating NCQ
1293 * capability, but it seems to be broken on some
1294 * chipsets including NVIDIAs.
1295 */
1296 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131 1297 pi.flags |= ATA_FLAG_FPDMA_AA;
40fb59e7
MC		 1298
1299 /*
1300 * All AHCI controllers should be forward-compatible
1301 * with the new auxiliary field. This code should be
1302 * conditionalized if any buggy AHCI controllers are
1303 * encountered.
1304 */
1305 pi.flags |= ATA_FLAG_FPDMA_AUX;
453d3131 1306 }
1da177e4 1307
7d50b60b
TH		 1308 if (hpriv->cap & HOST_CAP_PMP)
1309 pi.flags |= ATA_FLAG_PMP;
1310
0cbb0e77 1311 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1312
1fd68434
RW		 1313 if (ahci_broken_system_poweroff(pdev)) {
1314 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1315 dev_info(&pdev->dev,
1316 "quirky BIOS, skipping spindown on poweroff\n");
1317 }
1318
9b10ae86
TH		 1319 if (ahci_broken_suspend(pdev)) {
1320 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1321 dev_warn(&pdev->dev,
1322 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1323 }
1324
5594639a
TH		 1325 if (ahci_broken_online(pdev)) {
1326 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1327 dev_info(&pdev->dev,
1328 "online status unreliable, applying workaround\n");
1329 }
1330
837f5f8f
TH		 1331 /* CAP.NP sometimes indicate the index of the last enabled
1332 * port, at other times, that of the last possible port, so
1333 * determining the maximum port number requires looking at
1334 * both CAP.NP and port_map.
1335 */
1336 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1337
1338 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1339 if (!host)
1340 return -ENOMEM;
4447d351
TH		 1341 host->private_data = hpriv;
1342
f3d7f23f 1343 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1344 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1345 else
1346 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1347
18f7ba4c
KCA		 1348 if (pi.flags & ATA_FLAG_EM)
1349 ahci_reset_em(host);
1350
4447d351 1351 for (i = 0; i < host->n_ports; i++) {
dab632e8 1352 struct ata_port *ap = host->ports[i];
4447d351 1353
318893e1
AR		 1354 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1355 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1356 0x100 + ap->port_no * 0x80, "port");
1357
18f7ba4c
KCA		 1358 /* set enclosure management message type */
1359 if (ap->flags & ATA_FLAG_EM)
008dbd61 1360 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1361
1362
dab632e8 1363 /* disabled/not-implemented port */
350756f6 1364 if (!(hpriv->port_map & (1 << i)))
dab632e8 1365 ap->ops = &ata_dummy_port_ops;
4447d351 1366 }
d447df14 1367
edc93052
TH		 1368 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1369 ahci_p5wdh_workaround(host);
1370
f80ae7e4
TH		 1371 /* apply gtf filter quirk */
1372 ahci_gtf_filter_workaround(host);
1373
4447d351
TH		 1374 /* initialize adapter */
1375 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1376 if (rc)
24dc5f33 1377 return rc;
1da177e4 1378
3303040d 1379 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1380 if (rc)
1381 return rc;
1da177e4 1382
781d6550 1383 ahci_pci_init_controller(host);
439fcaec 1384 ahci_pci_print_info(host);
1da177e4 1385
4447d351 1386 pci_set_master(pdev);
5ca72c4f
AG		 1387
1388 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1389 return ahci_host_activate(host, pdev->irq, n_msis);
1390
4447d351
TH		 1391 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1392 &ahci_sht);
907f4678 1393}
1da177e4 1394
2fc75da0 1395module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1396
1397MODULE_AUTHOR("Jeff Garzik");
1398MODULE_DESCRIPTION("AHCI SATA low-level driver");
1399MODULE_LICENSE("GPL");
1400MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1401MODULE_VERSION(DRV_VERSION);
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