[mirror_ubuntu-jammy-kernel.git] / drivers / ata / ahci.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 *  ahci.h - Common AHCI SATA definitions and declarations
 *
 *  Maintained by:  Tejun Heo <tj@kernel.org>
 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004-2005 Red Hat, Inc.
 *
 * libata documentation is available via 'make {ps|pdf}docs',
 * as Documentation/driver-api/libata.rst
 *
 * AHCI hardware documentation:
 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
 */

#ifndef _AHCI_H
#define _AHCI_H

#include <linux/pci.h>
#include <linux/clk.h>
#include <linux/libata.h>
#include <linux/phy/phy.h>
#include <linux/regulator/consumer.h>

/* Enclosure Management Control */
#define EM_CTRL_MSG_TYPE              0x000f0000

/* Enclosure Management LED Message Type */
#define EM_MSG_LED_HBA_PORT           0x0000000f
#define EM_MSG_LED_PMP_SLOT           0x0000ff00
#define EM_MSG_LED_VALUE              0xffff0000
#define EM_MSG_LED_VALUE_ACTIVITY     0x00070000
#define EM_MSG_LED_VALUE_OFF          0xfff80000
#define EM_MSG_LED_VALUE_ON           0x00010000

enum {
	AHCI_MAX_PORTS		= 32,
	AHCI_MAX_CLKS		= 5,
	AHCI_MAX_SG		= 168, /* hardware max is 64K */
	AHCI_DMA_BOUNDARY	= 0xffffffff,
	AHCI_MAX_CMDS		= 32,
	AHCI_CMD_SZ		= 32,
	AHCI_CMD_SLOT_SZ	= AHCI_MAX_CMDS * AHCI_CMD_SZ,
	AHCI_RX_FIS_SZ		= 256,
	AHCI_CMD_TBL_CDB	= 0x40,
	AHCI_CMD_TBL_HDR_SZ	= 0x80,
	AHCI_CMD_TBL_SZ		= AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
	AHCI_CMD_TBL_AR_SZ	= AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
	AHCI_PORT_PRIV_DMA_SZ	= AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
				  AHCI_RX_FIS_SZ,
	AHCI_PORT_PRIV_FBS_DMA_SZ	= AHCI_CMD_SLOT_SZ +
					  AHCI_CMD_TBL_AR_SZ +
					  (AHCI_RX_FIS_SZ * 16),
	AHCI_IRQ_ON_SG		= (1 << 31),
	AHCI_CMD_ATAPI		= (1 << 5),
	AHCI_CMD_WRITE		= (1 << 6),
	AHCI_CMD_PREFETCH	= (1 << 7),
	AHCI_CMD_RESET		= (1 << 8),
	AHCI_CMD_CLR_BUSY	= (1 << 10),

	RX_FIS_PIO_SETUP	= 0x20,	/* offset of PIO Setup FIS data */
	RX_FIS_D2H_REG		= 0x40,	/* offset of D2H Register FIS data */
	RX_FIS_SDB		= 0x58, /* offset of SDB FIS data */
	RX_FIS_UNK		= 0x60, /* offset of Unknown FIS data */

	/* global controller registers */
	HOST_CAP		= 0x00, /* host capabilities */
	HOST_CTL		= 0x04, /* global host control */
	HOST_IRQ_STAT		= 0x08, /* interrupt status */
	HOST_PORTS_IMPL		= 0x0c, /* bitmap of implemented ports */
	HOST_VERSION		= 0x10, /* AHCI spec. version compliancy */
	HOST_EM_LOC		= 0x1c, /* Enclosure Management location */
	HOST_EM_CTL		= 0x20, /* Enclosure Management Control */
	HOST_CAP2		= 0x24, /* host capabilities, extended */

	/* HOST_CTL bits */
	HOST_RESET		= (1 << 0),  /* reset controller; self-clear */
	HOST_IRQ_EN		= (1 << 1),  /* global IRQ enable */
	HOST_MRSM		= (1 << 2),  /* MSI Revert to Single Message */
	HOST_AHCI_EN		= (1 << 31), /* AHCI enabled */

	/* HOST_CAP bits */
	HOST_CAP_SXS		= (1 << 5),  /* Supports External SATA */
	HOST_CAP_EMS		= (1 << 6),  /* Enclosure Management support */
	HOST_CAP_CCC		= (1 << 7),  /* Command Completion Coalescing */
	HOST_CAP_PART		= (1 << 13), /* Partial state capable */
	HOST_CAP_SSC		= (1 << 14), /* Slumber state capable */
	HOST_CAP_PIO_MULTI	= (1 << 15), /* PIO multiple DRQ support */
	HOST_CAP_FBS		= (1 << 16), /* FIS-based switching support */
	HOST_CAP_PMP		= (1 << 17), /* Port Multiplier support */
	HOST_CAP_ONLY		= (1 << 18), /* Supports AHCI mode only */
	HOST_CAP_CLO		= (1 << 24), /* Command List Override support */
	HOST_CAP_LED		= (1 << 25), /* Supports activity LED */
	HOST_CAP_ALPM		= (1 << 26), /* Aggressive Link PM support */
	HOST_CAP_SSS		= (1 << 27), /* Staggered Spin-up */
	HOST_CAP_MPS		= (1 << 28), /* Mechanical presence switch */
	HOST_CAP_SNTF		= (1 << 29), /* SNotification register */
	HOST_CAP_NCQ		= (1 << 30), /* Native Command Queueing */
	HOST_CAP_64		= (1 << 31), /* PCI DAC (64-bit DMA) support */

	/* HOST_CAP2 bits */
	HOST_CAP2_BOH		= (1 << 0),  /* BIOS/OS handoff supported */
	HOST_CAP2_NVMHCI	= (1 << 1),  /* NVMHCI supported */
	HOST_CAP2_APST		= (1 << 2),  /* Automatic partial to slumber */
	HOST_CAP2_SDS		= (1 << 3),  /* Support device sleep */
	HOST_CAP2_SADM		= (1 << 4),  /* Support aggressive DevSlp */
	HOST_CAP2_DESO		= (1 << 5),  /* DevSlp from slumber only */

	/* registers for each SATA port */
	PORT_LST_ADDR		= 0x00, /* command list DMA addr */
	PORT_LST_ADDR_HI	= 0x04, /* command list DMA addr hi */
	PORT_FIS_ADDR		= 0x08, /* FIS rx buf addr */
	PORT_FIS_ADDR_HI	= 0x0c, /* FIS rx buf addr hi */
	PORT_IRQ_STAT		= 0x10, /* interrupt status */
	PORT_IRQ_MASK		= 0x14, /* interrupt enable/disable mask */
	PORT_CMD		= 0x18, /* port command */
	PORT_TFDATA		= 0x20,	/* taskfile data */
	PORT_SIG		= 0x24,	/* device TF signature */
	PORT_CMD_ISSUE		= 0x38, /* command issue */
	PORT_SCR_STAT		= 0x28, /* SATA phy register: SStatus */
	PORT_SCR_CTL		= 0x2c, /* SATA phy register: SControl */
	PORT_SCR_ERR		= 0x30, /* SATA phy register: SError */
	PORT_SCR_ACT		= 0x34, /* SATA phy register: SActive */
	PORT_SCR_NTF		= 0x3c, /* SATA phy register: SNotification */
	PORT_FBS		= 0x40, /* FIS-based Switching */
	PORT_DEVSLP		= 0x44, /* device sleep */

	/* PORT_IRQ_{STAT,MASK} bits */
	PORT_IRQ_COLD_PRES	= (1 << 31), /* cold presence detect */
	PORT_IRQ_TF_ERR		= (1 << 30), /* task file error */
	PORT_IRQ_HBUS_ERR	= (1 << 29), /* host bus fatal error */
	PORT_IRQ_HBUS_DATA_ERR	= (1 << 28), /* host bus data error */
	PORT_IRQ_IF_ERR		= (1 << 27), /* interface fatal error */
	PORT_IRQ_IF_NONFATAL	= (1 << 26), /* interface non-fatal error */
	PORT_IRQ_OVERFLOW	= (1 << 24), /* xfer exhausted available S/G */
	PORT_IRQ_BAD_PMP	= (1 << 23), /* incorrect port multiplier */

	PORT_IRQ_PHYRDY		= (1 << 22), /* PhyRdy changed */
	PORT_IRQ_DEV_ILCK	= (1 << 7), /* device interlock */
	PORT_IRQ_CONNECT	= (1 << 6), /* port connect change status */
	PORT_IRQ_SG_DONE	= (1 << 5), /* descriptor processed */
	PORT_IRQ_UNK_FIS	= (1 << 4), /* unknown FIS rx'd */
	PORT_IRQ_SDB_FIS	= (1 << 3), /* Set Device Bits FIS rx'd */
	PORT_IRQ_DMAS_FIS	= (1 << 2), /* DMA Setup FIS rx'd */
	PORT_IRQ_PIOS_FIS	= (1 << 1), /* PIO Setup FIS rx'd */
	PORT_IRQ_D2H_REG_FIS	= (1 << 0), /* D2H Register FIS rx'd */

	PORT_IRQ_FREEZE		= PORT_IRQ_HBUS_ERR |
				  PORT_IRQ_IF_ERR |
				  PORT_IRQ_CONNECT |
				  PORT_IRQ_PHYRDY |
				  PORT_IRQ_UNK_FIS |
				  PORT_IRQ_BAD_PMP,
	PORT_IRQ_ERROR		= PORT_IRQ_FREEZE |
				  PORT_IRQ_TF_ERR |
				  PORT_IRQ_HBUS_DATA_ERR,
	DEF_PORT_IRQ		= PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
				  PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
				  PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,

	/* PORT_CMD bits */
	PORT_CMD_ASP		= (1 << 27), /* Aggressive Slumber/Partial */
	PORT_CMD_ALPE		= (1 << 26), /* Aggressive Link PM enable */
	PORT_CMD_ATAPI		= (1 << 24), /* Device is ATAPI */
	PORT_CMD_FBSCP		= (1 << 22), /* FBS Capable Port */
	PORT_CMD_ESP		= (1 << 21), /* External Sata Port */
	PORT_CMD_HPCP		= (1 << 18), /* HotPlug Capable Port */
	PORT_CMD_PMP		= (1 << 17), /* PMP attached */
	PORT_CMD_LIST_ON	= (1 << 15), /* cmd list DMA engine running */
	PORT_CMD_FIS_ON		= (1 << 14), /* FIS DMA engine running */
	PORT_CMD_FIS_RX		= (1 << 4), /* Enable FIS receive DMA engine */
	PORT_CMD_CLO		= (1 << 3), /* Command list override */
	PORT_CMD_POWER_ON	= (1 << 2), /* Power up device */
	PORT_CMD_SPIN_UP	= (1 << 1), /* Spin up device */
	PORT_CMD_START		= (1 << 0), /* Enable port DMA engine */

	PORT_CMD_ICC_MASK	= (0xf << 28), /* i/f ICC state mask */
	PORT_CMD_ICC_ACTIVE	= (0x1 << 28), /* Put i/f in active state */
	PORT_CMD_ICC_PARTIAL	= (0x2 << 28), /* Put i/f in partial state */
	PORT_CMD_ICC_SLUMBER	= (0x6 << 28), /* Put i/f in slumber state */

	/* PORT_FBS bits */
	PORT_FBS_DWE_OFFSET	= 16, /* FBS device with error offset */
	PORT_FBS_ADO_OFFSET	= 12, /* FBS active dev optimization offset */
	PORT_FBS_DEV_OFFSET	= 8,  /* FBS device to issue offset */
	PORT_FBS_DEV_MASK	= (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
	PORT_FBS_SDE		= (1 << 2), /* FBS single device error */
	PORT_FBS_DEC		= (1 << 1), /* FBS device error clear */
	PORT_FBS_EN		= (1 << 0), /* Enable FBS */

	/* PORT_DEVSLP bits */
	PORT_DEVSLP_DM_OFFSET	= 25,             /* DITO multiplier offset */
	PORT_DEVSLP_DM_MASK	= (0xf << 25),    /* DITO multiplier mask */
	PORT_DEVSLP_DITO_OFFSET	= 15,             /* DITO offset */
	PORT_DEVSLP_MDAT_OFFSET	= 10,             /* Minimum assertion time */
	PORT_DEVSLP_DETO_OFFSET	= 2,              /* DevSlp exit timeout */
	PORT_DEVSLP_DSP		= (1 << 1),       /* DevSlp present */
	PORT_DEVSLP_ADSE	= (1 << 0),       /* Aggressive DevSlp enable */

	/* hpriv->flags bits */

#define AHCI_HFLAGS(flags)		.private_data	= (void *)(flags)

	AHCI_HFLAG_NO_NCQ		= (1 << 0),
	AHCI_HFLAG_IGN_IRQ_IF_ERR	= (1 << 1), /* ignore IRQ_IF_ERR */
	AHCI_HFLAG_IGN_SERR_INTERNAL	= (1 << 2), /* ignore SERR_INTERNAL */
	AHCI_HFLAG_32BIT_ONLY		= (1 << 3), /* force 32bit */
	AHCI_HFLAG_MV_PATA		= (1 << 4), /* PATA port */
	AHCI_HFLAG_NO_MSI		= (1 << 5), /* no PCI MSI */
	AHCI_HFLAG_NO_PMP		= (1 << 6), /* no PMP */
	AHCI_HFLAG_SECT255		= (1 << 8), /* max 255 sectors */
	AHCI_HFLAG_YES_NCQ		= (1 << 9), /* force NCQ cap on */
	AHCI_HFLAG_NO_SUSPEND		= (1 << 10), /* don't suspend */
	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= (1 << 11), /* treat SRST timeout as
							link offline */
	AHCI_HFLAG_NO_SNTF		= (1 << 12), /* no sntf */
	AHCI_HFLAG_NO_FPDMA_AA		= (1 << 13), /* no FPDMA AA */
	AHCI_HFLAG_YES_FBS		= (1 << 14), /* force FBS cap on */
	AHCI_HFLAG_DELAY_ENGINE		= (1 << 15), /* do not start engine on
						        port start (wait until
						        error-handling stage) */
	AHCI_HFLAG_NO_DEVSLP		= (1 << 17), /* no device sleep */
	AHCI_HFLAG_NO_FBS		= (1 << 18), /* no FBS */

#ifdef CONFIG_PCI_MSI
	AHCI_HFLAG_MULTI_MSI		= (1 << 20), /* per-port MSI(-X) */
#else
	/* compile out MSI infrastructure */
	AHCI_HFLAG_MULTI_MSI		= 0,
#endif
	AHCI_HFLAG_WAKE_BEFORE_STOP	= (1 << 22), /* wake before DMA stop */
	AHCI_HFLAG_YES_ALPM		= (1 << 23), /* force ALPM cap on */
	AHCI_HFLAG_NO_WRITE_TO_RO	= (1 << 24), /* don't write to read
							only registers */
	AHCI_HFLAG_IS_MOBILE		= (1 << 25), /* mobile chipset, use
							SATA_MOBILE_LPM_POLICY
							as default lpm_policy */
	AHCI_HFLAG_SUSPEND_PHYS		= (1 << 26), /* handle PHYs during
							suspend/resume */

	/* ap->flags bits */

	AHCI_FLAG_COMMON		= ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
					  ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,

	ICH_MAP				= 0x90, /* ICH MAP register */
	PCS_6				= 0x92, /* 6 port PCS */
	PCS_7				= 0x94, /* 7+ port PCS (Denverton) */

	/* em constants */
	EM_MAX_SLOTS			= 8,
	EM_MAX_RETRY			= 5,

	/* em_ctl bits */
	EM_CTL_RST		= (1 << 9), /* Reset */
	EM_CTL_TM		= (1 << 8), /* Transmit Message */
	EM_CTL_MR		= (1 << 0), /* Message Received */
	EM_CTL_ALHD		= (1 << 26), /* Activity LED */
	EM_CTL_XMT		= (1 << 25), /* Transmit Only */
	EM_CTL_SMB		= (1 << 24), /* Single Message Buffer */
	EM_CTL_SGPIO		= (1 << 19), /* SGPIO messages supported */
	EM_CTL_SES		= (1 << 18), /* SES-2 messages supported */
	EM_CTL_SAFTE		= (1 << 17), /* SAF-TE messages supported */
	EM_CTL_LED		= (1 << 16), /* LED messages supported */

	/* em message type */
	EM_MSG_TYPE_LED		= (1 << 0), /* LED */
	EM_MSG_TYPE_SAFTE	= (1 << 1), /* SAF-TE */
	EM_MSG_TYPE_SES2	= (1 << 2), /* SES-2 */
	EM_MSG_TYPE_SGPIO	= (1 << 3), /* SGPIO */
};

struct ahci_cmd_hdr {
	__le32			opts;
	__le32			status;
	__le32			tbl_addr;
	__le32			tbl_addr_hi;
	__le32			reserved[4];
};

struct ahci_sg {
	__le32			addr;
	__le32			addr_hi;
	__le32			reserved;
	__le32			flags_size;
};

struct ahci_em_priv {
	enum sw_activity blink_policy;
	struct timer_list timer;
	unsigned long saved_activity;
	unsigned long activity;
	unsigned long led_state;
	struct ata_link *link;
};

struct ahci_port_priv {
	struct ata_link		*active_link;
	struct ahci_cmd_hdr	*cmd_slot;
	dma_addr_t		cmd_slot_dma;
	void			*cmd_tbl;
	dma_addr_t		cmd_tbl_dma;
	void			*rx_fis;
	dma_addr_t		rx_fis_dma;
	/* for NCQ spurious interrupt analysis */
	unsigned int		ncq_saw_d2h:1;
	unsigned int		ncq_saw_dmas:1;
	unsigned int		ncq_saw_sdb:1;
	spinlock_t		lock;		/* protects parent ata_port */
	u32 			intr_mask;	/* interrupts to enable */
	bool			fbs_supported;	/* set iff FBS is supported */
	bool			fbs_enabled;	/* set iff FBS is enabled */
	int			fbs_last_dev;	/* save FBS.DEV of last FIS */
	/* enclosure management info per PM slot */
	struct ahci_em_priv	em_priv[EM_MAX_SLOTS];
	char			*irq_desc;	/* desc in /proc/interrupts */
};

struct ahci_host_priv {
	/* Input fields */
	unsigned int		flags;		/* AHCI_HFLAG_* */
	u32			force_port_map;	/* force port map */
	u32			mask_port_map;	/* mask out particular bits */

	void __iomem *		mmio;		/* bus-independent mem map */
	u32			cap;		/* cap to use */
	u32			cap2;		/* cap2 to use */
	u32			version;	/* cached version */
	u32			port_map;	/* port map to use */
	u32			saved_cap;	/* saved initial cap */
	u32			saved_cap2;	/* saved initial cap2 */
	u32			saved_port_map;	/* saved initial port_map */
	u32 			em_loc; /* enclosure management location */
	u32			em_buf_sz;	/* EM buffer size in byte */
	u32			em_msg_type;	/* EM message type */
	u32			remapped_nvme;	/* NVMe remapped device count */
	bool			got_runtime_pm; /* Did we do pm_runtime_get? */
	struct clk		*clks[AHCI_MAX_CLKS]; /* Optional */
	struct reset_control	*rsts;		/* Optional */
	struct regulator	**target_pwrs;	/* Optional */
	struct regulator	*ahci_regulator;/* Optional */
	struct regulator	*phy_regulator;/* Optional */
	/*
	 * If platform uses PHYs. There is a 1:1 relation between the port number and
	 * the PHY position in this array.
	 */
	struct phy		**phys;
	unsigned		nports;		/* Number of ports */
	void			*plat_data;	/* Other platform data */
	unsigned int		irq;		/* interrupt line */
	/*
	 * Optional ahci_start_engine override, if not set this gets set to the
	 * default ahci_start_engine during ahci_save_initial_config, this can
	 * be overridden anytime before the host is activated.
	 */
	void			(*start_engine)(struct ata_port *ap);
	/*
	 * Optional ahci_stop_engine override, if not set this gets set to the
	 * default ahci_stop_engine during ahci_save_initial_config, this can
	 * be overridden anytime before the host is activated.
	 */
	int			(*stop_engine)(struct ata_port *ap);

	irqreturn_t 		(*irq_handler)(int irq, void *dev_instance);

	/* only required for per-port MSI(-X) support */
	int			(*get_irq_vector)(struct ata_host *host,
						  int port);
};

extern int ahci_ignore_sss;

extern struct device_attribute *ahci_shost_attrs[];
extern struct device_attribute *ahci_sdev_attrs[];

/*
 * This must be instantiated by the edge drivers.  Read the comments
 * for ATA_BASE_SHT
 */
#define AHCI_SHT(drv_name)						\
	ATA_NCQ_SHT(drv_name),						\
	.can_queue		= AHCI_MAX_CMDS,			\
	.sg_tablesize		= AHCI_MAX_SG,				\
	.dma_boundary		= AHCI_DMA_BOUNDARY,			\
	.shost_attrs		= ahci_shost_attrs,			\
	.sdev_attrs		= ahci_sdev_attrs

extern struct ata_port_operations ahci_ops;
extern struct ata_port_operations ahci_platform_ops;
extern struct ata_port_operations ahci_pmp_retry_srst_ops;

unsigned int ahci_dev_classify(struct ata_port *ap);
void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
			u32 opts);
void ahci_save_initial_config(struct device *dev,
			      struct ahci_host_priv *hpriv);
void ahci_init_controller(struct ata_host *host);
int ahci_reset_controller(struct ata_host *host);

int ahci_do_softreset(struct ata_link *link, unsigned int *class,
		      int pmp, unsigned long deadline,
		      int (*check_ready)(struct ata_link *link));

int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
		      unsigned long deadline, bool *online);

unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
int ahci_stop_engine(struct ata_port *ap);
void ahci_start_fis_rx(struct ata_port *ap);
void ahci_start_engine(struct ata_port *ap);
int ahci_check_ready(struct ata_link *link);
int ahci_kick_engine(struct ata_port *ap);
int ahci_port_resume(struct ata_port *ap);
void ahci_set_em_messages(struct ahci_host_priv *hpriv,
			  struct ata_port_info *pi);
int ahci_reset_em(struct ata_host *host);
void ahci_print_info(struct ata_host *host, const char *scc_s);
int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
void ahci_error_handler(struct ata_port *ap);
u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);

static inline void __iomem *__ahci_port_base(struct ata_host *host,
					     unsigned int port_no)
{
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;

	return mmio + 0x100 + (port_no * 0x80);
}

static inline void __iomem *ahci_port_base(struct ata_port *ap)
{
	return __ahci_port_base(ap->host, ap->port_no);
}

static inline int ahci_nr_ports(u32 cap)
{
	return (cap & 0x1f) + 1;
}

#endif /* _AHCI_H */
Commit	Line	Data
c82ee6d3	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
365cfa1e AV	2	/*
	3	* ahci.h - Common AHCI SATA definitions and declarations
	4	*
8c3d3d4b	5	* Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e AV	6	* Please ALWAYS copy linux-ide@vger.kernel.org
	7	* on emails.
	8	*
	9	* Copyright 2004-2005 Red Hat, Inc.
	10	*
365cfa1e	11	* libata documentation is available via 'make {ps\|pdf}docs',
9bb9a39c	12	* as Documentation/driver-api/libata.rst
365cfa1e AV	13	*
	14	* AHCI hardware documentation:
	15	* http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
	16	* http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
365cfa1e AV	17	*/
	18
	19	#ifndef _AHCI_H
	20	#define _AHCI_H
	21
f893180b	22	#include <linux/pci.h>
f1e70c2c	23	#include <linux/clk.h>
365cfa1e	24	#include <linux/libata.h>
21b5faee	25	#include <linux/phy/phy.h>
4b3e603a	26	#include <linux/regulator/consumer.h>
365cfa1e AV	27
	28	/* Enclosure Management Control */
	29	#define EM_CTRL_MSG_TYPE 0x000f0000
	30
	31	/* Enclosure Management LED Message Type */
	32	#define EM_MSG_LED_HBA_PORT 0x0000000f
	33	#define EM_MSG_LED_PMP_SLOT 0x0000ff00
	34	#define EM_MSG_LED_VALUE 0xffff0000
	35	#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
	36	#define EM_MSG_LED_VALUE_OFF 0xfff80000
	37	#define EM_MSG_LED_VALUE_ON 0x00010000
	38
	39	enum {
	40	AHCI_MAX_PORTS = 32,
ee309f38	41	AHCI_MAX_CLKS = 5,
365cfa1e AV	42	AHCI_MAX_SG = 168, /* hardware max is 64K */
	43	AHCI_DMA_BOUNDARY = 0xffffffff,
	44	AHCI_MAX_CMDS = 32,
	45	AHCI_CMD_SZ = 32,
	46	AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
	47	AHCI_RX_FIS_SZ = 256,
	48	AHCI_CMD_TBL_CDB = 0x40,
	49	AHCI_CMD_TBL_HDR_SZ = 0x80,
	50	AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
	51	AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
	52	AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
	53	AHCI_RX_FIS_SZ,
	54	AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
	55	AHCI_CMD_TBL_AR_SZ +
	56	(AHCI_RX_FIS_SZ * 16),
	57	AHCI_IRQ_ON_SG = (1 << 31),
	58	AHCI_CMD_ATAPI = (1 << 5),
	59	AHCI_CMD_WRITE = (1 << 6),
	60	AHCI_CMD_PREFETCH = (1 << 7),
	61	AHCI_CMD_RESET = (1 << 8),
	62	AHCI_CMD_CLR_BUSY = (1 << 10),
	63
6ad60195	64	RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */
365cfa1e AV	65	RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
	66	RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
	67	RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
	68
	69	/* global controller registers */
	70	HOST_CAP = 0x00, /* host capabilities */
	71	HOST_CTL = 0x04, /* global host control */
	72	HOST_IRQ_STAT = 0x08, /* interrupt status */
	73	HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
	74	HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
	75	HOST_EM_LOC = 0x1c, /* Enclosure Management location */
	76	HOST_EM_CTL = 0x20, /* Enclosure Management Control */
	77	HOST_CAP2 = 0x24, /* host capabilities, extended */
	78
	79	/* HOST_CTL bits */
	80	HOST_RESET = (1 << 0), /* reset controller; self-clear */
	81	HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
ab0f9e78	82	HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */
365cfa1e AV	83	HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
	84
	85	/* HOST_CAP bits */
	86	HOST_CAP_SXS = (1 << 5), /* Supports External SATA */
	87	HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
	88	HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */
	89	HOST_CAP_PART = (1 << 13), /* Partial state capable */
	90	HOST_CAP_SSC = (1 << 14), /* Slumber state capable */
	91	HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */
	92	HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */
	93	HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
	94	HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */
	95	HOST_CAP_CLO = (1 << 24), /* Command List Override support */
	96	HOST_CAP_LED = (1 << 25), /* Supports activity LED */
	97	HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
	98	HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
	99	HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */
	100	HOST_CAP_SNTF = (1 << 29), /* SNotification register */
	101	HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
	102	HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
	103
	104	/* HOST_CAP2 bits */
	105	HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */
	106	HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */
	107	HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */
65fe1f0f SH	108	HOST_CAP2_SDS = (1 << 3), /* Support device sleep */
	109	HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */
	110	HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */
365cfa1e AV	111
	112	/* registers for each SATA port */
	113	PORT_LST_ADDR = 0x00, /* command list DMA addr */
	114	PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
	115	PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
	116	PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
	117	PORT_IRQ_STAT = 0x10, /* interrupt status */
	118	PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
	119	PORT_CMD = 0x18, /* port command */
	120	PORT_TFDATA = 0x20, /* taskfile data */
	121	PORT_SIG = 0x24, /* device TF signature */
	122	PORT_CMD_ISSUE = 0x38, /* command issue */
	123	PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
	124	PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
	125	PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
	126	PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
	127	PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
	128	PORT_FBS = 0x40, /* FIS-based Switching */
65fe1f0f	129	PORT_DEVSLP = 0x44, /* device sleep */
365cfa1e AV	130
	131	/* PORT_IRQ_{STAT,MASK} bits */
	132	PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
	133	PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
	134	PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
	135	PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
	136	PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
	137	PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
	138	PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
	139	PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
	140
	141	PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
	142	PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
	143	PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
	144	PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
	145	PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
	146	PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
	147	PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
	148	PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
	149	PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
	150
	151	PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR \|
	152	PORT_IRQ_IF_ERR \|
	153	PORT_IRQ_CONNECT \|
	154	PORT_IRQ_PHYRDY \|
	155	PORT_IRQ_UNK_FIS \|
	156	PORT_IRQ_BAD_PMP,
	157	PORT_IRQ_ERROR = PORT_IRQ_FREEZE \|
	158	PORT_IRQ_TF_ERR \|
	159	PORT_IRQ_HBUS_DATA_ERR,
	160	DEF_PORT_IRQ = PORT_IRQ_ERROR \| PORT_IRQ_SG_DONE \|
	161	PORT_IRQ_SDB_FIS \| PORT_IRQ_DMAS_FIS \|
	162	PORT_IRQ_PIOS_FIS \| PORT_IRQ_D2H_REG_FIS,
	163
	164	/* PORT_CMD bits */
	165	PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
	166	PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
	167	PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
	168	PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
8a3e33cf ML	169	PORT_CMD_ESP = (1 << 21), /* External Sata Port */
8a3e33cf ML	170	PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */
365cfa1e AV	171	PORT_CMD_PMP = (1 << 17), /* PMP attached */
	172	PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
	173	PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
	174	PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
	175	PORT_CMD_CLO = (1 << 3), /* Command list override */
	176	PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
	177	PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
	178	PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
	179
	180	PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
	181	PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
	182	PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
	183	PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
	184
65fe1f0f	185	/* PORT_FBS bits */
365cfa1e AV	186	PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
	187	PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
	188	PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */
	189	PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */
	190	PORT_FBS_SDE = (1 << 2), /* FBS single device error */
	191	PORT_FBS_DEC = (1 << 1), /* FBS device error clear */
	192	PORT_FBS_EN = (1 << 0), /* Enable FBS */
	193
65fe1f0f SH	194	/* PORT_DEVSLP bits */
	195	PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */
	196	PORT_DEVSLP_DM_MASK = (0xf << 25), /* DITO multiplier mask */
	197	PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */
	198	PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */
	199	PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */
	200	PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */
	201	PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */
	202
365cfa1e	203	/* hpriv->flags bits */
55d5ec31 BN	204
	205	#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
	206
365cfa1e AV	207	AHCI_HFLAG_NO_NCQ = (1 << 0),
	208	AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
	209	AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
	210	AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
	211	AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
	212	AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
	213	AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
365cfa1e AV	214	AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
	215	AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
	216	AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
	217	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
	218	link offline */
	219	AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */
83f2b963	220	AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */
5f173107	221	AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */
66583c9f BN	222	AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on
	223	port start (wait until
	224	error-handling stage) */
0cf4a7d6	225	AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */
6ea4fa70	226	AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */
d867b95f	227
f893180b	228	#ifdef CONFIG_PCI_MSI
0b9e2988	229	AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */
f893180b DW	230	#else
	231	/* compile out MSI infrastructure */
	232	AHCI_HFLAG_MULTI_MSI = 0,
f893180b	233	#endif
fb329633	234	AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */
ef0da1bf	235	AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */
7fab72f8 DB	236	AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read
7fab72f8 DB	237	only registers */
ebb82e3c HG	238	AHCI_HFLAG_IS_MOBILE = (1 << 25), /* mobile chipset, use
	239	SATA_MOBILE_LPM_POLICY
	240	as default lpm_policy */
49e54187 MR	241	AHCI_HFLAG_SUSPEND_PHYS = (1 << 26), /* handle PHYs during
49e54187 MR	242	suspend/resume */
365cfa1e AV	243
	244	/* ap->flags bits */
	245
9cbe056f	246	AHCI_FLAG_COMMON = ATA_FLAG_SATA \| ATA_FLAG_PIO_DMA \|
1a0f6b7e	247	ATA_FLAG_ACPI_SATA \| ATA_FLAG_AN,
365cfa1e AV	248
365cfa1e AV	249	ICH_MAP = 0x90, /* ICH MAP register */
c312ef17 DW	250	PCS_6 = 0x92, /* 6 port PCS */
c312ef17 DW	251	PCS_7 = 0x94, /* 7+ port PCS (Denverton) */
365cfa1e AV	252
	253	/* em constants */
	254	EM_MAX_SLOTS = 8,
	255	EM_MAX_RETRY = 5,
	256
	257	/* em_ctl bits */
c0623166 HZ	258	EM_CTL_RST = (1 << 9), /* Reset */
c0623166 HZ	259	EM_CTL_TM = (1 << 8), /* Transmit Message */
25985edc	260	EM_CTL_MR = (1 << 0), /* Message Received */
c0623166 HZ	261	EM_CTL_ALHD = (1 << 26), /* Activity LED */
	262	EM_CTL_XMT = (1 << 25), /* Transmit Only */
	263	EM_CTL_SMB = (1 << 24), /* Single Message Buffer */
6e5fe5b1 HR	264	EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */
	265	EM_CTL_SES = (1 << 18), /* SES-2 messages supported */
	266	EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */
	267	EM_CTL_LED = (1 << 16), /* LED messages supported */
008dbd61 HZ	268
	269	/* em message type */
	270	EM_MSG_TYPE_LED = (1 << 0), /* LED */
	271	EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */
	272	EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */
	273	EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */
365cfa1e AV	274	};
	275
	276	struct ahci_cmd_hdr {
	277	__le32 opts;
	278	__le32 status;
	279	__le32 tbl_addr;
	280	__le32 tbl_addr_hi;
	281	__le32 reserved[4];
	282	};
	283
	284	struct ahci_sg {
	285	__le32 addr;
	286	__le32 addr_hi;
	287	__le32 reserved;
	288	__le32 flags_size;
	289	};
	290
	291	struct ahci_em_priv {
	292	enum sw_activity blink_policy;
	293	struct timer_list timer;
	294	unsigned long saved_activity;
	295	unsigned long activity;
	296	unsigned long led_state;
1843594c	297	struct ata_link *link;
365cfa1e AV	298	};
	299
	300	struct ahci_port_priv {
	301	struct ata_link *active_link;
	302	struct ahci_cmd_hdr *cmd_slot;
	303	dma_addr_t cmd_slot_dma;
	304	void *cmd_tbl;
	305	dma_addr_t cmd_tbl_dma;
	306	void *rx_fis;
	307	dma_addr_t rx_fis_dma;
	308	/* for NCQ spurious interrupt analysis */
	309	unsigned int ncq_saw_d2h:1;
	310	unsigned int ncq_saw_dmas:1;
	311	unsigned int ncq_saw_sdb:1;
5ca72c4f	312	spinlock_t lock; /* protects parent ata_port */
365cfa1e AV	313	u32 intr_mask; /* interrupts to enable */
	314	bool fbs_supported; /* set iff FBS is supported */
	315	bool fbs_enabled; /* set iff FBS is enabled */
	316	int fbs_last_dev; /* save FBS.DEV of last FIS */
	317	/* enclosure management info per PM slot */
	318	struct ahci_em_priv em_priv[EM_MAX_SLOTS];
b29900e6	319	char irq_desc; / desc in /proc/interrupts */
365cfa1e AV	320	};
	321
	322	struct ahci_host_priv {
725c7b57	323	/* Input fields */
365cfa1e	324	unsigned int flags; /* AHCI_HFLAG_* */
725c7b57 AT	325	u32 force_port_map; /* force port map */
	326	u32 mask_port_map; /* mask out particular bits */
	327
	328	void __iomem * mmio; /* bus-independent mem map */
365cfa1e AV	329	u32 cap; /* cap to use */
365cfa1e AV	330	u32 cap2; /* cap2 to use */
8ea909cb	331	u32 version; /* cached version */
365cfa1e AV	332	u32 port_map; /* port map to use */
	333	u32 saved_cap; /* saved initial cap */
	334	u32 saved_cap2; /* saved initial cap2 */
	335	u32 saved_port_map; /* saved initial port_map */
	336	u32 em_loc; /* enclosure management location */
c0623166	337	u32 em_buf_sz; /* EM buffer size in byte */
008dbd61	338	u32 em_msg_type; /* EM message type */
894fba7f	339	u32 remapped_nvme; /* NVMe remapped device count */
e708e46e	340	bool got_runtime_pm; /* Did we do pm_runtime_get? */
156c5887	341	struct clk clks[AHCI_MAX_CLKS]; / Optional */
9d2ab995	342	struct reset_control rsts; / Optional */
c7d7ddee	343	struct regulator *target_pwrs; / Optional */
a37da918	344	struct regulator ahci_regulator;/ Optional */
f20fb266	345	struct regulator phy_regulator;/ Optional */
b1a9edbd AT	346	/*
	347	* If platform uses PHYs. There is a 1:1 relation between the port number and
	348	* the PHY position in this array.
	349	*/
	350	struct phy **phys;
	351	unsigned nports; /* Number of ports */
d50b110f	352	void plat_data; / Other platform data */
21bfd1aa	353	unsigned int irq; /* interrupt line */
039ece38 HG	354	/*
	355	* Optional ahci_start_engine override, if not set this gets set to the
	356	* default ahci_start_engine during ahci_save_initial_config, this can
	357	* be overridden anytime before the host is activated.
	358	*/
	359	void (start_engine)(struct ata_port ap);
fa89f53b EW	360	/*
	361	* Optional ahci_stop_engine override, if not set this gets set to the
	362	* default ahci_stop_engine during ahci_save_initial_config, this can
	363	* be overridden anytime before the host is activated.
	364	*/
	365	int (stop_engine)(struct ata_port ap);
	366
f070d671	367	irqreturn_t (irq_handler)(int irq, void dev_instance);
365cfa1e	368
0b9e2988 CH	369	/* only required for per-port MSI(-X) support */
	370	int (get_irq_vector)(struct ata_host host,
	371	int port);
	372	};
f893180b	373
365cfa1e AV	374	extern int ahci_ignore_sss;
365cfa1e AV	375
fad16e7a TH	376	extern struct device_attribute *ahci_shost_attrs[];
	377	extern struct device_attribute *ahci_sdev_attrs[];
	378
018d5ef2 AM	379	/*
	380	* This must be instantiated by the edge drivers. Read the comments
	381	* for ATA_BASE_SHT
	382	*/
fad16e7a TH	383	#define AHCI_SHT(drv_name) \
fad16e7a TH	384	ATA_NCQ_SHT(drv_name), \
e2d1f8a0	385	.can_queue = AHCI_MAX_CMDS, \
fad16e7a TH	386	.sg_tablesize = AHCI_MAX_SG, \
	387	.dma_boundary = AHCI_DMA_BOUNDARY, \
	388	.shost_attrs = ahci_shost_attrs, \
	389	.sdev_attrs = ahci_sdev_attrs
	390
365cfa1e	391	extern struct ata_port_operations ahci_ops;
8b789d89	392	extern struct ata_port_operations ahci_platform_ops;
345347c5	393	extern struct ata_port_operations ahci_pmp_retry_srst_ops;
365cfa1e	394
bbb4ab43	395	unsigned int ahci_dev_classify(struct ata_port *ap);
02cdfcf0 DM	396	void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
02cdfcf0 DM	397	u32 opts);
365cfa1e	398	void ahci_save_initial_config(struct device *dev,
725c7b57	399	struct ahci_host_priv *hpriv);
365cfa1e AV	400	void ahci_init_controller(struct ata_host *host);
	401	int ahci_reset_controller(struct ata_host *host);
	402
	403	int ahci_do_softreset(struct ata_link link, unsigned int class,
	404	int pmp, unsigned long deadline,
	405	int (check_ready)(struct ata_link link));
	406
d436501e BG	407	int ahci_do_hardreset(struct ata_link link, unsigned int class,
	408	unsigned long deadline, bool *online);
	409
39e0ee99	410	unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
365cfa1e	411	int ahci_stop_engine(struct ata_port *ap);
39e0ee99	412	void ahci_start_fis_rx(struct ata_port *ap);
365cfa1e AV	413	void ahci_start_engine(struct ata_port *ap);
	414	int ahci_check_ready(struct ata_link *link);
	415	int ahci_kick_engine(struct ata_port *ap);
02cdfcf0	416	int ahci_port_resume(struct ata_port *ap);
365cfa1e AV	417	void ahci_set_em_messages(struct ahci_host_priv *hpriv,
	418	struct ata_port_info *pi);
	419	int ahci_reset_em(struct ata_host *host);
365cfa1e	420	void ahci_print_info(struct ata_host host, const char scc_s);
21bfd1aa	421	int ahci_host_activate(struct ata_host host, struct scsi_host_template sht);
8b789d89	422	void ahci_error_handler(struct ata_port *ap);
f070d671	423	u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
365cfa1e AV	424
	425	static inline void __iomem __ahci_port_base(struct ata_host host,
	426	unsigned int port_no)
	427	{
	428	struct ahci_host_priv *hpriv = host->private_data;
	429	void __iomem *mmio = hpriv->mmio;
	430
	431	return mmio + 0x100 + (port_no * 0x80);
	432	}
	433
	434	static inline void __iomem ahci_port_base(struct ata_port ap)
	435	{
	436	return __ahci_port_base(ap->host, ap->port_no);
	437	}
	438
	439	static inline int ahci_nr_ports(u32 cap)
	440	{
	441	return (cap & 0x1f) + 1;
	442	}
	443
	444	#endif /* _AHCI_H */