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766a2d97 BN |
1 | /* |
2 | * Broadcom SATA3 AHCI Controller Driver | |
3 | * | |
4 | * Copyright © 2009-2015 Broadcom Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2, or (at your option) | |
9 | * any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/ahci_platform.h> | |
18 | #include <linux/compiler.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/libata.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/string.h> | |
29 | ||
30 | #include "ahci.h" | |
31 | ||
32 | #define DRV_NAME "brcm-ahci" | |
33 | ||
34 | #define SATA_TOP_CTRL_VERSION 0x0 | |
35 | #define SATA_TOP_CTRL_BUS_CTRL 0x4 | |
36 | #define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */ | |
37 | #define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */ | |
38 | #define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */ | |
39 | #define PIODATA_ENDIAN_SHIFT 6 | |
40 | #define ENDIAN_SWAP_NONE 0 | |
41 | #define ENDIAN_SWAP_FULL 2 | |
42 | #define OVERRIDE_HWINIT BIT(16) | |
43 | #define SATA_TOP_CTRL_TP_CTRL 0x8 | |
44 | #define SATA_TOP_CTRL_PHY_CTRL 0xc | |
45 | #define SATA_TOP_CTRL_PHY_CTRL_1 0x0 | |
46 | #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14) | |
47 | #define SATA_TOP_CTRL_PHY_CTRL_2 0x4 | |
48 | #define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0) | |
49 | #define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1) | |
50 | #define SATA_TOP_CTRL_2_SW_RST_RX BIT(2) | |
51 | #define SATA_TOP_CTRL_2_SW_RST_TX BIT(3) | |
52 | #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14) | |
53 | #define SATA_TOP_CTRL_PHY_OFFS 0x8 | |
54 | #define SATA_TOP_MAX_PHYS 2 | |
55 | #define SATA_TOP_CTRL_SATA_TP_OUT 0x1c | |
56 | #define SATA_TOP_CTRL_CLIENT_INIT_CTRL 0x20 | |
57 | ||
58 | /* On big-endian MIPS, buses are reversed to big endian, so switch them back */ | |
59 | #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) | |
60 | #define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */ | |
61 | #define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */ | |
62 | #else | |
63 | #define DATA_ENDIAN 0 | |
64 | #define MMIO_ENDIAN 0 | |
65 | #endif | |
66 | ||
67 | #define BUS_CTRL_ENDIAN_CONF \ | |
68 | ((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) | \ | |
69 | (DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) | \ | |
70 | (MMIO_ENDIAN << MMIO_ENDIAN_SHIFT)) | |
71 | ||
7de32445 JS |
72 | enum brcm_ahci_quirks { |
73 | BRCM_AHCI_QUIRK_NO_NCQ = BIT(0), | |
74 | }; | |
75 | ||
766a2d97 BN |
76 | struct brcm_ahci_priv { |
77 | struct device *dev; | |
78 | void __iomem *top_ctrl; | |
79 | u32 port_mask; | |
7de32445 | 80 | u32 quirks; |
766a2d97 BN |
81 | }; |
82 | ||
83 | static const struct ata_port_info ahci_brcm_port_info = { | |
84 | .flags = AHCI_FLAG_COMMON, | |
85 | .pio_mask = ATA_PIO4, | |
86 | .udma_mask = ATA_UDMA6, | |
87 | .port_ops = &ahci_platform_ops, | |
88 | }; | |
89 | ||
90 | static inline u32 brcm_sata_readreg(void __iomem *addr) | |
91 | { | |
92 | /* | |
93 | * MIPS endianness is configured by boot strap, which also reverses all | |
94 | * bus endianness (i.e., big-endian CPU + big endian bus ==> native | |
95 | * endian I/O). | |
96 | * | |
97 | * Other architectures (e.g., ARM) either do not support big endian, or | |
98 | * else leave I/O in little endian mode. | |
99 | */ | |
f9114d35 | 100 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
766a2d97 BN |
101 | return __raw_readl(addr); |
102 | else | |
103 | return readl_relaxed(addr); | |
104 | } | |
105 | ||
106 | static inline void brcm_sata_writereg(u32 val, void __iomem *addr) | |
107 | { | |
108 | /* See brcm_sata_readreg() comments */ | |
f9114d35 | 109 | if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
766a2d97 BN |
110 | __raw_writel(val, addr); |
111 | else | |
112 | writel_relaxed(val, addr); | |
113 | } | |
114 | ||
115 | static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port) | |
116 | { | |
117 | void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + | |
118 | (port * SATA_TOP_CTRL_PHY_OFFS); | |
119 | void __iomem *p; | |
120 | u32 reg; | |
121 | ||
122 | /* clear PHY_DEFAULT_POWER_STATE */ | |
123 | p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; | |
124 | reg = brcm_sata_readreg(p); | |
125 | reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; | |
126 | brcm_sata_writereg(reg, p); | |
127 | ||
128 | /* reset the PHY digital logic */ | |
129 | p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; | |
130 | reg = brcm_sata_readreg(p); | |
131 | reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | | |
132 | SATA_TOP_CTRL_2_SW_RST_RX); | |
133 | reg |= SATA_TOP_CTRL_2_SW_RST_TX; | |
134 | brcm_sata_writereg(reg, p); | |
135 | reg = brcm_sata_readreg(p); | |
136 | reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; | |
137 | brcm_sata_writereg(reg, p); | |
138 | reg = brcm_sata_readreg(p); | |
139 | reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET; | |
140 | brcm_sata_writereg(reg, p); | |
141 | (void)brcm_sata_readreg(p); | |
142 | } | |
143 | ||
144 | static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port) | |
145 | { | |
146 | void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL + | |
147 | (port * SATA_TOP_CTRL_PHY_OFFS); | |
148 | void __iomem *p; | |
149 | u32 reg; | |
150 | ||
151 | /* power-off the PHY digital logic */ | |
152 | p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2; | |
153 | reg = brcm_sata_readreg(p); | |
154 | reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB | | |
155 | SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX | | |
156 | SATA_TOP_CTRL_2_PHY_GLOBAL_RESET); | |
157 | brcm_sata_writereg(reg, p); | |
158 | ||
159 | /* set PHY_DEFAULT_POWER_STATE */ | |
160 | p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1; | |
161 | reg = brcm_sata_readreg(p); | |
162 | reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE; | |
163 | brcm_sata_writereg(reg, p); | |
164 | } | |
165 | ||
166 | static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv) | |
167 | { | |
168 | int i; | |
169 | ||
170 | for (i = 0; i < SATA_TOP_MAX_PHYS; i++) | |
171 | if (priv->port_mask & BIT(i)) | |
172 | brcm_sata_phy_enable(priv, i); | |
173 | } | |
174 | ||
175 | static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv) | |
176 | { | |
177 | int i; | |
178 | ||
179 | for (i = 0; i < SATA_TOP_MAX_PHYS; i++) | |
180 | if (priv->port_mask & BIT(i)) | |
181 | brcm_sata_phy_disable(priv, i); | |
182 | } | |
183 | ||
184 | static u32 brcm_ahci_get_portmask(struct platform_device *pdev, | |
185 | struct brcm_ahci_priv *priv) | |
186 | { | |
187 | void __iomem *ahci; | |
188 | struct resource *res; | |
189 | u32 impl; | |
190 | ||
191 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci"); | |
192 | ahci = devm_ioremap_resource(&pdev->dev, res); | |
193 | if (IS_ERR(ahci)) | |
194 | return 0; | |
195 | ||
196 | impl = readl(ahci + HOST_PORTS_IMPL); | |
197 | ||
198 | if (fls(impl) > SATA_TOP_MAX_PHYS) | |
199 | dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n", | |
200 | impl); | |
201 | else if (!impl) | |
202 | dev_info(priv->dev, "no ports found\n"); | |
203 | ||
204 | devm_iounmap(&pdev->dev, ahci); | |
205 | devm_release_mem_region(&pdev->dev, res->start, resource_size(res)); | |
206 | ||
207 | return impl; | |
208 | } | |
209 | ||
210 | static void brcm_sata_init(struct brcm_ahci_priv *priv) | |
211 | { | |
212 | /* Configure endianness */ | |
213 | brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF, | |
214 | priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL); | |
215 | } | |
216 | ||
8b34fe59 | 217 | #ifdef CONFIG_PM_SLEEP |
766a2d97 BN |
218 | static int brcm_ahci_suspend(struct device *dev) |
219 | { | |
220 | struct ata_host *host = dev_get_drvdata(dev); | |
221 | struct ahci_host_priv *hpriv = host->private_data; | |
222 | struct brcm_ahci_priv *priv = hpriv->plat_data; | |
223 | int ret; | |
224 | ||
225 | ret = ahci_platform_suspend(dev); | |
226 | brcm_sata_phys_disable(priv); | |
227 | return ret; | |
228 | } | |
229 | ||
230 | static int brcm_ahci_resume(struct device *dev) | |
231 | { | |
232 | struct ata_host *host = dev_get_drvdata(dev); | |
233 | struct ahci_host_priv *hpriv = host->private_data; | |
234 | struct brcm_ahci_priv *priv = hpriv->plat_data; | |
235 | ||
236 | brcm_sata_init(priv); | |
237 | brcm_sata_phys_enable(priv); | |
238 | return ahci_platform_resume(dev); | |
239 | } | |
8b34fe59 | 240 | #endif |
766a2d97 BN |
241 | |
242 | static struct scsi_host_template ahci_platform_sht = { | |
243 | AHCI_SHT(DRV_NAME), | |
244 | }; | |
245 | ||
246 | static int brcm_ahci_probe(struct platform_device *pdev) | |
247 | { | |
248 | struct device *dev = &pdev->dev; | |
249 | struct brcm_ahci_priv *priv; | |
250 | struct ahci_host_priv *hpriv; | |
251 | struct resource *res; | |
252 | int ret; | |
253 | ||
254 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
255 | if (!priv) | |
256 | return -ENOMEM; | |
257 | priv->dev = dev; | |
258 | ||
259 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl"); | |
260 | priv->top_ctrl = devm_ioremap_resource(dev, res); | |
261 | if (IS_ERR(priv->top_ctrl)) | |
262 | return PTR_ERR(priv->top_ctrl); | |
263 | ||
7de32445 JS |
264 | if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) |
265 | priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ; | |
266 | ||
766a2d97 BN |
267 | brcm_sata_init(priv); |
268 | ||
269 | priv->port_mask = brcm_ahci_get_portmask(pdev, priv); | |
270 | if (!priv->port_mask) | |
271 | return -ENODEV; | |
272 | ||
273 | brcm_sata_phys_enable(priv); | |
274 | ||
275 | hpriv = ahci_platform_get_resources(pdev); | |
276 | if (IS_ERR(hpriv)) | |
277 | return PTR_ERR(hpriv); | |
278 | hpriv->plat_data = priv; | |
279 | ||
280 | ret = ahci_platform_enable_resources(hpriv); | |
281 | if (ret) | |
282 | return ret; | |
283 | ||
7de32445 JS |
284 | if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ) |
285 | hpriv->flags |= AHCI_HFLAG_NO_NCQ; | |
286 | ||
766a2d97 BN |
287 | ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info, |
288 | &ahci_platform_sht); | |
289 | if (ret) | |
290 | return ret; | |
291 | ||
292 | dev_info(dev, "Broadcom AHCI SATA3 registered\n"); | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
297 | static int brcm_ahci_remove(struct platform_device *pdev) | |
298 | { | |
299 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
300 | struct ahci_host_priv *hpriv = host->private_data; | |
301 | struct brcm_ahci_priv *priv = hpriv->plat_data; | |
302 | int ret; | |
303 | ||
304 | ret = ata_platform_remove_one(pdev); | |
305 | if (ret) | |
306 | return ret; | |
307 | ||
308 | brcm_sata_phys_disable(priv); | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | static const struct of_device_id ahci_of_match[] = { | |
314 | {.compatible = "brcm,bcm7445-ahci"}, | |
315 | {}, | |
316 | }; | |
317 | MODULE_DEVICE_TABLE(of, ahci_of_match); | |
318 | ||
319 | static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume); | |
320 | ||
321 | static struct platform_driver brcm_ahci_driver = { | |
322 | .probe = brcm_ahci_probe, | |
323 | .remove = brcm_ahci_remove, | |
324 | .driver = { | |
325 | .name = DRV_NAME, | |
326 | .of_match_table = ahci_of_match, | |
327 | .pm = &ahci_brcm_pm_ops, | |
328 | }, | |
329 | }; | |
330 | module_platform_driver(brcm_ahci_driver); | |
331 | ||
332 | MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver"); | |
333 | MODULE_AUTHOR("Brian Norris"); | |
334 | MODULE_LICENSE("GPL"); | |
335 | MODULE_ALIAS("platform:sata-brcmstb"); |