[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci_brcmstb.c

/*
 * Broadcom SATA3 AHCI Controller Driver
 *
 * Copyright © 2009-2015 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/ahci_platform.h>
#include <linux/compiler.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/libata.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/string.h>

#include "ahci.h"

#define DRV_NAME					"brcm-ahci"

#define SATA_TOP_CTRL_VERSION				0x0
#define SATA_TOP_CTRL_BUS_CTRL				0x4
 #define MMIO_ENDIAN_SHIFT				0 /* CPU->AHCI */
 #define DMADESC_ENDIAN_SHIFT				2 /* AHCI->DDR */
 #define DMADATA_ENDIAN_SHIFT				4 /* AHCI->DDR */
 #define PIODATA_ENDIAN_SHIFT				6
  #define ENDIAN_SWAP_NONE				0
  #define ENDIAN_SWAP_FULL				2
 #define OVERRIDE_HWINIT				BIT(16)
#define SATA_TOP_CTRL_TP_CTRL				0x8
#define SATA_TOP_CTRL_PHY_CTRL				0xc
 #define SATA_TOP_CTRL_PHY_CTRL_1			0x0
  #define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE	BIT(14)
 #define SATA_TOP_CTRL_PHY_CTRL_2			0x4
  #define SATA_TOP_CTRL_2_SW_RST_MDIOREG		BIT(0)
  #define SATA_TOP_CTRL_2_SW_RST_OOB			BIT(1)
  #define SATA_TOP_CTRL_2_SW_RST_RX			BIT(2)
  #define SATA_TOP_CTRL_2_SW_RST_TX			BIT(3)
  #define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET		BIT(14)
 #define SATA_TOP_CTRL_PHY_OFFS				0x8
 #define SATA_TOP_MAX_PHYS				2

/* On big-endian MIPS, buses are reversed to big endian, so switch them back */
#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
#define DATA_ENDIAN			 2 /* AHCI->DDR inbound accesses */
#define MMIO_ENDIAN			 2 /* CPU->AHCI outbound accesses */
#else
#define DATA_ENDIAN			 0
#define MMIO_ENDIAN			 0
#endif

#define BUS_CTRL_ENDIAN_CONF				\
	((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) |	\
	(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) |		\
	(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))

enum brcm_ahci_quirks {
	BRCM_AHCI_QUIRK_NO_NCQ		= BIT(0),
	BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE	= BIT(1),
};

struct brcm_ahci_priv {
	struct device *dev;
	void __iomem *top_ctrl;
	u32 port_mask;
	u32 quirks;
};

static const struct ata_port_info ahci_brcm_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_platform_ops,
};

static inline u32 brcm_sata_readreg(void __iomem *addr)
{
	/*
	 * MIPS endianness is configured by boot strap, which also reverses all
	 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
	 * endian I/O).
	 *
	 * Other architectures (e.g., ARM) either do not support big endian, or
	 * else leave I/O in little endian mode.
	 */
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		return __raw_readl(addr);
	else
		return readl_relaxed(addr);
}

static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
{
	/* See brcm_sata_readreg() comments */
	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
		__raw_writel(val, addr);
	else
		writel_relaxed(val, addr);
}

static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
{
	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
				(port * SATA_TOP_CTRL_PHY_OFFS);
	void __iomem *p;
	u32 reg;

	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
		return;

	/* clear PHY_DEFAULT_POWER_STATE */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	reg = brcm_sata_readreg(p);
	reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	brcm_sata_writereg(reg, p);

	/* reset the PHY digital logic */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	reg = brcm_sata_readreg(p);
	reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
		 SATA_TOP_CTRL_2_SW_RST_RX);
	reg |= SATA_TOP_CTRL_2_SW_RST_TX;
	brcm_sata_writereg(reg, p);
	reg = brcm_sata_readreg(p);
	reg |= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	brcm_sata_writereg(reg, p);
	reg = brcm_sata_readreg(p);
	reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	brcm_sata_writereg(reg, p);
	(void)brcm_sata_readreg(p);
}

static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
{
	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
				(port * SATA_TOP_CTRL_PHY_OFFS);
	void __iomem *p;
	u32 reg;

	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
		return;

	/* power-off the PHY digital logic */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	reg = brcm_sata_readreg(p);
	reg |= (SATA_TOP_CTRL_2_SW_RST_MDIOREG | SATA_TOP_CTRL_2_SW_RST_OOB |
		SATA_TOP_CTRL_2_SW_RST_RX | SATA_TOP_CTRL_2_SW_RST_TX |
		SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
	brcm_sata_writereg(reg, p);

	/* set PHY_DEFAULT_POWER_STATE */
	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	reg = brcm_sata_readreg(p);
	reg |= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	brcm_sata_writereg(reg, p);
}

static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
{
	int i;

	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
		if (priv->port_mask & BIT(i))
			brcm_sata_phy_enable(priv, i);
}

static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
{
	int i;

	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
		if (priv->port_mask & BIT(i))
			brcm_sata_phy_disable(priv, i);
}

static u32 brcm_ahci_get_portmask(struct platform_device *pdev,
				  struct brcm_ahci_priv *priv)
{
	void __iomem *ahci;
	struct resource *res;
	u32 impl;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
	ahci = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(ahci))
		return 0;

	impl = readl(ahci + HOST_PORTS_IMPL);

	if (fls(impl) > SATA_TOP_MAX_PHYS)
		dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
			 impl);
	else if (!impl)
		dev_info(priv->dev, "no ports found\n");

	devm_iounmap(&pdev->dev, ahci);
	devm_release_mem_region(&pdev->dev, res->start, resource_size(res));

	return impl;
}

static void brcm_sata_init(struct brcm_ahci_priv *priv)
{
	/* Configure endianness */
	brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF,
			   priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
}

#ifdef CONFIG_PM_SLEEP
static int brcm_ahci_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	int ret;

	ret = ahci_platform_suspend(dev);
	brcm_sata_phys_disable(priv);
	return ret;
}

static int brcm_ahci_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;

	brcm_sata_init(priv);
	brcm_sata_phys_enable(priv);
	return ahci_platform_resume(dev);
}
#endif

static struct scsi_host_template ahci_platform_sht = {
	AHCI_SHT(DRV_NAME),
};

static int brcm_ahci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct brcm_ahci_priv *priv;
	struct ahci_host_priv *hpriv;
	struct resource *res;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;
	priv->dev = dev;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
	priv->top_ctrl = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->top_ctrl))
		return PTR_ERR(priv->top_ctrl);

	if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) {
		priv->quirks |= BRCM_AHCI_QUIRK_NO_NCQ;
		priv->quirks |= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
	}

	brcm_sata_init(priv);

	priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
	if (!priv->port_mask)
		return -ENODEV;

	brcm_sata_phys_enable(priv);

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);
	hpriv->plat_data = priv;

	ret = ahci_platform_enable_resources(hpriv);
	if (ret)
		return ret;

	if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
		hpriv->flags |= AHCI_HFLAG_NO_NCQ;

	ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
				      &ahci_platform_sht);
	if (ret)
		return ret;

	dev_info(dev, "Broadcom AHCI SATA3 registered\n");

	return 0;
}

static int brcm_ahci_remove(struct platform_device *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct brcm_ahci_priv *priv = hpriv->plat_data;
	int ret;

	ret = ata_platform_remove_one(pdev);
	if (ret)
		return ret;

	brcm_sata_phys_disable(priv);

	return 0;
}

static const struct of_device_id ahci_of_match[] = {
	{.compatible = "brcm,bcm7425-ahci"},
	{.compatible = "brcm,bcm7445-ahci"},
	{},
};
MODULE_DEVICE_TABLE(of, ahci_of_match);

static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);

static struct platform_driver brcm_ahci_driver = {
	.probe = brcm_ahci_probe,
	.remove = brcm_ahci_remove,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_of_match,
		.pm = &ahci_brcm_pm_ops,
	},
};
module_platform_driver(brcm_ahci_driver);

MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
MODULE_AUTHOR("Brian Norris");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:sata-brcmstb");
Commit	Line	Data
766a2d97 BN	1	/*
	2	* Broadcom SATA3 AHCI Controller Driver
	3	*
	4	* Copyright © 2009-2015 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2, or (at your option)
	9	* any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/ahci_platform.h>
	18	#include <linux/compiler.h>
	19	#include <linux/device.h>
	20	#include <linux/init.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/io.h>
	23	#include <linux/kernel.h>
	24	#include <linux/libata.h>
	25	#include <linux/module.h>
	26	#include <linux/of.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/string.h>
	29
	30	#include "ahci.h"
	31
	32	#define DRV_NAME "brcm-ahci"
	33
	34	#define SATA_TOP_CTRL_VERSION 0x0
	35	#define SATA_TOP_CTRL_BUS_CTRL 0x4
	36	#define MMIO_ENDIAN_SHIFT 0 /* CPU->AHCI */
	37	#define DMADESC_ENDIAN_SHIFT 2 /* AHCI->DDR */
	38	#define DMADATA_ENDIAN_SHIFT 4 /* AHCI->DDR */
	39	#define PIODATA_ENDIAN_SHIFT 6
	40	#define ENDIAN_SWAP_NONE 0
	41	#define ENDIAN_SWAP_FULL 2
	42	#define OVERRIDE_HWINIT BIT(16)
	43	#define SATA_TOP_CTRL_TP_CTRL 0x8
	44	#define SATA_TOP_CTRL_PHY_CTRL 0xc
	45	#define SATA_TOP_CTRL_PHY_CTRL_1 0x0
	46	#define SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE BIT(14)
	47	#define SATA_TOP_CTRL_PHY_CTRL_2 0x4
	48	#define SATA_TOP_CTRL_2_SW_RST_MDIOREG BIT(0)
	49	#define SATA_TOP_CTRL_2_SW_RST_OOB BIT(1)
	50	#define SATA_TOP_CTRL_2_SW_RST_RX BIT(2)
	51	#define SATA_TOP_CTRL_2_SW_RST_TX BIT(3)
	52	#define SATA_TOP_CTRL_2_PHY_GLOBAL_RESET BIT(14)
	53	#define SATA_TOP_CTRL_PHY_OFFS 0x8
	54	#define SATA_TOP_MAX_PHYS 2
766a2d97 BN	55
	56	/* On big-endian MIPS, buses are reversed to big endian, so switch them back */
	57	#if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
	58	#define DATA_ENDIAN 2 /* AHCI->DDR inbound accesses */
	59	#define MMIO_ENDIAN 2 /* CPU->AHCI outbound accesses */
	60	#else
	61	#define DATA_ENDIAN 0
	62	#define MMIO_ENDIAN 0
	63	#endif
	64
	65	#define BUS_CTRL_ENDIAN_CONF \
	66	((DATA_ENDIAN << DMADATA_ENDIAN_SHIFT) \| \
	67	(DATA_ENDIAN << DMADESC_ENDIAN_SHIFT) \| \
	68	(MMIO_ENDIAN << MMIO_ENDIAN_SHIFT))
	69
7de32445 JS	70	enum brcm_ahci_quirks {
7de32445 JS	71	BRCM_AHCI_QUIRK_NO_NCQ = BIT(0),
b46f79bc	72	BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE = BIT(1),
7de32445 JS	73	};
7de32445 JS	74
766a2d97 BN	75	struct brcm_ahci_priv {
	76	struct device *dev;
	77	void __iomem *top_ctrl;
	78	u32 port_mask;
7de32445	79	u32 quirks;
766a2d97 BN	80	};
	81
	82	static const struct ata_port_info ahci_brcm_port_info = {
	83	.flags = AHCI_FLAG_COMMON,
	84	.pio_mask = ATA_PIO4,
	85	.udma_mask = ATA_UDMA6,
	86	.port_ops = &ahci_platform_ops,
	87	};
	88
	89	static inline u32 brcm_sata_readreg(void __iomem *addr)
	90	{
	91	/*
	92	* MIPS endianness is configured by boot strap, which also reverses all
	93	* bus endianness (i.e., big-endian CPU + big endian bus ==> native
	94	* endian I/O).
	95	*
	96	* Other architectures (e.g., ARM) either do not support big endian, or
	97	* else leave I/O in little endian mode.
	98	*/
f9114d35	99	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
766a2d97 BN	100	return __raw_readl(addr);
	101	else
	102	return readl_relaxed(addr);
	103	}
	104
	105	static inline void brcm_sata_writereg(u32 val, void __iomem *addr)
	106	{
	107	/* See brcm_sata_readreg() comments */
f9114d35	108	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
766a2d97 BN	109	__raw_writel(val, addr);
	110	else
	111	writel_relaxed(val, addr);
	112	}
	113
	114	static void brcm_sata_phy_enable(struct brcm_ahci_priv *priv, int port)
	115	{
	116	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
	117	(port * SATA_TOP_CTRL_PHY_OFFS);
	118	void __iomem *p;
	119	u32 reg;
	120
b46f79bc JS	121	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
	122	return;
	123
766a2d97 BN	124	/* clear PHY_DEFAULT_POWER_STATE */
	125	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	126	reg = brcm_sata_readreg(p);
	127	reg &= ~SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	128	brcm_sata_writereg(reg, p);
	129
	130	/* reset the PHY digital logic */
	131	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	132	reg = brcm_sata_readreg(p);
	133	reg &= ~(SATA_TOP_CTRL_2_SW_RST_MDIOREG \| SATA_TOP_CTRL_2_SW_RST_OOB \|
	134	SATA_TOP_CTRL_2_SW_RST_RX);
	135	reg \|= SATA_TOP_CTRL_2_SW_RST_TX;
	136	brcm_sata_writereg(reg, p);
	137	reg = brcm_sata_readreg(p);
	138	reg \|= SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	139	brcm_sata_writereg(reg, p);
	140	reg = brcm_sata_readreg(p);
	141	reg &= ~SATA_TOP_CTRL_2_PHY_GLOBAL_RESET;
	142	brcm_sata_writereg(reg, p);
	143	(void)brcm_sata_readreg(p);
	144	}
	145
	146	static void brcm_sata_phy_disable(struct brcm_ahci_priv *priv, int port)
	147	{
	148	void __iomem *phyctrl = priv->top_ctrl + SATA_TOP_CTRL_PHY_CTRL +
	149	(port * SATA_TOP_CTRL_PHY_OFFS);
	150	void __iomem *p;
	151	u32 reg;
	152
b46f79bc JS	153	if (priv->quirks & BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE)
	154	return;
	155
766a2d97 BN	156	/* power-off the PHY digital logic */
	157	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_2;
	158	reg = brcm_sata_readreg(p);
	159	reg \|= (SATA_TOP_CTRL_2_SW_RST_MDIOREG \| SATA_TOP_CTRL_2_SW_RST_OOB \|
	160	SATA_TOP_CTRL_2_SW_RST_RX \| SATA_TOP_CTRL_2_SW_RST_TX \|
	161	SATA_TOP_CTRL_2_PHY_GLOBAL_RESET);
	162	brcm_sata_writereg(reg, p);
	163
	164	/* set PHY_DEFAULT_POWER_STATE */
	165	p = phyctrl + SATA_TOP_CTRL_PHY_CTRL_1;
	166	reg = brcm_sata_readreg(p);
	167	reg \|= SATA_TOP_CTRL_1_PHY_DEFAULT_POWER_STATE;
	168	brcm_sata_writereg(reg, p);
	169	}
	170
	171	static void brcm_sata_phys_enable(struct brcm_ahci_priv *priv)
	172	{
	173	int i;
	174
	175	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
	176	if (priv->port_mask & BIT(i))
	177	brcm_sata_phy_enable(priv, i);
	178	}
	179
	180	static void brcm_sata_phys_disable(struct brcm_ahci_priv *priv)
	181	{
	182	int i;
	183
	184	for (i = 0; i < SATA_TOP_MAX_PHYS; i++)
	185	if (priv->port_mask & BIT(i))
	186	brcm_sata_phy_disable(priv, i);
	187	}
	188
	189	static u32 brcm_ahci_get_portmask(struct platform_device *pdev,
	190	struct brcm_ahci_priv *priv)
	191	{
	192	void __iomem *ahci;
	193	struct resource *res;
	194	u32 impl;
	195
	196	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ahci");
	197	ahci = devm_ioremap_resource(&pdev->dev, res);
	198	if (IS_ERR(ahci))
	199	return 0;
	200
	201	impl = readl(ahci + HOST_PORTS_IMPL);
	202
	203	if (fls(impl) > SATA_TOP_MAX_PHYS)
	204	dev_warn(priv->dev, "warning: more ports than PHYs (%#x)\n",
	205	impl);
	206	else if (!impl)
	207	dev_info(priv->dev, "no ports found\n");
	208
	209	devm_iounmap(&pdev->dev, ahci);
	210	devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
	211
	212	return impl;
	213	}
	214
	215	static void brcm_sata_init(struct brcm_ahci_priv *priv)
	216	{
	217	/* Configure endianness */
	218	brcm_sata_writereg(BUS_CTRL_ENDIAN_CONF,
	219	priv->top_ctrl + SATA_TOP_CTRL_BUS_CTRL);
220	}
221
8b34fe59	222	#ifdef CONFIG_PM_SLEEP
766a2d97 BN	223	static int brcm_ahci_suspend(struct device *dev)
	224	{
	225	struct ata_host *host = dev_get_drvdata(dev);
	226	struct ahci_host_priv *hpriv = host->private_data;
	227	struct brcm_ahci_priv *priv = hpriv->plat_data;
	228	int ret;
	229
	230	ret = ahci_platform_suspend(dev);
	231	brcm_sata_phys_disable(priv);
	232	return ret;
	233	}
	234
	235	static int brcm_ahci_resume(struct device *dev)
	236	{
	237	struct ata_host *host = dev_get_drvdata(dev);
	238	struct ahci_host_priv *hpriv = host->private_data;
	239	struct brcm_ahci_priv *priv = hpriv->plat_data;
	240
	241	brcm_sata_init(priv);
	242	brcm_sata_phys_enable(priv);
	243	return ahci_platform_resume(dev);
	244	}
8b34fe59	245	#endif
766a2d97 BN	246
	247	static struct scsi_host_template ahci_platform_sht = {
	248	AHCI_SHT(DRV_NAME),
	249	};
	250
	251	static int brcm_ahci_probe(struct platform_device *pdev)
	252	{
	253	struct device *dev = &pdev->dev;
	254	struct brcm_ahci_priv *priv;
	255	struct ahci_host_priv *hpriv;
	256	struct resource *res;
	257	int ret;
	258
	259	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	260	if (!priv)
	261	return -ENOMEM;
	262	priv->dev = dev;
	263
	264	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "top-ctrl");
	265	priv->top_ctrl = devm_ioremap_resource(dev, res);
	266	if (IS_ERR(priv->top_ctrl))
	267	return PTR_ERR(priv->top_ctrl);
	268
b46f79bc	269	if (of_device_is_compatible(dev->of_node, "brcm,bcm7425-ahci")) {
7de32445	270	priv->quirks \|= BRCM_AHCI_QUIRK_NO_NCQ;
b46f79bc JS	271	priv->quirks \|= BRCM_AHCI_QUIRK_SKIP_PHY_ENABLE;
b46f79bc JS	272	}
7de32445	273
766a2d97 BN	274	brcm_sata_init(priv);
	275
	276	priv->port_mask = brcm_ahci_get_portmask(pdev, priv);
	277	if (!priv->port_mask)
	278	return -ENODEV;
	279
	280	brcm_sata_phys_enable(priv);
	281
	282	hpriv = ahci_platform_get_resources(pdev);
	283	if (IS_ERR(hpriv))
	284	return PTR_ERR(hpriv);
	285	hpriv->plat_data = priv;
	286
	287	ret = ahci_platform_enable_resources(hpriv);
	288	if (ret)
	289	return ret;
	290
7de32445 JS	291	if (priv->quirks & BRCM_AHCI_QUIRK_NO_NCQ)
	292	hpriv->flags \|= AHCI_HFLAG_NO_NCQ;
	293
766a2d97 BN	294	ret = ahci_platform_init_host(pdev, hpriv, &ahci_brcm_port_info,
	295	&ahci_platform_sht);
	296	if (ret)
	297	return ret;
	298
	299	dev_info(dev, "Broadcom AHCI SATA3 registered\n");
	300
	301	return 0;
	302	}
	303
	304	static int brcm_ahci_remove(struct platform_device *pdev)
	305	{
	306	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	307	struct ahci_host_priv *hpriv = host->private_data;
	308	struct brcm_ahci_priv *priv = hpriv->plat_data;
	309	int ret;
	310
	311	ret = ata_platform_remove_one(pdev);
	312	if (ret)
	313	return ret;
	314
	315	brcm_sata_phys_disable(priv);
	316
	317	return 0;
	318	}
	319
	320	static const struct of_device_id ahci_of_match[] = {
1980eb9b	321	{.compatible = "brcm,bcm7425-ahci"},
766a2d97 BN	322	{.compatible = "brcm,bcm7445-ahci"},
	323	{},
	324	};
	325	MODULE_DEVICE_TABLE(of, ahci_of_match);
	326
	327	static SIMPLE_DEV_PM_OPS(ahci_brcm_pm_ops, brcm_ahci_suspend, brcm_ahci_resume);
	328
	329	static struct platform_driver brcm_ahci_driver = {
	330	.probe = brcm_ahci_probe,
	331	.remove = brcm_ahci_remove,
	332	.driver = {
	333	.name = DRV_NAME,
	334	.of_match_table = ahci_of_match,
	335	.pm = &ahci_brcm_pm_ops,
	336	},
	337	};
	338	module_platform_driver(brcm_ahci_driver);
	339
	340	MODULE_DESCRIPTION("Broadcom SATA3 AHCI Controller Driver");
	341	MODULE_AUTHOR("Brian Norris");
	342	MODULE_LICENSE("GPL");
	343	MODULE_ALIAS("platform:sata-brcmstb");