[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci_imx.c

/*
 * copyright (c) 2013 Freescale Semiconductor, Inc.
 * Freescale IMX AHCI SATA platform driver
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/ahci_platform.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/libata.h>
#include "ahci.h"

enum {
	PORT_PHY_CTL = 0x178,			/* Port0 PHY Control */
	PORT_PHY_CTL_PDDQ_LOC = 0x100000,	/* PORT_PHY_CTL bits */
	HOST_TIMER1MS = 0xe0,			/* Timer 1-ms */
};

enum ahci_imx_type {
	AHCI_IMX53,
	AHCI_IMX6Q,
};

struct imx_ahci_priv {
	struct platform_device *ahci_pdev;
	enum ahci_imx_type type;
	struct clk *ahb_clk;
	struct regmap *gpr;
	bool no_device;
	bool first_time;
};

static int ahci_imx_hotplug;
module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");

static void ahci_imx_host_stop(struct ata_host *host);

static int imx_sata_enable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	int ret;

	if (imxpriv->no_device)
		return 0;

	if (hpriv->target_pwr) {
		ret = regulator_enable(hpriv->target_pwr);
		if (ret)
			return ret;
	}

	ret = ahci_platform_enable_clks(hpriv);
	if (ret < 0)
		goto disable_regulator;

	if (imxpriv->type == AHCI_IMX6Q) {
		/*
		 * set PHY Paremeters, two steps to configure the GPR13,
		 * one write for rest of parameters, mask of first write
		 * is 0x07ffffff, and the other one write for setting
		 * the mpll_clk_en.
		 */
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
				   IMX6Q_GPR13_SATA_SPD_MODE_MASK |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
				   IMX6Q_GPR13_SATA_TX_BOOST_MASK |
				   IMX6Q_GPR13_SATA_TX_LVL_MASK |
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN |
				   IMX6Q_GPR13_SATA_TX_EDGE_RATE,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
				   IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
				   IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
				   IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	}

	usleep_range(1000, 2000);

	return 0;

disable_regulator:
	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);

	return ret;
}

static void imx_sata_disable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	if (imxpriv->no_device)
		return;

	if (imxpriv->type == AHCI_IMX6Q) {
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	}

	ahci_platform_disable_clks(hpriv);

	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);
}

static void ahci_imx_error_handler(struct ata_port *ap)
{
	u32 reg_val;
	struct ata_device *dev;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	ahci_error_handler(ap);

	if (!(imxpriv->first_time) || ahci_imx_hotplug)
		return;

	imxpriv->first_time = false;

	ata_for_each_dev(dev, &ap->link, ENABLED)
		return;
	/*
	 * Disable link to save power.  An imx ahci port can't be recovered
	 * without full reset once the pddq mode is enabled making it
	 * impossible to use as part of libata LPM.
	 */
	reg_val = readl(mmio + PORT_PHY_CTL);
	writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
	imx_sata_disable(hpriv);
	imxpriv->no_device = true;
}

static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
		       unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	int ret = -EIO;

	if (imxpriv->type == AHCI_IMX53)
		ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	else if (imxpriv->type == AHCI_IMX6Q)
		ret = ahci_ops.softreset(link, class, deadline);

	return ret;
}

static struct ata_port_operations ahci_imx_ops = {
	.inherits	= &ahci_ops,
	.host_stop	= ahci_imx_host_stop,
	.error_handler	= ahci_imx_error_handler,
	.softreset	= ahci_imx_softreset,
};

static const struct ata_port_info ahci_imx_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_imx_ops,
};

static const struct of_device_id imx_ahci_of_match[] = {
	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
	{},
};
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);

static int imx_ahci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *of_id;
	struct ahci_host_priv *hpriv;
	struct imx_ahci_priv *imxpriv;
	unsigned int reg_val;
	int ret;

	of_id = of_match_device(imx_ahci_of_match, dev);
	if (!of_id)
		return -EINVAL;

	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
	if (!imxpriv)
		return -ENOMEM;

	imxpriv->no_device = false;
	imxpriv->first_time = true;
	imxpriv->type = (enum ahci_imx_type)of_id->data;
	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	if (IS_ERR(imxpriv->ahb_clk)) {
		dev_err(dev, "can't get ahb clock.\n");
		return PTR_ERR(imxpriv->ahb_clk);
	}

	if (imxpriv->type == AHCI_IMX6Q) {
		imxpriv->gpr = syscon_regmap_lookup_by_compatible(
							"fsl,imx6q-iomuxc-gpr");
		if (IS_ERR(imxpriv->gpr)) {
			dev_err(dev,
				"failed to find fsl,imx6q-iomux-gpr regmap\n");
			return PTR_ERR(imxpriv->gpr);
		}
	}

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	hpriv->plat_data = imxpriv;

	ret = imx_sata_enable(hpriv);
	if (ret)
		return ret;

	/*
	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	 * and IP vendor specific register HOST_TIMER1MS.
	 * Configure CAP_SSS (support stagered spin up).
	 * Implement the port0.
	 * Get the ahb clock rate, and configure the TIMER1MS register.
	 */
	reg_val = readl(hpriv->mmio + HOST_CAP);
	if (!(reg_val & HOST_CAP_SSS)) {
		reg_val |= HOST_CAP_SSS;
		writel(reg_val, hpriv->mmio + HOST_CAP);
	}
	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	if (!(reg_val & 0x1)) {
		reg_val |= 0x1;
		writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
	}

	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
	writel(reg_val, hpriv->mmio + HOST_TIMER1MS);

	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
	if (ret)
		imx_sata_disable(hpriv);

	return ret;
}

static void ahci_imx_host_stop(struct ata_host *host)
{
	struct ahci_host_priv *hpriv = host->private_data;

	imx_sata_disable(hpriv);
}

#ifdef CONFIG_PM_SLEEP
static int imx_ahci_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = ahci_platform_suspend_host(dev);
	if (ret)
		return ret;

	imx_sata_disable(hpriv);

	return 0;
}

static int imx_ahci_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = imx_sata_enable(hpriv);
	if (ret)
		return ret;

	return ahci_platform_resume_host(dev);
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);

static struct platform_driver imx_ahci_driver = {
	.probe = imx_ahci_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = "ahci-imx",
		.owner = THIS_MODULE,
		.of_match_table = imx_ahci_of_match,
		.pm = &ahci_imx_pm_ops,
	},
};
module_platform_driver(imx_ahci_driver);

MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("ahci:imx");
Commit	Line	Data
9e54eae2	1	/*
8b789d89	2	* copyright (c) 2013 Freescale Semiconductor, Inc.
9e54eae2	3	* Freescale IMX AHCI SATA platform driver
9e54eae2 RZ	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/ahci_platform.h>
	25	#include <linux/of_device.h>
	26	#include <linux/mfd/syscon.h>
	27	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
8b789d89	28	#include <linux/libata.h>
9e54eae2 RZ	29	#include "ahci.h"
	30
	31	enum {
8b789d89 RZ	32	PORT_PHY_CTL = 0x178, /* Port0 PHY Control */
	33	PORT_PHY_CTL_PDDQ_LOC = 0x100000, /* PORT_PHY_CTL bits */
	34	HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
9e54eae2 RZ	35	};
9e54eae2 RZ	36
4a23d179 MV	37	enum ahci_imx_type {
	38	AHCI_IMX53,
	39	AHCI_IMX6Q,
	40	};
	41
9e54eae2 RZ	42	struct imx_ahci_priv {
9e54eae2 RZ	43	struct platform_device *ahci_pdev;
4a23d179	44	enum ahci_imx_type type;
9e54eae2 RZ	45	struct clk *ahb_clk;
9e54eae2 RZ	46	struct regmap *gpr;
8b789d89 RZ	47	bool no_device;
	48	bool first_time;
	49	};
	50
	51	static int ahci_imx_hotplug;
	52	module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
	53	MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
	54
90870d79 HG	55	static void ahci_imx_host_stop(struct ata_host *host);
	56
	57	static int imx_sata_enable(struct ahci_host_priv *hpriv)
8403e2ec	58	{
90870d79	59	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
8403e2ec MV	60	int ret;
8403e2ec MV	61
90870d79 HG	62	if (imxpriv->no_device)
	63	return 0;
	64
	65	if (hpriv->target_pwr) {
	66	ret = regulator_enable(hpriv->target_pwr);
	67	if (ret)
4a23d179	68	return ret;
4a23d179 MV	69	}
4a23d179 MV	70
90870d79 HG	71	ret = ahci_platform_enable_clks(hpriv);
	72	if (ret < 0)
	73	goto disable_regulator;
8403e2ec	74
4a23d179	75	if (imxpriv->type == AHCI_IMX6Q) {
90870d79 HG	76	/*
	77	* set PHY Paremeters, two steps to configure the GPR13,
	78	* one write for rest of parameters, mask of first write
	79	* is 0x07ffffff, and the other one write for setting
	80	* the mpll_clk_en.
	81	*/
	82	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	83	IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK \|
	84	IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK \|
	85	IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK \|
	86	IMX6Q_GPR13_SATA_SPD_MODE_MASK \|
	87	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	88	IMX6Q_GPR13_SATA_TX_ATTEN_MASK \|
	89	IMX6Q_GPR13_SATA_TX_BOOST_MASK \|
	90	IMX6Q_GPR13_SATA_TX_LVL_MASK \|
	91	IMX6Q_GPR13_SATA_MPLL_CLK_EN \|
	92	IMX6Q_GPR13_SATA_TX_EDGE_RATE,
	93	IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB \|
	94	IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M \|
	95	IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F \|
	96	IMX6Q_GPR13_SATA_SPD_MODE_3P0G \|
	97	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	98	IMX6Q_GPR13_SATA_TX_ATTEN_9_16 \|
	99	IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB \|
	100	IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
4a23d179 MV	101	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	102	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	103	IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	104	}
8403e2ec MV	105
	106	usleep_range(1000, 2000);
	107
	108	return 0;
4a23d179	109
90870d79 HG	110	disable_regulator:
	111	if (hpriv->target_pwr)
	112	regulator_disable(hpriv->target_pwr);
	113
4a23d179	114	return ret;
8403e2ec MV	115	}
8403e2ec MV	116
90870d79	117	static void imx_sata_disable(struct ahci_host_priv *hpriv)
8403e2ec	118	{
90870d79 HG	119	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	120
	121	if (imxpriv->no_device)
	122	return;
8403e2ec	123
4a23d179 MV	124	if (imxpriv->type == AHCI_IMX6Q) {
	125	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	126	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	127	!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	128	}
	129
90870d79	130	ahci_platform_disable_clks(hpriv);
4a23d179	131
90870d79 HG	132	if (hpriv->target_pwr)
90870d79 HG	133	regulator_disable(hpriv->target_pwr);
8403e2ec MV	134	}
8403e2ec MV	135
8b789d89 RZ	136	static void ahci_imx_error_handler(struct ata_port *ap)
	137	{
	138	u32 reg_val;
	139	struct ata_device *dev;
	140	struct ata_host *host = dev_get_drvdata(ap->dev);
	141	struct ahci_host_priv *hpriv = host->private_data;
	142	void __iomem *mmio = hpriv->mmio;
90870d79	143	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
8b789d89 RZ	144
	145	ahci_error_handler(ap);
	146
	147	if (!(imxpriv->first_time) \|\| ahci_imx_hotplug)
	148	return;
	149
	150	imxpriv->first_time = false;
	151
	152	ata_for_each_dev(dev, &ap->link, ENABLED)
	153	return;
	154	/*
	155	* Disable link to save power. An imx ahci port can't be recovered
	156	* without full reset once the pddq mode is enabled making it
	157	* impossible to use as part of libata LPM.
	158	*/
	159	reg_val = readl(mmio + PORT_PHY_CTL);
	160	writel(reg_val \| PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
90870d79	161	imx_sata_disable(hpriv);
8b789d89 RZ	162	imxpriv->no_device = true;
	163	}
	164
ee4e5a9a	165	static int ahci_imx_softreset(struct ata_link link, unsigned int class,
4a23d179 MV	166	unsigned long deadline)
	167	{
	168	struct ata_port *ap = link->ap;
90870d79 HG	169	struct ata_host *host = dev_get_drvdata(ap->dev);
	170	struct ahci_host_priv *hpriv = host->private_data;
	171	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
4a23d179 MV	172	int ret = -EIO;
	173
	174	if (imxpriv->type == AHCI_IMX53)
	175	ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	176	else if (imxpriv->type == AHCI_IMX6Q)
	177	ret = ahci_ops.softreset(link, class, deadline);
	178
	179	return ret;
	180	}
	181
8b789d89	182	static struct ata_port_operations ahci_imx_ops = {
90870d79 HG	183	.inherits = &ahci_ops,
90870d79 HG	184	.host_stop = ahci_imx_host_stop,
8b789d89	185	.error_handler = ahci_imx_error_handler,
4a23d179	186	.softreset = ahci_imx_softreset,
8b789d89 RZ	187	};
	188
	189	static const struct ata_port_info ahci_imx_port_info = {
	190	.flags = AHCI_FLAG_COMMON,
	191	.pio_mask = ATA_PIO4,
	192	.udma_mask = ATA_UDMA6,
	193	.port_ops = &ahci_imx_ops,
9e54eae2 RZ	194	};
9e54eae2 RZ	195
9e54eae2	196	static const struct of_device_id imx_ahci_of_match[] = {
4a23d179 MV	197	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
4a23d179 MV	198	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
9e54eae2 RZ	199	{},
	200	};
	201	MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
	202
	203	static int imx_ahci_probe(struct platform_device *pdev)
	204	{
	205	struct device *dev = &pdev->dev;
9e54eae2	206	const struct of_device_id *of_id;
90870d79	207	struct ahci_host_priv *hpriv;
9e54eae2	208	struct imx_ahci_priv *imxpriv;
90870d79	209	unsigned int reg_val;
9e54eae2 RZ	210	int ret;
9e54eae2 RZ	211
4a23d179 MV	212	of_id = of_match_device(imx_ahci_of_match, dev);
	213	if (!of_id)
	214	return -EINVAL;
	215
9e54eae2	216	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
90870d79	217	if (!imxpriv)
9e54eae2	218	return -ENOMEM;
9e54eae2	219
8b789d89 RZ	220	imxpriv->no_device = false;
8b789d89 RZ	221	imxpriv->first_time = true;
90870d79	222	imxpriv->type = (enum ahci_imx_type)of_id->data;
9e54eae2 RZ	223	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	224	if (IS_ERR(imxpriv->ahb_clk)) {
	225	dev_err(dev, "can't get ahb clock.\n");
90870d79	226	return PTR_ERR(imxpriv->ahb_clk);
9e54eae2 RZ	227	}
9e54eae2 RZ	228
90870d79 HG	229	if (imxpriv->type == AHCI_IMX6Q) {
	230	imxpriv->gpr = syscon_regmap_lookup_by_compatible(
	231	"fsl,imx6q-iomuxc-gpr");
	232	if (IS_ERR(imxpriv->gpr)) {
	233	dev_err(dev,
	234	"failed to find fsl,imx6q-iomux-gpr regmap\n");
	235	return PTR_ERR(imxpriv->gpr);
4a23d179 MV	236	}
	237	}
	238
90870d79 HG	239	hpriv = ahci_platform_get_resources(pdev);
	240	if (IS_ERR(hpriv))
	241	return PTR_ERR(hpriv);
	242
	243	hpriv->plat_data = imxpriv;
9e54eae2	244
90870d79 HG	245	ret = imx_sata_enable(hpriv);
	246	if (ret)
	247	return ret;
9e54eae2	248
90870d79 HG	249	/*
	250	* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	251	* and IP vendor specific register HOST_TIMER1MS.
	252	* Configure CAP_SSS (support stagered spin up).
	253	* Implement the port0.
	254	* Get the ahb clock rate, and configure the TIMER1MS register.
	255	*/
	256	reg_val = readl(hpriv->mmio + HOST_CAP);
	257	if (!(reg_val & HOST_CAP_SSS)) {
	258	reg_val \|= HOST_CAP_SSS;
	259	writel(reg_val, hpriv->mmio + HOST_CAP);
	260	}
	261	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	262	if (!(reg_val & 0x1)) {
	263	reg_val \|= 0x1;
	264	writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
9e54eae2 RZ	265	}
9e54eae2 RZ	266
90870d79 HG	267	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
90870d79 HG	268	writel(reg_val, hpriv->mmio + HOST_TIMER1MS);
9e54eae2	269
90870d79 HG	270	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
	271	if (ret)
	272	imx_sata_disable(hpriv);
9e54eae2	273
90870d79 HG	274	return ret;
90870d79 HG	275	}
4a23d179	276
90870d79 HG	277	static void ahci_imx_host_stop(struct ata_host *host)
	278	{
	279	struct ahci_host_priv *hpriv = host->private_data;
8403e2ec	280
90870d79 HG	281	imx_sata_disable(hpriv);
90870d79 HG	282	}
9e54eae2	283
46ce6b74	284	#ifdef CONFIG_PM_SLEEP
90870d79 HG	285	static int imx_ahci_suspend(struct device *dev)
	286	{
	287	struct ata_host *host = dev_get_drvdata(dev);
	288	struct ahci_host_priv *hpriv = host->private_data;
	289	int ret;
9e54eae2	290
90870d79 HG	291	ret = ahci_platform_suspend_host(dev);
90870d79 HG	292	if (ret)
9e54eae2	293	return ret;
90870d79 HG	294
90870d79 HG	295	imx_sata_disable(hpriv);
9e54eae2 RZ	296
	297	return 0;
	298	}
	299
90870d79	300	static int imx_ahci_resume(struct device *dev)
9e54eae2	301	{
90870d79 HG	302	struct ata_host *host = dev_get_drvdata(dev);
	303	struct ahci_host_priv *hpriv = host->private_data;
	304	int ret;
9e54eae2	305
90870d79 HG	306	ret = imx_sata_enable(hpriv);
	307	if (ret)
	308	return ret;
	309
	310	return ahci_platform_resume_host(dev);
9e54eae2	311	}
46ce6b74	312	#endif
9e54eae2	313
90870d79 HG	314	static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
90870d79 HG	315
9e54eae2 RZ	316	static struct platform_driver imx_ahci_driver = {
9e54eae2 RZ	317	.probe = imx_ahci_probe,
90870d79	318	.remove = ata_platform_remove_one,
9e54eae2 RZ	319	.driver = {
	320	.name = "ahci-imx",
	321	.owner = THIS_MODULE,
	322	.of_match_table = imx_ahci_of_match,
90870d79	323	.pm = &ahci_imx_pm_ops,
9e54eae2 RZ	324	},
	325	};
	326	module_platform_driver(imx_ahci_driver);
	327
	328	MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
	329	MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
	330	MODULE_LICENSE("GPL");
	331	MODULE_ALIAS("ahci:imx");