[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci_imx.c

/*
 * copyright (c) 2013 Freescale Semiconductor, Inc.
 * Freescale IMX AHCI SATA platform driver
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/ahci_platform.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/libata.h>
#include "ahci.h"

enum {
	/* Timer 1-ms Register */
	IMX_TIMER1MS				= 0x00e0,
	/* Port0 PHY Control Register */
	IMX_P0PHYCR				= 0x0178,
	IMX_P0PHYCR_TEST_PDDQ			= 1 << 20,
	IMX_P0PHYCR_CR_READ			= 1 << 19,
	IMX_P0PHYCR_CR_WRITE			= 1 << 18,
	IMX_P0PHYCR_CR_CAP_DATA			= 1 << 17,
	IMX_P0PHYCR_CR_CAP_ADDR			= 1 << 16,
	/* Port0 PHY Status Register */
	IMX_P0PHYSR				= 0x017c,
	IMX_P0PHYSR_CR_ACK			= 1 << 18,
	IMX_P0PHYSR_CR_DATA_OUT			= 0xffff << 0,
	/* Lane0 Output Status Register */
	IMX_LANE0_OUT_STAT			= 0x2003,
	IMX_LANE0_OUT_STAT_RX_PLL_STATE		= 1 << 1,
	/* Clock Reset Register */
	IMX_CLOCK_RESET				= 0x7f3f,
	IMX_CLOCK_RESET_RESET			= 1 << 0,
};

enum ahci_imx_type {
	AHCI_IMX53,
	AHCI_IMX6Q,
};

struct imx_ahci_priv {
	struct platform_device *ahci_pdev;
	enum ahci_imx_type type;
	struct clk *sata_clk;
	struct clk *sata_ref_clk;
	struct clk *ahb_clk;
	struct regmap *gpr;
	bool no_device;
	bool first_time;
};

static int ahci_imx_hotplug;
module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");

static void ahci_imx_host_stop(struct ata_host *host);

static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
{
	int timeout = 10;
	u32 crval;
	u32 srval;

	/* Assert or deassert the bit */
	crval = readl(mmio + IMX_P0PHYCR);
	if (assert)
		crval |= bit;
	else
		crval &= ~bit;
	writel(crval, mmio + IMX_P0PHYCR);

	/* Wait for the cr_ack signal */
	do {
		srval = readl(mmio + IMX_P0PHYSR);
		if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
			break;
		usleep_range(100, 200);
	} while (--timeout);

	return timeout ? 0 : -ETIMEDOUT;
}

static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
{
	u32 crval = addr;
	int ret;

	/* Supply the address on cr_data_in */
	writel(crval, mmio + IMX_P0PHYCR);

	/* Assert the cr_cap_addr signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
	if (ret)
		return ret;

	/* Deassert cr_cap_addr */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
	if (ret)
		return ret;

	return 0;
}

static int imx_phy_reg_write(u16 val, void __iomem *mmio)
{
	u32 crval = val;
	int ret;

	/* Supply the data on cr_data_in */
	writel(crval, mmio + IMX_P0PHYCR);

	/* Assert the cr_cap_data signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
	if (ret)
		return ret;

	/* Deassert cr_cap_data */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
	if (ret)
		return ret;

	if (val & IMX_CLOCK_RESET_RESET) {
		/*
		 * In case we're resetting the phy, it's unable to acknowledge,
		 * so we return immediately here.
		 */
		crval |= IMX_P0PHYCR_CR_WRITE;
		writel(crval, mmio + IMX_P0PHYCR);
		goto out;
	}

	/* Assert the cr_write signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
	if (ret)
		return ret;

	/* Deassert cr_write */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
	if (ret)
		return ret;

out:
	return 0;
}

static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
{
	int ret;

	/* Assert the cr_read signal */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
	if (ret)
		return ret;

	/* Capture the data from cr_data_out[] */
	*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;

	/* Deassert cr_read */
	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
	if (ret)
		return ret;

	return 0;
}

static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
{
	void __iomem *mmio = hpriv->mmio;
	int timeout = 10;
	u16 val;
	int ret;

	/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
	ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
	if (ret)
		return ret;
	ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
	if (ret)
		return ret;

	/* Wait for PHY RX_PLL to be stable */
	do {
		usleep_range(100, 200);
		ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
		if (ret)
			return ret;
		ret = imx_phy_reg_read(&val, mmio);
		if (ret)
			return ret;
		if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
			break;
	} while (--timeout);

	return timeout ? 0 : -ETIMEDOUT;
}

static int imx_sata_enable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	struct device *dev = &imxpriv->ahci_pdev->dev;
	int ret;

	if (imxpriv->no_device)
		return 0;

	if (hpriv->target_pwr) {
		ret = regulator_enable(hpriv->target_pwr);
		if (ret)
			return ret;
	}

	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
	if (ret < 0)
		goto disable_regulator;

	if (imxpriv->type == AHCI_IMX6Q) {
		/*
		 * set PHY Paremeters, two steps to configure the GPR13,
		 * one write for rest of parameters, mask of first write
		 * is 0x07ffffff, and the other one write for setting
		 * the mpll_clk_en.
		 */
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
				   IMX6Q_GPR13_SATA_SPD_MODE_MASK |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
				   IMX6Q_GPR13_SATA_TX_BOOST_MASK |
				   IMX6Q_GPR13_SATA_TX_LVL_MASK |
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN |
				   IMX6Q_GPR13_SATA_TX_EDGE_RATE,
				   IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB |
				   IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
				   IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
				   IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
				   IMX6Q_GPR13_SATA_MPLL_SS_EN |
				   IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
				   IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
				   IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN);

		usleep_range(100, 200);

		ret = imx_sata_phy_reset(hpriv);
		if (ret) {
			dev_err(dev, "failed to reset phy: %d\n", ret);
			goto disable_regulator;
		}
	}

	usleep_range(1000, 2000);

	return 0;

disable_regulator:
	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);

	return ret;
}

static void imx_sata_disable(struct ahci_host_priv *hpriv)
{
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	if (imxpriv->no_device)
		return;

	if (imxpriv->type == AHCI_IMX6Q) {
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				   IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				   !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	}

	clk_disable_unprepare(imxpriv->sata_ref_clk);

	if (hpriv->target_pwr)
		regulator_disable(hpriv->target_pwr);
}

static void ahci_imx_error_handler(struct ata_port *ap)
{
	u32 reg_val;
	struct ata_device *dev;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	ahci_error_handler(ap);

	if (!(imxpriv->first_time) || ahci_imx_hotplug)
		return;

	imxpriv->first_time = false;

	ata_for_each_dev(dev, &ap->link, ENABLED)
		return;
	/*
	 * Disable link to save power.  An imx ahci port can't be recovered
	 * without full reset once the pddq mode is enabled making it
	 * impossible to use as part of libata LPM.
	 */
	reg_val = readl(mmio + IMX_P0PHYCR);
	writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
	imx_sata_disable(hpriv);
	imxpriv->no_device = true;

	dev_info(ap->dev, "no device found, disabling link.\n");
	dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
}

static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
		       unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	int ret = -EIO;

	if (imxpriv->type == AHCI_IMX53)
		ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	else if (imxpriv->type == AHCI_IMX6Q)
		ret = ahci_ops.softreset(link, class, deadline);

	return ret;
}

static struct ata_port_operations ahci_imx_ops = {
	.inherits	= &ahci_ops,
	.host_stop	= ahci_imx_host_stop,
	.error_handler	= ahci_imx_error_handler,
	.softreset	= ahci_imx_softreset,
};

static const struct ata_port_info ahci_imx_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_imx_ops,
};

static const struct of_device_id imx_ahci_of_match[] = {
	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
	{},
};
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);

static int imx_ahci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *of_id;
	struct ahci_host_priv *hpriv;
	struct imx_ahci_priv *imxpriv;
	unsigned int reg_val;
	int ret;

	of_id = of_match_device(imx_ahci_of_match, dev);
	if (!of_id)
		return -EINVAL;

	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
	if (!imxpriv)
		return -ENOMEM;

	imxpriv->ahci_pdev = pdev;
	imxpriv->no_device = false;
	imxpriv->first_time = true;
	imxpriv->type = (enum ahci_imx_type)of_id->data;

	imxpriv->sata_clk = devm_clk_get(dev, "sata");
	if (IS_ERR(imxpriv->sata_clk)) {
		dev_err(dev, "can't get sata clock.\n");
		return PTR_ERR(imxpriv->sata_clk);
	}

	imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
	if (IS_ERR(imxpriv->sata_ref_clk)) {
		dev_err(dev, "can't get sata_ref clock.\n");
		return PTR_ERR(imxpriv->sata_ref_clk);
	}

	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	if (IS_ERR(imxpriv->ahb_clk)) {
		dev_err(dev, "can't get ahb clock.\n");
		return PTR_ERR(imxpriv->ahb_clk);
	}

	if (imxpriv->type == AHCI_IMX6Q) {
		imxpriv->gpr = syscon_regmap_lookup_by_compatible(
							"fsl,imx6q-iomuxc-gpr");
		if (IS_ERR(imxpriv->gpr)) {
			dev_err(dev,
				"failed to find fsl,imx6q-iomux-gpr regmap\n");
			return PTR_ERR(imxpriv->gpr);
		}
	}

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	hpriv->plat_data = imxpriv;

	ret = clk_prepare_enable(imxpriv->sata_clk);
	if (ret)
		return ret;

	ret = imx_sata_enable(hpriv);
	if (ret)
		goto disable_clk;

	/*
	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	 * and IP vendor specific register IMX_TIMER1MS.
	 * Configure CAP_SSS (support stagered spin up).
	 * Implement the port0.
	 * Get the ahb clock rate, and configure the TIMER1MS register.
	 */
	reg_val = readl(hpriv->mmio + HOST_CAP);
	if (!(reg_val & HOST_CAP_SSS)) {
		reg_val |= HOST_CAP_SSS;
		writel(reg_val, hpriv->mmio + HOST_CAP);
	}
	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	if (!(reg_val & 0x1)) {
		reg_val |= 0x1;
		writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
	}

	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);

	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
				      0, 0, 0);
	if (ret)
		goto disable_sata;

	return 0;

disable_sata:
	imx_sata_disable(hpriv);
disable_clk:
	clk_disable_unprepare(imxpriv->sata_clk);
	return ret;
}

static void ahci_imx_host_stop(struct ata_host *host)
{
	struct ahci_host_priv *hpriv = host->private_data;
	struct imx_ahci_priv *imxpriv = hpriv->plat_data;

	imx_sata_disable(hpriv);
	clk_disable_unprepare(imxpriv->sata_clk);
}

#ifdef CONFIG_PM_SLEEP
static int imx_ahci_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = ahci_platform_suspend_host(dev);
	if (ret)
		return ret;

	imx_sata_disable(hpriv);

	return 0;
}

static int imx_ahci_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int ret;

	ret = imx_sata_enable(hpriv);
	if (ret)
		return ret;

	return ahci_platform_resume_host(dev);
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);

static struct platform_driver imx_ahci_driver = {
	.probe = imx_ahci_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = "ahci-imx",
		.owner = THIS_MODULE,
		.of_match_table = imx_ahci_of_match,
		.pm = &ahci_imx_pm_ops,
	},
};
module_platform_driver(imx_ahci_driver);

MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("ahci:imx");
Commit	Line	Data
9e54eae2	1	/*
8b789d89	2	* copyright (c) 2013 Freescale Semiconductor, Inc.
9e54eae2	3	* Freescale IMX AHCI SATA platform driver
9e54eae2 RZ	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/ahci_platform.h>
	25	#include <linux/of_device.h>
	26	#include <linux/mfd/syscon.h>
	27	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
8b789d89	28	#include <linux/libata.h>
9e54eae2 RZ	29	#include "ahci.h"
	30
	31	enum {
24a9ad5b SG	32	/* Timer 1-ms Register */
	33	IMX_TIMER1MS = 0x00e0,
	34	/* Port0 PHY Control Register */
	35	IMX_P0PHYCR = 0x0178,
	36	IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
e783c51c SG	37	IMX_P0PHYCR_CR_READ = 1 << 19,
	38	IMX_P0PHYCR_CR_WRITE = 1 << 18,
	39	IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
	40	IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
	41	/* Port0 PHY Status Register */
	42	IMX_P0PHYSR = 0x017c,
	43	IMX_P0PHYSR_CR_ACK = 1 << 18,
	44	IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
	45	/* Lane0 Output Status Register */
	46	IMX_LANE0_OUT_STAT = 0x2003,
	47	IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
	48	/* Clock Reset Register */
	49	IMX_CLOCK_RESET = 0x7f3f,
	50	IMX_CLOCK_RESET_RESET = 1 << 0,
9e54eae2 RZ	51	};
9e54eae2 RZ	52
4a23d179 MV	53	enum ahci_imx_type {
	54	AHCI_IMX53,
	55	AHCI_IMX6Q,
	56	};
	57
9e54eae2 RZ	58	struct imx_ahci_priv {
9e54eae2 RZ	59	struct platform_device *ahci_pdev;
4a23d179	60	enum ahci_imx_type type;
e6dd42a9 SG	61	struct clk *sata_clk;
e6dd42a9 SG	62	struct clk *sata_ref_clk;
9e54eae2 RZ	63	struct clk *ahb_clk;
9e54eae2 RZ	64	struct regmap *gpr;
8b789d89 RZ	65	bool no_device;
	66	bool first_time;
	67	};
	68
	69	static int ahci_imx_hotplug;
	70	module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
	71	MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
	72
90870d79 HG	73	static void ahci_imx_host_stop(struct ata_host *host);
90870d79 HG	74
e783c51c SG	75	static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
	76	{
	77	int timeout = 10;
	78	u32 crval;
	79	u32 srval;
	80
	81	/* Assert or deassert the bit */
	82	crval = readl(mmio + IMX_P0PHYCR);
	83	if (assert)
	84	crval \|= bit;
	85	else
	86	crval &= ~bit;
	87	writel(crval, mmio + IMX_P0PHYCR);
	88
	89	/* Wait for the cr_ack signal */
	90	do {
	91	srval = readl(mmio + IMX_P0PHYSR);
	92	if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
	93	break;
	94	usleep_range(100, 200);
	95	} while (--timeout);
	96
	97	return timeout ? 0 : -ETIMEDOUT;
	98	}
	99
	100	static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
	101	{
	102	u32 crval = addr;
	103	int ret;
	104
	105	/* Supply the address on cr_data_in */
	106	writel(crval, mmio + IMX_P0PHYCR);
	107
	108	/* Assert the cr_cap_addr signal */
	109	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
	110	if (ret)
	111	return ret;
	112
	113	/* Deassert cr_cap_addr */
	114	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
	115	if (ret)
	116	return ret;
	117
	118	return 0;
	119	}
	120
	121	static int imx_phy_reg_write(u16 val, void __iomem *mmio)
	122	{
	123	u32 crval = val;
	124	int ret;
	125
	126	/* Supply the data on cr_data_in */
	127	writel(crval, mmio + IMX_P0PHYCR);
	128
	129	/* Assert the cr_cap_data signal */
	130	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
	131	if (ret)
	132	return ret;
	133
	134	/* Deassert cr_cap_data */
	135	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
	136	if (ret)
	137	return ret;
	138
139	if (val & IMX_CLOCK_RESET_RESET) {
140	/*
141	* In case we're resetting the phy, it's unable to acknowledge,
142	* so we return immediately here.
143	*/
144	crval \|= IMX_P0PHYCR_CR_WRITE;
145	writel(crval, mmio + IMX_P0PHYCR);
146	goto out;
147	}
148
149	/* Assert the cr_write signal */
150	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
151	if (ret)
152	return ret;
153
154	/* Deassert cr_write */
155	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
156	if (ret)
157	return ret;
158
159	out:
160	return 0;
161	}
162
163	static int imx_phy_reg_read(u16 val, void __iomem mmio)
164	{
165	int ret;
166
167	/* Assert the cr_read signal */
168	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
169	if (ret)
170	return ret;
171
172	/* Capture the data from cr_data_out[] */
173	*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
174
175	/* Deassert cr_read */
176	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
177	if (ret)
178	return ret;
179
180	return 0;
181	}
182
183	static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
184	{
185	void __iomem *mmio = hpriv->mmio;
186	int timeout = 10;
187	u16 val;
188	int ret;
189
190	/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
191	ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
192	if (ret)
193	return ret;
194	ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
195	if (ret)
196	return ret;
197
198	/* Wait for PHY RX_PLL to be stable */
199	do {
200	usleep_range(100, 200);
201	ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
202	if (ret)
203	return ret;
204	ret = imx_phy_reg_read(&val, mmio);
205	if (ret)
206	return ret;
207	if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
208	break;
209	} while (--timeout);
210
211	return timeout ? 0 : -ETIMEDOUT;
212	}
213
90870d79	214	static int imx_sata_enable(struct ahci_host_priv *hpriv)
8403e2ec	215	{
90870d79	216	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
e783c51c	217	struct device *dev = &imxpriv->ahci_pdev->dev;
8403e2ec MV	218	int ret;
8403e2ec MV	219
90870d79 HG	220	if (imxpriv->no_device)
	221	return 0;
	222
	223	if (hpriv->target_pwr) {
	224	ret = regulator_enable(hpriv->target_pwr);
	225	if (ret)
4a23d179	226	return ret;
4a23d179 MV	227	}
4a23d179 MV	228
e6dd42a9	229	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
90870d79 HG	230	if (ret < 0)
90870d79 HG	231	goto disable_regulator;
8403e2ec	232
4a23d179	233	if (imxpriv->type == AHCI_IMX6Q) {
90870d79 HG	234	/*
	235	* set PHY Paremeters, two steps to configure the GPR13,
	236	* one write for rest of parameters, mask of first write
	237	* is 0x07ffffff, and the other one write for setting
	238	* the mpll_clk_en.
	239	*/
	240	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	241	IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK \|
	242	IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK \|
	243	IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK \|
	244	IMX6Q_GPR13_SATA_SPD_MODE_MASK \|
	245	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	246	IMX6Q_GPR13_SATA_TX_ATTEN_MASK \|
	247	IMX6Q_GPR13_SATA_TX_BOOST_MASK \|
	248	IMX6Q_GPR13_SATA_TX_LVL_MASK \|
	249	IMX6Q_GPR13_SATA_MPLL_CLK_EN \|
	250	IMX6Q_GPR13_SATA_TX_EDGE_RATE,
	251	IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB \|
	252	IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M \|
	253	IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F \|
	254	IMX6Q_GPR13_SATA_SPD_MODE_3P0G \|
	255	IMX6Q_GPR13_SATA_MPLL_SS_EN \|
	256	IMX6Q_GPR13_SATA_TX_ATTEN_9_16 \|
	257	IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB \|
	258	IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
4a23d179 MV	259	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	260	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	261	IMX6Q_GPR13_SATA_MPLL_CLK_EN);
e783c51c	262
3685f251 SG	263	usleep_range(100, 200);
3685f251 SG	264
e783c51c SG	265	ret = imx_sata_phy_reset(hpriv);
	266	if (ret) {
	267	dev_err(dev, "failed to reset phy: %d\n", ret);
	268	goto disable_regulator;
	269	}
4a23d179	270	}
8403e2ec MV	271
	272	usleep_range(1000, 2000);
	273
	274	return 0;
4a23d179	275
90870d79 HG	276	disable_regulator:
	277	if (hpriv->target_pwr)
	278	regulator_disable(hpriv->target_pwr);
	279
4a23d179	280	return ret;
8403e2ec MV	281	}
8403e2ec MV	282
90870d79	283	static void imx_sata_disable(struct ahci_host_priv *hpriv)
8403e2ec	284	{
90870d79 HG	285	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
	286
	287	if (imxpriv->no_device)
	288	return;
8403e2ec	289
4a23d179 MV	290	if (imxpriv->type == AHCI_IMX6Q) {
	291	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	292	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	293	!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	294	}
	295
e6dd42a9	296	clk_disable_unprepare(imxpriv->sata_ref_clk);
4a23d179	297
90870d79 HG	298	if (hpriv->target_pwr)
90870d79 HG	299	regulator_disable(hpriv->target_pwr);
8403e2ec MV	300	}
8403e2ec MV	301
8b789d89 RZ	302	static void ahci_imx_error_handler(struct ata_port *ap)
	303	{
	304	u32 reg_val;
	305	struct ata_device *dev;
	306	struct ata_host *host = dev_get_drvdata(ap->dev);
	307	struct ahci_host_priv *hpriv = host->private_data;
	308	void __iomem *mmio = hpriv->mmio;
90870d79	309	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
8b789d89 RZ	310
	311	ahci_error_handler(ap);
	312
	313	if (!(imxpriv->first_time) \|\| ahci_imx_hotplug)
	314	return;
	315
	316	imxpriv->first_time = false;
	317
	318	ata_for_each_dev(dev, &ap->link, ENABLED)
	319	return;
	320	/*
	321	* Disable link to save power. An imx ahci port can't be recovered
	322	* without full reset once the pddq mode is enabled making it
	323	* impossible to use as part of libata LPM.
	324	*/
24a9ad5b SG	325	reg_val = readl(mmio + IMX_P0PHYCR);
24a9ad5b SG	326	writel(reg_val \| IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
90870d79	327	imx_sata_disable(hpriv);
8b789d89	328	imxpriv->no_device = true;
f118ae59 RK	329
	330	dev_info(ap->dev, "no device found, disabling link.\n");
	331	dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
8b789d89 RZ	332	}
8b789d89 RZ	333
ee4e5a9a	334	static int ahci_imx_softreset(struct ata_link link, unsigned int class,
4a23d179 MV	335	unsigned long deadline)
	336	{
	337	struct ata_port *ap = link->ap;
90870d79 HG	338	struct ata_host *host = dev_get_drvdata(ap->dev);
	339	struct ahci_host_priv *hpriv = host->private_data;
	340	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
4a23d179 MV	341	int ret = -EIO;
	342
	343	if (imxpriv->type == AHCI_IMX53)
	344	ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
	345	else if (imxpriv->type == AHCI_IMX6Q)
	346	ret = ahci_ops.softreset(link, class, deadline);
	347
	348	return ret;
	349	}
	350
8b789d89	351	static struct ata_port_operations ahci_imx_ops = {
90870d79 HG	352	.inherits = &ahci_ops,
90870d79 HG	353	.host_stop = ahci_imx_host_stop,
8b789d89	354	.error_handler = ahci_imx_error_handler,
4a23d179	355	.softreset = ahci_imx_softreset,
8b789d89 RZ	356	};
	357
	358	static const struct ata_port_info ahci_imx_port_info = {
	359	.flags = AHCI_FLAG_COMMON,
	360	.pio_mask = ATA_PIO4,
	361	.udma_mask = ATA_UDMA6,
	362	.port_ops = &ahci_imx_ops,
9e54eae2 RZ	363	};
9e54eae2 RZ	364
9e54eae2	365	static const struct of_device_id imx_ahci_of_match[] = {
4a23d179 MV	366	{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
4a23d179 MV	367	{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
9e54eae2 RZ	368	{},
	369	};
	370	MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
	371
	372	static int imx_ahci_probe(struct platform_device *pdev)
	373	{
	374	struct device *dev = &pdev->dev;
9e54eae2	375	const struct of_device_id *of_id;
90870d79	376	struct ahci_host_priv *hpriv;
9e54eae2	377	struct imx_ahci_priv *imxpriv;
90870d79	378	unsigned int reg_val;
9e54eae2 RZ	379	int ret;
9e54eae2 RZ	380
4a23d179 MV	381	of_id = of_match_device(imx_ahci_of_match, dev);
	382	if (!of_id)
	383	return -EINVAL;
	384
9e54eae2	385	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
90870d79	386	if (!imxpriv)
9e54eae2	387	return -ENOMEM;
9e54eae2	388
e783c51c	389	imxpriv->ahci_pdev = pdev;
8b789d89 RZ	390	imxpriv->no_device = false;
8b789d89 RZ	391	imxpriv->first_time = true;
90870d79	392	imxpriv->type = (enum ahci_imx_type)of_id->data;
e6dd42a9 SG	393
	394	imxpriv->sata_clk = devm_clk_get(dev, "sata");
	395	if (IS_ERR(imxpriv->sata_clk)) {
	396	dev_err(dev, "can't get sata clock.\n");
	397	return PTR_ERR(imxpriv->sata_clk);
	398	}
	399
	400	imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
	401	if (IS_ERR(imxpriv->sata_ref_clk)) {
	402	dev_err(dev, "can't get sata_ref clock.\n");
	403	return PTR_ERR(imxpriv->sata_ref_clk);
	404	}
	405
9e54eae2 RZ	406	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	407	if (IS_ERR(imxpriv->ahb_clk)) {
	408	dev_err(dev, "can't get ahb clock.\n");
90870d79	409	return PTR_ERR(imxpriv->ahb_clk);
9e54eae2 RZ	410	}
9e54eae2 RZ	411
90870d79 HG	412	if (imxpriv->type == AHCI_IMX6Q) {
	413	imxpriv->gpr = syscon_regmap_lookup_by_compatible(
	414	"fsl,imx6q-iomuxc-gpr");
	415	if (IS_ERR(imxpriv->gpr)) {
	416	dev_err(dev,
	417	"failed to find fsl,imx6q-iomux-gpr regmap\n");
	418	return PTR_ERR(imxpriv->gpr);
4a23d179 MV	419	}
	420	}
	421
90870d79 HG	422	hpriv = ahci_platform_get_resources(pdev);
	423	if (IS_ERR(hpriv))
	424	return PTR_ERR(hpriv);
	425
	426	hpriv->plat_data = imxpriv;
9e54eae2	427
e6dd42a9	428	ret = clk_prepare_enable(imxpriv->sata_clk);
90870d79 HG	429	if (ret)
90870d79 HG	430	return ret;
9e54eae2	431
e6dd42a9 SG	432	ret = imx_sata_enable(hpriv);
	433	if (ret)
	434	goto disable_clk;
	435
90870d79 HG	436	/*
90870d79 HG	437	* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
24a9ad5b	438	* and IP vendor specific register IMX_TIMER1MS.
90870d79 HG	439	* Configure CAP_SSS (support stagered spin up).
	440	* Implement the port0.
	441	* Get the ahb clock rate, and configure the TIMER1MS register.
	442	*/
	443	reg_val = readl(hpriv->mmio + HOST_CAP);
	444	if (!(reg_val & HOST_CAP_SSS)) {
	445	reg_val \|= HOST_CAP_SSS;
	446	writel(reg_val, hpriv->mmio + HOST_CAP);
	447	}
	448	reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
	449	if (!(reg_val & 0x1)) {
	450	reg_val \|= 0x1;
	451	writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
9e54eae2 RZ	452	}
9e54eae2 RZ	453
90870d79	454	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
24a9ad5b	455	writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
9e54eae2	456
f9f36917 KW	457	ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
f9f36917 KW	458	0, 0, 0);
90870d79	459	if (ret)
e6dd42a9 SG	460	goto disable_sata;
	461
	462	return 0;
9e54eae2	463
e6dd42a9 SG	464	disable_sata:
	465	imx_sata_disable(hpriv);
	466	disable_clk:
	467	clk_disable_unprepare(imxpriv->sata_clk);
90870d79 HG	468	return ret;
90870d79 HG	469	}
4a23d179	470
90870d79 HG	471	static void ahci_imx_host_stop(struct ata_host *host)
	472	{
	473	struct ahci_host_priv *hpriv = host->private_data;
e6dd42a9	474	struct imx_ahci_priv *imxpriv = hpriv->plat_data;
8403e2ec	475
90870d79	476	imx_sata_disable(hpriv);
e6dd42a9	477	clk_disable_unprepare(imxpriv->sata_clk);
90870d79	478	}
9e54eae2	479
46ce6b74	480	#ifdef CONFIG_PM_SLEEP
90870d79 HG	481	static int imx_ahci_suspend(struct device *dev)
	482	{
	483	struct ata_host *host = dev_get_drvdata(dev);
	484	struct ahci_host_priv *hpriv = host->private_data;
	485	int ret;
9e54eae2	486
90870d79 HG	487	ret = ahci_platform_suspend_host(dev);
90870d79 HG	488	if (ret)
9e54eae2	489	return ret;
90870d79 HG	490
90870d79 HG	491	imx_sata_disable(hpriv);
9e54eae2 RZ	492
	493	return 0;
	494	}
	495
90870d79	496	static int imx_ahci_resume(struct device *dev)
9e54eae2	497	{
90870d79 HG	498	struct ata_host *host = dev_get_drvdata(dev);
	499	struct ahci_host_priv *hpriv = host->private_data;
	500	int ret;
9e54eae2	501
90870d79 HG	502	ret = imx_sata_enable(hpriv);
	503	if (ret)
	504	return ret;
	505
	506	return ahci_platform_resume_host(dev);
9e54eae2	507	}
46ce6b74	508	#endif
9e54eae2	509
90870d79 HG	510	static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
90870d79 HG	511
9e54eae2 RZ	512	static struct platform_driver imx_ahci_driver = {
9e54eae2 RZ	513	.probe = imx_ahci_probe,
90870d79	514	.remove = ata_platform_remove_one,
9e54eae2 RZ	515	.driver = {
	516	.name = "ahci-imx",
	517	.owner = THIS_MODULE,
	518	.of_match_table = imx_ahci_of_match,
90870d79	519	.pm = &ahci_imx_pm_ops,
9e54eae2 RZ	520	},
	521	};
	522	module_platform_driver(imx_ahci_driver);
	523
	524	MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
	525	MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
	526	MODULE_LICENSE("GPL");
	527	MODULE_ALIAS("ahci:imx");