[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci_imx.c

/*
 * copyright (c) 2013 Freescale Semiconductor, Inc.
 * Freescale IMX AHCI SATA platform driver
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program. If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/ahci_platform.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/libata.h>
#include "ahci.h"

enum {
	PORT_PHY_CTL = 0x178,			/* Port0 PHY Control */
	PORT_PHY_CTL_PDDQ_LOC = 0x100000,	/* PORT_PHY_CTL bits */
	HOST_TIMER1MS = 0xe0,			/* Timer 1-ms */
};

struct imx_ahci_priv {
	struct platform_device *ahci_pdev;
	struct clk *sata_ref_clk;
	struct clk *ahb_clk;
	struct regmap *gpr;
	bool no_device;
	bool first_time;
};

static int ahci_imx_hotplug;
module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");

static void ahci_imx_error_handler(struct ata_port *ap)
{
	u32 reg_val;
	struct ata_device *dev;
	struct ata_host *host = dev_get_drvdata(ap->dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);

	ahci_error_handler(ap);

	if (!(imxpriv->first_time) || ahci_imx_hotplug)
		return;

	imxpriv->first_time = false;

	ata_for_each_dev(dev, &ap->link, ENABLED)
		return;
	/*
	 * Disable link to save power.  An imx ahci port can't be recovered
	 * without full reset once the pddq mode is enabled making it
	 * impossible to use as part of libata LPM.
	 */
	reg_val = readl(mmio + PORT_PHY_CTL);
	writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
			IMX6Q_GPR13_SATA_MPLL_CLK_EN,
			!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	clk_disable_unprepare(imxpriv->sata_ref_clk);
	imxpriv->no_device = true;
}

static struct ata_port_operations ahci_imx_ops = {
	.inherits	= &ahci_platform_ops,
	.error_handler	= ahci_imx_error_handler,
};

static const struct ata_port_info ahci_imx_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_imx_ops,
};

static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
{
	int ret = 0;
	unsigned int reg_val;
	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);

	imxpriv->gpr =
		syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	if (IS_ERR(imxpriv->gpr)) {
		dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
		return PTR_ERR(imxpriv->gpr);
	}

	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
	if (ret < 0) {
		dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
		return ret;
	}

	/*
	 * set PHY Paremeters, two steps to configure the GPR13,
	 * one write for rest of parameters, mask of first write
	 * is 0x07ffffff, and the other one write for setting
	 * the mpll_clk_en.
	 */
	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
			| IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
			| IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
			| IMX6Q_GPR13_SATA_SPD_MODE_MASK
			| IMX6Q_GPR13_SATA_MPLL_SS_EN
			| IMX6Q_GPR13_SATA_TX_ATTEN_MASK
			| IMX6Q_GPR13_SATA_TX_BOOST_MASK
			| IMX6Q_GPR13_SATA_TX_LVL_MASK
			| IMX6Q_GPR13_SATA_MPLL_CLK_EN
			| IMX6Q_GPR13_SATA_TX_EDGE_RATE
			, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
			| IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
			| IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
			| IMX6Q_GPR13_SATA_SPD_MODE_3P0G
			| IMX6Q_GPR13_SATA_MPLL_SS_EN
			| IMX6Q_GPR13_SATA_TX_ATTEN_9_16
			| IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
			| IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
			IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	usleep_range(100, 200);

	/*
	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	 * and IP vendor specific register HOST_TIMER1MS.
	 * Configure CAP_SSS (support stagered spin up).
	 * Implement the port0.
	 * Get the ahb clock rate, and configure the TIMER1MS register.
	 */
	reg_val = readl(mmio + HOST_CAP);
	if (!(reg_val & HOST_CAP_SSS)) {
		reg_val |= HOST_CAP_SSS;
		writel(reg_val, mmio + HOST_CAP);
	}
	reg_val = readl(mmio + HOST_PORTS_IMPL);
	if (!(reg_val & 0x1)) {
		reg_val |= 0x1;
		writel(reg_val, mmio + HOST_PORTS_IMPL);
	}

	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
	writel(reg_val, mmio + HOST_TIMER1MS);

	return 0;
}

static void imx6q_sata_exit(struct device *dev)
{
	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);

	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
			!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	clk_disable_unprepare(imxpriv->sata_ref_clk);
}

static int imx_ahci_suspend(struct device *dev)
{
	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);

	/*
	 * If no_device is set, The CLKs had been gated off in the
	 * initialization so don't do it again here.
	 */
	if (!imxpriv->no_device) {
		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
		clk_disable_unprepare(imxpriv->sata_ref_clk);
	}

	return 0;
}

static int imx_ahci_resume(struct device *dev)
{
	struct imx_ahci_priv *imxpriv =  dev_get_drvdata(dev->parent);
	int ret;

	if (!imxpriv->no_device) {
		ret = clk_prepare_enable(imxpriv->sata_ref_clk);
		if (ret < 0) {
			dev_err(dev, "pre-enable sata_ref clock err:%d\n", ret);
			return ret;
		}

		regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
				IMX6Q_GPR13_SATA_MPLL_CLK_EN,
				IMX6Q_GPR13_SATA_MPLL_CLK_EN);
		usleep_range(1000, 2000);
	}

	return 0;
}

static struct ahci_platform_data imx6q_sata_pdata = {
	.init = imx6q_sata_init,
	.exit = imx6q_sata_exit,
	.ata_port_info = &ahci_imx_port_info,
	.suspend = imx_ahci_suspend,
	.resume = imx_ahci_resume,
};

static const struct of_device_id imx_ahci_of_match[] = {
	{ .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
	{},
};
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);

static int imx_ahci_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct resource *mem, *irq, res[2];
	const struct of_device_id *of_id;
	const struct ahci_platform_data *pdata = NULL;
	struct imx_ahci_priv *imxpriv;
	struct device *ahci_dev;
	struct platform_device *ahci_pdev;
	int ret;

	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
	if (!imxpriv) {
		dev_err(dev, "can't alloc ahci_host_priv\n");
		return -ENOMEM;
	}

	ahci_pdev = platform_device_alloc("ahci", -1);
	if (!ahci_pdev)
		return -ENODEV;

	ahci_dev = &ahci_pdev->dev;
	ahci_dev->parent = dev;

	imxpriv->no_device = false;
	imxpriv->first_time = true;
	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	if (IS_ERR(imxpriv->ahb_clk)) {
		dev_err(dev, "can't get ahb clock.\n");
		ret = PTR_ERR(imxpriv->ahb_clk);
		goto err_out;
	}

	imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
	if (IS_ERR(imxpriv->sata_ref_clk)) {
		dev_err(dev, "can't get sata_ref clock.\n");
		ret = PTR_ERR(imxpriv->sata_ref_clk);
		goto err_out;
	}

	imxpriv->ahci_pdev = ahci_pdev;
	platform_set_drvdata(pdev, imxpriv);

	of_id = of_match_device(imx_ahci_of_match, dev);
	if (of_id) {
		pdata = of_id->data;
	} else {
		ret = -EINVAL;
		goto err_out;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!mem || !irq) {
		dev_err(dev, "no mmio/irq resource\n");
		ret = -ENOMEM;
		goto err_out;
	}

	res[0] = *mem;
	res[1] = *irq;

	ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
	ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
	ahci_dev->of_node = dev->of_node;

	ret = platform_device_add_resources(ahci_pdev, res, 2);
	if (ret)
		goto err_out;

	ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
	if (ret)
		goto err_out;

	ret = platform_device_add(ahci_pdev);
	if (ret) {
err_out:
		platform_device_put(ahci_pdev);
		return ret;
	}

	return 0;
}

static int imx_ahci_remove(struct platform_device *pdev)
{
	struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
	struct platform_device *ahci_pdev = imxpriv->ahci_pdev;

	platform_device_unregister(ahci_pdev);
	return 0;
}

static struct platform_driver imx_ahci_driver = {
	.probe = imx_ahci_probe,
	.remove = imx_ahci_remove,
	.driver = {
		.name = "ahci-imx",
		.owner = THIS_MODULE,
		.of_match_table = imx_ahci_of_match,
	},
};
module_platform_driver(imx_ahci_driver);

MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("ahci:imx");
Commit	Line	Data
9e54eae2	1	/*
8b789d89	2	* copyright (c) 2013 Freescale Semiconductor, Inc.
9e54eae2	3	* Freescale IMX AHCI SATA platform driver
9e54eae2 RZ	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/regmap.h>
	24	#include <linux/ahci_platform.h>
	25	#include <linux/of_device.h>
	26	#include <linux/mfd/syscon.h>
	27	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
8b789d89	28	#include <linux/libata.h>
9e54eae2 RZ	29	#include "ahci.h"
	30
	31	enum {
8b789d89 RZ	32	PORT_PHY_CTL = 0x178, /* Port0 PHY Control */
	33	PORT_PHY_CTL_PDDQ_LOC = 0x100000, /* PORT_PHY_CTL bits */
	34	HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
9e54eae2 RZ	35	};
	36
	37	struct imx_ahci_priv {
	38	struct platform_device *ahci_pdev;
	39	struct clk *sata_ref_clk;
	40	struct clk *ahb_clk;
	41	struct regmap *gpr;
8b789d89 RZ	42	bool no_device;
	43	bool first_time;
	44	};
	45
	46	static int ahci_imx_hotplug;
	47	module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
	48	MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
	49
	50	static void ahci_imx_error_handler(struct ata_port *ap)
	51	{
	52	u32 reg_val;
	53	struct ata_device *dev;
	54	struct ata_host *host = dev_get_drvdata(ap->dev);
	55	struct ahci_host_priv *hpriv = host->private_data;
	56	void __iomem *mmio = hpriv->mmio;
	57	struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
	58
	59	ahci_error_handler(ap);
	60
	61	if (!(imxpriv->first_time) \|\| ahci_imx_hotplug)
	62	return;
	63
	64	imxpriv->first_time = false;
	65
	66	ata_for_each_dev(dev, &ap->link, ENABLED)
	67	return;
	68	/*
	69	* Disable link to save power. An imx ahci port can't be recovered
	70	* without full reset once the pddq mode is enabled making it
	71	* impossible to use as part of libata LPM.
	72	*/
	73	reg_val = readl(mmio + PORT_PHY_CTL);
	74	writel(reg_val \| PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
	75	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	76	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	77	!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	78	clk_disable_unprepare(imxpriv->sata_ref_clk);
	79	imxpriv->no_device = true;
	80	}
	81
	82	static struct ata_port_operations ahci_imx_ops = {
	83	.inherits = &ahci_platform_ops,
	84	.error_handler = ahci_imx_error_handler,
	85	};
	86
	87	static const struct ata_port_info ahci_imx_port_info = {
	88	.flags = AHCI_FLAG_COMMON,
	89	.pio_mask = ATA_PIO4,
	90	.udma_mask = ATA_UDMA6,
	91	.port_ops = &ahci_imx_ops,
9e54eae2 RZ	92	};
	93
	94	static int imx6q_sata_init(struct device dev, void __iomem mmio)
	95	{
	96	int ret = 0;
	97	unsigned int reg_val;
	98	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
	99
	100	imxpriv->gpr =
	101	syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
	102	if (IS_ERR(imxpriv->gpr)) {
	103	dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
	104	return PTR_ERR(imxpriv->gpr);
	105	}
	106
	107	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
	108	if (ret < 0) {
	109	dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
	110	return ret;
	111	}
	112
	113	/*
	114	* set PHY Paremeters, two steps to configure the GPR13,
	115	* one write for rest of parameters, mask of first write
10becdb4	116	* is 0x07ffffff, and the other one write for setting
9e54eae2 RZ	117	* the mpll_clk_en.
	118	*/
	119	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
	120	\| IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
	121	\| IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
	122	\| IMX6Q_GPR13_SATA_SPD_MODE_MASK
	123	\| IMX6Q_GPR13_SATA_MPLL_SS_EN
	124	\| IMX6Q_GPR13_SATA_TX_ATTEN_MASK
	125	\| IMX6Q_GPR13_SATA_TX_BOOST_MASK
	126	\| IMX6Q_GPR13_SATA_TX_LVL_MASK
10becdb4	127	\| IMX6Q_GPR13_SATA_MPLL_CLK_EN
9e54eae2 RZ	128	\| IMX6Q_GPR13_SATA_TX_EDGE_RATE
	129	, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
	130	\| IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
	131	\| IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
	132	\| IMX6Q_GPR13_SATA_SPD_MODE_3P0G
	133	\| IMX6Q_GPR13_SATA_MPLL_SS_EN
	134	\| IMX6Q_GPR13_SATA_TX_ATTEN_9_16
	135	\| IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
	136	\| IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
	137	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	138	IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	139	usleep_range(100, 200);
	140
	141	/*
	142	* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
	143	* and IP vendor specific register HOST_TIMER1MS.
	144	* Configure CAP_SSS (support stagered spin up).
	145	* Implement the port0.
	146	* Get the ahb clock rate, and configure the TIMER1MS register.
	147	*/
	148	reg_val = readl(mmio + HOST_CAP);
	149	if (!(reg_val & HOST_CAP_SSS)) {
	150	reg_val \|= HOST_CAP_SSS;
	151	writel(reg_val, mmio + HOST_CAP);
	152	}
	153	reg_val = readl(mmio + HOST_PORTS_IMPL);
	154	if (!(reg_val & 0x1)) {
	155	reg_val \|= 0x1;
	156	writel(reg_val, mmio + HOST_PORTS_IMPL);
	157	}
	158
	159	reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
	160	writel(reg_val, mmio + HOST_TIMER1MS);
	161
	162	return 0;
	163	}
	164
	165	static void imx6q_sata_exit(struct device *dev)
	166	{
	167	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
	168
	169	regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	170	!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	171	clk_disable_unprepare(imxpriv->sata_ref_clk);
	172	}
	173
8b789d89 RZ	174	static int imx_ahci_suspend(struct device *dev)
	175	{
	176	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
	177
	178	/*
	179	* If no_device is set, The CLKs had been gated off in the
	180	* initialization so don't do it again here.
	181	*/
	182	if (!imxpriv->no_device) {
	183	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	184	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	185	!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	186	clk_disable_unprepare(imxpriv->sata_ref_clk);
	187	}
	188
	189	return 0;
	190	}
	191
	192	static int imx_ahci_resume(struct device *dev)
	193	{
	194	struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
	195	int ret;
	196
	197	if (!imxpriv->no_device) {
	198	ret = clk_prepare_enable(imxpriv->sata_ref_clk);
	199	if (ret < 0) {
	200	dev_err(dev, "pre-enable sata_ref clock err:%d\n", ret);
	201	return ret;
	202	}
	203
	204	regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
	205	IMX6Q_GPR13_SATA_MPLL_CLK_EN,
	206	IMX6Q_GPR13_SATA_MPLL_CLK_EN);
	207	usleep_range(1000, 2000);
	208	}
	209
	210	return 0;
	211	}
	212
9e54eae2 RZ	213	static struct ahci_platform_data imx6q_sata_pdata = {
	214	.init = imx6q_sata_init,
	215	.exit = imx6q_sata_exit,
8b789d89 RZ	216	.ata_port_info = &ahci_imx_port_info,
	217	.suspend = imx_ahci_suspend,
	218	.resume = imx_ahci_resume,
9e54eae2 RZ	219	};
	220
	221	static const struct of_device_id imx_ahci_of_match[] = {
	222	{ .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
	223	{},
	224	};
	225	MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
	226
	227	static int imx_ahci_probe(struct platform_device *pdev)
	228	{
	229	struct device *dev = &pdev->dev;
	230	struct resource mem, irq, res[2];
	231	const struct of_device_id *of_id;
	232	const struct ahci_platform_data *pdata = NULL;
	233	struct imx_ahci_priv *imxpriv;
	234	struct device *ahci_dev;
	235	struct platform_device *ahci_pdev;
	236	int ret;
	237
	238	imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
	239	if (!imxpriv) {
	240	dev_err(dev, "can't alloc ahci_host_priv\n");
	241	return -ENOMEM;
	242	}
	243
	244	ahci_pdev = platform_device_alloc("ahci", -1);
	245	if (!ahci_pdev)
	246	return -ENODEV;
	247
	248	ahci_dev = &ahci_pdev->dev;
	249	ahci_dev->parent = dev;
	250
8b789d89 RZ	251	imxpriv->no_device = false;
8b789d89 RZ	252	imxpriv->first_time = true;
9e54eae2 RZ	253	imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
	254	if (IS_ERR(imxpriv->ahb_clk)) {
	255	dev_err(dev, "can't get ahb clock.\n");
	256	ret = PTR_ERR(imxpriv->ahb_clk);
	257	goto err_out;
	258	}
	259
	260	imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
	261	if (IS_ERR(imxpriv->sata_ref_clk)) {
	262	dev_err(dev, "can't get sata_ref clock.\n");
	263	ret = PTR_ERR(imxpriv->sata_ref_clk);
	264	goto err_out;
	265	}
	266
	267	imxpriv->ahci_pdev = ahci_pdev;
	268	platform_set_drvdata(pdev, imxpriv);
	269
	270	of_id = of_match_device(imx_ahci_of_match, dev);
	271	if (of_id) {
	272	pdata = of_id->data;
	273	} else {
	274	ret = -EINVAL;
	275	goto err_out;
	276	}
	277
	278	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	279	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	280	if (!mem \|\| !irq) {
	281	dev_err(dev, "no mmio/irq resource\n");
	282	ret = -ENOMEM;
	283	goto err_out;
	284	}
	285
	286	res[0] = *mem;
	287	res[1] = *irq;
	288
	289	ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
	290	ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
	291	ahci_dev->of_node = dev->of_node;
	292
	293	ret = platform_device_add_resources(ahci_pdev, res, 2);
	294	if (ret)
	295	goto err_out;
	296
	297	ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
	298	if (ret)
	299	goto err_out;
	300
	301	ret = platform_device_add(ahci_pdev);
	302	if (ret) {
	303	err_out:
	304	platform_device_put(ahci_pdev);
	305	return ret;
	306	}
	307
	308	return 0;
	309	}
	310
	311	static int imx_ahci_remove(struct platform_device *pdev)
	312	{
	313	struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
	314	struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
	315
	316	platform_device_unregister(ahci_pdev);
317	return 0;
318	}
319
320	static struct platform_driver imx_ahci_driver = {
321	.probe = imx_ahci_probe,
322	.remove = imx_ahci_remove,
323	.driver = {
324	.name = "ahci-imx",
325	.owner = THIS_MODULE,
326	.of_match_table = imx_ahci_of_match,
327	},
328	};
329	module_platform_driver(imx_ahci_driver);
330
331	MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
332	MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
333	MODULE_LICENSE("GPL");
334	MODULE_ALIAS("ahci:imx");