[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci_mvebu.c

/*
 * AHCI glue platform driver for Marvell EBU SOCs
 *
 * Copyright (C) 2014 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Marcin Wojtas <mw@semihalf.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/ahci_platform.h>
#include <linux/kernel.h>
#include <linux/mbus.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "ahci.h"

#define DRV_NAME "ahci-mvebu"

#define AHCI_VENDOR_SPECIFIC_0_ADDR  0xa0
#define AHCI_VENDOR_SPECIFIC_0_DATA  0xa4

#define AHCI_WINDOW_CTRL(win)	(0x60 + ((win) << 4))
#define AHCI_WINDOW_BASE(win)	(0x64 + ((win) << 4))
#define AHCI_WINDOW_SIZE(win)	(0x68 + ((win) << 4))

struct ahci_mvebu_plat_data {
	int (*plat_config)(struct ahci_host_priv *hpriv);
};

static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv,
				   const struct mbus_dram_target_info *dram)
{
	int i;

	for (i = 0; i < 4; i++) {
		writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i));
		writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i));
		writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i));
	}

	for (i = 0; i < dram->num_cs; i++) {
		const struct mbus_dram_window *cs = dram->cs + i;

		writel((cs->mbus_attr << 8) |
		       (dram->mbus_dram_target_id << 4) | 1,
		       hpriv->mmio + AHCI_WINDOW_CTRL(i));
		writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i));
		writel(((cs->size - 1) & 0xffff0000),
		       hpriv->mmio + AHCI_WINDOW_SIZE(i));
	}
}

static void ahci_mvebu_regret_option(struct ahci_host_priv *hpriv)
{
	/*
	 * Enable the regret bit to allow the SATA unit to regret a
	 * request that didn't receive an acknowlegde and avoid a
	 * deadlock
	 */
	writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
	writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
}

static int ahci_mvebu_armada_380_config(struct ahci_host_priv *hpriv)
{
	const struct mbus_dram_target_info *dram;
	int rc = 0;

	dram = mv_mbus_dram_info();
	if (dram)
		ahci_mvebu_mbus_config(hpriv, dram);
	else
		rc = -ENODEV;

	ahci_mvebu_regret_option(hpriv);

	return rc;
}

/**
 * ahci_mvebu_stop_engine
 *
 * @ap:	Target ata port
 *
 * Errata Ref#226 - SATA Disk HOT swap issue when connected through
 * Port Multiplier in FIS-based Switching mode.
 *
 * To avoid the issue, according to design, the bits[11:8, 0] of
 * register PxFBS are cleared when Port Command and Status (0x18) bit[0]
 * changes its value from 1 to 0, i.e. falling edge of Port
 * Command and Status bit[0] sends PULSE that resets PxFBS
 * bits[11:8; 0].
 *
 * This function is used to override function of "ahci_stop_engine"
 * from libahci.c by adding the mvebu work around(WA) to save PxFBS
 * value before the PxCMD ST write of 0, then restore PxFBS value.
 *
 * Return: 0 on success; Error code otherwise.
 */
int ahci_mvebu_stop_engine(struct ata_port *ap)
{
	void __iomem *port_mmio = ahci_port_base(ap);
	u32 tmp, port_fbs;

	tmp = readl(port_mmio + PORT_CMD);

	/* check if the HBA is idle */
	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
		return 0;

	/* save the port PxFBS register for later restore */
	port_fbs = readl(port_mmio + PORT_FBS);

	/* setting HBA to idle */
	tmp &= ~PORT_CMD_START;
	writel(tmp, port_mmio + PORT_CMD);

	/*
	 * bit #15 PxCMD signal doesn't clear PxFBS,
	 * restore the PxFBS register right after clearing the PxCMD ST,
	 * no need to wait for the PxCMD bit #15.
	 */
	writel(port_fbs, port_mmio + PORT_FBS);

	/* wait for engine to stop. This could be as long as 500 msec */
	tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
	if (tmp & PORT_CMD_LIST_ON)
		return -EIO;

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_mvebu_suspend(struct platform_device *pdev, pm_message_t state)
{
	return ahci_platform_suspend_host(&pdev->dev);
}

static int ahci_mvebu_resume(struct platform_device *pdev)
{
	struct ata_host *host = platform_get_drvdata(pdev);
	struct ahci_host_priv *hpriv = host->private_data;
	const struct ahci_mvebu_plat_data *pdata = hpriv->plat_data;

	if (pdata->plat_config)
		pdata->plat_config(hpriv);

	return ahci_platform_resume_host(&pdev->dev);
}
#else
#define ahci_mvebu_suspend NULL
#define ahci_mvebu_resume NULL
#endif

static const struct ata_port_info ahci_mvebu_port_info = {
	.flags	   = AHCI_FLAG_COMMON,
	.pio_mask  = ATA_PIO4,
	.udma_mask = ATA_UDMA6,
	.port_ops  = &ahci_platform_ops,
};

static struct scsi_host_template ahci_platform_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_mvebu_probe(struct platform_device *pdev)
{
	const struct ahci_mvebu_plat_data *pdata;
	struct ahci_host_priv *hpriv;
	int rc;

	pdata = of_device_get_match_data(&pdev->dev);
	if (!pdata)
		return -EINVAL;

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	hpriv->plat_data = (void *)pdata;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	hpriv->stop_engine = ahci_mvebu_stop_engine;

	pdata = hpriv->plat_data;
	if (pdata->plat_config) {
		rc = pdata->plat_config(hpriv);
		if (rc)
			goto disable_resources;
	}

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info,
				     &ahci_platform_sht);
	if (rc)
		goto disable_resources;

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);
	return rc;
}

static const struct ahci_mvebu_plat_data ahci_mvebu_armada_380_plat_data = {
	.plat_config = ahci_mvebu_armada_380_config,
};

static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = {
	.plat_config = NULL,
};

static const struct of_device_id ahci_mvebu_of_match[] = {
	{
		.compatible = "marvell,armada-380-ahci",
		.data = &ahci_mvebu_armada_380_plat_data,
	},
	{
		.compatible = "marvell,armada-3700-ahci",
		.data = &ahci_mvebu_armada_3700_plat_data,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);

/*
 * We currently don't provide power management related operations,
 * since there is no suspend/resume support at the platform level for
 * Armada 38x for the moment.
 */
static struct platform_driver ahci_mvebu_driver = {
	.probe = ahci_mvebu_probe,
	.remove = ata_platform_remove_one,
	.suspend = ahci_mvebu_suspend,
	.resume = ahci_mvebu_resume,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_mvebu_of_match,
	},
};
module_platform_driver(ahci_mvebu_driver);

MODULE_DESCRIPTION("Marvell EBU AHCI SATA driver");
MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Marcin Wojtas <mw@semihalf.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:ahci_mvebu");
Commit	Line	Data
a3464ed2 TP	1	/*
	2	* AHCI glue platform driver for Marvell EBU SOCs
	3	*
	4	* Copyright (C) 2014 Marvell
	5	*
	6	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	7	* Marcin Wojtas <mw@semihalf.com>
	8	*
	9	* This file is licensed under the terms of the GNU General Public
	10	* License version 2. This program is licensed "as is" without any
	11	* warranty of any kind, whether express or implied.
	12	*/
	13
	14	#include <linux/ahci_platform.h>
	15	#include <linux/kernel.h>
	16	#include <linux/mbus.h>
	17	#include <linux/module.h>
	18	#include <linux/of_device.h>
	19	#include <linux/platform_device.h>
	20	#include "ahci.h"
	21
018d5ef2 AM	22	#define DRV_NAME "ahci-mvebu"
018d5ef2 AM	23
a3464ed2 TP	24	#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
	25	#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
	26
	27	#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
	28	#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
	29	#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
	30
02c9789a MR	31	struct ahci_mvebu_plat_data {
	32	int (plat_config)(struct ahci_host_priv hpriv);
	33	};
	34
a3464ed2 TP	35	static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv,
	36	const struct mbus_dram_target_info *dram)
	37	{
	38	int i;
	39
	40	for (i = 0; i < 4; i++) {
	41	writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i));
	42	writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i));
	43	writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i));
	44	}
	45
	46	for (i = 0; i < dram->num_cs; i++) {
	47	const struct mbus_dram_window *cs = dram->cs + i;
	48
	49	writel((cs->mbus_attr << 8) \|
	50	(dram->mbus_dram_target_id << 4) \| 1,
	51	hpriv->mmio + AHCI_WINDOW_CTRL(i));
e96998fc	52	writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i));
a3464ed2 TP	53	writel(((cs->size - 1) & 0xffff0000),
	54	hpriv->mmio + AHCI_WINDOW_SIZE(i));
	55	}
	56	}
	57
	58	static void ahci_mvebu_regret_option(struct ahci_host_priv *hpriv)
	59	{
	60	/*
	61	* Enable the regret bit to allow the SATA unit to regret a
	62	* request that didn't receive an acknowlegde and avoid a
	63	* deadlock
	64	*/
	65	writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
	66	writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
	67	}
	68
02c9789a MR	69	static int ahci_mvebu_armada_380_config(struct ahci_host_priv *hpriv)
	70	{
	71	const struct mbus_dram_target_info *dram;
	72	int rc = 0;
	73
	74	dram = mv_mbus_dram_info();
	75	if (dram)
	76	ahci_mvebu_mbus_config(hpriv, dram);
	77	else
	78	rc = -ENODEV;
	79
	80	ahci_mvebu_regret_option(hpriv);
	81
	82	return rc;
	83	}
	84
2429b8b3 EW	85	/**
	86	* ahci_mvebu_stop_engine
	87	*
	88	* @ap: Target ata port
	89	*
	90	* Errata Ref#226 - SATA Disk HOT swap issue when connected through
	91	* Port Multiplier in FIS-based Switching mode.
	92	*
	93	* To avoid the issue, according to design, the bits[11:8, 0] of
	94	* register PxFBS are cleared when Port Command and Status (0x18) bit[0]
	95	* changes its value from 1 to 0, i.e. falling edge of Port
	96	* Command and Status bit[0] sends PULSE that resets PxFBS
	97	* bits[11:8; 0].
	98	*
	99	* This function is used to override function of "ahci_stop_engine"
	100	* from libahci.c by adding the mvebu work around(WA) to save PxFBS
	101	* value before the PxCMD ST write of 0, then restore PxFBS value.
	102	*
	103	* Return: 0 on success; Error code otherwise.
	104	*/
	105	int ahci_mvebu_stop_engine(struct ata_port *ap)
	106	{
	107	void __iomem *port_mmio = ahci_port_base(ap);
	108	u32 tmp, port_fbs;
	109
	110	tmp = readl(port_mmio + PORT_CMD);
	111
	112	/* check if the HBA is idle */
	113	if ((tmp & (PORT_CMD_START \| PORT_CMD_LIST_ON)) == 0)
	114	return 0;
	115
	116	/* save the port PxFBS register for later restore */
	117	port_fbs = readl(port_mmio + PORT_FBS);
	118
	119	/* setting HBA to idle */
	120	tmp &= ~PORT_CMD_START;
	121	writel(tmp, port_mmio + PORT_CMD);
	122
	123	/*
	124	* bit #15 PxCMD signal doesn't clear PxFBS,
	125	* restore the PxFBS register right after clearing the PxCMD ST,
	126	* no need to wait for the PxCMD bit #15.
	127	*/
	128	writel(port_fbs, port_mmio + PORT_FBS);
	129
	130	/* wait for engine to stop. This could be as long as 500 msec */
	131	tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
	132	PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
	133	if (tmp & PORT_CMD_LIST_ON)
	134	return -EIO;
	135
	136	return 0;
	137	}
	138
4f1dd973	139	#ifdef CONFIG_PM_SLEEP
d6ecf158 TP	140	static int ahci_mvebu_suspend(struct platform_device *pdev, pm_message_t state)
	141	{
	142	return ahci_platform_suspend_host(&pdev->dev);
	143	}
	144
	145	static int ahci_mvebu_resume(struct platform_device *pdev)
	146	{
	147	struct ata_host *host = platform_get_drvdata(pdev);
	148	struct ahci_host_priv *hpriv = host->private_data;
02c9789a	149	const struct ahci_mvebu_plat_data *pdata = hpriv->plat_data;
d6ecf158	150
02c9789a MR	151	if (pdata->plat_config)
02c9789a MR	152	pdata->plat_config(hpriv);
d6ecf158 TP	153
	154	return ahci_platform_resume_host(&pdev->dev);
	155	}
4f1dd973 AB	156	#else
	157	#define ahci_mvebu_suspend NULL
	158	#define ahci_mvebu_resume NULL
	159	#endif
d6ecf158	160
a3464ed2 TP	161	static const struct ata_port_info ahci_mvebu_port_info = {
	162	.flags = AHCI_FLAG_COMMON,
	163	.pio_mask = ATA_PIO4,
	164	.udma_mask = ATA_UDMA6,
	165	.port_ops = &ahci_platform_ops,
	166	};
	167
018d5ef2 AM	168	static struct scsi_host_template ahci_platform_sht = {
	169	AHCI_SHT(DRV_NAME),
	170	};
	171
a3464ed2 TP	172	static int ahci_mvebu_probe(struct platform_device *pdev)
a3464ed2 TP	173	{
02c9789a	174	const struct ahci_mvebu_plat_data *pdata;
a3464ed2	175	struct ahci_host_priv *hpriv;
a3464ed2 TP	176	int rc;
a3464ed2 TP	177
02c9789a MR	178	pdata = of_device_get_match_data(&pdev->dev);
	179	if (!pdata)
	180	return -EINVAL;
	181
a3464ed2 TP	182	hpriv = ahci_platform_get_resources(pdev);
	183	if (IS_ERR(hpriv))
	184	return PTR_ERR(hpriv);
	185
02c9789a MR	186	hpriv->plat_data = (void *)pdata;
02c9789a MR	187
a3464ed2 TP	188	rc = ahci_platform_enable_resources(hpriv);
	189	if (rc)
	190	return rc;
	191
2429b8b3 EW	192	hpriv->stop_engine = ahci_mvebu_stop_engine;
2429b8b3 EW	193
02c9789a MR	194	pdata = hpriv->plat_data;
	195	if (pdata->plat_config) {
	196	rc = pdata->plat_config(hpriv);
	197	if (rc)
	198	goto disable_resources;
15d3ce7b	199	}
a3464ed2	200
018d5ef2 AM	201	rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info,
018d5ef2 AM	202	&ahci_platform_sht);
a3464ed2 TP	203	if (rc)
	204	goto disable_resources;
	205
	206	return 0;
	207
	208	disable_resources:
	209	ahci_platform_disable_resources(hpriv);
	210	return rc;
	211	}
	212
02c9789a MR	213	static const struct ahci_mvebu_plat_data ahci_mvebu_armada_380_plat_data = {
	214	.plat_config = ahci_mvebu_armada_380_config,
	215	};
	216
	217	static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = {
	218	.plat_config = NULL,
	219	};
	220
a3464ed2	221	static const struct of_device_id ahci_mvebu_of_match[] = {
02c9789a MR	222	{
	223	.compatible = "marvell,armada-380-ahci",
	224	.data = &ahci_mvebu_armada_380_plat_data,
	225	},
	226	{
	227	.compatible = "marvell,armada-3700-ahci",
	228	.data = &ahci_mvebu_armada_3700_plat_data,
	229	},
a3464ed2 TP	230	{ },
	231	};
	232	MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
	233
	234	/*
	235	* We currently don't provide power management related operations,
	236	* since there is no suspend/resume support at the platform level for
	237	* Armada 38x for the moment.
	238	*/
	239	static struct platform_driver ahci_mvebu_driver = {
	240	.probe = ahci_mvebu_probe,
	241	.remove = ata_platform_remove_one,
d6ecf158 TP	242	.suspend = ahci_mvebu_suspend,
d6ecf158 TP	243	.resume = ahci_mvebu_resume,
a3464ed2	244	.driver = {
018d5ef2	245	.name = DRV_NAME,
a3464ed2 TP	246	.of_match_table = ahci_mvebu_of_match,
	247	},
	248	};
	249	module_platform_driver(ahci_mvebu_driver);
	250
	251	MODULE_DESCRIPTION("Marvell EBU AHCI SATA driver");
	252	MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Marcin Wojtas <mw@semihalf.com>");
	253	MODULE_LICENSE("GPL");
	254	MODULE_ALIAS("platform:ahci_mvebu");