[mirror_ubuntu-bionic-kernel.git] / drivers / ata / ahci_qoriq.c

/*
 * Freescale QorIQ AHCI SATA platform driver
 *
 * Copyright 2015 Freescale, Inc.
 *   Tang Yuantian <Yuantian.Tang@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pm.h>
#include <linux/ahci_platform.h>
#include <linux/device.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include "ahci.h"

#define DRV_NAME "ahci-qoriq"

/* port register definition */
#define PORT_PHY1	0xA8
#define PORT_PHY2	0xAC
#define PORT_PHY3	0xB0
#define PORT_PHY4	0xB4
#define PORT_PHY5	0xB8
#define PORT_AXICC	0xBC
#define PORT_TRANS	0xC8

/* port register default value */
#define AHCI_PORT_PHY_1_CFG	0xa003fffe
#define AHCI_PORT_TRANS_CFG	0x08000029
#define AHCI_PORT_AXICC_CFG	0x3fffffff

/* for ls1021a */
#define LS1021A_PORT_PHY2	0x28183414
#define LS1021A_PORT_PHY3	0x0e080e06
#define LS1021A_PORT_PHY4	0x064a080b
#define LS1021A_PORT_PHY5	0x2aa86470
#define LS1021A_AXICC_ADDR	0xC0

#define SATA_ECC_DISABLE	0x00020000
#define ECC_DIS_ARMV8_CH2	0x80000000

enum ahci_qoriq_type {
	AHCI_LS1021A,
	AHCI_LS1043A,
	AHCI_LS2080A,
	AHCI_LS1046A,
};

struct ahci_qoriq_priv {
	struct ccsr_ahci *reg_base;
	enum ahci_qoriq_type type;
	void __iomem *ecc_addr;
	bool is_dmacoherent;
};

static const struct of_device_id ahci_qoriq_of_match[] = {
	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
	{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);

static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
			  unsigned long deadline)
{
	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	void __iomem *port_mmio = ahci_port_base(link->ap);
	u32 px_cmd, px_is, px_val;
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	int rc;
	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);

	DPRINTK("ENTER\n");

	ahci_stop_engine(ap);

	/*
	 * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	 * A-009042: The device detection initialization sequence
	 * mistakenly resets some registers.
	 *
	 * Workaround for this is:
	 * The software should read and store PxCMD and PxIS values
	 * before issuing the device detection initialization sequence.
	 * After the sequence is complete, software should restore the
	 * PxCMD and PxIS with the stored values.
	 */
	if (ls1021a_workaround) {
		px_cmd = readl(port_mmio + PORT_CMD);
		px_is = readl(port_mmio + PORT_IRQ_STAT);
	}

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	rc = sata_link_hardreset(link, timing, deadline, &online,
				 ahci_check_ready);

	/* restore the PxCMD and PxIS on ls1021 */
	if (ls1021a_workaround) {
		px_val = readl(port_mmio + PORT_CMD);
		if (px_val != px_cmd)
			writel(px_cmd, port_mmio + PORT_CMD);

		px_val = readl(port_mmio + PORT_IRQ_STAT);
		if (px_val != px_is)
			writel(px_is, port_mmio + PORT_IRQ_STAT);
	}

	hpriv->start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);

	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	return rc;
}

static struct ata_port_operations ahci_qoriq_ops = {
	.inherits	= &ahci_ops,
	.hardreset	= ahci_qoriq_hardreset,
};

static const struct ata_port_info ahci_qoriq_port_info = {
	.flags		= AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_qoriq_ops,
};

static struct scsi_host_template ahci_qoriq_sht = {
	AHCI_SHT(DRV_NAME),
};

static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
{
	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	void __iomem *reg_base = hpriv->mmio;

	switch (qpriv->type) {
	case AHCI_LS1021A:
		if (!qpriv->ecc_addr)
			return -EINVAL;
		writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
		writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
		writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
		writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG,
					reg_base + LS1021A_AXICC_ADDR);
		break;

	case AHCI_LS1043A:
		if (!qpriv->ecc_addr)
			return -EINVAL;
		writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS2080A:
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;

	case AHCI_LS1046A:
		if (!qpriv->ecc_addr)
			return -EINVAL;
		writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
		writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
		writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
		if (qpriv->is_dmacoherent)
			writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
		break;
	}

	return 0;
}

static int ahci_qoriq_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ahci_qoriq_priv *qoriq_priv;
	const struct of_device_id *of_id;
	struct resource *res;
	int rc;

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	of_id = of_match_node(ahci_qoriq_of_match, np);
	if (!of_id)
		return -ENODEV;

	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	if (!qoriq_priv)
		return -ENOMEM;

	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
			"sata-ecc");
	if (res) {
		qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
		if (IS_ERR(qoriq_priv->ecc_addr))
			return PTR_ERR(qoriq_priv->ecc_addr);
	}
	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	hpriv->plat_data = qoriq_priv;
	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
				     &ahci_qoriq_sht);
	if (rc)
		goto disable_resources;

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_qoriq_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	int rc;

	rc = ahci_platform_enable_resources(hpriv);
	if (rc)
		return rc;

	rc = ahci_qoriq_phy_init(hpriv);
	if (rc)
		goto disable_resources;

	rc = ahci_platform_resume_host(dev);
	if (rc)
		goto disable_resources;

	/* We resumed so update PM runtime state */
	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);

	return 0;

disable_resources:
	ahci_platform_disable_resources(hpriv);

	return rc;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
			 ahci_qoriq_resume);

static struct platform_driver ahci_qoriq_driver = {
	.probe = ahci_qoriq_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = ahci_qoriq_of_match,
		.pm = &ahci_qoriq_pm_ops,
	},
};
module_platform_driver(ahci_qoriq_driver);

MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
ecfb4598 TY	1	/*
	2	* Freescale QorIQ AHCI SATA platform driver
	3	*
	4	* Copyright 2015 Freescale, Inc.
	5	* Tang Yuantian <Yuantian.Tang@freescale.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2, or (at your option)
	10	* any later version.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/module.h>
	15	#include <linux/pm.h>
	16	#include <linux/ahci_platform.h>
	17	#include <linux/device.h>
	18	#include <linux/of_address.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/libata.h>
	23	#include "ahci.h"
	24
	25	#define DRV_NAME "ahci-qoriq"
	26
	27	/* port register definition */
	28	#define PORT_PHY1 0xA8
	29	#define PORT_PHY2 0xAC
	30	#define PORT_PHY3 0xB0
	31	#define PORT_PHY4 0xB4
	32	#define PORT_PHY5 0xB8
16af080e	33	#define PORT_AXICC 0xBC
ecfb4598 TY	34	#define PORT_TRANS 0xC8
	35
	36	/* port register default value */
	37	#define AHCI_PORT_PHY_1_CFG 0xa003fffe
e3a6dadc	38	#define AHCI_PORT_TRANS_CFG 0x08000029
16af080e	39	#define AHCI_PORT_AXICC_CFG 0x3fffffff
dfcdc5fe TY	40
	41	/* for ls1021a */
	42	#define LS1021A_PORT_PHY2 0x28183414
	43	#define LS1021A_PORT_PHY3 0x0e080e06
	44	#define LS1021A_PORT_PHY4 0x064a080b
	45	#define LS1021A_PORT_PHY5 0x2aa86470
16af080e	46	#define LS1021A_AXICC_ADDR 0xC0
ecfb4598 TY	47
ecfb4598 TY	48	#define SATA_ECC_DISABLE 0x00020000
01f2901a	49	#define ECC_DIS_ARMV8_CH2 0x80000000
ecfb4598 TY	50
	51	enum ahci_qoriq_type {
	52	AHCI_LS1021A,
	53	AHCI_LS1043A,
d19f9aaf	54	AHCI_LS2080A,
2facc6da	55	AHCI_LS1046A,
ecfb4598 TY	56	};
	57
	58	struct ahci_qoriq_priv {
	59	struct ccsr_ahci *reg_base;
	60	enum ahci_qoriq_type type;
	61	void __iomem *ecc_addr;
386dc3b8	62	bool is_dmacoherent;
ecfb4598 TY	63	};
	64
	65	static const struct of_device_id ahci_qoriq_of_match[] = {
	66	{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
	67	{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
d19f9aaf	68	{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
2facc6da	69	{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
ecfb4598 TY	70	{},
	71	};
	72	MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
	73
	74	static int ahci_qoriq_hardreset(struct ata_link link, unsigned int class,
	75	unsigned long deadline)
	76	{
	77	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
	78	void __iomem *port_mmio = ahci_port_base(link->ap);
	79	u32 px_cmd, px_is, px_val;
	80	struct ata_port *ap = link->ap;
	81	struct ahci_port_priv *pp = ap->private_data;
	82	struct ahci_host_priv *hpriv = ap->host->private_data;
	83	struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
	84	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	85	struct ata_taskfile tf;
	86	bool online;
	87	int rc;
eb351031	88	bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
ecfb4598 TY	89
	90	DPRINTK("ENTER\n");
	91
	92	ahci_stop_engine(ap);
	93
	94	/*
	95	* There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
	96	* A-009042: The device detection initialization sequence
	97	* mistakenly resets some registers.
	98	*
	99	* Workaround for this is:
	100	* The software should read and store PxCMD and PxIS values
	101	* before issuing the device detection initialization sequence.
	102	* After the sequence is complete, software should restore the
	103	* PxCMD and PxIS with the stored values.
	104	*/
eb351031	105	if (ls1021a_workaround) {
ecfb4598 TY	106	px_cmd = readl(port_mmio + PORT_CMD);
	107	px_is = readl(port_mmio + PORT_IRQ_STAT);
	108	}
	109
	110	/* clear D2H reception area to properly wait for D2H FIS */
	111	ata_tf_init(link->device, &tf);
	112	tf.command = ATA_BUSY;
	113	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	114
	115	rc = sata_link_hardreset(link, timing, deadline, &online,
	116	ahci_check_ready);
	117
	118	/* restore the PxCMD and PxIS on ls1021 */
eb351031	119	if (ls1021a_workaround) {
ecfb4598 TY	120	px_val = readl(port_mmio + PORT_CMD);
	121	if (px_val != px_cmd)
	122	writel(px_cmd, port_mmio + PORT_CMD);
	123
	124	px_val = readl(port_mmio + PORT_IRQ_STAT);
	125	if (px_val != px_is)
	126	writel(px_is, port_mmio + PORT_IRQ_STAT);
	127	}
	128
	129	hpriv->start_engine(ap);
	130
	131	if (online)
	132	*class = ahci_dev_classify(ap);
	133
	134	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
	135	return rc;
	136	}
	137
	138	static struct ata_port_operations ahci_qoriq_ops = {
	139	.inherits = &ahci_ops,
	140	.hardreset = ahci_qoriq_hardreset,
	141	};
	142
1ce788d2	143	static const struct ata_port_info ahci_qoriq_port_info = {
ecfb4598 TY	144	.flags = AHCI_FLAG_COMMON \| ATA_FLAG_NCQ,
	145	.pio_mask = ATA_PIO4,
	146	.udma_mask = ATA_UDMA6,
	147	.port_ops = &ahci_qoriq_ops,
	148	};
	149
	150	static struct scsi_host_template ahci_qoriq_sht = {
	151	AHCI_SHT(DRV_NAME),
	152	};
	153
	154	static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
	155	{
	156	struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
	157	void __iomem *reg_base = hpriv->mmio;
	158
	159	switch (qpriv->type) {
	160	case AHCI_LS1021A:
01f2901a TY	161	if (!qpriv->ecc_addr)
01f2901a TY	162	return -EINVAL;
ecfb4598 TY	163	writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
ecfb4598 TY	164	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
dfcdc5fe TY	165	writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
	166	writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
	167	writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
	168	writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
ecfb4598	169	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	170	if (qpriv->is_dmacoherent)
	171	writel(AHCI_PORT_AXICC_CFG,
	172	reg_base + LS1021A_AXICC_ADDR);
ecfb4598 TY	173	break;
	174
	175	case AHCI_LS1043A:
01f2901a TY	176	if (!qpriv->ecc_addr)
	177	return -EINVAL;
	178	writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
ef0cc7fe	179	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
ef0cc7fe	180	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	181	if (qpriv->is_dmacoherent)
386dc3b8 TY	182	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ef0cc7fe TY	183	break;
ef0cc7fe TY	184
d19f9aaf	185	case AHCI_LS2080A:
ecfb4598	186	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
e3a6dadc	187	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	188	if (qpriv->is_dmacoherent)
386dc3b8 TY	189	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
ecfb4598	190	break;
2facc6da TY	191
2facc6da TY	192	case AHCI_LS1046A:
01f2901a TY	193	if (!qpriv->ecc_addr)
	194	return -EINVAL;
	195	writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
2facc6da TY	196	writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
2facc6da TY	197	writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
386dc3b8 TY	198	if (qpriv->is_dmacoherent)
386dc3b8 TY	199	writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
2facc6da	200	break;
ecfb4598 TY	201	}
	202
	203	return 0;
	204	}
	205
	206	static int ahci_qoriq_probe(struct platform_device *pdev)
	207	{
	208	struct device_node *np = pdev->dev.of_node;
	209	struct device *dev = &pdev->dev;
	210	struct ahci_host_priv *hpriv;
	211	struct ahci_qoriq_priv *qoriq_priv;
	212	const struct of_device_id *of_id;
	213	struct resource *res;
	214	int rc;
	215
	216	hpriv = ahci_platform_get_resources(pdev);
	217	if (IS_ERR(hpriv))
	218	return PTR_ERR(hpriv);
	219
	220	of_id = of_match_node(ahci_qoriq_of_match, np);
	221	if (!of_id)
	222	return -ENODEV;
	223
	224	qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
	225	if (!qoriq_priv)
	226	return -ENOMEM;
	227
	228	qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
	229
2facc6da TY	230	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	231	"sata-ecc");
	232	if (res) {
ecfb4598 TY	233	qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
	234	if (IS_ERR(qoriq_priv->ecc_addr))
	235	return PTR_ERR(qoriq_priv->ecc_addr);
	236	}
386dc3b8	237	qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
ecfb4598 TY	238
	239	rc = ahci_platform_enable_resources(hpriv);
	240	if (rc)
	241	return rc;
	242
	243	hpriv->plat_data = qoriq_priv;
	244	rc = ahci_qoriq_phy_init(hpriv);
	245	if (rc)
	246	goto disable_resources;
	247
	248	rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
	249	&ahci_qoriq_sht);
	250	if (rc)
	251	goto disable_resources;
	252
	253	return 0;
	254
	255	disable_resources:
	256	ahci_platform_disable_resources(hpriv);
	257
	258	return rc;
	259	}
	260
	261	#ifdef CONFIG_PM_SLEEP
	262	static int ahci_qoriq_resume(struct device *dev)
	263	{
	264	struct ata_host *host = dev_get_drvdata(dev);
	265	struct ahci_host_priv *hpriv = host->private_data;
	266	int rc;
	267
	268	rc = ahci_platform_enable_resources(hpriv);
	269	if (rc)
	270	return rc;
	271
	272	rc = ahci_qoriq_phy_init(hpriv);
	273	if (rc)
	274	goto disable_resources;
	275
	276	rc = ahci_platform_resume_host(dev);
	277	if (rc)
	278	goto disable_resources;
	279
	280	/* We resumed so update PM runtime state */
	281	pm_runtime_disable(dev);
	282	pm_runtime_set_active(dev);
	283	pm_runtime_enable(dev);
	284
	285	return 0;
	286
	287	disable_resources:
	288	ahci_platform_disable_resources(hpriv);
	289
	290	return rc;
	291	}
	292	#endif
	293
	294	static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
	295	ahci_qoriq_resume);
	296
	297	static struct platform_driver ahci_qoriq_driver = {
	298	.probe = ahci_qoriq_probe,
	299	.remove = ata_platform_remove_one,
	300	.driver = {
	301	.name = DRV_NAME,
302	.of_match_table = ahci_qoriq_of_match,
303	.pm = &ahci_qoriq_pm_ops,
304	},
305	};
306	module_platform_driver(ahci_qoriq_driver);
307
308	MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
309	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
310	MODULE_LICENSE("GPL");