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ecfb4598 TY |
1 | /* |
2 | * Freescale QorIQ AHCI SATA platform driver | |
3 | * | |
4 | * Copyright 2015 Freescale, Inc. | |
5 | * Tang Yuantian <Yuantian.Tang@freescale.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2, or (at your option) | |
10 | * any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/pm.h> | |
16 | #include <linux/ahci_platform.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/of_address.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/libata.h> | |
23 | #include "ahci.h" | |
24 | ||
25 | #define DRV_NAME "ahci-qoriq" | |
26 | ||
27 | /* port register definition */ | |
28 | #define PORT_PHY1 0xA8 | |
29 | #define PORT_PHY2 0xAC | |
30 | #define PORT_PHY3 0xB0 | |
31 | #define PORT_PHY4 0xB4 | |
32 | #define PORT_PHY5 0xB8 | |
16af080e | 33 | #define PORT_AXICC 0xBC |
ecfb4598 TY |
34 | #define PORT_TRANS 0xC8 |
35 | ||
36 | /* port register default value */ | |
37 | #define AHCI_PORT_PHY_1_CFG 0xa003fffe | |
e3a6dadc | 38 | #define AHCI_PORT_TRANS_CFG 0x08000029 |
16af080e | 39 | #define AHCI_PORT_AXICC_CFG 0x3fffffff |
dfcdc5fe TY |
40 | |
41 | /* for ls1021a */ | |
42 | #define LS1021A_PORT_PHY2 0x28183414 | |
43 | #define LS1021A_PORT_PHY3 0x0e080e06 | |
44 | #define LS1021A_PORT_PHY4 0x064a080b | |
45 | #define LS1021A_PORT_PHY5 0x2aa86470 | |
16af080e | 46 | #define LS1021A_AXICC_ADDR 0xC0 |
ecfb4598 TY |
47 | |
48 | #define SATA_ECC_DISABLE 0x00020000 | |
01f2901a | 49 | #define ECC_DIS_ARMV8_CH2 0x80000000 |
ecfb4598 TY |
50 | |
51 | enum ahci_qoriq_type { | |
52 | AHCI_LS1021A, | |
53 | AHCI_LS1043A, | |
d19f9aaf | 54 | AHCI_LS2080A, |
2facc6da | 55 | AHCI_LS1046A, |
ce8f4537 | 56 | AHCI_LS2088A, |
ecfb4598 TY |
57 | }; |
58 | ||
59 | struct ahci_qoriq_priv { | |
60 | struct ccsr_ahci *reg_base; | |
61 | enum ahci_qoriq_type type; | |
62 | void __iomem *ecc_addr; | |
386dc3b8 | 63 | bool is_dmacoherent; |
ecfb4598 TY |
64 | }; |
65 | ||
66 | static const struct of_device_id ahci_qoriq_of_match[] = { | |
67 | { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A}, | |
68 | { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A}, | |
d19f9aaf | 69 | { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A}, |
2facc6da | 70 | { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A}, |
ce8f4537 | 71 | { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A}, |
ecfb4598 TY |
72 | {}, |
73 | }; | |
74 | MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); | |
75 | ||
76 | static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class, | |
77 | unsigned long deadline) | |
78 | { | |
79 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
80 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
81 | u32 px_cmd, px_is, px_val; | |
82 | struct ata_port *ap = link->ap; | |
83 | struct ahci_port_priv *pp = ap->private_data; | |
84 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
85 | struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data; | |
86 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
87 | struct ata_taskfile tf; | |
88 | bool online; | |
89 | int rc; | |
eb351031 | 90 | bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A); |
ecfb4598 TY |
91 | |
92 | DPRINTK("ENTER\n"); | |
93 | ||
94 | ahci_stop_engine(ap); | |
95 | ||
96 | /* | |
97 | * There is a errata on ls1021a Rev1.0 and Rev2.0 which is: | |
98 | * A-009042: The device detection initialization sequence | |
99 | * mistakenly resets some registers. | |
100 | * | |
101 | * Workaround for this is: | |
102 | * The software should read and store PxCMD and PxIS values | |
103 | * before issuing the device detection initialization sequence. | |
104 | * After the sequence is complete, software should restore the | |
105 | * PxCMD and PxIS with the stored values. | |
106 | */ | |
eb351031 | 107 | if (ls1021a_workaround) { |
ecfb4598 TY |
108 | px_cmd = readl(port_mmio + PORT_CMD); |
109 | px_is = readl(port_mmio + PORT_IRQ_STAT); | |
110 | } | |
111 | ||
112 | /* clear D2H reception area to properly wait for D2H FIS */ | |
113 | ata_tf_init(link->device, &tf); | |
114 | tf.command = ATA_BUSY; | |
115 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
116 | ||
117 | rc = sata_link_hardreset(link, timing, deadline, &online, | |
118 | ahci_check_ready); | |
119 | ||
120 | /* restore the PxCMD and PxIS on ls1021 */ | |
eb351031 | 121 | if (ls1021a_workaround) { |
ecfb4598 TY |
122 | px_val = readl(port_mmio + PORT_CMD); |
123 | if (px_val != px_cmd) | |
124 | writel(px_cmd, port_mmio + PORT_CMD); | |
125 | ||
126 | px_val = readl(port_mmio + PORT_IRQ_STAT); | |
127 | if (px_val != px_is) | |
128 | writel(px_is, port_mmio + PORT_IRQ_STAT); | |
129 | } | |
130 | ||
131 | hpriv->start_engine(ap); | |
132 | ||
133 | if (online) | |
134 | *class = ahci_dev_classify(ap); | |
135 | ||
136 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
137 | return rc; | |
138 | } | |
139 | ||
140 | static struct ata_port_operations ahci_qoriq_ops = { | |
141 | .inherits = &ahci_ops, | |
142 | .hardreset = ahci_qoriq_hardreset, | |
143 | }; | |
144 | ||
1ce788d2 | 145 | static const struct ata_port_info ahci_qoriq_port_info = { |
ecfb4598 TY |
146 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ, |
147 | .pio_mask = ATA_PIO4, | |
148 | .udma_mask = ATA_UDMA6, | |
149 | .port_ops = &ahci_qoriq_ops, | |
150 | }; | |
151 | ||
152 | static struct scsi_host_template ahci_qoriq_sht = { | |
153 | AHCI_SHT(DRV_NAME), | |
154 | }; | |
155 | ||
156 | static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) | |
157 | { | |
158 | struct ahci_qoriq_priv *qpriv = hpriv->plat_data; | |
159 | void __iomem *reg_base = hpriv->mmio; | |
160 | ||
161 | switch (qpriv->type) { | |
162 | case AHCI_LS1021A: | |
01f2901a TY |
163 | if (!qpriv->ecc_addr) |
164 | return -EINVAL; | |
ecfb4598 TY |
165 | writel(SATA_ECC_DISABLE, qpriv->ecc_addr); |
166 | writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); | |
dfcdc5fe TY |
167 | writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2); |
168 | writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3); | |
169 | writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4); | |
170 | writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5); | |
ecfb4598 | 171 | writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); |
386dc3b8 TY |
172 | if (qpriv->is_dmacoherent) |
173 | writel(AHCI_PORT_AXICC_CFG, | |
174 | reg_base + LS1021A_AXICC_ADDR); | |
ecfb4598 TY |
175 | break; |
176 | ||
177 | case AHCI_LS1043A: | |
01f2901a TY |
178 | if (!qpriv->ecc_addr) |
179 | return -EINVAL; | |
6022c5ca YT |
180 | writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, |
181 | qpriv->ecc_addr); | |
ef0cc7fe | 182 | writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); |
ef0cc7fe | 183 | writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); |
386dc3b8 TY |
184 | if (qpriv->is_dmacoherent) |
185 | writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); | |
ef0cc7fe TY |
186 | break; |
187 | ||
d19f9aaf | 188 | case AHCI_LS2080A: |
ecfb4598 | 189 | writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); |
e3a6dadc | 190 | writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); |
386dc3b8 TY |
191 | if (qpriv->is_dmacoherent) |
192 | writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); | |
ecfb4598 | 193 | break; |
2facc6da TY |
194 | |
195 | case AHCI_LS1046A: | |
01f2901a TY |
196 | if (!qpriv->ecc_addr) |
197 | return -EINVAL; | |
6022c5ca YT |
198 | writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, |
199 | qpriv->ecc_addr); | |
2facc6da TY |
200 | writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); |
201 | writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); | |
386dc3b8 TY |
202 | if (qpriv->is_dmacoherent) |
203 | writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); | |
2facc6da | 204 | break; |
ce8f4537 TY |
205 | |
206 | case AHCI_LS2088A: | |
207 | writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); | |
208 | writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); | |
209 | if (qpriv->is_dmacoherent) | |
210 | writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); | |
211 | break; | |
ecfb4598 TY |
212 | } |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | static int ahci_qoriq_probe(struct platform_device *pdev) | |
218 | { | |
219 | struct device_node *np = pdev->dev.of_node; | |
220 | struct device *dev = &pdev->dev; | |
221 | struct ahci_host_priv *hpriv; | |
222 | struct ahci_qoriq_priv *qoriq_priv; | |
223 | const struct of_device_id *of_id; | |
224 | struct resource *res; | |
225 | int rc; | |
226 | ||
227 | hpriv = ahci_platform_get_resources(pdev); | |
228 | if (IS_ERR(hpriv)) | |
229 | return PTR_ERR(hpriv); | |
230 | ||
231 | of_id = of_match_node(ahci_qoriq_of_match, np); | |
232 | if (!of_id) | |
233 | return -ENODEV; | |
234 | ||
235 | qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL); | |
236 | if (!qoriq_priv) | |
237 | return -ENOMEM; | |
238 | ||
239 | qoriq_priv->type = (enum ahci_qoriq_type)of_id->data; | |
240 | ||
2facc6da TY |
241 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
242 | "sata-ecc"); | |
243 | if (res) { | |
ecfb4598 TY |
244 | qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res); |
245 | if (IS_ERR(qoriq_priv->ecc_addr)) | |
246 | return PTR_ERR(qoriq_priv->ecc_addr); | |
247 | } | |
386dc3b8 | 248 | qoriq_priv->is_dmacoherent = of_dma_is_coherent(np); |
ecfb4598 TY |
249 | |
250 | rc = ahci_platform_enable_resources(hpriv); | |
251 | if (rc) | |
252 | return rc; | |
253 | ||
254 | hpriv->plat_data = qoriq_priv; | |
255 | rc = ahci_qoriq_phy_init(hpriv); | |
256 | if (rc) | |
257 | goto disable_resources; | |
258 | ||
259 | rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info, | |
260 | &ahci_qoriq_sht); | |
261 | if (rc) | |
262 | goto disable_resources; | |
263 | ||
264 | return 0; | |
265 | ||
266 | disable_resources: | |
267 | ahci_platform_disable_resources(hpriv); | |
268 | ||
269 | return rc; | |
270 | } | |
271 | ||
272 | #ifdef CONFIG_PM_SLEEP | |
273 | static int ahci_qoriq_resume(struct device *dev) | |
274 | { | |
275 | struct ata_host *host = dev_get_drvdata(dev); | |
276 | struct ahci_host_priv *hpriv = host->private_data; | |
277 | int rc; | |
278 | ||
279 | rc = ahci_platform_enable_resources(hpriv); | |
280 | if (rc) | |
281 | return rc; | |
282 | ||
283 | rc = ahci_qoriq_phy_init(hpriv); | |
284 | if (rc) | |
285 | goto disable_resources; | |
286 | ||
287 | rc = ahci_platform_resume_host(dev); | |
288 | if (rc) | |
289 | goto disable_resources; | |
290 | ||
291 | /* We resumed so update PM runtime state */ | |
292 | pm_runtime_disable(dev); | |
293 | pm_runtime_set_active(dev); | |
294 | pm_runtime_enable(dev); | |
295 | ||
296 | return 0; | |
297 | ||
298 | disable_resources: | |
299 | ahci_platform_disable_resources(hpriv); | |
300 | ||
301 | return rc; | |
302 | } | |
303 | #endif | |
304 | ||
305 | static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend, | |
306 | ahci_qoriq_resume); | |
307 | ||
308 | static struct platform_driver ahci_qoriq_driver = { | |
309 | .probe = ahci_qoriq_probe, | |
310 | .remove = ata_platform_remove_one, | |
311 | .driver = { | |
312 | .name = DRV_NAME, | |
313 | .of_match_table = ahci_qoriq_of_match, | |
314 | .pm = &ahci_qoriq_pm_ops, | |
315 | }, | |
316 | }; | |
317 | module_platform_driver(ahci_qoriq_driver); | |
318 | ||
319 | MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver"); | |
320 | MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>"); | |
321 | MODULE_LICENSE("GPL"); |