]>
Commit | Line | Data |
---|---|---|
ecfb4598 TY |
1 | /* |
2 | * Freescale QorIQ AHCI SATA platform driver | |
3 | * | |
4 | * Copyright 2015 Freescale, Inc. | |
5 | * Tang Yuantian <Yuantian.Tang@freescale.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2, or (at your option) | |
10 | * any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/pm.h> | |
16 | #include <linux/ahci_platform.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/of_address.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/libata.h> | |
23 | #include "ahci.h" | |
24 | ||
25 | #define DRV_NAME "ahci-qoriq" | |
26 | ||
27 | /* port register definition */ | |
28 | #define PORT_PHY1 0xA8 | |
29 | #define PORT_PHY2 0xAC | |
30 | #define PORT_PHY3 0xB0 | |
31 | #define PORT_PHY4 0xB4 | |
32 | #define PORT_PHY5 0xB8 | |
33 | #define PORT_TRANS 0xC8 | |
34 | ||
35 | /* port register default value */ | |
36 | #define AHCI_PORT_PHY_1_CFG 0xa003fffe | |
37 | #define AHCI_PORT_PHY_2_CFG 0x28183411 | |
38 | #define AHCI_PORT_PHY_3_CFG 0x0e081004 | |
39 | #define AHCI_PORT_PHY_4_CFG 0x00480811 | |
40 | #define AHCI_PORT_PHY_5_CFG 0x192c96a4 | |
41 | #define AHCI_PORT_TRANS_CFG 0x08000025 | |
42 | ||
43 | #define SATA_ECC_DISABLE 0x00020000 | |
44 | ||
45 | enum ahci_qoriq_type { | |
46 | AHCI_LS1021A, | |
47 | AHCI_LS1043A, | |
d19f9aaf | 48 | AHCI_LS2080A, |
ecfb4598 TY |
49 | }; |
50 | ||
51 | struct ahci_qoriq_priv { | |
52 | struct ccsr_ahci *reg_base; | |
53 | enum ahci_qoriq_type type; | |
54 | void __iomem *ecc_addr; | |
55 | }; | |
56 | ||
57 | static const struct of_device_id ahci_qoriq_of_match[] = { | |
58 | { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A}, | |
59 | { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A}, | |
d19f9aaf | 60 | { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A}, |
ecfb4598 TY |
61 | {}, |
62 | }; | |
63 | MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match); | |
64 | ||
65 | static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class, | |
66 | unsigned long deadline) | |
67 | { | |
68 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
69 | void __iomem *port_mmio = ahci_port_base(link->ap); | |
70 | u32 px_cmd, px_is, px_val; | |
71 | struct ata_port *ap = link->ap; | |
72 | struct ahci_port_priv *pp = ap->private_data; | |
73 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
74 | struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data; | |
75 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
76 | struct ata_taskfile tf; | |
77 | bool online; | |
78 | int rc; | |
eb351031 | 79 | bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A); |
ecfb4598 TY |
80 | |
81 | DPRINTK("ENTER\n"); | |
82 | ||
83 | ahci_stop_engine(ap); | |
84 | ||
85 | /* | |
86 | * There is a errata on ls1021a Rev1.0 and Rev2.0 which is: | |
87 | * A-009042: The device detection initialization sequence | |
88 | * mistakenly resets some registers. | |
89 | * | |
90 | * Workaround for this is: | |
91 | * The software should read and store PxCMD and PxIS values | |
92 | * before issuing the device detection initialization sequence. | |
93 | * After the sequence is complete, software should restore the | |
94 | * PxCMD and PxIS with the stored values. | |
95 | */ | |
eb351031 | 96 | if (ls1021a_workaround) { |
ecfb4598 TY |
97 | px_cmd = readl(port_mmio + PORT_CMD); |
98 | px_is = readl(port_mmio + PORT_IRQ_STAT); | |
99 | } | |
100 | ||
101 | /* clear D2H reception area to properly wait for D2H FIS */ | |
102 | ata_tf_init(link->device, &tf); | |
103 | tf.command = ATA_BUSY; | |
104 | ata_tf_to_fis(&tf, 0, 0, d2h_fis); | |
105 | ||
106 | rc = sata_link_hardreset(link, timing, deadline, &online, | |
107 | ahci_check_ready); | |
108 | ||
109 | /* restore the PxCMD and PxIS on ls1021 */ | |
eb351031 | 110 | if (ls1021a_workaround) { |
ecfb4598 TY |
111 | px_val = readl(port_mmio + PORT_CMD); |
112 | if (px_val != px_cmd) | |
113 | writel(px_cmd, port_mmio + PORT_CMD); | |
114 | ||
115 | px_val = readl(port_mmio + PORT_IRQ_STAT); | |
116 | if (px_val != px_is) | |
117 | writel(px_is, port_mmio + PORT_IRQ_STAT); | |
118 | } | |
119 | ||
120 | hpriv->start_engine(ap); | |
121 | ||
122 | if (online) | |
123 | *class = ahci_dev_classify(ap); | |
124 | ||
125 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
126 | return rc; | |
127 | } | |
128 | ||
129 | static struct ata_port_operations ahci_qoriq_ops = { | |
130 | .inherits = &ahci_ops, | |
131 | .hardreset = ahci_qoriq_hardreset, | |
132 | }; | |
133 | ||
134 | static const struct ata_port_info ahci_qoriq_port_info = { | |
135 | .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ, | |
136 | .pio_mask = ATA_PIO4, | |
137 | .udma_mask = ATA_UDMA6, | |
138 | .port_ops = &ahci_qoriq_ops, | |
139 | }; | |
140 | ||
141 | static struct scsi_host_template ahci_qoriq_sht = { | |
142 | AHCI_SHT(DRV_NAME), | |
143 | }; | |
144 | ||
145 | static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv) | |
146 | { | |
147 | struct ahci_qoriq_priv *qpriv = hpriv->plat_data; | |
148 | void __iomem *reg_base = hpriv->mmio; | |
149 | ||
150 | switch (qpriv->type) { | |
151 | case AHCI_LS1021A: | |
152 | writel(SATA_ECC_DISABLE, qpriv->ecc_addr); | |
153 | writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); | |
154 | writel(AHCI_PORT_PHY_2_CFG, reg_base + PORT_PHY2); | |
155 | writel(AHCI_PORT_PHY_3_CFG, reg_base + PORT_PHY3); | |
156 | writel(AHCI_PORT_PHY_4_CFG, reg_base + PORT_PHY4); | |
157 | writel(AHCI_PORT_PHY_5_CFG, reg_base + PORT_PHY5); | |
158 | writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); | |
159 | break; | |
160 | ||
161 | case AHCI_LS1043A: | |
d19f9aaf | 162 | case AHCI_LS2080A: |
ecfb4598 TY |
163 | writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); |
164 | break; | |
165 | } | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | static int ahci_qoriq_probe(struct platform_device *pdev) | |
171 | { | |
172 | struct device_node *np = pdev->dev.of_node; | |
173 | struct device *dev = &pdev->dev; | |
174 | struct ahci_host_priv *hpriv; | |
175 | struct ahci_qoriq_priv *qoriq_priv; | |
176 | const struct of_device_id *of_id; | |
177 | struct resource *res; | |
178 | int rc; | |
179 | ||
180 | hpriv = ahci_platform_get_resources(pdev); | |
181 | if (IS_ERR(hpriv)) | |
182 | return PTR_ERR(hpriv); | |
183 | ||
184 | of_id = of_match_node(ahci_qoriq_of_match, np); | |
185 | if (!of_id) | |
186 | return -ENODEV; | |
187 | ||
188 | qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL); | |
189 | if (!qoriq_priv) | |
190 | return -ENOMEM; | |
191 | ||
192 | qoriq_priv->type = (enum ahci_qoriq_type)of_id->data; | |
193 | ||
194 | if (qoriq_priv->type == AHCI_LS1021A) { | |
195 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
196 | "sata-ecc"); | |
197 | qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res); | |
198 | if (IS_ERR(qoriq_priv->ecc_addr)) | |
199 | return PTR_ERR(qoriq_priv->ecc_addr); | |
200 | } | |
201 | ||
202 | rc = ahci_platform_enable_resources(hpriv); | |
203 | if (rc) | |
204 | return rc; | |
205 | ||
206 | hpriv->plat_data = qoriq_priv; | |
207 | rc = ahci_qoriq_phy_init(hpriv); | |
208 | if (rc) | |
209 | goto disable_resources; | |
210 | ||
211 | rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info, | |
212 | &ahci_qoriq_sht); | |
213 | if (rc) | |
214 | goto disable_resources; | |
215 | ||
216 | return 0; | |
217 | ||
218 | disable_resources: | |
219 | ahci_platform_disable_resources(hpriv); | |
220 | ||
221 | return rc; | |
222 | } | |
223 | ||
224 | #ifdef CONFIG_PM_SLEEP | |
225 | static int ahci_qoriq_resume(struct device *dev) | |
226 | { | |
227 | struct ata_host *host = dev_get_drvdata(dev); | |
228 | struct ahci_host_priv *hpriv = host->private_data; | |
229 | int rc; | |
230 | ||
231 | rc = ahci_platform_enable_resources(hpriv); | |
232 | if (rc) | |
233 | return rc; | |
234 | ||
235 | rc = ahci_qoriq_phy_init(hpriv); | |
236 | if (rc) | |
237 | goto disable_resources; | |
238 | ||
239 | rc = ahci_platform_resume_host(dev); | |
240 | if (rc) | |
241 | goto disable_resources; | |
242 | ||
243 | /* We resumed so update PM runtime state */ | |
244 | pm_runtime_disable(dev); | |
245 | pm_runtime_set_active(dev); | |
246 | pm_runtime_enable(dev); | |
247 | ||
248 | return 0; | |
249 | ||
250 | disable_resources: | |
251 | ahci_platform_disable_resources(hpriv); | |
252 | ||
253 | return rc; | |
254 | } | |
255 | #endif | |
256 | ||
257 | static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend, | |
258 | ahci_qoriq_resume); | |
259 | ||
260 | static struct platform_driver ahci_qoriq_driver = { | |
261 | .probe = ahci_qoriq_probe, | |
262 | .remove = ata_platform_remove_one, | |
263 | .driver = { | |
264 | .name = DRV_NAME, | |
265 | .of_match_table = ahci_qoriq_of_match, | |
266 | .pm = &ahci_qoriq_pm_ops, | |
267 | }, | |
268 | }; | |
269 | module_platform_driver(ahci_qoriq_driver); | |
270 | ||
271 | MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver"); | |
272 | MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>"); | |
273 | MODULE_LICENSE("GPL"); |