[mirror_ubuntu-artful-kernel.git] / drivers / ata / ahci_tegra.c

/*
 * drivers/ata/ahci_tegra.c
 *
 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
 *
 * Author:
 *	Mikko Perttunen <mperttunen@nvidia.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/ahci_platform.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>

#include <soc/tegra/fuse.h>
#include <soc/tegra/pmc.h>

#include "ahci.h"

#define DRV_NAME "tegra-ahci"

#define SATA_CONFIGURATION_0				0x180
#define SATA_CONFIGURATION_EN_FPCI			BIT(0)

#define SCFG_OFFSET					0x1000

#define T_SATA0_CFG_1					0x04
#define T_SATA0_CFG_1_IO_SPACE				BIT(0)
#define T_SATA0_CFG_1_MEMORY_SPACE			BIT(1)
#define T_SATA0_CFG_1_BUS_MASTER			BIT(2)
#define T_SATA0_CFG_1_SERR				BIT(8)

#define T_SATA0_CFG_9					0x24
#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT		13

#define SATA_FPCI_BAR5					0x94
#define SATA_FPCI_BAR5_START_SHIFT			4

#define SATA_INTR_MASK					0x188
#define SATA_INTR_MASK_IP_INT_MASK			BIT(16)

#define T_SATA0_AHCI_HBA_CAP_BKDR			0x300

#define T_SATA0_BKDOOR_CC				0x4a4

#define T_SATA0_CFG_SATA				0x54c
#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN		BIT(12)

#define T_SATA0_CFG_MISC				0x550

#define T_SATA0_INDEX					0x680

#define T_SATA0_CHX_PHY_CTRL1_GEN1			0x690
#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK		0xff
#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT		0
#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK		(0xff << 8)
#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT	8

#define T_SATA0_CHX_PHY_CTRL1_GEN2			0x694
#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK		0xff
#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT		0
#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK		(0xff << 12)
#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT	12

#define T_SATA0_CHX_PHY_CTRL2				0x69c
#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1		0x23

#define T_SATA0_CHX_PHY_CTRL11				0x6d0
#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ		(0x2800 << 16)

#define FUSE_SATA_CALIB					0x124
#define FUSE_SATA_CALIB_MASK				0x3

struct sata_pad_calibration {
	u8 gen1_tx_amp;
	u8 gen1_tx_peak;
	u8 gen2_tx_amp;
	u8 gen2_tx_peak;
};

static const struct sata_pad_calibration tegra124_pad_calibration[] = {
	{0x18, 0x04, 0x18, 0x0a},
	{0x0e, 0x04, 0x14, 0x0a},
	{0x0e, 0x07, 0x1a, 0x0e},
	{0x14, 0x0e, 0x1a, 0x0e},
};

struct tegra_ahci_priv {
	struct platform_device	   *pdev;
	void __iomem		   *sata_regs;
	struct reset_control	   *sata_rst;
	struct reset_control	   *sata_oob_rst;
	struct reset_control	   *sata_cold_rst;
	/* Needs special handling, cannot use ahci_platform */
	struct clk		   *sata_clk;
	struct regulator_bulk_data supplies[5];
};

static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
{
	struct tegra_ahci_priv *tegra = hpriv->plat_data;
	int ret;

	ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
				    tegra->supplies);
	if (ret)
		return ret;

	ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
						tegra->sata_clk,
						tegra->sata_rst);
	if (ret)
		goto disable_regulators;

	reset_control_assert(tegra->sata_oob_rst);
	reset_control_assert(tegra->sata_cold_rst);

	ret = ahci_platform_enable_resources(hpriv);
	if (ret)
		goto disable_power;

	reset_control_deassert(tegra->sata_cold_rst);
	reset_control_deassert(tegra->sata_oob_rst);

	return 0;

disable_power:
	clk_disable_unprepare(tegra->sata_clk);

	tegra_powergate_power_off(TEGRA_POWERGATE_SATA);

disable_regulators:
	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);

	return ret;
}

static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
{
	struct tegra_ahci_priv *tegra = hpriv->plat_data;

	ahci_platform_disable_resources(hpriv);

	reset_control_assert(tegra->sata_rst);
	reset_control_assert(tegra->sata_oob_rst);
	reset_control_assert(tegra->sata_cold_rst);

	clk_disable_unprepare(tegra->sata_clk);
	tegra_powergate_power_off(TEGRA_POWERGATE_SATA);

	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
}

static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
{
	struct tegra_ahci_priv *tegra = hpriv->plat_data;
	int ret;
	unsigned int val;
	struct sata_pad_calibration calib;

	ret = tegra_ahci_power_on(hpriv);
	if (ret) {
		dev_err(&tegra->pdev->dev,
			"failed to power on AHCI controller: %d\n", ret);
		return ret;
	}

	val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
	val |= SATA_CONFIGURATION_EN_FPCI;
	writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);

	/* Pad calibration */

	ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
	if (ret) {
		dev_err(&tegra->pdev->dev,
			"failed to read calibration fuse: %d\n", ret);
		return ret;
	}

	calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];

	writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);

	val = readl(tegra->sata_regs +
		SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
	val |= calib.gen1_tx_amp <<
			T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
	val |= calib.gen1_tx_peak <<
			T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
	writel(val, tegra->sata_regs + SCFG_OFFSET +
		T_SATA0_CHX_PHY_CTRL1_GEN1);

	val = readl(tegra->sata_regs +
			SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
	val |= calib.gen2_tx_amp <<
			T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
	val |= calib.gen2_tx_peak <<
			T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
	writel(val, tegra->sata_regs + SCFG_OFFSET +
		T_SATA0_CHX_PHY_CTRL1_GEN2);

	writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
		tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
	writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
		tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);

	writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);

	/* Program controller device ID */

	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
	val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);

	writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);

	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
	val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);

	/* Enable IO & memory access, bus master mode */

	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
	val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
		T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);

	/* Program SATA MMIO */

	writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
	       tegra->sata_regs + SATA_FPCI_BAR5);

	writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);

	/* Unmask SATA interrupts */

	val = readl(tegra->sata_regs + SATA_INTR_MASK);
	val |= SATA_INTR_MASK_IP_INT_MASK;
	writel(val, tegra->sata_regs + SATA_INTR_MASK);

	return 0;
}

static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
{
	tegra_ahci_power_off(hpriv);
}

static void tegra_ahci_host_stop(struct ata_host *host)
{
	struct ahci_host_priv *hpriv = host->private_data;

	tegra_ahci_controller_deinit(hpriv);
}

static struct ata_port_operations ahci_tegra_port_ops = {
	.inherits	= &ahci_ops,
	.host_stop	= tegra_ahci_host_stop,
};

static const struct ata_port_info ahci_tegra_port_info = {
	.flags		= AHCI_FLAG_COMMON,
	.pio_mask	= ATA_PIO4,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &ahci_tegra_port_ops,
};

static const struct of_device_id tegra_ahci_of_match[] = {
	{ .compatible = "nvidia,tegra124-ahci" },
	{}
};
MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);

static struct scsi_host_template ahci_platform_sht = {
	AHCI_SHT(DRV_NAME),
};

static int tegra_ahci_probe(struct platform_device *pdev)
{
	struct ahci_host_priv *hpriv;
	struct tegra_ahci_priv *tegra;
	struct resource *res;
	int ret;

	hpriv = ahci_platform_get_resources(pdev);
	if (IS_ERR(hpriv))
		return PTR_ERR(hpriv);

	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
	if (!tegra)
		return -ENOMEM;

	hpriv->plat_data = tegra;

	tegra->pdev = pdev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(tegra->sata_regs))
		return PTR_ERR(tegra->sata_regs);

	tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
	if (IS_ERR(tegra->sata_rst)) {
		dev_err(&pdev->dev, "Failed to get sata reset\n");
		return PTR_ERR(tegra->sata_rst);
	}

	tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
	if (IS_ERR(tegra->sata_oob_rst)) {
		dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
		return PTR_ERR(tegra->sata_oob_rst);
	}

	tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
	if (IS_ERR(tegra->sata_cold_rst)) {
		dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
		return PTR_ERR(tegra->sata_cold_rst);
	}

	tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
	if (IS_ERR(tegra->sata_clk)) {
		dev_err(&pdev->dev, "Failed to get sata clock\n");
		return PTR_ERR(tegra->sata_clk);
	}

	tegra->supplies[0].supply = "avdd";
	tegra->supplies[1].supply = "hvdd";
	tegra->supplies[2].supply = "vddio";
	tegra->supplies[3].supply = "target-5v";
	tegra->supplies[4].supply = "target-12v";

	ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
				      tegra->supplies);
	if (ret) {
		dev_err(&pdev->dev, "Failed to get regulators\n");
		return ret;
	}

	ret = tegra_ahci_controller_init(hpriv);
	if (ret)
		return ret;

	ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info,
				      &ahci_platform_sht);
	if (ret)
		goto deinit_controller;

	return 0;

deinit_controller:
	tegra_ahci_controller_deinit(hpriv);

	return ret;
};

static struct platform_driver tegra_ahci_driver = {
	.probe = tegra_ahci_probe,
	.remove = ata_platform_remove_one,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = tegra_ahci_of_match,
	},
	/* LP0 suspend support not implemented */
};
module_platform_driver(tegra_ahci_driver);

MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ccfde508 MP	1	/*
	2	* drivers/ata/ahci_tegra.c
	3	*
	4	* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
	5	*
	6	* Author:
	7	* Mikko Perttunen <mperttunen@nvidia.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/ahci_platform.h>
ccfde508 MP	21	#include <linux/errno.h>
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/of_device.h>
	25	#include <linux/platform_device.h>
ccfde508	26	#include <linux/regulator/consumer.h>
e327f115 MP	27	#include <linux/reset.h>
	28
	29	#include <soc/tegra/fuse.h>
0e574077	30	#include <soc/tegra/pmc.h>
e327f115	31
ccfde508 MP	32	#include "ahci.h"
ccfde508 MP	33
018d5ef2 AM	34	#define DRV_NAME "tegra-ahci"
018d5ef2 AM	35
ccfde508 MP	36	#define SATA_CONFIGURATION_0 0x180
	37	#define SATA_CONFIGURATION_EN_FPCI BIT(0)
	38
	39	#define SCFG_OFFSET 0x1000
	40
	41	#define T_SATA0_CFG_1 0x04
	42	#define T_SATA0_CFG_1_IO_SPACE BIT(0)
	43	#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
	44	#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
	45	#define T_SATA0_CFG_1_SERR BIT(8)
	46
	47	#define T_SATA0_CFG_9 0x24
	48	#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
	49
	50	#define SATA_FPCI_BAR5 0x94
	51	#define SATA_FPCI_BAR5_START_SHIFT 4
	52
	53	#define SATA_INTR_MASK 0x188
	54	#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
	55
	56	#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
	57
	58	#define T_SATA0_BKDOOR_CC 0x4a4
	59
	60	#define T_SATA0_CFG_SATA 0x54c
	61	#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
	62
	63	#define T_SATA0_CFG_MISC 0x550
	64
	65	#define T_SATA0_INDEX 0x680
	66
	67	#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
	68	#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
	69	#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
	70	#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
	71	#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
	72
	73	#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
	74	#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
	75	#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
	76	#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
	77	#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
	78
	79	#define T_SATA0_CHX_PHY_CTRL2 0x69c
	80	#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
	81
	82	#define T_SATA0_CHX_PHY_CTRL11 0x6d0
	83	#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
	84
	85	#define FUSE_SATA_CALIB 0x124
	86	#define FUSE_SATA_CALIB_MASK 0x3
	87
	88	struct sata_pad_calibration {
	89	u8 gen1_tx_amp;
	90	u8 gen1_tx_peak;
	91	u8 gen2_tx_amp;
	92	u8 gen2_tx_peak;
	93	};
	94
	95	static const struct sata_pad_calibration tegra124_pad_calibration[] = {
	96	{0x18, 0x04, 0x18, 0x0a},
	97	{0x0e, 0x04, 0x14, 0x0a},
	98	{0x0e, 0x07, 0x1a, 0x0e},
	99	{0x14, 0x0e, 0x1a, 0x0e},
100	};
101
102	struct tegra_ahci_priv {
103	struct platform_device *pdev;
104	void __iomem *sata_regs;
105	struct reset_control *sata_rst;
106	struct reset_control *sata_oob_rst;
107	struct reset_control *sata_cold_rst;
108	/* Needs special handling, cannot use ahci_platform */
109	struct clk *sata_clk;
110	struct regulator_bulk_data supplies[5];
111	};
112
113	static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
114	{
115	struct tegra_ahci_priv *tegra = hpriv->plat_data;
116	int ret;
117
118	ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
119	tegra->supplies);
120	if (ret)
121	return ret;
122
123	ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
124	tegra->sata_clk,
125	tegra->sata_rst);
126	if (ret)
127	goto disable_regulators;
128
129	reset_control_assert(tegra->sata_oob_rst);
130	reset_control_assert(tegra->sata_cold_rst);
131
132	ret = ahci_platform_enable_resources(hpriv);
133	if (ret)
134	goto disable_power;
135
136	reset_control_deassert(tegra->sata_cold_rst);
137	reset_control_deassert(tegra->sata_oob_rst);
138
139	return 0;
140
141	disable_power:
142	clk_disable_unprepare(tegra->sata_clk);
143
144	tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
145
146	disable_regulators:
147	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
148
149	return ret;
150	}
151
152	static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
153	{
154	struct tegra_ahci_priv *tegra = hpriv->plat_data;
155
156	ahci_platform_disable_resources(hpriv);
157
158	reset_control_assert(tegra->sata_rst);
159	reset_control_assert(tegra->sata_oob_rst);
160	reset_control_assert(tegra->sata_cold_rst);
161
162	clk_disable_unprepare(tegra->sata_clk);
163	tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
164
165	regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
166	}
167
168	static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
169	{
170	struct tegra_ahci_priv *tegra = hpriv->plat_data;
171	int ret;
172	unsigned int val;
173	struct sata_pad_calibration calib;
174
175	ret = tegra_ahci_power_on(hpriv);
176	if (ret) {
177	dev_err(&tegra->pdev->dev,
178	"failed to power on AHCI controller: %d\n", ret);
179	return ret;
180	}
181
182	val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
183	val \|= SATA_CONFIGURATION_EN_FPCI;
184	writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
185
186	/* Pad calibration */
187
e327f115 MP	188	ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
	189	if (ret) {
	190	dev_err(&tegra->pdev->dev,
	191	"failed to read calibration fuse: %d\n", ret);
	192	return ret;
	193	}
ccfde508 MP	194
	195	calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
	196
	197	writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
	198
	199	val = readl(tegra->sata_regs +
	200	SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
	201	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
	202	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
	203	val \|= calib.gen1_tx_amp <<
	204	T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
	205	val \|= calib.gen1_tx_peak <<
	206	T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
	207	writel(val, tegra->sata_regs + SCFG_OFFSET +
	208	T_SATA0_CHX_PHY_CTRL1_GEN1);
	209
	210	val = readl(tegra->sata_regs +
	211	SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
	212	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
	213	val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
	214	val \|= calib.gen2_tx_amp <<
	215	T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
	216	val \|= calib.gen2_tx_peak <<
	217	T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
	218	writel(val, tegra->sata_regs + SCFG_OFFSET +
	219	T_SATA0_CHX_PHY_CTRL1_GEN2);
	220
	221	writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
	222	tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
	223	writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
	224	tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
	225
	226	writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
	227
	228	/* Program controller device ID */
	229
	230	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
	231	val \|= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
	232	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
	233
	234	writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
	235
	236	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
	237	val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
	238	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
	239
	240	/* Enable IO & memory access, bus master mode */
	241
	242	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
	243	val \|= T_SATA0_CFG_1_IO_SPACE \| T_SATA0_CFG_1_MEMORY_SPACE \|
	244	T_SATA0_CFG_1_BUS_MASTER \| T_SATA0_CFG_1_SERR;
	245	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
	246
	247	/* Program SATA MMIO */
	248
	249	writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
	250	tegra->sata_regs + SATA_FPCI_BAR5);
	251
	252	writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
	253	tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
	254
	255	/* Unmask SATA interrupts */
	256
	257	val = readl(tegra->sata_regs + SATA_INTR_MASK);
258	val \|= SATA_INTR_MASK_IP_INT_MASK;
259	writel(val, tegra->sata_regs + SATA_INTR_MASK);
260
261	return 0;
262	}
263
264	static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
265	{
266	tegra_ahci_power_off(hpriv);
267	}
268
269	static void tegra_ahci_host_stop(struct ata_host *host)
270	{
271	struct ahci_host_priv *hpriv = host->private_data;
272
273	tegra_ahci_controller_deinit(hpriv);
274	}
275
276	static struct ata_port_operations ahci_tegra_port_ops = {
277	.inherits = &ahci_ops,
278	.host_stop = tegra_ahci_host_stop,
279	};
280
281	static const struct ata_port_info ahci_tegra_port_info = {
282	.flags = AHCI_FLAG_COMMON,
283	.pio_mask = ATA_PIO4,
284	.udma_mask = ATA_UDMA6,
285	.port_ops = &ahci_tegra_port_ops,
286	};
287
288	static const struct of_device_id tegra_ahci_of_match[] = {
289	{ .compatible = "nvidia,tegra124-ahci" },
290	{}
291	};
292	MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
293
018d5ef2 AM	294	static struct scsi_host_template ahci_platform_sht = {
	295	AHCI_SHT(DRV_NAME),
	296	};
	297
ccfde508 MP	298	static int tegra_ahci_probe(struct platform_device *pdev)
	299	{
	300	struct ahci_host_priv *hpriv;
	301	struct tegra_ahci_priv *tegra;
	302	struct resource *res;
	303	int ret;
	304
	305	hpriv = ahci_platform_get_resources(pdev);
	306	if (IS_ERR(hpriv))
	307	return PTR_ERR(hpriv);
	308
	309	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
	310	if (!tegra)
	311	return -ENOMEM;
	312
	313	hpriv->plat_data = tegra;
	314
	315	tegra->pdev = pdev;
	316
	317	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	318	tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
	319	if (IS_ERR(tegra->sata_regs))
	320	return PTR_ERR(tegra->sata_regs);
	321
	322	tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
	323	if (IS_ERR(tegra->sata_rst)) {
	324	dev_err(&pdev->dev, "Failed to get sata reset\n");
	325	return PTR_ERR(tegra->sata_rst);
	326	}
	327
	328	tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
	329	if (IS_ERR(tegra->sata_oob_rst)) {
	330	dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
	331	return PTR_ERR(tegra->sata_oob_rst);
	332	}
	333
	334	tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
	335	if (IS_ERR(tegra->sata_cold_rst)) {
	336	dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
	337	return PTR_ERR(tegra->sata_cold_rst);
	338	}
	339
	340	tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
	341	if (IS_ERR(tegra->sata_clk)) {
	342	dev_err(&pdev->dev, "Failed to get sata clock\n");
	343	return PTR_ERR(tegra->sata_clk);
	344	}
	345
	346	tegra->supplies[0].supply = "avdd";
	347	tegra->supplies[1].supply = "hvdd";
	348	tegra->supplies[2].supply = "vddio";
	349	tegra->supplies[3].supply = "target-5v";
	350	tegra->supplies[4].supply = "target-12v";
	351
	352	ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
	353	tegra->supplies);
	354	if (ret) {
	355	dev_err(&pdev->dev, "Failed to get regulators\n");
	356	return ret;
	357	}
	358
	359	ret = tegra_ahci_controller_init(hpriv);
	360	if (ret)
	361	return ret;
362
018d5ef2 AM	363	ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info,
018d5ef2 AM	364	&ahci_platform_sht);
ccfde508 MP	365	if (ret)
	366	goto deinit_controller;
	367
	368	return 0;
	369
	370	deinit_controller:
	371	tegra_ahci_controller_deinit(hpriv);
	372
	373	return ret;
	374	};
	375
	376	static struct platform_driver tegra_ahci_driver = {
	377	.probe = tegra_ahci_probe,
	378	.remove = ata_platform_remove_one,
	379	.driver = {
018d5ef2	380	.name = DRV_NAME,
ccfde508 MP	381	.of_match_table = tegra_ahci_of_match,
	382	},
	383	/* LP0 suspend support not implemented */
	384	};
	385	module_platform_driver(tegra_ahci_driver);
	386
	387	MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
	388	MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
	389	MODULE_LICENSE("GPL v2");