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ata_piix: reorganize controller IDs
[mirror_ubuntu-artful-kernel.git] / drivers / ata / ata_piix.c
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1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
b8b275ef 94#include <linux/dmi.h>
1da177e4
LT		 95
96#define DRV_NAME "ata_piix"
2a3103ce 97#define DRV_VERSION "2.12"
1da177e4
LT		 98
99enum {
100 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
101 ICH5_PMR = 0x90, /* port mapping register */
102 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 103 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 104
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 108
800b3996
TH		 109 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
110 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 111
1da177e4
LT		 112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
1d076e5b 121 /* controller IDs */
00242ec8
TH		 122 piix_pata_mwdma = 0, /* PIIX3 MWDMA only */
123 piix_pata_33, /* PIIX4 at 33Mhz */
124 ich_pata_33, /* ICH up to UDMA 33 only */
125 ich_pata_66, /* ICH up to 66 Mhz */
126 ich_pata_100, /* ICH up to UDMA 100 */
127 ich5_sata,
128 ich6_sata,
129 ich6_sata_ahci,
130 ich6m_sata_ahci,
131 ich8_sata_ahci,
132 ich8_2port_sata,
133 tolapai_sata_ahci,
85cd7251 134
d33f58b8
TH		 135 /* constants for mapping table */
136 P0 = 0, /* port 0 */
137 P1 = 1, /* port 1 */
138 P2 = 2, /* port 2 */
139 P3 = 3, /* port 3 */
140 IDE = -1, /* IDE */
141 NA = -2, /* not avaliable */
142 RV = -3, /* reserved */
143
7b6dbd68 144 PIIX_AHCI_DEVICE = 6,
b8b275ef
TH		 145
146 /* host->flags bits */
147 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
1da177e4
LT		 148};
149
d33f58b8
TH		 150struct piix_map_db {
151 const u32 mask;
73291a1c 152 const u16 port_enable;
d33f58b8
TH		 153 const int map[][4];
154};
155
d96715c1
TH		 156struct piix_host_priv {
157 const int *map;
158};
159
2dcb407e
JG		 160static int piix_init_one(struct pci_dev *pdev,
161 const struct pci_device_id *ent);
ccc4672a 162static void piix_pata_error_handler(struct ata_port *ap);
2dcb407e
JG		 163static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
164static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
165static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
eb4a2c7f 166static int ich_pata_cable_detect(struct ata_port *ap);
b8b275ef
TH		 167#ifdef CONFIG_PM
168static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
169static int piix_pci_device_resume(struct pci_dev *pdev);
170#endif
1da177e4
LT		 171
172static unsigned int in_module_init = 1;
173
3b7d697d 174static const struct pci_device_id piix_pci_tbl[] = {
d2cdfc0d
AC		 175 /* Intel PIIX3 for the 430HX etc */
176 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
669a5db4
JG		 177 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
178 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
179 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
669a5db4
JG		 180 /* Intel PIIX4 */
181 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 /* Intel PIIX4 */
183 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
184 /* Intel PIIX */
185 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
186 /* Intel ICH (i810, i815, i840) UDMA 66*/
187 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
188 /* Intel ICH0 : UDMA 33*/
189 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
190 /* Intel ICH2M */
191 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
193 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH3M */
195 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 /* Intel ICH3 (E7500/1) UDMA 100 */
197 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
199 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* Intel ICH5 */
2eb829e9 202 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4
JG		 203 /* C-ICH (i810E2) */
204 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 205 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 206 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
207 /* ICH6 (and 6) (i915) UDMA 100 */
208 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
209 /* ICH7/7-R (i945, i975) UDMA 100*/
2eb829e9 210 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
669a5db4 211 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
c1e6f28c
CL		 212 /* ICH8 Mobile PATA Controller */
213 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 214
215 /* NOTE: The following PCI ids must be kept in sync with the
216 * list in drivers/pci/quirks.c.
217 */
218
1d076e5b 219 /* 82801EB (ICH5) */
1da177e4 220 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 221 /* 82801EB (ICH5) */
1da177e4 222 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 223 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 224 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 225 /* 6300ESB pretending RAID */
5e56a37c 226 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 227 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 228 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 229 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 230 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 231 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
232 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
233 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 234 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 235 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 236 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 237 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 238 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 239 /* SATA Controller 1 IDE (ICH8) */
08f12edc 240 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 241 /* SATA Controller 2 IDE (ICH8) */
00242ec8 242 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 243 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 244 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573
JG		 245 /* SATA Controller IDE (ICH9) */
246 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
247 /* SATA Controller IDE (ICH9) */
00242ec8 248 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 249 /* SATA Controller IDE (ICH9) */
00242ec8 250 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 251 /* SATA Controller IDE (ICH9M) */
00242ec8 252 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573 253 /* SATA Controller IDE (ICH9M) */
00242ec8 254 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
f98b6573
JG		 255 /* SATA Controller IDE (ICH9M) */
256 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
c5cf0ffa
JG		 257 /* SATA Controller IDE (Tolapai) */
258 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
1da177e4
LT		 259
260 { } /* terminate list */
261};
262
263static struct pci_driver piix_pci_driver = {
264 .name = DRV_NAME,
265 .id_table = piix_pci_tbl,
266 .probe = piix_init_one,
267 .remove = ata_pci_remove_one,
438ac6d5 268#ifdef CONFIG_PM
b8b275ef
TH		 269 .suspend = piix_pci_device_suspend,
270 .resume = piix_pci_device_resume,
438ac6d5 271#endif
1da177e4
LT		 272};
273
193515d5 274static struct scsi_host_template piix_sht = {
1da177e4
LT		 275 .module = THIS_MODULE,
276 .name = DRV_NAME,
277 .ioctl = ata_scsi_ioctl,
278 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 279 .can_queue = ATA_DEF_QUEUE,
280 .this_id = ATA_SHT_THIS_ID,
281 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 282 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
283 .emulated = ATA_SHT_EMULATED,
284 .use_clustering = ATA_SHT_USE_CLUSTERING,
285 .proc_name = DRV_NAME,
286 .dma_boundary = ATA_DMA_BOUNDARY,
287 .slave_configure = ata_scsi_slave_config,
ccf68c34 288 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 289 .bios_param = ata_std_bios_param,
1da177e4
LT		 290};
291
057ace5e 292static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 293 .set_piomode = piix_set_piomode,
294 .set_dmamode = piix_set_dmamode,
89bad589 295 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 296
297 .tf_load = ata_tf_load,
298 .tf_read = ata_tf_read,
299 .check_status = ata_check_status,
300 .exec_command = ata_exec_command,
301 .dev_select = ata_std_dev_select,
302
1da177e4
LT		 303 .bmdma_setup = ata_bmdma_setup,
304 .bmdma_start = ata_bmdma_start,
305 .bmdma_stop = ata_bmdma_stop,
306 .bmdma_status = ata_bmdma_status,
307 .qc_prep = ata_qc_prep,
308 .qc_issue = ata_qc_issue_prot,
0d5ff566 309 .data_xfer = ata_data_xfer,
1da177e4 310
3f037db0
TH		 311 .freeze = ata_bmdma_freeze,
312 .thaw = ata_bmdma_thaw,
ccc4672a 313 .error_handler = piix_pata_error_handler,
3f037db0 314 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 315 .cable_detect = ata_cable_40wire,
1da177e4
LT		 316
317 .irq_handler = ata_interrupt,
318 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 319 .irq_on = ata_irq_on,
1da177e4
LT		 320
321 .port_start = ata_port_start,
1da177e4
LT		 322};
323
669a5db4 324static const struct ata_port_operations ich_pata_ops = {
669a5db4
JG		 325 .set_piomode = piix_set_piomode,
326 .set_dmamode = ich_set_dmamode,
327 .mode_filter = ata_pci_default_filter,
328
329 .tf_load = ata_tf_load,
330 .tf_read = ata_tf_read,
331 .check_status = ata_check_status,
332 .exec_command = ata_exec_command,
333 .dev_select = ata_std_dev_select,
334
335 .bmdma_setup = ata_bmdma_setup,
336 .bmdma_start = ata_bmdma_start,
337 .bmdma_stop = ata_bmdma_stop,
338 .bmdma_status = ata_bmdma_status,
339 .qc_prep = ata_qc_prep,
340 .qc_issue = ata_qc_issue_prot,
0d5ff566 341 .data_xfer = ata_data_xfer,
669a5db4
JG		 342
343 .freeze = ata_bmdma_freeze,
344 .thaw = ata_bmdma_thaw,
eb4a2c7f 345 .error_handler = piix_pata_error_handler,
669a5db4 346 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 347 .cable_detect = ich_pata_cable_detect,
669a5db4
JG		 348
349 .irq_handler = ata_interrupt,
350 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 351 .irq_on = ata_irq_on,
669a5db4
JG		 352
353 .port_start = ata_port_start,
669a5db4
JG		 354};
355
057ace5e 356static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 357 .tf_load = ata_tf_load,
358 .tf_read = ata_tf_read,
359 .check_status = ata_check_status,
360 .exec_command = ata_exec_command,
361 .dev_select = ata_std_dev_select,
362
1da177e4
LT		 363 .bmdma_setup = ata_bmdma_setup,
364 .bmdma_start = ata_bmdma_start,
365 .bmdma_stop = ata_bmdma_stop,
366 .bmdma_status = ata_bmdma_status,
367 .qc_prep = ata_qc_prep,
368 .qc_issue = ata_qc_issue_prot,
0d5ff566 369 .data_xfer = ata_data_xfer,
1da177e4 370
3f037db0
TH		 371 .freeze = ata_bmdma_freeze,
372 .thaw = ata_bmdma_thaw,
2f91d81d 373 .error_handler = ata_bmdma_error_handler,
3f037db0 374 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 375
376 .irq_handler = ata_interrupt,
377 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 378 .irq_on = ata_irq_on,
1da177e4
LT		 379
380 .port_start = ata_port_start,
1da177e4
LT		 381};
382
d96715c1 383static const struct piix_map_db ich5_map_db = {
d33f58b8 384 .mask = 0x7,
ea35d29e 385 .port_enable = 0x3,
d33f58b8
TH		 386 .map = {
387 /* PM PS SM SS MAP */
388 { P0, NA, P1, NA }, /* 000b */
389 { P1, NA, P0, NA }, /* 001b */
390 { RV, RV, RV, RV },
391 { RV, RV, RV, RV },
392 { P0, P1, IDE, IDE }, /* 100b */
393 { P1, P0, IDE, IDE }, /* 101b */
394 { IDE, IDE, P0, P1 }, /* 110b */
395 { IDE, IDE, P1, P0 }, /* 111b */
396 },
397};
398
d96715c1 399static const struct piix_map_db ich6_map_db = {
d33f58b8 400 .mask = 0x3,
ea35d29e 401 .port_enable = 0xf,
d33f58b8
TH		 402 .map = {
403 /* PM PS SM SS MAP */
79ea24e7 404 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 405 { IDE, IDE, P1, P3 }, /* 01b */
406 { P0, P2, IDE, IDE }, /* 10b */
407 { RV, RV, RV, RV },
408 },
409};
410
d96715c1 411static const struct piix_map_db ich6m_map_db = {
d33f58b8 412 .mask = 0x3,
ea35d29e 413 .port_enable = 0x5,
67083741
TH		 414
415 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 416 * it anyway. MAP 01b have been spotted on both ICH6M and
417 * ICH7M.
67083741
TH		 418 */
419 .map = {
420 /* PM PS SM SS MAP */
e04b3b9d 421 { P0, P2, NA, NA }, /* 00b */
67083741
TH		 422 { IDE, IDE, P1, P3 }, /* 01b */
423 { P0, P2, IDE, IDE }, /* 10b */
424 { RV, RV, RV, RV },
425 },
426};
427
08f12edc
JG		 428static const struct piix_map_db ich8_map_db = {
429 .mask = 0x3,
430 .port_enable = 0x3,
08f12edc
JG		 431 .map = {
432 /* PM PS SM SS MAP */
158f30c8 433 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 434 { RV, RV, RV, RV },
ac2b0437 435 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
08f12edc
JG		 436 { RV, RV, RV, RV },
437 },
438};
439
00242ec8 440static const struct piix_map_db ich8_2port_map_db = {
e2d352af
JG		 441 .mask = 0x3,
442 .port_enable = 0x3,
443 .map = {
444 /* PM PS SM SS MAP */
445 { P0, NA, P1, NA }, /* 00b */
446 { RV, RV, RV, RV }, /* 01b */
447 { RV, RV, RV, RV }, /* 10b */
448 { RV, RV, RV, RV },
449 },
c5cf0ffa
JG		 450};
451
00242ec8 452static const struct piix_map_db tolapai_map_db = {
8f73a688
JG		 453 .mask = 0x3,
454 .port_enable = 0x3,
455 .map = {
456 /* PM PS SM SS MAP */
457 { P0, NA, P1, NA }, /* 00b */
458 { RV, RV, RV, RV }, /* 01b */
459 { RV, RV, RV, RV }, /* 10b */
460 { RV, RV, RV, RV },
461 },
462};
463
d96715c1
TH		 464static const struct piix_map_db *piix_map_db_table[] = {
465 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 466 [ich6_sata] = &ich6_map_db,
467 [ich6_sata_ahci] = &ich6_map_db,
468 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 469 [ich8_sata_ahci] = &ich8_map_db,
00242ec8 470 [ich8_2port_sata] = &ich8_2port_map_db,
c5cf0ffa 471 [tolapai_sata_ahci] = &tolapai_map_db,
d96715c1
TH		 472};
473
1da177e4 474static struct ata_port_info piix_port_info[] = {
00242ec8
TH		 475 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
476 {
477 .sht = &piix_sht,
478 .flags = PIIX_PATA_FLAGS,
479 .pio_mask = 0x1f, /* pio0-4 */
480 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
481 .port_ops = &piix_pata_ops,
482 },
483
ec300d99 484 [piix_pata_33] = /* PIIX4 at 33MHz */
1d076e5b
TH		 485 {
486 .sht = &piix_sht,
b3362f88 487 .flags = PIIX_PATA_FLAGS,
1d076e5b 488 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 489 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 490 .udma_mask = ATA_UDMA_MASK_40C,
491 .port_ops = &piix_pata_ops,
492 },
493
ec300d99 494 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
669a5db4
JG		 495 {
496 .sht = &piix_sht,
b3362f88 497 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 498 .pio_mask = 0x1f, /* pio 0-4 */
499 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
500 .udma_mask = ATA_UDMA2, /* UDMA33 */
501 .port_ops = &ich_pata_ops,
502 },
ec300d99
JG		 503
504 [ich_pata_66] = /* ICH controllers up to 66MHz */
1da177e4
LT		 505 {
506 .sht = &piix_sht,
b3362f88 507 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 508 .pio_mask = 0x1f, /* pio 0-4 */
509 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
510 .udma_mask = ATA_UDMA4,
511 .port_ops = &ich_pata_ops,
512 },
85cd7251 513
ec300d99 514 [ich_pata_100] =
669a5db4
JG		 515 {
516 .sht = &piix_sht,
b3362f88 517 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 518 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 519 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 520 .udma_mask = ATA_UDMA5, /* udma0-5 */
521 .port_ops = &ich_pata_ops,
1da177e4
LT		 522 },
523
ec300d99 524 [ich5_sata] =
1da177e4
LT		 525 {
526 .sht = &piix_sht,
228c1590 527 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 528 .pio_mask = 0x1f, /* pio0-4 */
529 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 530 .udma_mask = ATA_UDMA6,
1da177e4
LT		 531 .port_ops = &piix_sata_ops,
532 },
533
ec300d99 534 [ich6_sata] =
1da177e4
LT		 535 {
536 .sht = &piix_sht,
b3362f88 537 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 538 .pio_mask = 0x1f, /* pio0-4 */
539 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 540 .udma_mask = ATA_UDMA6,
1da177e4
LT		 541 .port_ops = &piix_sata_ops,
542 },
543
ec300d99 544 [ich6_sata_ahci] =
c368ca4e
JG		 545 {
546 .sht = &piix_sht,
b3362f88 547 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 548 PIIX_FLAG_AHCI,
c368ca4e
JG		 549 .pio_mask = 0x1f, /* pio0-4 */
550 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 551 .udma_mask = ATA_UDMA6,
c368ca4e
JG		 552 .port_ops = &piix_sata_ops,
553 },
1d076e5b 554
ec300d99 555 [ich6m_sata_ahci] =
1d076e5b
TH		 556 {
557 .sht = &piix_sht,
b3362f88 558 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 559 PIIX_FLAG_AHCI,
1d076e5b
TH		 560 .pio_mask = 0x1f, /* pio0-4 */
561 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 562 .udma_mask = ATA_UDMA6,
1d076e5b
TH		 563 .port_ops = &piix_sata_ops,
564 },
08f12edc 565
ec300d99 566 [ich8_sata_ahci] =
08f12edc
JG		 567 {
568 .sht = &piix_sht,
b3362f88 569 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 570 PIIX_FLAG_AHCI,
571 .pio_mask = 0x1f, /* pio0-4 */
572 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 573 .udma_mask = ATA_UDMA6,
08f12edc
JG		 574 .port_ops = &piix_sata_ops,
575 },
669a5db4 576
00242ec8 577 [ich8_2port_sata] =
c5cf0ffa
JG		 578 {
579 .sht = &piix_sht,
580 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
581 PIIX_FLAG_AHCI,
582 .pio_mask = 0x1f, /* pio0-4 */
583 .mwdma_mask = 0x07, /* mwdma0-2 */
584 .udma_mask = ATA_UDMA6,
585 .port_ops = &piix_sata_ops,
586 },
8f73a688 587
00242ec8 588 [tolapai_sata_ahci] =
8f73a688
JG		 589 {
590 .sht = &piix_sht,
591 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
592 PIIX_FLAG_AHCI,
593 .pio_mask = 0x1f, /* pio0-4 */
594 .mwdma_mask = 0x07, /* mwdma0-2 */
595 .udma_mask = ATA_UDMA6,
596 .port_ops = &piix_sata_ops,
597 },
1da177e4
LT		 598};
599
600static struct pci_bits piix_enable_bits[] = {
601 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
602 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
603};
604
605MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
606MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
607MODULE_LICENSE("GPL");
608MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
609MODULE_VERSION(DRV_VERSION);
610
fc085150
AC		 611struct ich_laptop {
612 u16 device;
613 u16 subvendor;
614 u16 subdevice;
615};
616
617/*
618 * List of laptops that use short cables rather than 80 wire
619 */
620
621static const struct ich_laptop ich_laptop[] = {
622 /* devid, subvendor, subdev */
623 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
2655e2ce 624 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
babfb682 625 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
12340106 626 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
54174db3 627 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
b33620f9 628 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
fc085150
AC		 629 /* end marker */
630 { 0, }
631};
632
1da177e4 633/**
eb4a2c7f 634 * ich_pata_cable_detect - Probe host controller cable detect info
1da177e4
LT		 635 * @ap: Port for which cable detect info is desired
636 *
637 * Read 80c cable indicator from ATA PCI device's PCI config
638 * register. This register is normally set by firmware (BIOS).
639 *
640 * LOCKING:
641 * None (inherited from caller).
642 */
669a5db4 643
eb4a2c7f 644static int ich_pata_cable_detect(struct ata_port *ap)
1da177e4 645{
cca3974e 646 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 647 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 648 u8 tmp, mask;
649
fc085150
AC		 650 /* Check for specials - Acer Aspire 5602WLMi */
651 while (lap->device) {
652 if (lap->device == pdev->device &&
653 lap->subvendor == pdev->subsystem_vendor &&
2dcb407e 654 lap->subdevice == pdev->subsystem_device)
eb4a2c7f 655 return ATA_CBL_PATA40_SHORT;
2dcb407e 656
fc085150
AC		 657 lap++;
658 }
659
1da177e4 660 /* check BIOS cable detect results */
2a88d1ac 661 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 662 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
663 if ((tmp & mask) == 0)
eb4a2c7f
AC		 664 return ATA_CBL_PATA40;
665 return ATA_CBL_PATA80;
1da177e4
LT		 666}
667
668/**
ccc4672a 669 * piix_pata_prereset - prereset for PATA host controller
cc0680a5 670 * @link: Target link
d4b2bab4 671 * @deadline: deadline jiffies for the operation
1da177e4 672 *
573db6b8
TH		 673 * LOCKING:
674 * None (inherited from caller).
675 */
cc0680a5 676static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
1da177e4 677{
cc0680a5 678 struct ata_port *ap = link->ap;
cca3974e 679 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 680
c961922b
AC		 681 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
682 return -ENOENT;
cc0680a5 683 return ata_std_prereset(link, deadline);
ccc4672a
TH		 684}
685
686static void piix_pata_error_handler(struct ata_port *ap)
687{
688 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
689 ata_std_postreset);
1da177e4
LT		 690}
691
1da177e4
LT		 692/**
693 * piix_set_piomode - Initialize host controller PATA PIO timings
694 * @ap: Port whose timings we are configuring
695 * @adev: um
1da177e4
LT		 696 *
697 * Set PIO mode for device, in host controller PCI config space.
698 *
699 * LOCKING:
700 * None (inherited from caller).
701 */
702
2dcb407e 703static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
1da177e4
LT		 704{
705 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 706 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 707 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 708 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 709 unsigned int slave_port = 0x44;
710 u16 master_data;
711 u8 slave_data;
669a5db4
JG		 712 u8 udma_enable;
713 int control = 0;
85cd7251 714
669a5db4
JG		 715 /*
716 * See Intel Document 298600-004 for the timing programing rules
717 * for ICH controllers.
718 */
1da177e4
LT		 719
720 static const /* ISP RTC */
721 u8 timings[][2] = { { 0, 0 },
722 { 0, 0 },
723 { 1, 0 },
724 { 2, 1 },
725 { 2, 3 }, };
726
669a5db4
JG		 727 if (pio >= 2)
728 control |= 1; /* TIME1 enable */
729 if (ata_pio_need_iordy(adev))
730 control |= 2; /* IE enable */
731
85cd7251 732 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 733 if (adev->class == ATA_DEV_ATA)
734 control |= 4; /* PPE enable */
735
a5bf5f5a
TH		 736 /* PIO configuration clears DTE unconditionally. It will be
737 * programmed in set_dmamode which is guaranteed to be called
738 * after set_piomode if any DMA mode is available.
739 */
1da177e4
LT		 740 pci_read_config_word(dev, master_port, &master_data);
741 if (is_slave) {
a5bf5f5a
TH		 742 /* clear TIME1|IE1|PPE1|DTE1 */
743 master_data &= 0xff0f;
669a5db4 744 /* Enable SITRE (seperate slave timing register) */
1da177e4 745 master_data |= 0x4000;
669a5db4
JG		 746 /* enable PPE1, IE1 and TIME1 as needed */
747 master_data |= (control << 4);
1da177e4 748 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 749 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4 750 /* Load the timing nibble for this slave */
a5bf5f5a
TH		 751 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
752 << (ap->port_no ? 4 : 0);
1da177e4 753 } else {
a5bf5f5a
TH		 754 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
755 master_data &= 0xccf0;
669a5db4
JG		 756 /* Enable PPE, IE and TIME as appropriate */
757 master_data |= control;
a5bf5f5a 758 /* load ISP and RCT */
1da177e4
LT		 759 master_data |=
760 (timings[pio][0] << 12) |
761 (timings[pio][1] << 8);
762 }
763 pci_write_config_word(dev, master_port, master_data);
764 if (is_slave)
765 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 766
767 /* Ensure the UDMA bit is off - it will be turned back on if
768 UDMA is selected */
85cd7251 769
669a5db4
JG		 770 if (ap->udma_mask) {
771 pci_read_config_byte(dev, 0x48, &udma_enable);
772 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
773 pci_write_config_byte(dev, 0x48, udma_enable);
774 }
1da177e4
LT		 775}
776
777/**
669a5db4 778 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 779 * @ap: Port whose timings we are configuring
669a5db4 780 * @adev: Drive in question
1da177e4 781 * @udma: udma mode, 0 - 6
c32a8fd7 782 * @isich: set if the chip is an ICH device
1da177e4
LT		 783 *
784 * Set UDMA mode for device, in host controller PCI config space.
785 *
786 * LOCKING:
787 * None (inherited from caller).
788 */
789
2dcb407e 790static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 791{
cca3974e 792 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 793 u8 master_port = ap->port_no ? 0x42 : 0x40;
794 u16 master_data;
795 u8 speed = adev->dma_mode;
796 int devid = adev->devno + 2 * ap->port_no;
dedf61db 797 u8 udma_enable = 0;
85cd7251 798
669a5db4
JG		 799 static const /* ISP RTC */
800 u8 timings[][2] = { { 0, 0 },
801 { 0, 0 },
802 { 1, 0 },
803 { 2, 1 },
804 { 2, 3 }, };
805
806 pci_read_config_word(dev, master_port, &master_data);
d2cdfc0d
AC		 807 if (ap->udma_mask)
808 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 809
810 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 811 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
812 u16 udma_timing;
813 u16 ideconf;
814 int u_clock, u_speed;
85cd7251 815
669a5db4 816 /*
2dcb407e 817 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 818 * selection of dividers
819 *
669a5db4 820 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 821 * except UDMA0 which is 00
669a5db4
JG		 822 */
823 u_speed = min(2 - (udma & 1), udma);
824 if (udma == 5)
825 u_clock = 0x1000; /* 100Mhz */
826 else if (udma > 2)
827 u_clock = 1; /* 66Mhz */
828 else
829 u_clock = 0; /* 33Mhz */
85cd7251 830
669a5db4 831 udma_enable |= (1 << devid);
85cd7251 832
669a5db4
JG		 833 /* Load the CT/RP selection */
834 pci_read_config_word(dev, 0x4A, &udma_timing);
835 udma_timing &= ~(3 << (4 * devid));
836 udma_timing |= u_speed << (4 * devid);
837 pci_write_config_word(dev, 0x4A, udma_timing);
838
85cd7251 839 if (isich) {
669a5db4
JG		 840 /* Select a 33/66/100Mhz clock */
841 pci_read_config_word(dev, 0x54, &ideconf);
842 ideconf &= ~(0x1001 << devid);
843 ideconf |= u_clock << devid;
844 /* For ICH or later we should set bit 10 for better
845 performance (WR_PingPong_En) */
846 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 847 }
1da177e4 848 } else {
669a5db4
JG		 849 /*
850 * MWDMA is driven by the PIO timings. We must also enable
851 * IORDY unconditionally along with TIME1. PPE has already
852 * been set when the PIO timing was set.
853 */
854 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
855 unsigned int control;
856 u8 slave_data;
857 const unsigned int needed_pio[3] = {
858 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
859 };
860 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 861
669a5db4 862 control = 3; /* IORDY|TIME1 */
85cd7251 863
669a5db4
JG		 864 /* If the drive MWDMA is faster than it can do PIO then
865 we must force PIO into PIO0 */
85cd7251 866
669a5db4
JG		 867 if (adev->pio_mode < needed_pio[mwdma])
868 /* Enable DMA timing only */
869 control |= 8; /* PIO cycles in PIO0 */
870
871 if (adev->devno) { /* Slave */
872 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
873 master_data |= control << 4;
874 pci_read_config_byte(dev, 0x44, &slave_data);
a5bf5f5a 875 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 876 /* Load the matching timing */
877 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
878 pci_write_config_byte(dev, 0x44, slave_data);
879 } else { /* Master */
85cd7251 880 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 881 and master timing bits */
882 master_data |= control;
883 master_data |=
884 (timings[pio][0] << 12) |
885 (timings[pio][1] << 8);
886 }
a5bf5f5a
TH		 887
888 if (ap->udma_mask) {
889 udma_enable &= ~(1 << devid);
890 pci_write_config_word(dev, master_port, master_data);
891 }
1da177e4 892 }
669a5db4
JG		 893 /* Don't scribble on 0x48 if the controller does not support UDMA */
894 if (ap->udma_mask)
895 pci_write_config_byte(dev, 0x48, udma_enable);
896}
897
898/**
899 * piix_set_dmamode - Initialize host controller PATA DMA timings
900 * @ap: Port whose timings we are configuring
901 * @adev: um
902 *
903 * Set MW/UDMA mode for device, in host controller PCI config space.
904 *
905 * LOCKING:
906 * None (inherited from caller).
907 */
908
2dcb407e 909static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 910{
911 do_pata_set_dmamode(ap, adev, 0);
912}
913
914/**
915 * ich_set_dmamode - Initialize host controller PATA DMA timings
916 * @ap: Port whose timings we are configuring
917 * @adev: um
918 *
919 * Set MW/UDMA mode for device, in host controller PCI config space.
920 *
921 * LOCKING:
922 * None (inherited from caller).
923 */
924
2dcb407e 925static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
669a5db4
JG		 926{
927 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 928}
929
b8b275ef 930#ifdef CONFIG_PM
8c3832eb
TH		 931static int piix_broken_suspend(void)
932{
1855256c 933 static const struct dmi_system_id sysids[] = {
4c74d4ec
TH		 934 {
935 .ident = "TECRA M3",
936 .matches = {
937 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
938 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
939 },
940 },
8c3832eb
TH		 941 {
942 .ident = "TECRA M5",
943 .matches = {
944 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
945 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
946 },
b8b275ef 947 },
5c08ea01
TH		 948 {
949 .ident = "TECRA M7",
950 .matches = {
951 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
952 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
953 },
954 },
3cc0b9d3
TH		 955 {
956 .ident = "Satellite U200",
957 .matches = {
958 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
959 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
960 },
961 },
62320e23
YC		 962 {
963 .ident = "Satellite Pro U200",
964 .matches = {
965 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
966 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
967 },
968 },
8c3832eb
TH		 969 {
970 .ident = "Satellite U205",
971 .matches = {
972 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
973 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
974 },
b8b275ef 975 },
de753e5e
TH		 976 {
977 .ident = "SATELLITE U205",
978 .matches = {
979 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
980 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
981 },
982 },
8c3832eb
TH		 983 {
984 .ident = "Portege M500",
985 .matches = {
986 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
987 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
988 },
b8b275ef 989 },
7d051548
JG		 990
991 { } /* terminate list */
8c3832eb 992 };
7abe79c3
TH		 993 static const char *oemstrs[] = {
994 "Tecra M3,",
995 };
996 int i;
8c3832eb
TH		 997
998 if (dmi_check_system(sysids))
999 return 1;
1000
7abe79c3
TH		 1001 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1002 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1003 return 1;
1004
8c3832eb
TH		 1005 return 0;
1006}
b8b275ef
TH		 1007
1008static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1009{
1010 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1011 unsigned long flags;
1012 int rc = 0;
1013
1014 rc = ata_host_suspend(host, mesg);
1015 if (rc)
1016 return rc;
1017
1018 /* Some braindamaged ACPI suspend implementations expect the
1019 * controller to be awake on entry; otherwise, it burns cpu
1020 * cycles and power trying to do something to the sleeping
1021 * beauty.
1022 */
8c3832eb 1023 if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) {
b8b275ef
TH		 1024 pci_save_state(pdev);
1025
1026 /* mark its power state as "unknown", since we don't
1027 * know if e.g. the BIOS will change its device state
1028 * when we suspend.
1029 */
1030 if (pdev->current_state == PCI_D0)
1031 pdev->current_state = PCI_UNKNOWN;
1032
1033 /* tell resume that it's waking up from broken suspend */
1034 spin_lock_irqsave(&host->lock, flags);
1035 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1036 spin_unlock_irqrestore(&host->lock, flags);
1037 } else
1038 ata_pci_device_do_suspend(pdev, mesg);
1039
1040 return 0;
1041}
1042
1043static int piix_pci_device_resume(struct pci_dev *pdev)
1044{
1045 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1046 unsigned long flags;
1047 int rc;
1048
1049 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1050 spin_lock_irqsave(&host->lock, flags);
1051 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1052 spin_unlock_irqrestore(&host->lock, flags);
1053
1054 pci_set_power_state(pdev, PCI_D0);
1055 pci_restore_state(pdev);
1056
1057 /* PCI device wasn't disabled during suspend. Use
0b62e13b
TH		 1058 * pci_reenable_device() to avoid affecting the enable
1059 * count.
b8b275ef 1060 */
0b62e13b 1061 rc = pci_reenable_device(pdev);
b8b275ef
TH		 1062 if (rc)
1063 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1064 "device after resume (%d)\n", rc);
1065 } else
1066 rc = ata_pci_device_do_resume(pdev);
1067
1068 if (rc == 0)
1069 ata_host_resume(host);
1070
1071 return rc;
1072}
1073#endif
1074
1da177e4
LT		 1075#define AHCI_PCI_BAR 5
1076#define AHCI_GLOBAL_CTL 0x04
1077#define AHCI_ENABLE (1 << 31)
1078static int piix_disable_ahci(struct pci_dev *pdev)
1079{
ea6ba10b 1080 void __iomem *mmio;
1da177e4
LT		 1081 u32 tmp;
1082 int rc = 0;
1083
1084 /* BUG: pci_enable_device has not yet been called. This
1085 * works because this device is usually set up by BIOS.
1086 */
1087
374b1873
JG		 1088 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1089 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 1090 return 0;
7b6dbd68 1091
374b1873 1092 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 1093 if (!mmio)
1094 return -ENOMEM;
7b6dbd68 1095
1da177e4
LT		 1096 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1097 if (tmp & AHCI_ENABLE) {
1098 tmp &= ~AHCI_ENABLE;
1099 writel(tmp, mmio + AHCI_GLOBAL_CTL);
1100
1101 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1102 if (tmp & AHCI_ENABLE)
1103 rc = -EIO;
1104 }
7b6dbd68 1105
374b1873 1106 pci_iounmap(pdev, mmio);
1da177e4
LT		 1107 return rc;
1108}
1109
c621b140
AC		 1110/**
1111 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 1112 * @ata_dev: the PCI device to check
2e9edbf8 1113 *
c621b140
AC		 1114 * Check for the present of 450NX errata #19 and errata #25. If
1115 * they are found return an error code so we can turn off DMA
1116 */
1117
1118static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1119{
1120 struct pci_dev *pdev = NULL;
1121 u16 cfg;
c621b140 1122 int no_piix_dma = 0;
2e9edbf8 1123
2dcb407e 1124 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
c621b140
AC		 1125 /* Look for 450NX PXB. Check for problem configurations
1126 A PCI quirk checks bit 6 already */
c621b140
AC		 1127 pci_read_config_word(pdev, 0x41, &cfg);
1128 /* Only on the original revision: IDE DMA can hang */
44c10138 1129 if (pdev->revision == 0x00)
c621b140
AC		 1130 no_piix_dma = 1;
1131 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
44c10138 1132 else if (cfg & (1<<14) && pdev->revision < 5)
c621b140
AC		 1133 no_piix_dma = 2;
1134 }
31a34fe7 1135 if (no_piix_dma)
c621b140 1136 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 1137 if (no_piix_dma == 2)
c621b140
AC		 1138 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1139 return no_piix_dma;
2e9edbf8 1140}
c621b140 1141
ea35d29e 1142static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 1143 struct ata_port_info *pinfo,
ea35d29e
JG		 1144 const struct piix_map_db *map_db)
1145{
1146 u16 pcs, new_pcs;
1147
1148 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1149
1150 new_pcs = pcs | map_db->port_enable;
1151
1152 if (new_pcs != pcs) {
1153 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1154 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1155 msleep(150);
1156 }
1157}
1158
d33f58b8 1159static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 1160 struct ata_port_info *pinfo,
1161 const struct piix_map_db *map_db)
d33f58b8 1162{
d96715c1 1163 struct piix_host_priv *hpriv = pinfo[0].private_data;
b4482a4b 1164 const int *map;
d33f58b8
TH		 1165 int i, invalid_map = 0;
1166 u8 map_value;
1167
1168 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1169
1170 map = map_db->map[map_value & map_db->mask];
1171
1172 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1173 for (i = 0; i < 4; i++) {
1174 switch (map[i]) {
1175 case RV:
1176 invalid_map = 1;
1177 printk(" XX");
1178 break;
1179
1180 case NA:
1181 printk(" --");
1182 break;
1183
1184 case IDE:
1185 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 1186 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 1187 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 1188 i++;
1189 printk(" IDE IDE");
1190 break;
1191
1192 default:
1193 printk(" P%d", map[i]);
1194 if (i & 1)
cca3974e 1195 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 1196 break;
1197 }
1198 }
1199 printk(" ]\n");
1200
1201 if (invalid_map)
1202 dev_printk(KERN_ERR, &pdev->dev,
1203 "invalid MAP value %u\n", map_value);
1204
d96715c1 1205 hpriv->map = map;
d33f58b8
TH		 1206}
1207
43a98f05
TH		 1208static void piix_iocfg_bit18_quirk(struct pci_dev *pdev)
1209{
1855256c 1210 static const struct dmi_system_id sysids[] = {
43a98f05
TH		 1211 {
1212 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1213 * isn't used to boot the system which
1214 * disables the channel.
1215 */
1216 .ident = "M570U",
1217 .matches = {
1218 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1219 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1220 },
1221 },
7d051548
JG		 1222
1223 { } /* terminate list */
43a98f05
TH		 1224 };
1225 u32 iocfg;
1226
1227 if (!dmi_check_system(sysids))
1228 return;
1229
1230 /* The datasheet says that bit 18 is NOOP but certain systems
1231 * seem to use it to disable a channel. Clear the bit on the
1232 * affected systems.
1233 */
1234 pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg);
1235 if (iocfg & (1 << 18)) {
1236 dev_printk(KERN_INFO, &pdev->dev,
1237 "applying IOCFG bit18 quirk\n");
1238 iocfg &= ~(1 << 18);
1239 pci_write_config_dword(pdev, PIIX_IOCFG, iocfg);
1240 }
1241}
1242
1da177e4
LT		 1243/**
1244 * piix_init_one - Register PIIX ATA PCI device with kernel services
1245 * @pdev: PCI device to register
1246 * @ent: Entry in piix_pci_tbl matching with @pdev
1247 *
1248 * Called from kernel PCI layer. We probe for combined mode (sigh),
1249 * and then hand over control to libata, for it to do the rest.
1250 *
1251 * LOCKING:
1252 * Inherited from PCI layer (may sleep).
1253 *
1254 * RETURNS:
1255 * Zero on success, or -ERRNO value.
1256 */
1257
2dcb407e 1258static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1259{
1260 static int printed_version;
24dc5f33 1261 struct device *dev = &pdev->dev;
d33f58b8 1262 struct ata_port_info port_info[2];
1626aeb8 1263 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
d96715c1 1264 struct piix_host_priv *hpriv;
cca3974e 1265 unsigned long port_flags;
1da177e4
LT		 1266
1267 if (!printed_version++)
6248e647
JG		 1268 dev_printk(KERN_DEBUG, &pdev->dev,
1269 "version " DRV_VERSION "\n");
1da177e4
LT		 1270
1271 /* no hotplugging support (FIXME) */
1272 if (!in_module_init)
1273 return -ENODEV;
1274
24dc5f33 1275 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
d96715c1
TH		 1276 if (!hpriv)
1277 return -ENOMEM;
1278
d33f58b8
TH		 1279 port_info[0] = piix_port_info[ent->driver_data];
1280 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1281 port_info[0].private_data = hpriv;
1282 port_info[1].private_data = hpriv;
1da177e4 1283
cca3974e 1284 port_flags = port_info[0].flags;
ff0fc146 1285
cca3974e 1286 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1287 u8 tmp;
1288 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1289 if (tmp == PIIX_AHCI_DEVICE) {
1290 int rc = piix_disable_ahci(pdev);
1291 if (rc)
1292 return rc;
1293 }
1da177e4
LT		 1294 }
1295
d33f58b8 1296 /* Initialize SATA map */
cca3974e 1297 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1298 piix_init_sata_map(pdev, port_info,
1299 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1300 piix_init_pcs(pdev, port_info,
1301 piix_map_db_table[ent->driver_data]);
ea35d29e 1302 }
1da177e4 1303
43a98f05
TH		 1304 /* apply IOCFG bit18 quirk */
1305 piix_iocfg_bit18_quirk(pdev);
1306
1da177e4
LT		 1307 /* On ICH5, some BIOSen disable the interrupt using the
1308 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1309 * On ICH6, this bit has the same effect, but only when
1310 * MSI is disabled (and it is disabled, as we don't use
1311 * message-signalled interrupts currently).
1312 */
cca3974e 1313 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1314 pci_intx(pdev, 1);
1da177e4 1315
c621b140
AC		 1316 if (piix_check_450nx_errata(pdev)) {
1317 /* This writes into the master table but it does not
1318 really matter for this errata as we will apply it to
1319 all the PIIX devices on the board */
d33f58b8
TH		 1320 port_info[0].mwdma_mask = 0;
1321 port_info[0].udma_mask = 0;
1322 port_info[1].mwdma_mask = 0;
1323 port_info[1].udma_mask = 0;
c621b140 1324 }
1626aeb8 1325 return ata_pci_init_one(pdev, ppi);
1da177e4
LT		 1326}
1327
1da177e4
LT		 1328static int __init piix_init(void)
1329{
1330 int rc;
1331
b7887196
PR		 1332 DPRINTK("pci_register_driver\n");
1333 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1334 if (rc)
1335 return rc;
1336
1337 in_module_init = 0;
1338
1339 DPRINTK("done\n");
1340 return 0;
1341}
1342
1da177e4
LT		 1343static void __exit piix_exit(void)
1344{
1345 pci_unregister_driver(&piix_pci_driver);
1346}
1347
1348module_init(piix_init);
1349module_exit(piix_exit);
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