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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
18 | * | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed AC |
40 | * Documentation |
41 | * Publically available from Intel web site. Errata documentation | |
42 | * is also publically available. As an aide to anyone hacking on this | |
2c5ff671 | 43 | * driver the list of errata that are relevant is below, going back to |
d96212ed AC |
44 | * PIIX4. Older device documentation is now a bit tricky to find. |
45 | * | |
46 | * The chipsets all follow very much the same design. The orginal Triton | |
47 | * series chipsets do _not_ support independant device timings, but this | |
48 | * is fixed in Triton II. With the odd mobile exception the chips then | |
49 | * change little except in gaining more modes until SATA arrives. This | |
50 | * driver supports only the chips with independant timing (that is those | |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix | |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
75 | * | |
76 | * Should have been BIOS fixed: | |
77 | * 450NX: errata #19 - DMA hangs on old 450NX | |
78 | * 450NX: errata #20 - DMA hangs on old 450NX | |
79 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
80 | * ICH3 errata #15 - IDE deadlock under high load | |
81 | * (BIOS must set dev 31 fn 0 bit 23) | |
82 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
83 | */ |
84 | ||
85 | #include <linux/kernel.h> | |
86 | #include <linux/module.h> | |
87 | #include <linux/pci.h> | |
88 | #include <linux/init.h> | |
89 | #include <linux/blkdev.h> | |
90 | #include <linux/delay.h> | |
6248e647 | 91 | #include <linux/device.h> |
1da177e4 LT |
92 | #include <scsi/scsi_host.h> |
93 | #include <linux/libata.h> | |
b8b275ef | 94 | #include <linux/dmi.h> |
1da177e4 LT |
95 | |
96 | #define DRV_NAME "ata_piix" | |
eb4a2c7f | 97 | #define DRV_VERSION "2.11" |
1da177e4 LT |
98 | |
99 | enum { | |
100 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
101 | ICH5_PMR = 0x90, /* port mapping register */ | |
102 | ICH5_PCS = 0x92, /* port control and status */ | |
7b6dbd68 | 103 | PIIX_SCC = 0x0A, /* sub-class code register */ |
1da177e4 | 104 | |
d4358048 | 105 | PIIX_FLAG_SCR = (1 << 26), /* SCR available */ |
ff0fc146 TH |
106 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
107 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ | |
1da177e4 | 108 | |
800b3996 TH |
109 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
110 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, | |
b3362f88 | 111 | |
1da177e4 LT |
112 | /* combined mode. if set, PATA is channel 0. |
113 | * if clear, PATA is channel 1. | |
114 | */ | |
6a690df5 HR |
115 | PIIX_PORT_ENABLED = (1 << 0), |
116 | PIIX_PORT_PRESENT = (1 << 4), | |
1da177e4 LT |
117 | |
118 | PIIX_80C_PRI = (1 << 5) | (1 << 4), | |
119 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
120 | ||
1d076e5b | 121 | /* controller IDs */ |
d2cdfc0d | 122 | piix_pata_33 = 0, /* PIIX4 at 33Mhz */ |
669a5db4 JG |
123 | ich_pata_33 = 1, /* ICH up to UDMA 33 only */ |
124 | ich_pata_66 = 2, /* ICH up to 66 Mhz */ | |
125 | ich_pata_100 = 3, /* ICH up to UDMA 100 */ | |
126 | ich_pata_133 = 4, /* ICH up to UDMA 133 */ | |
127 | ich5_sata = 5, | |
5e56a37c TH |
128 | ich6_sata = 6, |
129 | ich6_sata_ahci = 7, | |
130 | ich6m_sata_ahci = 8, | |
131 | ich8_sata_ahci = 9, | |
d2cdfc0d | 132 | piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ |
85cd7251 | 133 | |
d33f58b8 TH |
134 | /* constants for mapping table */ |
135 | P0 = 0, /* port 0 */ | |
136 | P1 = 1, /* port 1 */ | |
137 | P2 = 2, /* port 2 */ | |
138 | P3 = 3, /* port 3 */ | |
139 | IDE = -1, /* IDE */ | |
140 | NA = -2, /* not avaliable */ | |
141 | RV = -3, /* reserved */ | |
142 | ||
7b6dbd68 | 143 | PIIX_AHCI_DEVICE = 6, |
b8b275ef TH |
144 | |
145 | /* host->flags bits */ | |
146 | PIIX_HOST_BROKEN_SUSPEND = (1 << 24), | |
1da177e4 LT |
147 | }; |
148 | ||
d33f58b8 TH |
149 | struct piix_map_db { |
150 | const u32 mask; | |
73291a1c | 151 | const u16 port_enable; |
d33f58b8 TH |
152 | const int map[][4]; |
153 | }; | |
154 | ||
d96715c1 TH |
155 | struct piix_host_priv { |
156 | const int *map; | |
157 | }; | |
158 | ||
1da177e4 LT |
159 | static int piix_init_one (struct pci_dev *pdev, |
160 | const struct pci_device_id *ent); | |
ccc4672a | 161 | static void piix_pata_error_handler(struct ata_port *ap); |
669a5db4 JG |
162 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); |
163 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); | |
164 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev); | |
eb4a2c7f | 165 | static int ich_pata_cable_detect(struct ata_port *ap); |
b8b275ef TH |
166 | #ifdef CONFIG_PM |
167 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
168 | static int piix_pci_device_resume(struct pci_dev *pdev); | |
169 | #endif | |
1da177e4 LT |
170 | |
171 | static unsigned int in_module_init = 1; | |
172 | ||
3b7d697d | 173 | static const struct pci_device_id piix_pci_tbl[] = { |
d2cdfc0d AC |
174 | /* Intel PIIX3 for the 430HX etc */ |
175 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, | |
669a5db4 JG |
176 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
177 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ | |
178 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
669a5db4 JG |
179 | /* Intel PIIX4 */ |
180 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
181 | /* Intel PIIX4 */ | |
182 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
183 | /* Intel PIIX */ | |
184 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
185 | /* Intel ICH (i810, i815, i840) UDMA 66*/ | |
186 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, | |
187 | /* Intel ICH0 : UDMA 33*/ | |
188 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, | |
189 | /* Intel ICH2M */ | |
190 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
191 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ | |
192 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
193 | /* Intel ICH3M */ | |
194 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
195 | /* Intel ICH3 (E7500/1) UDMA 100 */ | |
196 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
197 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ | |
198 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
199 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
200 | /* Intel ICH5 */ | |
201 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, | |
202 | /* C-ICH (i810E2) */ | |
203 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
85cd7251 | 204 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
669a5db4 JG |
205 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
206 | /* ICH6 (and 6) (i915) UDMA 100 */ | |
207 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
208 | /* ICH7/7-R (i945, i975) UDMA 100*/ | |
209 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, | |
210 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
c1e6f28c CL |
211 | /* ICH8 Mobile PATA Controller */ |
212 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
1da177e4 LT |
213 | |
214 | /* NOTE: The following PCI ids must be kept in sync with the | |
215 | * list in drivers/pci/quirks.c. | |
216 | */ | |
217 | ||
1d076e5b | 218 | /* 82801EB (ICH5) */ |
1da177e4 | 219 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 220 | /* 82801EB (ICH5) */ |
1da177e4 | 221 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 222 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
5e56a37c | 223 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 224 | /* 6300ESB pretending RAID */ |
5e56a37c | 225 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 226 | /* 82801FB/FW (ICH6/ICH6W) */ |
1da177e4 | 227 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 228 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
1c24a412 | 229 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b TH |
230 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
231 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, | |
232 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ | |
1c24a412 | 233 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b | 234 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
c6446a4c | 235 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
f98b6573 | 236 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
1c24a412 | 237 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
f98b6573 | 238 | /* SATA Controller 1 IDE (ICH8) */ |
08f12edc | 239 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
f98b6573 | 240 | /* SATA Controller 2 IDE (ICH8) */ |
08f12edc | 241 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
f98b6573 | 242 | /* Mobile SATA Controller IDE (ICH8M) */ |
08f12edc | 243 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
f98b6573 JG |
244 | /* SATA Controller IDE (ICH9) */ |
245 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
246 | /* SATA Controller IDE (ICH9) */ | |
247 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
248 | /* SATA Controller IDE (ICH9) */ | |
249 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
250 | /* SATA Controller IDE (ICH9M) */ | |
251 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
252 | /* SATA Controller IDE (ICH9M) */ | |
253 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
254 | /* SATA Controller IDE (ICH9M) */ | |
255 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
1da177e4 LT |
256 | |
257 | { } /* terminate list */ | |
258 | }; | |
259 | ||
260 | static struct pci_driver piix_pci_driver = { | |
261 | .name = DRV_NAME, | |
262 | .id_table = piix_pci_tbl, | |
263 | .probe = piix_init_one, | |
264 | .remove = ata_pci_remove_one, | |
438ac6d5 | 265 | #ifdef CONFIG_PM |
b8b275ef TH |
266 | .suspend = piix_pci_device_suspend, |
267 | .resume = piix_pci_device_resume, | |
438ac6d5 | 268 | #endif |
1da177e4 LT |
269 | }; |
270 | ||
193515d5 | 271 | static struct scsi_host_template piix_sht = { |
1da177e4 LT |
272 | .module = THIS_MODULE, |
273 | .name = DRV_NAME, | |
274 | .ioctl = ata_scsi_ioctl, | |
275 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
276 | .can_queue = ATA_DEF_QUEUE, |
277 | .this_id = ATA_SHT_THIS_ID, | |
278 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
279 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
280 | .emulated = ATA_SHT_EMULATED, | |
281 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
282 | .proc_name = DRV_NAME, | |
283 | .dma_boundary = ATA_DMA_BOUNDARY, | |
284 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 285 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 286 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
287 | }; |
288 | ||
057ace5e | 289 | static const struct ata_port_operations piix_pata_ops = { |
1da177e4 LT |
290 | .port_disable = ata_port_disable, |
291 | .set_piomode = piix_set_piomode, | |
292 | .set_dmamode = piix_set_dmamode, | |
89bad589 | 293 | .mode_filter = ata_pci_default_filter, |
1da177e4 LT |
294 | |
295 | .tf_load = ata_tf_load, | |
296 | .tf_read = ata_tf_read, | |
297 | .check_status = ata_check_status, | |
298 | .exec_command = ata_exec_command, | |
299 | .dev_select = ata_std_dev_select, | |
300 | ||
1da177e4 LT |
301 | .bmdma_setup = ata_bmdma_setup, |
302 | .bmdma_start = ata_bmdma_start, | |
303 | .bmdma_stop = ata_bmdma_stop, | |
304 | .bmdma_status = ata_bmdma_status, | |
305 | .qc_prep = ata_qc_prep, | |
306 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 307 | .data_xfer = ata_data_xfer, |
1da177e4 | 308 | |
3f037db0 TH |
309 | .freeze = ata_bmdma_freeze, |
310 | .thaw = ata_bmdma_thaw, | |
ccc4672a | 311 | .error_handler = piix_pata_error_handler, |
3f037db0 | 312 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
eb4a2c7f | 313 | .cable_detect = ata_cable_40wire, |
1da177e4 LT |
314 | |
315 | .irq_handler = ata_interrupt, | |
316 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
317 | .irq_on = ata_irq_on, |
318 | .irq_ack = ata_irq_ack, | |
1da177e4 LT |
319 | |
320 | .port_start = ata_port_start, | |
1da177e4 LT |
321 | }; |
322 | ||
669a5db4 JG |
323 | static const struct ata_port_operations ich_pata_ops = { |
324 | .port_disable = ata_port_disable, | |
325 | .set_piomode = piix_set_piomode, | |
326 | .set_dmamode = ich_set_dmamode, | |
327 | .mode_filter = ata_pci_default_filter, | |
328 | ||
329 | .tf_load = ata_tf_load, | |
330 | .tf_read = ata_tf_read, | |
331 | .check_status = ata_check_status, | |
332 | .exec_command = ata_exec_command, | |
333 | .dev_select = ata_std_dev_select, | |
334 | ||
335 | .bmdma_setup = ata_bmdma_setup, | |
336 | .bmdma_start = ata_bmdma_start, | |
337 | .bmdma_stop = ata_bmdma_stop, | |
338 | .bmdma_status = ata_bmdma_status, | |
339 | .qc_prep = ata_qc_prep, | |
340 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 341 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
342 | |
343 | .freeze = ata_bmdma_freeze, | |
344 | .thaw = ata_bmdma_thaw, | |
eb4a2c7f | 345 | .error_handler = piix_pata_error_handler, |
669a5db4 | 346 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
eb4a2c7f | 347 | .cable_detect = ich_pata_cable_detect, |
669a5db4 JG |
348 | |
349 | .irq_handler = ata_interrupt, | |
350 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
351 | .irq_on = ata_irq_on, |
352 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
353 | |
354 | .port_start = ata_port_start, | |
669a5db4 JG |
355 | }; |
356 | ||
057ace5e | 357 | static const struct ata_port_operations piix_sata_ops = { |
1da177e4 LT |
358 | .port_disable = ata_port_disable, |
359 | ||
360 | .tf_load = ata_tf_load, | |
361 | .tf_read = ata_tf_read, | |
362 | .check_status = ata_check_status, | |
363 | .exec_command = ata_exec_command, | |
364 | .dev_select = ata_std_dev_select, | |
365 | ||
1da177e4 LT |
366 | .bmdma_setup = ata_bmdma_setup, |
367 | .bmdma_start = ata_bmdma_start, | |
368 | .bmdma_stop = ata_bmdma_stop, | |
369 | .bmdma_status = ata_bmdma_status, | |
370 | .qc_prep = ata_qc_prep, | |
371 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 372 | .data_xfer = ata_data_xfer, |
1da177e4 | 373 | |
3f037db0 TH |
374 | .freeze = ata_bmdma_freeze, |
375 | .thaw = ata_bmdma_thaw, | |
2f91d81d | 376 | .error_handler = ata_bmdma_error_handler, |
3f037db0 | 377 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
1da177e4 LT |
378 | |
379 | .irq_handler = ata_interrupt, | |
380 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
381 | .irq_on = ata_irq_on, |
382 | .irq_ack = ata_irq_ack, | |
1da177e4 LT |
383 | |
384 | .port_start = ata_port_start, | |
1da177e4 LT |
385 | }; |
386 | ||
d96715c1 | 387 | static const struct piix_map_db ich5_map_db = { |
d33f58b8 | 388 | .mask = 0x7, |
ea35d29e | 389 | .port_enable = 0x3, |
d33f58b8 TH |
390 | .map = { |
391 | /* PM PS SM SS MAP */ | |
392 | { P0, NA, P1, NA }, /* 000b */ | |
393 | { P1, NA, P0, NA }, /* 001b */ | |
394 | { RV, RV, RV, RV }, | |
395 | { RV, RV, RV, RV }, | |
396 | { P0, P1, IDE, IDE }, /* 100b */ | |
397 | { P1, P0, IDE, IDE }, /* 101b */ | |
398 | { IDE, IDE, P0, P1 }, /* 110b */ | |
399 | { IDE, IDE, P1, P0 }, /* 111b */ | |
400 | }, | |
401 | }; | |
402 | ||
d96715c1 | 403 | static const struct piix_map_db ich6_map_db = { |
d33f58b8 | 404 | .mask = 0x3, |
ea35d29e | 405 | .port_enable = 0xf, |
d33f58b8 TH |
406 | .map = { |
407 | /* PM PS SM SS MAP */ | |
79ea24e7 | 408 | { P0, P2, P1, P3 }, /* 00b */ |
d33f58b8 TH |
409 | { IDE, IDE, P1, P3 }, /* 01b */ |
410 | { P0, P2, IDE, IDE }, /* 10b */ | |
411 | { RV, RV, RV, RV }, | |
412 | }, | |
413 | }; | |
414 | ||
d96715c1 | 415 | static const struct piix_map_db ich6m_map_db = { |
d33f58b8 | 416 | .mask = 0x3, |
ea35d29e | 417 | .port_enable = 0x5, |
67083741 TH |
418 | |
419 | /* Map 01b isn't specified in the doc but some notebooks use | |
c6446a4c TH |
420 | * it anyway. MAP 01b have been spotted on both ICH6M and |
421 | * ICH7M. | |
67083741 TH |
422 | */ |
423 | .map = { | |
424 | /* PM PS SM SS MAP */ | |
e04b3b9d | 425 | { P0, P2, NA, NA }, /* 00b */ |
67083741 TH |
426 | { IDE, IDE, P1, P3 }, /* 01b */ |
427 | { P0, P2, IDE, IDE }, /* 10b */ | |
428 | { RV, RV, RV, RV }, | |
429 | }, | |
430 | }; | |
431 | ||
08f12edc JG |
432 | static const struct piix_map_db ich8_map_db = { |
433 | .mask = 0x3, | |
434 | .port_enable = 0x3, | |
08f12edc JG |
435 | .map = { |
436 | /* PM PS SM SS MAP */ | |
158f30c8 | 437 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
08f12edc | 438 | { RV, RV, RV, RV }, |
158f30c8 | 439 | { IDE, IDE, NA, NA }, /* 10b (IDE mode) */ |
08f12edc JG |
440 | { RV, RV, RV, RV }, |
441 | }, | |
442 | }; | |
443 | ||
d96715c1 TH |
444 | static const struct piix_map_db *piix_map_db_table[] = { |
445 | [ich5_sata] = &ich5_map_db, | |
d96715c1 TH |
446 | [ich6_sata] = &ich6_map_db, |
447 | [ich6_sata_ahci] = &ich6_map_db, | |
448 | [ich6m_sata_ahci] = &ich6m_map_db, | |
08f12edc | 449 | [ich8_sata_ahci] = &ich8_map_db, |
d96715c1 TH |
450 | }; |
451 | ||
1da177e4 | 452 | static struct ata_port_info piix_port_info[] = { |
d2cdfc0d | 453 | /* piix_pata_33: 0: PIIX4 at 33MHz */ |
1d076e5b TH |
454 | { |
455 | .sht = &piix_sht, | |
b3362f88 | 456 | .flags = PIIX_PATA_FLAGS, |
1d076e5b | 457 | .pio_mask = 0x1f, /* pio0-4 */ |
669a5db4 | 458 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
1d076e5b TH |
459 | .udma_mask = ATA_UDMA_MASK_40C, |
460 | .port_ops = &piix_pata_ops, | |
461 | }, | |
462 | ||
669a5db4 JG |
463 | /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/ |
464 | { | |
465 | .sht = &piix_sht, | |
b3362f88 | 466 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
467 | .pio_mask = 0x1f, /* pio 0-4 */ |
468 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ | |
469 | .udma_mask = ATA_UDMA2, /* UDMA33 */ | |
470 | .port_ops = &ich_pata_ops, | |
471 | }, | |
472 | /* ich_pata_66: 2 ICH controllers up to 66MHz */ | |
1da177e4 LT |
473 | { |
474 | .sht = &piix_sht, | |
b3362f88 | 475 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
476 | .pio_mask = 0x1f, /* pio 0-4 */ |
477 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ | |
478 | .udma_mask = ATA_UDMA4, | |
479 | .port_ops = &ich_pata_ops, | |
480 | }, | |
85cd7251 | 481 | |
669a5db4 JG |
482 | /* ich_pata_100: 3 */ |
483 | { | |
484 | .sht = &piix_sht, | |
b3362f88 | 485 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
1da177e4 | 486 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 | 487 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
669a5db4 JG |
488 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
489 | .port_ops = &ich_pata_ops, | |
1da177e4 LT |
490 | }, |
491 | ||
669a5db4 JG |
492 | /* ich_pata_133: 4 ICH with full UDMA6 */ |
493 | { | |
494 | .sht = &piix_sht, | |
b3362f88 | 495 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
669a5db4 JG |
496 | .pio_mask = 0x1f, /* pio 0-4 */ |
497 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ | |
498 | .udma_mask = ATA_UDMA6, /* UDMA133 */ | |
499 | .port_ops = &ich_pata_ops, | |
500 | }, | |
501 | ||
502 | /* ich5_sata: 5 */ | |
1da177e4 LT |
503 | { |
504 | .sht = &piix_sht, | |
228c1590 | 505 | .flags = PIIX_SATA_FLAGS, |
1da177e4 LT |
506 | .pio_mask = 0x1f, /* pio0-4 */ |
507 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 508 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
509 | .port_ops = &piix_sata_ops, |
510 | }, | |
511 | ||
5e56a37c | 512 | /* ich6_sata: 6 */ |
1da177e4 LT |
513 | { |
514 | .sht = &piix_sht, | |
b3362f88 | 515 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, |
1da177e4 LT |
516 | .pio_mask = 0x1f, /* pio0-4 */ |
517 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 518 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
519 | .port_ops = &piix_sata_ops, |
520 | }, | |
521 | ||
5e56a37c | 522 | /* ich6_sata_ahci: 7 */ |
c368ca4e JG |
523 | { |
524 | .sht = &piix_sht, | |
b3362f88 | 525 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
d33f58b8 | 526 | PIIX_FLAG_AHCI, |
c368ca4e JG |
527 | .pio_mask = 0x1f, /* pio0-4 */ |
528 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 529 | .udma_mask = ATA_UDMA6, |
c368ca4e JG |
530 | .port_ops = &piix_sata_ops, |
531 | }, | |
1d076e5b | 532 | |
5e56a37c | 533 | /* ich6m_sata_ahci: 8 */ |
1d076e5b TH |
534 | { |
535 | .sht = &piix_sht, | |
b3362f88 | 536 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
d33f58b8 | 537 | PIIX_FLAG_AHCI, |
1d076e5b TH |
538 | .pio_mask = 0x1f, /* pio0-4 */ |
539 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 540 | .udma_mask = ATA_UDMA6, |
1d076e5b TH |
541 | .port_ops = &piix_sata_ops, |
542 | }, | |
08f12edc | 543 | |
5e56a37c | 544 | /* ich8_sata_ahci: 9 */ |
08f12edc JG |
545 | { |
546 | .sht = &piix_sht, | |
b3362f88 | 547 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
08f12edc JG |
548 | PIIX_FLAG_AHCI, |
549 | .pio_mask = 0x1f, /* pio0-4 */ | |
550 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 551 | .udma_mask = ATA_UDMA6, |
08f12edc JG |
552 | .port_ops = &piix_sata_ops, |
553 | }, | |
669a5db4 | 554 | |
d2cdfc0d AC |
555 | /* piix_pata_mwdma: 10: PIIX3 MWDMA only */ |
556 | { | |
557 | .sht = &piix_sht, | |
558 | .flags = PIIX_PATA_FLAGS, | |
559 | .pio_mask = 0x1f, /* pio0-4 */ | |
560 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
561 | .port_ops = &piix_pata_ops, | |
562 | }, | |
1da177e4 LT |
563 | }; |
564 | ||
565 | static struct pci_bits piix_enable_bits[] = { | |
566 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
567 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
568 | }; | |
569 | ||
570 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
571 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
572 | MODULE_LICENSE("GPL"); | |
573 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
574 | MODULE_VERSION(DRV_VERSION); | |
575 | ||
fc085150 AC |
576 | struct ich_laptop { |
577 | u16 device; | |
578 | u16 subvendor; | |
579 | u16 subdevice; | |
580 | }; | |
581 | ||
582 | /* | |
583 | * List of laptops that use short cables rather than 80 wire | |
584 | */ | |
585 | ||
586 | static const struct ich_laptop ich_laptop[] = { | |
587 | /* devid, subvendor, subdev */ | |
588 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ | |
babfb682 | 589 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
12340106 | 590 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
b33620f9 | 591 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
fc085150 AC |
592 | /* end marker */ |
593 | { 0, } | |
594 | }; | |
595 | ||
1da177e4 | 596 | /** |
eb4a2c7f | 597 | * ich_pata_cable_detect - Probe host controller cable detect info |
1da177e4 LT |
598 | * @ap: Port for which cable detect info is desired |
599 | * | |
600 | * Read 80c cable indicator from ATA PCI device's PCI config | |
601 | * register. This register is normally set by firmware (BIOS). | |
602 | * | |
603 | * LOCKING: | |
604 | * None (inherited from caller). | |
605 | */ | |
669a5db4 | 606 | |
eb4a2c7f | 607 | static int ich_pata_cable_detect(struct ata_port *ap) |
1da177e4 | 608 | { |
cca3974e | 609 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
fc085150 | 610 | const struct ich_laptop *lap = &ich_laptop[0]; |
1da177e4 LT |
611 | u8 tmp, mask; |
612 | ||
fc085150 AC |
613 | /* Check for specials - Acer Aspire 5602WLMi */ |
614 | while (lap->device) { | |
615 | if (lap->device == pdev->device && | |
616 | lap->subvendor == pdev->subsystem_vendor && | |
617 | lap->subdevice == pdev->subsystem_device) { | |
eb4a2c7f | 618 | return ATA_CBL_PATA40_SHORT; |
fc085150 AC |
619 | } |
620 | lap++; | |
621 | } | |
622 | ||
1da177e4 | 623 | /* check BIOS cable detect results */ |
2a88d1ac | 624 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
1da177e4 LT |
625 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
626 | if ((tmp & mask) == 0) | |
eb4a2c7f AC |
627 | return ATA_CBL_PATA40; |
628 | return ATA_CBL_PATA80; | |
1da177e4 LT |
629 | } |
630 | ||
631 | /** | |
ccc4672a | 632 | * piix_pata_prereset - prereset for PATA host controller |
573db6b8 | 633 | * @ap: Target port |
d4b2bab4 | 634 | * @deadline: deadline jiffies for the operation |
1da177e4 | 635 | * |
573db6b8 TH |
636 | * LOCKING: |
637 | * None (inherited from caller). | |
638 | */ | |
d4b2bab4 | 639 | static int piix_pata_prereset(struct ata_port *ap, unsigned long deadline) |
1da177e4 | 640 | { |
cca3974e | 641 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 642 | |
c961922b AC |
643 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
644 | return -ENOENT; | |
d4b2bab4 | 645 | return ata_std_prereset(ap, deadline); |
ccc4672a TH |
646 | } |
647 | ||
648 | static void piix_pata_error_handler(struct ata_port *ap) | |
649 | { | |
650 | ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, | |
651 | ata_std_postreset); | |
1da177e4 LT |
652 | } |
653 | ||
1da177e4 LT |
654 | /** |
655 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
656 | * @ap: Port whose timings we are configuring | |
657 | * @adev: um | |
1da177e4 LT |
658 | * |
659 | * Set PIO mode for device, in host controller PCI config space. | |
660 | * | |
661 | * LOCKING: | |
662 | * None (inherited from caller). | |
663 | */ | |
664 | ||
665 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
666 | { | |
667 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
cca3974e | 668 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
1da177e4 | 669 | unsigned int is_slave = (adev->devno != 0); |
2a88d1ac | 670 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
1da177e4 LT |
671 | unsigned int slave_port = 0x44; |
672 | u16 master_data; | |
673 | u8 slave_data; | |
669a5db4 JG |
674 | u8 udma_enable; |
675 | int control = 0; | |
85cd7251 | 676 | |
669a5db4 JG |
677 | /* |
678 | * See Intel Document 298600-004 for the timing programing rules | |
679 | * for ICH controllers. | |
680 | */ | |
1da177e4 LT |
681 | |
682 | static const /* ISP RTC */ | |
683 | u8 timings[][2] = { { 0, 0 }, | |
684 | { 0, 0 }, | |
685 | { 1, 0 }, | |
686 | { 2, 1 }, | |
687 | { 2, 3 }, }; | |
688 | ||
669a5db4 JG |
689 | if (pio >= 2) |
690 | control |= 1; /* TIME1 enable */ | |
691 | if (ata_pio_need_iordy(adev)) | |
692 | control |= 2; /* IE enable */ | |
693 | ||
85cd7251 | 694 | /* Intel specifies that the PPE functionality is for disk only */ |
669a5db4 JG |
695 | if (adev->class == ATA_DEV_ATA) |
696 | control |= 4; /* PPE enable */ | |
697 | ||
a5bf5f5a TH |
698 | /* PIO configuration clears DTE unconditionally. It will be |
699 | * programmed in set_dmamode which is guaranteed to be called | |
700 | * after set_piomode if any DMA mode is available. | |
701 | */ | |
1da177e4 LT |
702 | pci_read_config_word(dev, master_port, &master_data); |
703 | if (is_slave) { | |
a5bf5f5a TH |
704 | /* clear TIME1|IE1|PPE1|DTE1 */ |
705 | master_data &= 0xff0f; | |
669a5db4 | 706 | /* Enable SITRE (seperate slave timing register) */ |
1da177e4 | 707 | master_data |= 0x4000; |
669a5db4 JG |
708 | /* enable PPE1, IE1 and TIME1 as needed */ |
709 | master_data |= (control << 4); | |
1da177e4 | 710 | pci_read_config_byte(dev, slave_port, &slave_data); |
2a88d1ac | 711 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 | 712 | /* Load the timing nibble for this slave */ |
a5bf5f5a TH |
713 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
714 | << (ap->port_no ? 4 : 0); | |
1da177e4 | 715 | } else { |
a5bf5f5a TH |
716 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
717 | master_data &= 0xccf0; | |
669a5db4 JG |
718 | /* Enable PPE, IE and TIME as appropriate */ |
719 | master_data |= control; | |
a5bf5f5a | 720 | /* load ISP and RCT */ |
1da177e4 LT |
721 | master_data |= |
722 | (timings[pio][0] << 12) | | |
723 | (timings[pio][1] << 8); | |
724 | } | |
725 | pci_write_config_word(dev, master_port, master_data); | |
726 | if (is_slave) | |
727 | pci_write_config_byte(dev, slave_port, slave_data); | |
669a5db4 JG |
728 | |
729 | /* Ensure the UDMA bit is off - it will be turned back on if | |
730 | UDMA is selected */ | |
85cd7251 | 731 | |
669a5db4 JG |
732 | if (ap->udma_mask) { |
733 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
734 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); | |
735 | pci_write_config_byte(dev, 0x48, udma_enable); | |
736 | } | |
1da177e4 LT |
737 | } |
738 | ||
739 | /** | |
669a5db4 | 740 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
1da177e4 | 741 | * @ap: Port whose timings we are configuring |
669a5db4 | 742 | * @adev: Drive in question |
1da177e4 | 743 | * @udma: udma mode, 0 - 6 |
c32a8fd7 | 744 | * @isich: set if the chip is an ICH device |
1da177e4 LT |
745 | * |
746 | * Set UDMA mode for device, in host controller PCI config space. | |
747 | * | |
748 | * LOCKING: | |
749 | * None (inherited from caller). | |
750 | */ | |
751 | ||
669a5db4 | 752 | static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich) |
1da177e4 | 753 | { |
cca3974e | 754 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
669a5db4 JG |
755 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
756 | u16 master_data; | |
757 | u8 speed = adev->dma_mode; | |
758 | int devid = adev->devno + 2 * ap->port_no; | |
dedf61db | 759 | u8 udma_enable = 0; |
85cd7251 | 760 | |
669a5db4 JG |
761 | static const /* ISP RTC */ |
762 | u8 timings[][2] = { { 0, 0 }, | |
763 | { 0, 0 }, | |
764 | { 1, 0 }, | |
765 | { 2, 1 }, | |
766 | { 2, 3 }, }; | |
767 | ||
768 | pci_read_config_word(dev, master_port, &master_data); | |
d2cdfc0d AC |
769 | if (ap->udma_mask) |
770 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
1da177e4 LT |
771 | |
772 | if (speed >= XFER_UDMA_0) { | |
669a5db4 JG |
773 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
774 | u16 udma_timing; | |
775 | u16 ideconf; | |
776 | int u_clock, u_speed; | |
85cd7251 | 777 | |
669a5db4 JG |
778 | /* |
779 | * UDMA is handled by a combination of clock switching and | |
85cd7251 JG |
780 | * selection of dividers |
781 | * | |
669a5db4 | 782 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
85cd7251 | 783 | * except UDMA0 which is 00 |
669a5db4 JG |
784 | */ |
785 | u_speed = min(2 - (udma & 1), udma); | |
786 | if (udma == 5) | |
787 | u_clock = 0x1000; /* 100Mhz */ | |
788 | else if (udma > 2) | |
789 | u_clock = 1; /* 66Mhz */ | |
790 | else | |
791 | u_clock = 0; /* 33Mhz */ | |
85cd7251 | 792 | |
669a5db4 | 793 | udma_enable |= (1 << devid); |
85cd7251 | 794 | |
669a5db4 JG |
795 | /* Load the CT/RP selection */ |
796 | pci_read_config_word(dev, 0x4A, &udma_timing); | |
797 | udma_timing &= ~(3 << (4 * devid)); | |
798 | udma_timing |= u_speed << (4 * devid); | |
799 | pci_write_config_word(dev, 0x4A, udma_timing); | |
800 | ||
85cd7251 | 801 | if (isich) { |
669a5db4 JG |
802 | /* Select a 33/66/100Mhz clock */ |
803 | pci_read_config_word(dev, 0x54, &ideconf); | |
804 | ideconf &= ~(0x1001 << devid); | |
805 | ideconf |= u_clock << devid; | |
806 | /* For ICH or later we should set bit 10 for better | |
807 | performance (WR_PingPong_En) */ | |
808 | pci_write_config_word(dev, 0x54, ideconf); | |
1da177e4 | 809 | } |
1da177e4 | 810 | } else { |
669a5db4 JG |
811 | /* |
812 | * MWDMA is driven by the PIO timings. We must also enable | |
813 | * IORDY unconditionally along with TIME1. PPE has already | |
814 | * been set when the PIO timing was set. | |
815 | */ | |
816 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
817 | unsigned int control; | |
818 | u8 slave_data; | |
819 | const unsigned int needed_pio[3] = { | |
820 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
821 | }; | |
822 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
85cd7251 | 823 | |
669a5db4 | 824 | control = 3; /* IORDY|TIME1 */ |
85cd7251 | 825 | |
669a5db4 JG |
826 | /* If the drive MWDMA is faster than it can do PIO then |
827 | we must force PIO into PIO0 */ | |
85cd7251 | 828 | |
669a5db4 JG |
829 | if (adev->pio_mode < needed_pio[mwdma]) |
830 | /* Enable DMA timing only */ | |
831 | control |= 8; /* PIO cycles in PIO0 */ | |
832 | ||
833 | if (adev->devno) { /* Slave */ | |
834 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ | |
835 | master_data |= control << 4; | |
836 | pci_read_config_byte(dev, 0x44, &slave_data); | |
a5bf5f5a | 837 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 JG |
838 | /* Load the matching timing */ |
839 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
840 | pci_write_config_byte(dev, 0x44, slave_data); | |
841 | } else { /* Master */ | |
85cd7251 | 842 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
669a5db4 JG |
843 | and master timing bits */ |
844 | master_data |= control; | |
845 | master_data |= | |
846 | (timings[pio][0] << 12) | | |
847 | (timings[pio][1] << 8); | |
848 | } | |
a5bf5f5a TH |
849 | |
850 | if (ap->udma_mask) { | |
851 | udma_enable &= ~(1 << devid); | |
852 | pci_write_config_word(dev, master_port, master_data); | |
853 | } | |
1da177e4 | 854 | } |
669a5db4 JG |
855 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
856 | if (ap->udma_mask) | |
857 | pci_write_config_byte(dev, 0x48, udma_enable); | |
858 | } | |
859 | ||
860 | /** | |
861 | * piix_set_dmamode - Initialize host controller PATA DMA timings | |
862 | * @ap: Port whose timings we are configuring | |
863 | * @adev: um | |
864 | * | |
865 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
866 | * | |
867 | * LOCKING: | |
868 | * None (inherited from caller). | |
869 | */ | |
870 | ||
871 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
872 | { | |
873 | do_pata_set_dmamode(ap, adev, 0); | |
874 | } | |
875 | ||
876 | /** | |
877 | * ich_set_dmamode - Initialize host controller PATA DMA timings | |
878 | * @ap: Port whose timings we are configuring | |
879 | * @adev: um | |
880 | * | |
881 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
882 | * | |
883 | * LOCKING: | |
884 | * None (inherited from caller). | |
885 | */ | |
886 | ||
887 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
888 | { | |
889 | do_pata_set_dmamode(ap, adev, 1); | |
1da177e4 LT |
890 | } |
891 | ||
b8b275ef TH |
892 | #ifdef CONFIG_PM |
893 | static struct dmi_system_id piix_broken_suspend_dmi_table[] = { | |
894 | { | |
895 | .ident = "TECRA M5", | |
896 | .matches = { | |
897 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
898 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), | |
899 | }, | |
900 | }, | |
901 | { | |
902 | .ident = "Satellite U200", | |
903 | .matches = { | |
904 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
905 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), | |
906 | }, | |
907 | }, | |
908 | { | |
909 | .ident = "Satellite U205", | |
910 | .matches = { | |
911 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
912 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), | |
913 | }, | |
914 | }, | |
915 | { | |
916 | .ident = "Portege M500", | |
917 | .matches = { | |
918 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
919 | DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), | |
920 | }, | |
921 | }, | |
922 | { } | |
923 | }; | |
924 | ||
925 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
926 | { | |
927 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
928 | unsigned long flags; | |
929 | int rc = 0; | |
930 | ||
931 | rc = ata_host_suspend(host, mesg); | |
932 | if (rc) | |
933 | return rc; | |
934 | ||
935 | /* Some braindamaged ACPI suspend implementations expect the | |
936 | * controller to be awake on entry; otherwise, it burns cpu | |
937 | * cycles and power trying to do something to the sleeping | |
938 | * beauty. | |
939 | */ | |
940 | if (dmi_check_system(piix_broken_suspend_dmi_table) && | |
941 | mesg.event == PM_EVENT_SUSPEND) { | |
942 | pci_save_state(pdev); | |
943 | ||
944 | /* mark its power state as "unknown", since we don't | |
945 | * know if e.g. the BIOS will change its device state | |
946 | * when we suspend. | |
947 | */ | |
948 | if (pdev->current_state == PCI_D0) | |
949 | pdev->current_state = PCI_UNKNOWN; | |
950 | ||
951 | /* tell resume that it's waking up from broken suspend */ | |
952 | spin_lock_irqsave(&host->lock, flags); | |
953 | host->flags |= PIIX_HOST_BROKEN_SUSPEND; | |
954 | spin_unlock_irqrestore(&host->lock, flags); | |
955 | } else | |
956 | ata_pci_device_do_suspend(pdev, mesg); | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
961 | static int piix_pci_device_resume(struct pci_dev *pdev) | |
962 | { | |
963 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
964 | unsigned long flags; | |
965 | int rc; | |
966 | ||
967 | if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { | |
968 | spin_lock_irqsave(&host->lock, flags); | |
969 | host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; | |
970 | spin_unlock_irqrestore(&host->lock, flags); | |
971 | ||
972 | pci_set_power_state(pdev, PCI_D0); | |
973 | pci_restore_state(pdev); | |
974 | ||
975 | /* PCI device wasn't disabled during suspend. Use | |
0b62e13b TH |
976 | * pci_reenable_device() to avoid affecting the enable |
977 | * count. | |
b8b275ef | 978 | */ |
0b62e13b | 979 | rc = pci_reenable_device(pdev); |
b8b275ef TH |
980 | if (rc) |
981 | dev_printk(KERN_ERR, &pdev->dev, "failed to enable " | |
982 | "device after resume (%d)\n", rc); | |
983 | } else | |
984 | rc = ata_pci_device_do_resume(pdev); | |
985 | ||
986 | if (rc == 0) | |
987 | ata_host_resume(host); | |
988 | ||
989 | return rc; | |
990 | } | |
991 | #endif | |
992 | ||
1da177e4 LT |
993 | #define AHCI_PCI_BAR 5 |
994 | #define AHCI_GLOBAL_CTL 0x04 | |
995 | #define AHCI_ENABLE (1 << 31) | |
996 | static int piix_disable_ahci(struct pci_dev *pdev) | |
997 | { | |
ea6ba10b | 998 | void __iomem *mmio; |
1da177e4 LT |
999 | u32 tmp; |
1000 | int rc = 0; | |
1001 | ||
1002 | /* BUG: pci_enable_device has not yet been called. This | |
1003 | * works because this device is usually set up by BIOS. | |
1004 | */ | |
1005 | ||
374b1873 JG |
1006 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
1007 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 1008 | return 0; |
7b6dbd68 | 1009 | |
374b1873 | 1010 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
1011 | if (!mmio) |
1012 | return -ENOMEM; | |
7b6dbd68 | 1013 | |
1da177e4 LT |
1014 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
1015 | if (tmp & AHCI_ENABLE) { | |
1016 | tmp &= ~AHCI_ENABLE; | |
1017 | writel(tmp, mmio + AHCI_GLOBAL_CTL); | |
1018 | ||
1019 | tmp = readl(mmio + AHCI_GLOBAL_CTL); | |
1020 | if (tmp & AHCI_ENABLE) | |
1021 | rc = -EIO; | |
1022 | } | |
7b6dbd68 | 1023 | |
374b1873 | 1024 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
1025 | return rc; |
1026 | } | |
1027 | ||
c621b140 AC |
1028 | /** |
1029 | * piix_check_450nx_errata - Check for problem 450NX setup | |
c893a3ae | 1030 | * @ata_dev: the PCI device to check |
2e9edbf8 | 1031 | * |
c621b140 AC |
1032 | * Check for the present of 450NX errata #19 and errata #25. If |
1033 | * they are found return an error code so we can turn off DMA | |
1034 | */ | |
1035 | ||
1036 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) | |
1037 | { | |
1038 | struct pci_dev *pdev = NULL; | |
1039 | u16 cfg; | |
c621b140 | 1040 | int no_piix_dma = 0; |
2e9edbf8 | 1041 | |
c621b140 AC |
1042 | while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) |
1043 | { | |
1044 | /* Look for 450NX PXB. Check for problem configurations | |
1045 | A PCI quirk checks bit 6 already */ | |
c621b140 AC |
1046 | pci_read_config_word(pdev, 0x41, &cfg); |
1047 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 1048 | if (pdev->revision == 0x00) |
c621b140 AC |
1049 | no_piix_dma = 1; |
1050 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 1051 | else if (cfg & (1<<14) && pdev->revision < 5) |
c621b140 AC |
1052 | no_piix_dma = 2; |
1053 | } | |
31a34fe7 | 1054 | if (no_piix_dma) |
c621b140 | 1055 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
31a34fe7 | 1056 | if (no_piix_dma == 2) |
c621b140 AC |
1057 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
1058 | return no_piix_dma; | |
2e9edbf8 | 1059 | } |
c621b140 | 1060 | |
ea35d29e | 1061 | static void __devinit piix_init_pcs(struct pci_dev *pdev, |
9dd9c164 | 1062 | struct ata_port_info *pinfo, |
ea35d29e JG |
1063 | const struct piix_map_db *map_db) |
1064 | { | |
1065 | u16 pcs, new_pcs; | |
1066 | ||
1067 | pci_read_config_word(pdev, ICH5_PCS, &pcs); | |
1068 | ||
1069 | new_pcs = pcs | map_db->port_enable; | |
1070 | ||
1071 | if (new_pcs != pcs) { | |
1072 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); | |
1073 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); | |
1074 | msleep(150); | |
1075 | } | |
1076 | } | |
1077 | ||
d33f58b8 | 1078 | static void __devinit piix_init_sata_map(struct pci_dev *pdev, |
d96715c1 TH |
1079 | struct ata_port_info *pinfo, |
1080 | const struct piix_map_db *map_db) | |
d33f58b8 | 1081 | { |
d96715c1 | 1082 | struct piix_host_priv *hpriv = pinfo[0].private_data; |
d33f58b8 TH |
1083 | const unsigned int *map; |
1084 | int i, invalid_map = 0; | |
1085 | u8 map_value; | |
1086 | ||
1087 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); | |
1088 | ||
1089 | map = map_db->map[map_value & map_db->mask]; | |
1090 | ||
1091 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); | |
1092 | for (i = 0; i < 4; i++) { | |
1093 | switch (map[i]) { | |
1094 | case RV: | |
1095 | invalid_map = 1; | |
1096 | printk(" XX"); | |
1097 | break; | |
1098 | ||
1099 | case NA: | |
1100 | printk(" --"); | |
1101 | break; | |
1102 | ||
1103 | case IDE: | |
1104 | WARN_ON((i & 1) || map[i + 1] != IDE); | |
669a5db4 | 1105 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
f814b75f | 1106 | pinfo[i / 2].private_data = hpriv; |
d33f58b8 TH |
1107 | i++; |
1108 | printk(" IDE IDE"); | |
1109 | break; | |
1110 | ||
1111 | default: | |
1112 | printk(" P%d", map[i]); | |
1113 | if (i & 1) | |
cca3974e | 1114 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
d33f58b8 TH |
1115 | break; |
1116 | } | |
1117 | } | |
1118 | printk(" ]\n"); | |
1119 | ||
1120 | if (invalid_map) | |
1121 | dev_printk(KERN_ERR, &pdev->dev, | |
1122 | "invalid MAP value %u\n", map_value); | |
1123 | ||
d96715c1 | 1124 | hpriv->map = map; |
d33f58b8 TH |
1125 | } |
1126 | ||
1da177e4 LT |
1127 | /** |
1128 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
1129 | * @pdev: PCI device to register | |
1130 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
1131 | * | |
1132 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
1133 | * and then hand over control to libata, for it to do the rest. | |
1134 | * | |
1135 | * LOCKING: | |
1136 | * Inherited from PCI layer (may sleep). | |
1137 | * | |
1138 | * RETURNS: | |
1139 | * Zero on success, or -ERRNO value. | |
1140 | */ | |
1141 | ||
1142 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1143 | { | |
1144 | static int printed_version; | |
24dc5f33 | 1145 | struct device *dev = &pdev->dev; |
d33f58b8 | 1146 | struct ata_port_info port_info[2]; |
1626aeb8 | 1147 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
d96715c1 | 1148 | struct piix_host_priv *hpriv; |
cca3974e | 1149 | unsigned long port_flags; |
1da177e4 LT |
1150 | |
1151 | if (!printed_version++) | |
6248e647 JG |
1152 | dev_printk(KERN_DEBUG, &pdev->dev, |
1153 | "version " DRV_VERSION "\n"); | |
1da177e4 LT |
1154 | |
1155 | /* no hotplugging support (FIXME) */ | |
1156 | if (!in_module_init) | |
1157 | return -ENODEV; | |
1158 | ||
24dc5f33 | 1159 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
d96715c1 TH |
1160 | if (!hpriv) |
1161 | return -ENOMEM; | |
1162 | ||
d33f58b8 TH |
1163 | port_info[0] = piix_port_info[ent->driver_data]; |
1164 | port_info[1] = piix_port_info[ent->driver_data]; | |
d96715c1 TH |
1165 | port_info[0].private_data = hpriv; |
1166 | port_info[1].private_data = hpriv; | |
1da177e4 | 1167 | |
cca3974e | 1168 | port_flags = port_info[0].flags; |
ff0fc146 | 1169 | |
cca3974e | 1170 | if (port_flags & PIIX_FLAG_AHCI) { |
8a60a071 JG |
1171 | u8 tmp; |
1172 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); | |
1173 | if (tmp == PIIX_AHCI_DEVICE) { | |
1174 | int rc = piix_disable_ahci(pdev); | |
1175 | if (rc) | |
1176 | return rc; | |
1177 | } | |
1da177e4 LT |
1178 | } |
1179 | ||
d33f58b8 | 1180 | /* Initialize SATA map */ |
cca3974e | 1181 | if (port_flags & ATA_FLAG_SATA) { |
d96715c1 TH |
1182 | piix_init_sata_map(pdev, port_info, |
1183 | piix_map_db_table[ent->driver_data]); | |
9dd9c164 TH |
1184 | piix_init_pcs(pdev, port_info, |
1185 | piix_map_db_table[ent->driver_data]); | |
ea35d29e | 1186 | } |
1da177e4 LT |
1187 | |
1188 | /* On ICH5, some BIOSen disable the interrupt using the | |
1189 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
1190 | * On ICH6, this bit has the same effect, but only when | |
1191 | * MSI is disabled (and it is disabled, as we don't use | |
1192 | * message-signalled interrupts currently). | |
1193 | */ | |
cca3974e | 1194 | if (port_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ff | 1195 | pci_intx(pdev, 1); |
1da177e4 | 1196 | |
c621b140 AC |
1197 | if (piix_check_450nx_errata(pdev)) { |
1198 | /* This writes into the master table but it does not | |
1199 | really matter for this errata as we will apply it to | |
1200 | all the PIIX devices on the board */ | |
d33f58b8 TH |
1201 | port_info[0].mwdma_mask = 0; |
1202 | port_info[0].udma_mask = 0; | |
1203 | port_info[1].mwdma_mask = 0; | |
1204 | port_info[1].udma_mask = 0; | |
c621b140 | 1205 | } |
1626aeb8 | 1206 | return ata_pci_init_one(pdev, ppi); |
1da177e4 LT |
1207 | } |
1208 | ||
1da177e4 LT |
1209 | static int __init piix_init(void) |
1210 | { | |
1211 | int rc; | |
1212 | ||
b7887196 PR |
1213 | DPRINTK("pci_register_driver\n"); |
1214 | rc = pci_register_driver(&piix_pci_driver); | |
1da177e4 LT |
1215 | if (rc) |
1216 | return rc; | |
1217 | ||
1218 | in_module_init = 0; | |
1219 | ||
1220 | DPRINTK("done\n"); | |
1221 | return 0; | |
1222 | } | |
1223 | ||
1da177e4 LT |
1224 | static void __exit piix_exit(void) |
1225 | { | |
1226 | pci_unregister_driver(&piix_pci_driver); | |
1227 | } | |
1228 | ||
1229 | module_init(piix_init); | |
1230 | module_exit(piix_exit); |