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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
18 | * | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed AC |
40 | * Documentation |
41 | * Publically available from Intel web site. Errata documentation | |
42 | * is also publically available. As an aide to anyone hacking on this | |
2c5ff671 | 43 | * driver the list of errata that are relevant is below, going back to |
d96212ed AC |
44 | * PIIX4. Older device documentation is now a bit tricky to find. |
45 | * | |
46 | * The chipsets all follow very much the same design. The orginal Triton | |
47 | * series chipsets do _not_ support independant device timings, but this | |
48 | * is fixed in Triton II. With the odd mobile exception the chips then | |
49 | * change little except in gaining more modes until SATA arrives. This | |
50 | * driver supports only the chips with independant timing (that is those | |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix | |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
75 | * | |
76 | * Should have been BIOS fixed: | |
77 | * 450NX: errata #19 - DMA hangs on old 450NX | |
78 | * 450NX: errata #20 - DMA hangs on old 450NX | |
79 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
80 | * ICH3 errata #15 - IDE deadlock under high load | |
81 | * (BIOS must set dev 31 fn 0 bit 23) | |
82 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
83 | */ |
84 | ||
85 | #include <linux/kernel.h> | |
86 | #include <linux/module.h> | |
87 | #include <linux/pci.h> | |
88 | #include <linux/init.h> | |
89 | #include <linux/blkdev.h> | |
90 | #include <linux/delay.h> | |
6248e647 | 91 | #include <linux/device.h> |
1da177e4 LT |
92 | #include <scsi/scsi_host.h> |
93 | #include <linux/libata.h> | |
b8b275ef | 94 | #include <linux/dmi.h> |
1da177e4 LT |
95 | |
96 | #define DRV_NAME "ata_piix" | |
2a3103ce | 97 | #define DRV_VERSION "2.12" |
1da177e4 LT |
98 | |
99 | enum { | |
100 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
101 | ICH5_PMR = 0x90, /* port mapping register */ | |
102 | ICH5_PCS = 0x92, /* port control and status */ | |
7b6dbd68 | 103 | PIIX_SCC = 0x0A, /* sub-class code register */ |
1da177e4 | 104 | |
d4358048 | 105 | PIIX_FLAG_SCR = (1 << 26), /* SCR available */ |
ff0fc146 TH |
106 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
107 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ | |
1da177e4 | 108 | |
800b3996 TH |
109 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
110 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, | |
b3362f88 | 111 | |
1da177e4 LT |
112 | /* combined mode. if set, PATA is channel 0. |
113 | * if clear, PATA is channel 1. | |
114 | */ | |
6a690df5 HR |
115 | PIIX_PORT_ENABLED = (1 << 0), |
116 | PIIX_PORT_PRESENT = (1 << 4), | |
1da177e4 LT |
117 | |
118 | PIIX_80C_PRI = (1 << 5) | (1 << 4), | |
119 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
120 | ||
1d076e5b | 121 | /* controller IDs */ |
d2cdfc0d | 122 | piix_pata_33 = 0, /* PIIX4 at 33Mhz */ |
669a5db4 JG |
123 | ich_pata_33 = 1, /* ICH up to UDMA 33 only */ |
124 | ich_pata_66 = 2, /* ICH up to 66 Mhz */ | |
125 | ich_pata_100 = 3, /* ICH up to UDMA 100 */ | |
669a5db4 | 126 | ich5_sata = 5, |
5e56a37c TH |
127 | ich6_sata = 6, |
128 | ich6_sata_ahci = 7, | |
129 | ich6m_sata_ahci = 8, | |
130 | ich8_sata_ahci = 9, | |
d2cdfc0d | 131 | piix_pata_mwdma = 10, /* PIIX3 MWDMA only */ |
c5cf0ffa | 132 | tolapai_sata_ahci = 11, |
85cd7251 | 133 | |
d33f58b8 TH |
134 | /* constants for mapping table */ |
135 | P0 = 0, /* port 0 */ | |
136 | P1 = 1, /* port 1 */ | |
137 | P2 = 2, /* port 2 */ | |
138 | P3 = 3, /* port 3 */ | |
139 | IDE = -1, /* IDE */ | |
140 | NA = -2, /* not avaliable */ | |
141 | RV = -3, /* reserved */ | |
142 | ||
7b6dbd68 | 143 | PIIX_AHCI_DEVICE = 6, |
b8b275ef TH |
144 | |
145 | /* host->flags bits */ | |
146 | PIIX_HOST_BROKEN_SUSPEND = (1 << 24), | |
1da177e4 LT |
147 | }; |
148 | ||
d33f58b8 TH |
149 | struct piix_map_db { |
150 | const u32 mask; | |
73291a1c | 151 | const u16 port_enable; |
d33f58b8 TH |
152 | const int map[][4]; |
153 | }; | |
154 | ||
d96715c1 TH |
155 | struct piix_host_priv { |
156 | const int *map; | |
157 | }; | |
158 | ||
1da177e4 LT |
159 | static int piix_init_one (struct pci_dev *pdev, |
160 | const struct pci_device_id *ent); | |
ccc4672a | 161 | static void piix_pata_error_handler(struct ata_port *ap); |
669a5db4 JG |
162 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); |
163 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); | |
164 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev); | |
eb4a2c7f | 165 | static int ich_pata_cable_detect(struct ata_port *ap); |
b8b275ef TH |
166 | #ifdef CONFIG_PM |
167 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
168 | static int piix_pci_device_resume(struct pci_dev *pdev); | |
169 | #endif | |
1da177e4 LT |
170 | |
171 | static unsigned int in_module_init = 1; | |
172 | ||
3b7d697d | 173 | static const struct pci_device_id piix_pci_tbl[] = { |
d2cdfc0d AC |
174 | /* Intel PIIX3 for the 430HX etc */ |
175 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, | |
669a5db4 JG |
176 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
177 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ | |
178 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
669a5db4 JG |
179 | /* Intel PIIX4 */ |
180 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
181 | /* Intel PIIX4 */ | |
182 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
183 | /* Intel PIIX */ | |
184 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
185 | /* Intel ICH (i810, i815, i840) UDMA 66*/ | |
186 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, | |
187 | /* Intel ICH0 : UDMA 33*/ | |
188 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, | |
189 | /* Intel ICH2M */ | |
190 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
191 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ | |
192 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
193 | /* Intel ICH3M */ | |
194 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
195 | /* Intel ICH3 (E7500/1) UDMA 100 */ | |
196 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
197 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ | |
198 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
199 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
200 | /* Intel ICH5 */ | |
2eb829e9 | 201 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 JG |
202 | /* C-ICH (i810E2) */ |
203 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
85cd7251 | 204 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
669a5db4 JG |
205 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
206 | /* ICH6 (and 6) (i915) UDMA 100 */ | |
207 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
208 | /* ICH7/7-R (i945, i975) UDMA 100*/ | |
2eb829e9 | 209 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
669a5db4 | 210 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
c1e6f28c CL |
211 | /* ICH8 Mobile PATA Controller */ |
212 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
1da177e4 LT |
213 | |
214 | /* NOTE: The following PCI ids must be kept in sync with the | |
215 | * list in drivers/pci/quirks.c. | |
216 | */ | |
217 | ||
1d076e5b | 218 | /* 82801EB (ICH5) */ |
1da177e4 | 219 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 220 | /* 82801EB (ICH5) */ |
1da177e4 | 221 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 222 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
5e56a37c | 223 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 224 | /* 6300ESB pretending RAID */ |
5e56a37c | 225 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 226 | /* 82801FB/FW (ICH6/ICH6W) */ |
1da177e4 | 227 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 228 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
1c24a412 | 229 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b TH |
230 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
231 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, | |
232 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ | |
1c24a412 | 233 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b | 234 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
c6446a4c | 235 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, |
f98b6573 | 236 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
1c24a412 | 237 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
f98b6573 | 238 | /* SATA Controller 1 IDE (ICH8) */ |
08f12edc | 239 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
f98b6573 | 240 | /* SATA Controller 2 IDE (ICH8) */ |
08f12edc | 241 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
f98b6573 | 242 | /* Mobile SATA Controller IDE (ICH8M) */ |
08f12edc | 243 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
f98b6573 JG |
244 | /* SATA Controller IDE (ICH9) */ |
245 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
246 | /* SATA Controller IDE (ICH9) */ | |
247 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
248 | /* SATA Controller IDE (ICH9) */ | |
249 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
250 | /* SATA Controller IDE (ICH9M) */ | |
251 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
252 | /* SATA Controller IDE (ICH9M) */ | |
253 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
254 | /* SATA Controller IDE (ICH9M) */ | |
255 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, | |
c5cf0ffa JG |
256 | /* SATA Controller IDE (Tolapai) */ |
257 | { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci }, | |
1da177e4 LT |
258 | |
259 | { } /* terminate list */ | |
260 | }; | |
261 | ||
262 | static struct pci_driver piix_pci_driver = { | |
263 | .name = DRV_NAME, | |
264 | .id_table = piix_pci_tbl, | |
265 | .probe = piix_init_one, | |
266 | .remove = ata_pci_remove_one, | |
438ac6d5 | 267 | #ifdef CONFIG_PM |
b8b275ef TH |
268 | .suspend = piix_pci_device_suspend, |
269 | .resume = piix_pci_device_resume, | |
438ac6d5 | 270 | #endif |
1da177e4 LT |
271 | }; |
272 | ||
193515d5 | 273 | static struct scsi_host_template piix_sht = { |
1da177e4 LT |
274 | .module = THIS_MODULE, |
275 | .name = DRV_NAME, | |
276 | .ioctl = ata_scsi_ioctl, | |
277 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
278 | .can_queue = ATA_DEF_QUEUE, |
279 | .this_id = ATA_SHT_THIS_ID, | |
280 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
281 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
282 | .emulated = ATA_SHT_EMULATED, | |
283 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
284 | .proc_name = DRV_NAME, | |
285 | .dma_boundary = ATA_DMA_BOUNDARY, | |
286 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 287 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 288 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
289 | }; |
290 | ||
057ace5e | 291 | static const struct ata_port_operations piix_pata_ops = { |
1da177e4 LT |
292 | .set_piomode = piix_set_piomode, |
293 | .set_dmamode = piix_set_dmamode, | |
89bad589 | 294 | .mode_filter = ata_pci_default_filter, |
1da177e4 LT |
295 | |
296 | .tf_load = ata_tf_load, | |
297 | .tf_read = ata_tf_read, | |
298 | .check_status = ata_check_status, | |
299 | .exec_command = ata_exec_command, | |
300 | .dev_select = ata_std_dev_select, | |
301 | ||
1da177e4 LT |
302 | .bmdma_setup = ata_bmdma_setup, |
303 | .bmdma_start = ata_bmdma_start, | |
304 | .bmdma_stop = ata_bmdma_stop, | |
305 | .bmdma_status = ata_bmdma_status, | |
306 | .qc_prep = ata_qc_prep, | |
307 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 308 | .data_xfer = ata_data_xfer, |
1da177e4 | 309 | |
3f037db0 TH |
310 | .freeze = ata_bmdma_freeze, |
311 | .thaw = ata_bmdma_thaw, | |
ccc4672a | 312 | .error_handler = piix_pata_error_handler, |
3f037db0 | 313 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
eb4a2c7f | 314 | .cable_detect = ata_cable_40wire, |
1da177e4 LT |
315 | |
316 | .irq_handler = ata_interrupt, | |
317 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 | 318 | .irq_on = ata_irq_on, |
1da177e4 LT |
319 | |
320 | .port_start = ata_port_start, | |
1da177e4 LT |
321 | }; |
322 | ||
669a5db4 | 323 | static const struct ata_port_operations ich_pata_ops = { |
669a5db4 JG |
324 | .set_piomode = piix_set_piomode, |
325 | .set_dmamode = ich_set_dmamode, | |
326 | .mode_filter = ata_pci_default_filter, | |
327 | ||
328 | .tf_load = ata_tf_load, | |
329 | .tf_read = ata_tf_read, | |
330 | .check_status = ata_check_status, | |
331 | .exec_command = ata_exec_command, | |
332 | .dev_select = ata_std_dev_select, | |
333 | ||
334 | .bmdma_setup = ata_bmdma_setup, | |
335 | .bmdma_start = ata_bmdma_start, | |
336 | .bmdma_stop = ata_bmdma_stop, | |
337 | .bmdma_status = ata_bmdma_status, | |
338 | .qc_prep = ata_qc_prep, | |
339 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 340 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
341 | |
342 | .freeze = ata_bmdma_freeze, | |
343 | .thaw = ata_bmdma_thaw, | |
eb4a2c7f | 344 | .error_handler = piix_pata_error_handler, |
669a5db4 | 345 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
eb4a2c7f | 346 | .cable_detect = ich_pata_cable_detect, |
669a5db4 JG |
347 | |
348 | .irq_handler = ata_interrupt, | |
349 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 | 350 | .irq_on = ata_irq_on, |
669a5db4 JG |
351 | |
352 | .port_start = ata_port_start, | |
669a5db4 JG |
353 | }; |
354 | ||
057ace5e | 355 | static const struct ata_port_operations piix_sata_ops = { |
1da177e4 LT |
356 | .tf_load = ata_tf_load, |
357 | .tf_read = ata_tf_read, | |
358 | .check_status = ata_check_status, | |
359 | .exec_command = ata_exec_command, | |
360 | .dev_select = ata_std_dev_select, | |
361 | ||
1da177e4 LT |
362 | .bmdma_setup = ata_bmdma_setup, |
363 | .bmdma_start = ata_bmdma_start, | |
364 | .bmdma_stop = ata_bmdma_stop, | |
365 | .bmdma_status = ata_bmdma_status, | |
366 | .qc_prep = ata_qc_prep, | |
367 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 368 | .data_xfer = ata_data_xfer, |
1da177e4 | 369 | |
3f037db0 TH |
370 | .freeze = ata_bmdma_freeze, |
371 | .thaw = ata_bmdma_thaw, | |
2f91d81d | 372 | .error_handler = ata_bmdma_error_handler, |
3f037db0 | 373 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
1da177e4 LT |
374 | |
375 | .irq_handler = ata_interrupt, | |
376 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 | 377 | .irq_on = ata_irq_on, |
1da177e4 LT |
378 | |
379 | .port_start = ata_port_start, | |
1da177e4 LT |
380 | }; |
381 | ||
d96715c1 | 382 | static const struct piix_map_db ich5_map_db = { |
d33f58b8 | 383 | .mask = 0x7, |
ea35d29e | 384 | .port_enable = 0x3, |
d33f58b8 TH |
385 | .map = { |
386 | /* PM PS SM SS MAP */ | |
387 | { P0, NA, P1, NA }, /* 000b */ | |
388 | { P1, NA, P0, NA }, /* 001b */ | |
389 | { RV, RV, RV, RV }, | |
390 | { RV, RV, RV, RV }, | |
391 | { P0, P1, IDE, IDE }, /* 100b */ | |
392 | { P1, P0, IDE, IDE }, /* 101b */ | |
393 | { IDE, IDE, P0, P1 }, /* 110b */ | |
394 | { IDE, IDE, P1, P0 }, /* 111b */ | |
395 | }, | |
396 | }; | |
397 | ||
d96715c1 | 398 | static const struct piix_map_db ich6_map_db = { |
d33f58b8 | 399 | .mask = 0x3, |
ea35d29e | 400 | .port_enable = 0xf, |
d33f58b8 TH |
401 | .map = { |
402 | /* PM PS SM SS MAP */ | |
79ea24e7 | 403 | { P0, P2, P1, P3 }, /* 00b */ |
d33f58b8 TH |
404 | { IDE, IDE, P1, P3 }, /* 01b */ |
405 | { P0, P2, IDE, IDE }, /* 10b */ | |
406 | { RV, RV, RV, RV }, | |
407 | }, | |
408 | }; | |
409 | ||
d96715c1 | 410 | static const struct piix_map_db ich6m_map_db = { |
d33f58b8 | 411 | .mask = 0x3, |
ea35d29e | 412 | .port_enable = 0x5, |
67083741 TH |
413 | |
414 | /* Map 01b isn't specified in the doc but some notebooks use | |
c6446a4c TH |
415 | * it anyway. MAP 01b have been spotted on both ICH6M and |
416 | * ICH7M. | |
67083741 TH |
417 | */ |
418 | .map = { | |
419 | /* PM PS SM SS MAP */ | |
e04b3b9d | 420 | { P0, P2, NA, NA }, /* 00b */ |
67083741 TH |
421 | { IDE, IDE, P1, P3 }, /* 01b */ |
422 | { P0, P2, IDE, IDE }, /* 10b */ | |
423 | { RV, RV, RV, RV }, | |
424 | }, | |
425 | }; | |
426 | ||
08f12edc JG |
427 | static const struct piix_map_db ich8_map_db = { |
428 | .mask = 0x3, | |
429 | .port_enable = 0x3, | |
08f12edc JG |
430 | .map = { |
431 | /* PM PS SM SS MAP */ | |
158f30c8 | 432 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
08f12edc | 433 | { RV, RV, RV, RV }, |
ac2b0437 | 434 | { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ |
08f12edc JG |
435 | { RV, RV, RV, RV }, |
436 | }, | |
437 | }; | |
438 | ||
c5cf0ffa JG |
439 | static const struct piix_map_db tolapai_map_db = { |
440 | .mask = 0x3, | |
441 | .port_enable = 0x3, | |
442 | .map = { | |
443 | /* PM PS SM SS MAP */ | |
444 | { P0, NA, P1, NA }, /* 00b */ | |
445 | { RV, RV, RV, RV }, /* 01b */ | |
446 | { RV, RV, RV, RV }, /* 10b */ | |
447 | { RV, RV, RV, RV }, | |
448 | }, | |
449 | }; | |
450 | ||
d96715c1 TH |
451 | static const struct piix_map_db *piix_map_db_table[] = { |
452 | [ich5_sata] = &ich5_map_db, | |
d96715c1 TH |
453 | [ich6_sata] = &ich6_map_db, |
454 | [ich6_sata_ahci] = &ich6_map_db, | |
455 | [ich6m_sata_ahci] = &ich6m_map_db, | |
08f12edc | 456 | [ich8_sata_ahci] = &ich8_map_db, |
c5cf0ffa | 457 | [tolapai_sata_ahci] = &tolapai_map_db, |
d96715c1 TH |
458 | }; |
459 | ||
1da177e4 | 460 | static struct ata_port_info piix_port_info[] = { |
ec300d99 | 461 | [piix_pata_33] = /* PIIX4 at 33MHz */ |
1d076e5b TH |
462 | { |
463 | .sht = &piix_sht, | |
b3362f88 | 464 | .flags = PIIX_PATA_FLAGS, |
1d076e5b | 465 | .pio_mask = 0x1f, /* pio0-4 */ |
669a5db4 | 466 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
1d076e5b TH |
467 | .udma_mask = ATA_UDMA_MASK_40C, |
468 | .port_ops = &piix_pata_ops, | |
469 | }, | |
470 | ||
ec300d99 | 471 | [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ |
669a5db4 JG |
472 | { |
473 | .sht = &piix_sht, | |
b3362f88 | 474 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
475 | .pio_mask = 0x1f, /* pio 0-4 */ |
476 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ | |
477 | .udma_mask = ATA_UDMA2, /* UDMA33 */ | |
478 | .port_ops = &ich_pata_ops, | |
479 | }, | |
ec300d99 JG |
480 | |
481 | [ich_pata_66] = /* ICH controllers up to 66MHz */ | |
1da177e4 LT |
482 | { |
483 | .sht = &piix_sht, | |
b3362f88 | 484 | .flags = PIIX_PATA_FLAGS, |
669a5db4 JG |
485 | .pio_mask = 0x1f, /* pio 0-4 */ |
486 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ | |
487 | .udma_mask = ATA_UDMA4, | |
488 | .port_ops = &ich_pata_ops, | |
489 | }, | |
85cd7251 | 490 | |
ec300d99 | 491 | [ich_pata_100] = |
669a5db4 JG |
492 | { |
493 | .sht = &piix_sht, | |
b3362f88 | 494 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
1da177e4 | 495 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 | 496 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
669a5db4 JG |
497 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
498 | .port_ops = &ich_pata_ops, | |
1da177e4 LT |
499 | }, |
500 | ||
ec300d99 | 501 | [ich5_sata] = |
1da177e4 LT |
502 | { |
503 | .sht = &piix_sht, | |
228c1590 | 504 | .flags = PIIX_SATA_FLAGS, |
1da177e4 LT |
505 | .pio_mask = 0x1f, /* pio0-4 */ |
506 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 507 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
508 | .port_ops = &piix_sata_ops, |
509 | }, | |
510 | ||
ec300d99 | 511 | [ich6_sata] = |
1da177e4 LT |
512 | { |
513 | .sht = &piix_sht, | |
b3362f88 | 514 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR, |
1da177e4 LT |
515 | .pio_mask = 0x1f, /* pio0-4 */ |
516 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 517 | .udma_mask = ATA_UDMA6, |
1da177e4 LT |
518 | .port_ops = &piix_sata_ops, |
519 | }, | |
520 | ||
ec300d99 | 521 | [ich6_sata_ahci] = |
c368ca4e JG |
522 | { |
523 | .sht = &piix_sht, | |
b3362f88 | 524 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
d33f58b8 | 525 | PIIX_FLAG_AHCI, |
c368ca4e JG |
526 | .pio_mask = 0x1f, /* pio0-4 */ |
527 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 528 | .udma_mask = ATA_UDMA6, |
c368ca4e JG |
529 | .port_ops = &piix_sata_ops, |
530 | }, | |
1d076e5b | 531 | |
ec300d99 | 532 | [ich6m_sata_ahci] = |
1d076e5b TH |
533 | { |
534 | .sht = &piix_sht, | |
b3362f88 | 535 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
d33f58b8 | 536 | PIIX_FLAG_AHCI, |
1d076e5b TH |
537 | .pio_mask = 0x1f, /* pio0-4 */ |
538 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 539 | .udma_mask = ATA_UDMA6, |
1d076e5b TH |
540 | .port_ops = &piix_sata_ops, |
541 | }, | |
08f12edc | 542 | |
ec300d99 | 543 | [ich8_sata_ahci] = |
08f12edc JG |
544 | { |
545 | .sht = &piix_sht, | |
b3362f88 | 546 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | |
08f12edc JG |
547 | PIIX_FLAG_AHCI, |
548 | .pio_mask = 0x1f, /* pio0-4 */ | |
549 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 550 | .udma_mask = ATA_UDMA6, |
08f12edc JG |
551 | .port_ops = &piix_sata_ops, |
552 | }, | |
669a5db4 | 553 | |
ec300d99 | 554 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ |
d2cdfc0d AC |
555 | { |
556 | .sht = &piix_sht, | |
557 | .flags = PIIX_PATA_FLAGS, | |
558 | .pio_mask = 0x1f, /* pio0-4 */ | |
559 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ | |
560 | .port_ops = &piix_pata_ops, | |
561 | }, | |
c5cf0ffa | 562 | |
ec300d99 | 563 | [tolapai_sata_ahci] = |
c5cf0ffa JG |
564 | { |
565 | .sht = &piix_sht, | |
566 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR | | |
567 | PIIX_FLAG_AHCI, | |
568 | .pio_mask = 0x1f, /* pio0-4 */ | |
569 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
570 | .udma_mask = ATA_UDMA6, | |
571 | .port_ops = &piix_sata_ops, | |
572 | }, | |
1da177e4 LT |
573 | }; |
574 | ||
575 | static struct pci_bits piix_enable_bits[] = { | |
576 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
577 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
578 | }; | |
579 | ||
580 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
581 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
582 | MODULE_LICENSE("GPL"); | |
583 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
584 | MODULE_VERSION(DRV_VERSION); | |
585 | ||
fc085150 AC |
586 | struct ich_laptop { |
587 | u16 device; | |
588 | u16 subvendor; | |
589 | u16 subdevice; | |
590 | }; | |
591 | ||
592 | /* | |
593 | * List of laptops that use short cables rather than 80 wire | |
594 | */ | |
595 | ||
596 | static const struct ich_laptop ich_laptop[] = { | |
597 | /* devid, subvendor, subdev */ | |
598 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ | |
babfb682 | 599 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
12340106 | 600 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
b33620f9 | 601 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
fc085150 AC |
602 | /* end marker */ |
603 | { 0, } | |
604 | }; | |
605 | ||
1da177e4 | 606 | /** |
eb4a2c7f | 607 | * ich_pata_cable_detect - Probe host controller cable detect info |
1da177e4 LT |
608 | * @ap: Port for which cable detect info is desired |
609 | * | |
610 | * Read 80c cable indicator from ATA PCI device's PCI config | |
611 | * register. This register is normally set by firmware (BIOS). | |
612 | * | |
613 | * LOCKING: | |
614 | * None (inherited from caller). | |
615 | */ | |
669a5db4 | 616 | |
eb4a2c7f | 617 | static int ich_pata_cable_detect(struct ata_port *ap) |
1da177e4 | 618 | { |
cca3974e | 619 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
fc085150 | 620 | const struct ich_laptop *lap = &ich_laptop[0]; |
1da177e4 LT |
621 | u8 tmp, mask; |
622 | ||
fc085150 AC |
623 | /* Check for specials - Acer Aspire 5602WLMi */ |
624 | while (lap->device) { | |
625 | if (lap->device == pdev->device && | |
626 | lap->subvendor == pdev->subsystem_vendor && | |
627 | lap->subdevice == pdev->subsystem_device) { | |
eb4a2c7f | 628 | return ATA_CBL_PATA40_SHORT; |
fc085150 AC |
629 | } |
630 | lap++; | |
631 | } | |
632 | ||
1da177e4 | 633 | /* check BIOS cable detect results */ |
2a88d1ac | 634 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
1da177e4 LT |
635 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
636 | if ((tmp & mask) == 0) | |
eb4a2c7f AC |
637 | return ATA_CBL_PATA40; |
638 | return ATA_CBL_PATA80; | |
1da177e4 LT |
639 | } |
640 | ||
641 | /** | |
ccc4672a | 642 | * piix_pata_prereset - prereset for PATA host controller |
cc0680a5 | 643 | * @link: Target link |
d4b2bab4 | 644 | * @deadline: deadline jiffies for the operation |
1da177e4 | 645 | * |
573db6b8 TH |
646 | * LOCKING: |
647 | * None (inherited from caller). | |
648 | */ | |
cc0680a5 | 649 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) |
1da177e4 | 650 | { |
cc0680a5 | 651 | struct ata_port *ap = link->ap; |
cca3974e | 652 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 653 | |
c961922b AC |
654 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
655 | return -ENOENT; | |
cc0680a5 | 656 | return ata_std_prereset(link, deadline); |
ccc4672a TH |
657 | } |
658 | ||
659 | static void piix_pata_error_handler(struct ata_port *ap) | |
660 | { | |
661 | ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, | |
662 | ata_std_postreset); | |
1da177e4 LT |
663 | } |
664 | ||
1da177e4 LT |
665 | /** |
666 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
667 | * @ap: Port whose timings we are configuring | |
668 | * @adev: um | |
1da177e4 LT |
669 | * |
670 | * Set PIO mode for device, in host controller PCI config space. | |
671 | * | |
672 | * LOCKING: | |
673 | * None (inherited from caller). | |
674 | */ | |
675 | ||
676 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
677 | { | |
678 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
cca3974e | 679 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
1da177e4 | 680 | unsigned int is_slave = (adev->devno != 0); |
2a88d1ac | 681 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
1da177e4 LT |
682 | unsigned int slave_port = 0x44; |
683 | u16 master_data; | |
684 | u8 slave_data; | |
669a5db4 JG |
685 | u8 udma_enable; |
686 | int control = 0; | |
85cd7251 | 687 | |
669a5db4 JG |
688 | /* |
689 | * See Intel Document 298600-004 for the timing programing rules | |
690 | * for ICH controllers. | |
691 | */ | |
1da177e4 LT |
692 | |
693 | static const /* ISP RTC */ | |
694 | u8 timings[][2] = { { 0, 0 }, | |
695 | { 0, 0 }, | |
696 | { 1, 0 }, | |
697 | { 2, 1 }, | |
698 | { 2, 3 }, }; | |
699 | ||
669a5db4 JG |
700 | if (pio >= 2) |
701 | control |= 1; /* TIME1 enable */ | |
702 | if (ata_pio_need_iordy(adev)) | |
703 | control |= 2; /* IE enable */ | |
704 | ||
85cd7251 | 705 | /* Intel specifies that the PPE functionality is for disk only */ |
669a5db4 JG |
706 | if (adev->class == ATA_DEV_ATA) |
707 | control |= 4; /* PPE enable */ | |
708 | ||
a5bf5f5a TH |
709 | /* PIO configuration clears DTE unconditionally. It will be |
710 | * programmed in set_dmamode which is guaranteed to be called | |
711 | * after set_piomode if any DMA mode is available. | |
712 | */ | |
1da177e4 LT |
713 | pci_read_config_word(dev, master_port, &master_data); |
714 | if (is_slave) { | |
a5bf5f5a TH |
715 | /* clear TIME1|IE1|PPE1|DTE1 */ |
716 | master_data &= 0xff0f; | |
669a5db4 | 717 | /* Enable SITRE (seperate slave timing register) */ |
1da177e4 | 718 | master_data |= 0x4000; |
669a5db4 JG |
719 | /* enable PPE1, IE1 and TIME1 as needed */ |
720 | master_data |= (control << 4); | |
1da177e4 | 721 | pci_read_config_byte(dev, slave_port, &slave_data); |
2a88d1ac | 722 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 | 723 | /* Load the timing nibble for this slave */ |
a5bf5f5a TH |
724 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
725 | << (ap->port_no ? 4 : 0); | |
1da177e4 | 726 | } else { |
a5bf5f5a TH |
727 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
728 | master_data &= 0xccf0; | |
669a5db4 JG |
729 | /* Enable PPE, IE and TIME as appropriate */ |
730 | master_data |= control; | |
a5bf5f5a | 731 | /* load ISP and RCT */ |
1da177e4 LT |
732 | master_data |= |
733 | (timings[pio][0] << 12) | | |
734 | (timings[pio][1] << 8); | |
735 | } | |
736 | pci_write_config_word(dev, master_port, master_data); | |
737 | if (is_slave) | |
738 | pci_write_config_byte(dev, slave_port, slave_data); | |
669a5db4 JG |
739 | |
740 | /* Ensure the UDMA bit is off - it will be turned back on if | |
741 | UDMA is selected */ | |
85cd7251 | 742 | |
669a5db4 JG |
743 | if (ap->udma_mask) { |
744 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
745 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); | |
746 | pci_write_config_byte(dev, 0x48, udma_enable); | |
747 | } | |
1da177e4 LT |
748 | } |
749 | ||
750 | /** | |
669a5db4 | 751 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
1da177e4 | 752 | * @ap: Port whose timings we are configuring |
669a5db4 | 753 | * @adev: Drive in question |
1da177e4 | 754 | * @udma: udma mode, 0 - 6 |
c32a8fd7 | 755 | * @isich: set if the chip is an ICH device |
1da177e4 LT |
756 | * |
757 | * Set UDMA mode for device, in host controller PCI config space. | |
758 | * | |
759 | * LOCKING: | |
760 | * None (inherited from caller). | |
761 | */ | |
762 | ||
669a5db4 | 763 | static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich) |
1da177e4 | 764 | { |
cca3974e | 765 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
669a5db4 JG |
766 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
767 | u16 master_data; | |
768 | u8 speed = adev->dma_mode; | |
769 | int devid = adev->devno + 2 * ap->port_no; | |
dedf61db | 770 | u8 udma_enable = 0; |
85cd7251 | 771 | |
669a5db4 JG |
772 | static const /* ISP RTC */ |
773 | u8 timings[][2] = { { 0, 0 }, | |
774 | { 0, 0 }, | |
775 | { 1, 0 }, | |
776 | { 2, 1 }, | |
777 | { 2, 3 }, }; | |
778 | ||
779 | pci_read_config_word(dev, master_port, &master_data); | |
d2cdfc0d AC |
780 | if (ap->udma_mask) |
781 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
1da177e4 LT |
782 | |
783 | if (speed >= XFER_UDMA_0) { | |
669a5db4 JG |
784 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
785 | u16 udma_timing; | |
786 | u16 ideconf; | |
787 | int u_clock, u_speed; | |
85cd7251 | 788 | |
669a5db4 JG |
789 | /* |
790 | * UDMA is handled by a combination of clock switching and | |
85cd7251 JG |
791 | * selection of dividers |
792 | * | |
669a5db4 | 793 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
85cd7251 | 794 | * except UDMA0 which is 00 |
669a5db4 JG |
795 | */ |
796 | u_speed = min(2 - (udma & 1), udma); | |
797 | if (udma == 5) | |
798 | u_clock = 0x1000; /* 100Mhz */ | |
799 | else if (udma > 2) | |
800 | u_clock = 1; /* 66Mhz */ | |
801 | else | |
802 | u_clock = 0; /* 33Mhz */ | |
85cd7251 | 803 | |
669a5db4 | 804 | udma_enable |= (1 << devid); |
85cd7251 | 805 | |
669a5db4 JG |
806 | /* Load the CT/RP selection */ |
807 | pci_read_config_word(dev, 0x4A, &udma_timing); | |
808 | udma_timing &= ~(3 << (4 * devid)); | |
809 | udma_timing |= u_speed << (4 * devid); | |
810 | pci_write_config_word(dev, 0x4A, udma_timing); | |
811 | ||
85cd7251 | 812 | if (isich) { |
669a5db4 JG |
813 | /* Select a 33/66/100Mhz clock */ |
814 | pci_read_config_word(dev, 0x54, &ideconf); | |
815 | ideconf &= ~(0x1001 << devid); | |
816 | ideconf |= u_clock << devid; | |
817 | /* For ICH or later we should set bit 10 for better | |
818 | performance (WR_PingPong_En) */ | |
819 | pci_write_config_word(dev, 0x54, ideconf); | |
1da177e4 | 820 | } |
1da177e4 | 821 | } else { |
669a5db4 JG |
822 | /* |
823 | * MWDMA is driven by the PIO timings. We must also enable | |
824 | * IORDY unconditionally along with TIME1. PPE has already | |
825 | * been set when the PIO timing was set. | |
826 | */ | |
827 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
828 | unsigned int control; | |
829 | u8 slave_data; | |
830 | const unsigned int needed_pio[3] = { | |
831 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
832 | }; | |
833 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
85cd7251 | 834 | |
669a5db4 | 835 | control = 3; /* IORDY|TIME1 */ |
85cd7251 | 836 | |
669a5db4 JG |
837 | /* If the drive MWDMA is faster than it can do PIO then |
838 | we must force PIO into PIO0 */ | |
85cd7251 | 839 | |
669a5db4 JG |
840 | if (adev->pio_mode < needed_pio[mwdma]) |
841 | /* Enable DMA timing only */ | |
842 | control |= 8; /* PIO cycles in PIO0 */ | |
843 | ||
844 | if (adev->devno) { /* Slave */ | |
845 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ | |
846 | master_data |= control << 4; | |
847 | pci_read_config_byte(dev, 0x44, &slave_data); | |
a5bf5f5a | 848 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 JG |
849 | /* Load the matching timing */ |
850 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
851 | pci_write_config_byte(dev, 0x44, slave_data); | |
852 | } else { /* Master */ | |
85cd7251 | 853 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
669a5db4 JG |
854 | and master timing bits */ |
855 | master_data |= control; | |
856 | master_data |= | |
857 | (timings[pio][0] << 12) | | |
858 | (timings[pio][1] << 8); | |
859 | } | |
a5bf5f5a TH |
860 | |
861 | if (ap->udma_mask) { | |
862 | udma_enable &= ~(1 << devid); | |
863 | pci_write_config_word(dev, master_port, master_data); | |
864 | } | |
1da177e4 | 865 | } |
669a5db4 JG |
866 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
867 | if (ap->udma_mask) | |
868 | pci_write_config_byte(dev, 0x48, udma_enable); | |
869 | } | |
870 | ||
871 | /** | |
872 | * piix_set_dmamode - Initialize host controller PATA DMA timings | |
873 | * @ap: Port whose timings we are configuring | |
874 | * @adev: um | |
875 | * | |
876 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
877 | * | |
878 | * LOCKING: | |
879 | * None (inherited from caller). | |
880 | */ | |
881 | ||
882 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
883 | { | |
884 | do_pata_set_dmamode(ap, adev, 0); | |
885 | } | |
886 | ||
887 | /** | |
888 | * ich_set_dmamode - Initialize host controller PATA DMA timings | |
889 | * @ap: Port whose timings we are configuring | |
890 | * @adev: um | |
891 | * | |
892 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
893 | * | |
894 | * LOCKING: | |
895 | * None (inherited from caller). | |
896 | */ | |
897 | ||
898 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
899 | { | |
900 | do_pata_set_dmamode(ap, adev, 1); | |
1da177e4 LT |
901 | } |
902 | ||
b8b275ef | 903 | #ifdef CONFIG_PM |
8c3832eb TH |
904 | static int piix_broken_suspend(void) |
905 | { | |
1855256c | 906 | static const struct dmi_system_id sysids[] = { |
4c74d4ec TH |
907 | { |
908 | .ident = "TECRA M3", | |
909 | .matches = { | |
910 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
911 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), | |
912 | }, | |
913 | }, | |
8c3832eb TH |
914 | { |
915 | .ident = "TECRA M5", | |
916 | .matches = { | |
917 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
918 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), | |
919 | }, | |
b8b275ef | 920 | }, |
5c08ea01 TH |
921 | { |
922 | .ident = "TECRA M7", | |
923 | .matches = { | |
924 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
925 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), | |
926 | }, | |
927 | }, | |
3cc0b9d3 TH |
928 | { |
929 | .ident = "Satellite U200", | |
930 | .matches = { | |
931 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
932 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), | |
933 | }, | |
934 | }, | |
8c3832eb TH |
935 | { |
936 | .ident = "Satellite U205", | |
937 | .matches = { | |
938 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
939 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), | |
940 | }, | |
b8b275ef | 941 | }, |
8c3832eb TH |
942 | { |
943 | .ident = "Portege M500", | |
944 | .matches = { | |
945 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
946 | DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), | |
947 | }, | |
b8b275ef | 948 | }, |
7d051548 JG |
949 | |
950 | { } /* terminate list */ | |
8c3832eb | 951 | }; |
7abe79c3 TH |
952 | static const char *oemstrs[] = { |
953 | "Tecra M3,", | |
954 | }; | |
955 | int i; | |
8c3832eb TH |
956 | |
957 | if (dmi_check_system(sysids)) | |
958 | return 1; | |
959 | ||
7abe79c3 TH |
960 | for (i = 0; i < ARRAY_SIZE(oemstrs); i++) |
961 | if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) | |
962 | return 1; | |
963 | ||
8c3832eb TH |
964 | return 0; |
965 | } | |
b8b275ef TH |
966 | |
967 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
968 | { | |
969 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
970 | unsigned long flags; | |
971 | int rc = 0; | |
972 | ||
973 | rc = ata_host_suspend(host, mesg); | |
974 | if (rc) | |
975 | return rc; | |
976 | ||
977 | /* Some braindamaged ACPI suspend implementations expect the | |
978 | * controller to be awake on entry; otherwise, it burns cpu | |
979 | * cycles and power trying to do something to the sleeping | |
980 | * beauty. | |
981 | */ | |
8c3832eb | 982 | if (piix_broken_suspend() && mesg.event == PM_EVENT_SUSPEND) { |
b8b275ef TH |
983 | pci_save_state(pdev); |
984 | ||
985 | /* mark its power state as "unknown", since we don't | |
986 | * know if e.g. the BIOS will change its device state | |
987 | * when we suspend. | |
988 | */ | |
989 | if (pdev->current_state == PCI_D0) | |
990 | pdev->current_state = PCI_UNKNOWN; | |
991 | ||
992 | /* tell resume that it's waking up from broken suspend */ | |
993 | spin_lock_irqsave(&host->lock, flags); | |
994 | host->flags |= PIIX_HOST_BROKEN_SUSPEND; | |
995 | spin_unlock_irqrestore(&host->lock, flags); | |
996 | } else | |
997 | ata_pci_device_do_suspend(pdev, mesg); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | ||
1002 | static int piix_pci_device_resume(struct pci_dev *pdev) | |
1003 | { | |
1004 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1005 | unsigned long flags; | |
1006 | int rc; | |
1007 | ||
1008 | if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { | |
1009 | spin_lock_irqsave(&host->lock, flags); | |
1010 | host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; | |
1011 | spin_unlock_irqrestore(&host->lock, flags); | |
1012 | ||
1013 | pci_set_power_state(pdev, PCI_D0); | |
1014 | pci_restore_state(pdev); | |
1015 | ||
1016 | /* PCI device wasn't disabled during suspend. Use | |
0b62e13b TH |
1017 | * pci_reenable_device() to avoid affecting the enable |
1018 | * count. | |
b8b275ef | 1019 | */ |
0b62e13b | 1020 | rc = pci_reenable_device(pdev); |
b8b275ef TH |
1021 | if (rc) |
1022 | dev_printk(KERN_ERR, &pdev->dev, "failed to enable " | |
1023 | "device after resume (%d)\n", rc); | |
1024 | } else | |
1025 | rc = ata_pci_device_do_resume(pdev); | |
1026 | ||
1027 | if (rc == 0) | |
1028 | ata_host_resume(host); | |
1029 | ||
1030 | return rc; | |
1031 | } | |
1032 | #endif | |
1033 | ||
1da177e4 LT |
1034 | #define AHCI_PCI_BAR 5 |
1035 | #define AHCI_GLOBAL_CTL 0x04 | |
1036 | #define AHCI_ENABLE (1 << 31) | |
1037 | static int piix_disable_ahci(struct pci_dev *pdev) | |
1038 | { | |
ea6ba10b | 1039 | void __iomem *mmio; |
1da177e4 LT |
1040 | u32 tmp; |
1041 | int rc = 0; | |
1042 | ||
1043 | /* BUG: pci_enable_device has not yet been called. This | |
1044 | * works because this device is usually set up by BIOS. | |
1045 | */ | |
1046 | ||
374b1873 JG |
1047 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
1048 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 1049 | return 0; |
7b6dbd68 | 1050 | |
374b1873 | 1051 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
1052 | if (!mmio) |
1053 | return -ENOMEM; | |
7b6dbd68 | 1054 | |
1da177e4 LT |
1055 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
1056 | if (tmp & AHCI_ENABLE) { | |
1057 | tmp &= ~AHCI_ENABLE; | |
1058 | writel(tmp, mmio + AHCI_GLOBAL_CTL); | |
1059 | ||
1060 | tmp = readl(mmio + AHCI_GLOBAL_CTL); | |
1061 | if (tmp & AHCI_ENABLE) | |
1062 | rc = -EIO; | |
1063 | } | |
7b6dbd68 | 1064 | |
374b1873 | 1065 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
1066 | return rc; |
1067 | } | |
1068 | ||
c621b140 AC |
1069 | /** |
1070 | * piix_check_450nx_errata - Check for problem 450NX setup | |
c893a3ae | 1071 | * @ata_dev: the PCI device to check |
2e9edbf8 | 1072 | * |
c621b140 AC |
1073 | * Check for the present of 450NX errata #19 and errata #25. If |
1074 | * they are found return an error code so we can turn off DMA | |
1075 | */ | |
1076 | ||
1077 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) | |
1078 | { | |
1079 | struct pci_dev *pdev = NULL; | |
1080 | u16 cfg; | |
c621b140 | 1081 | int no_piix_dma = 0; |
2e9edbf8 | 1082 | |
c621b140 AC |
1083 | while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) |
1084 | { | |
1085 | /* Look for 450NX PXB. Check for problem configurations | |
1086 | A PCI quirk checks bit 6 already */ | |
c621b140 AC |
1087 | pci_read_config_word(pdev, 0x41, &cfg); |
1088 | /* Only on the original revision: IDE DMA can hang */ | |
44c10138 | 1089 | if (pdev->revision == 0x00) |
c621b140 AC |
1090 | no_piix_dma = 1; |
1091 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
44c10138 | 1092 | else if (cfg & (1<<14) && pdev->revision < 5) |
c621b140 AC |
1093 | no_piix_dma = 2; |
1094 | } | |
31a34fe7 | 1095 | if (no_piix_dma) |
c621b140 | 1096 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
31a34fe7 | 1097 | if (no_piix_dma == 2) |
c621b140 AC |
1098 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
1099 | return no_piix_dma; | |
2e9edbf8 | 1100 | } |
c621b140 | 1101 | |
ea35d29e | 1102 | static void __devinit piix_init_pcs(struct pci_dev *pdev, |
9dd9c164 | 1103 | struct ata_port_info *pinfo, |
ea35d29e JG |
1104 | const struct piix_map_db *map_db) |
1105 | { | |
1106 | u16 pcs, new_pcs; | |
1107 | ||
1108 | pci_read_config_word(pdev, ICH5_PCS, &pcs); | |
1109 | ||
1110 | new_pcs = pcs | map_db->port_enable; | |
1111 | ||
1112 | if (new_pcs != pcs) { | |
1113 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); | |
1114 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); | |
1115 | msleep(150); | |
1116 | } | |
1117 | } | |
1118 | ||
d33f58b8 | 1119 | static void __devinit piix_init_sata_map(struct pci_dev *pdev, |
d96715c1 TH |
1120 | struct ata_port_info *pinfo, |
1121 | const struct piix_map_db *map_db) | |
d33f58b8 | 1122 | { |
d96715c1 | 1123 | struct piix_host_priv *hpriv = pinfo[0].private_data; |
d33f58b8 TH |
1124 | const unsigned int *map; |
1125 | int i, invalid_map = 0; | |
1126 | u8 map_value; | |
1127 | ||
1128 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); | |
1129 | ||
1130 | map = map_db->map[map_value & map_db->mask]; | |
1131 | ||
1132 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); | |
1133 | for (i = 0; i < 4; i++) { | |
1134 | switch (map[i]) { | |
1135 | case RV: | |
1136 | invalid_map = 1; | |
1137 | printk(" XX"); | |
1138 | break; | |
1139 | ||
1140 | case NA: | |
1141 | printk(" --"); | |
1142 | break; | |
1143 | ||
1144 | case IDE: | |
1145 | WARN_ON((i & 1) || map[i + 1] != IDE); | |
669a5db4 | 1146 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
f814b75f | 1147 | pinfo[i / 2].private_data = hpriv; |
d33f58b8 TH |
1148 | i++; |
1149 | printk(" IDE IDE"); | |
1150 | break; | |
1151 | ||
1152 | default: | |
1153 | printk(" P%d", map[i]); | |
1154 | if (i & 1) | |
cca3974e | 1155 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
d33f58b8 TH |
1156 | break; |
1157 | } | |
1158 | } | |
1159 | printk(" ]\n"); | |
1160 | ||
1161 | if (invalid_map) | |
1162 | dev_printk(KERN_ERR, &pdev->dev, | |
1163 | "invalid MAP value %u\n", map_value); | |
1164 | ||
d96715c1 | 1165 | hpriv->map = map; |
d33f58b8 TH |
1166 | } |
1167 | ||
43a98f05 TH |
1168 | static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) |
1169 | { | |
1855256c | 1170 | static const struct dmi_system_id sysids[] = { |
43a98f05 TH |
1171 | { |
1172 | /* Clevo M570U sets IOCFG bit 18 if the cdrom | |
1173 | * isn't used to boot the system which | |
1174 | * disables the channel. | |
1175 | */ | |
1176 | .ident = "M570U", | |
1177 | .matches = { | |
1178 | DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), | |
1179 | DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), | |
1180 | }, | |
1181 | }, | |
7d051548 JG |
1182 | |
1183 | { } /* terminate list */ | |
43a98f05 TH |
1184 | }; |
1185 | u32 iocfg; | |
1186 | ||
1187 | if (!dmi_check_system(sysids)) | |
1188 | return; | |
1189 | ||
1190 | /* The datasheet says that bit 18 is NOOP but certain systems | |
1191 | * seem to use it to disable a channel. Clear the bit on the | |
1192 | * affected systems. | |
1193 | */ | |
1194 | pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); | |
1195 | if (iocfg & (1 << 18)) { | |
1196 | dev_printk(KERN_INFO, &pdev->dev, | |
1197 | "applying IOCFG bit18 quirk\n"); | |
1198 | iocfg &= ~(1 << 18); | |
1199 | pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); | |
1200 | } | |
1201 | } | |
1202 | ||
1da177e4 LT |
1203 | /** |
1204 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
1205 | * @pdev: PCI device to register | |
1206 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
1207 | * | |
1208 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
1209 | * and then hand over control to libata, for it to do the rest. | |
1210 | * | |
1211 | * LOCKING: | |
1212 | * Inherited from PCI layer (may sleep). | |
1213 | * | |
1214 | * RETURNS: | |
1215 | * Zero on success, or -ERRNO value. | |
1216 | */ | |
1217 | ||
1218 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1219 | { | |
1220 | static int printed_version; | |
24dc5f33 | 1221 | struct device *dev = &pdev->dev; |
d33f58b8 | 1222 | struct ata_port_info port_info[2]; |
1626aeb8 | 1223 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
d96715c1 | 1224 | struct piix_host_priv *hpriv; |
cca3974e | 1225 | unsigned long port_flags; |
1da177e4 LT |
1226 | |
1227 | if (!printed_version++) | |
6248e647 JG |
1228 | dev_printk(KERN_DEBUG, &pdev->dev, |
1229 | "version " DRV_VERSION "\n"); | |
1da177e4 LT |
1230 | |
1231 | /* no hotplugging support (FIXME) */ | |
1232 | if (!in_module_init) | |
1233 | return -ENODEV; | |
1234 | ||
24dc5f33 | 1235 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
d96715c1 TH |
1236 | if (!hpriv) |
1237 | return -ENOMEM; | |
1238 | ||
d33f58b8 TH |
1239 | port_info[0] = piix_port_info[ent->driver_data]; |
1240 | port_info[1] = piix_port_info[ent->driver_data]; | |
d96715c1 TH |
1241 | port_info[0].private_data = hpriv; |
1242 | port_info[1].private_data = hpriv; | |
1da177e4 | 1243 | |
cca3974e | 1244 | port_flags = port_info[0].flags; |
ff0fc146 | 1245 | |
cca3974e | 1246 | if (port_flags & PIIX_FLAG_AHCI) { |
8a60a071 JG |
1247 | u8 tmp; |
1248 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); | |
1249 | if (tmp == PIIX_AHCI_DEVICE) { | |
1250 | int rc = piix_disable_ahci(pdev); | |
1251 | if (rc) | |
1252 | return rc; | |
1253 | } | |
1da177e4 LT |
1254 | } |
1255 | ||
d33f58b8 | 1256 | /* Initialize SATA map */ |
cca3974e | 1257 | if (port_flags & ATA_FLAG_SATA) { |
d96715c1 TH |
1258 | piix_init_sata_map(pdev, port_info, |
1259 | piix_map_db_table[ent->driver_data]); | |
9dd9c164 TH |
1260 | piix_init_pcs(pdev, port_info, |
1261 | piix_map_db_table[ent->driver_data]); | |
ea35d29e | 1262 | } |
1da177e4 | 1263 | |
43a98f05 TH |
1264 | /* apply IOCFG bit18 quirk */ |
1265 | piix_iocfg_bit18_quirk(pdev); | |
1266 | ||
1da177e4 LT |
1267 | /* On ICH5, some BIOSen disable the interrupt using the |
1268 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
1269 | * On ICH6, this bit has the same effect, but only when | |
1270 | * MSI is disabled (and it is disabled, as we don't use | |
1271 | * message-signalled interrupts currently). | |
1272 | */ | |
cca3974e | 1273 | if (port_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ff | 1274 | pci_intx(pdev, 1); |
1da177e4 | 1275 | |
c621b140 AC |
1276 | if (piix_check_450nx_errata(pdev)) { |
1277 | /* This writes into the master table but it does not | |
1278 | really matter for this errata as we will apply it to | |
1279 | all the PIIX devices on the board */ | |
d33f58b8 TH |
1280 | port_info[0].mwdma_mask = 0; |
1281 | port_info[0].udma_mask = 0; | |
1282 | port_info[1].mwdma_mask = 0; | |
1283 | port_info[1].udma_mask = 0; | |
c621b140 | 1284 | } |
1626aeb8 | 1285 | return ata_pci_init_one(pdev, ppi); |
1da177e4 LT |
1286 | } |
1287 | ||
1da177e4 LT |
1288 | static int __init piix_init(void) |
1289 | { | |
1290 | int rc; | |
1291 | ||
b7887196 PR |
1292 | DPRINTK("pci_register_driver\n"); |
1293 | rc = pci_register_driver(&piix_pci_driver); | |
1da177e4 LT |
1294 | if (rc) |
1295 | return rc; | |
1296 | ||
1297 | in_module_init = 0; | |
1298 | ||
1299 | DPRINTK("done\n"); | |
1300 | return 0; | |
1301 | } | |
1302 | ||
1da177e4 LT |
1303 | static void __exit piix_exit(void) |
1304 | { | |
1305 | pci_unregister_driver(&piix_pci_driver); | |
1306 | } | |
1307 | ||
1308 | module_init(piix_init); | |
1309 | module_exit(piix_exit); |