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1da177e4 | 1 | /* |
af36d7f0 JG |
2 | * ata_piix.c - Intel PATA/SATA controllers |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * | |
9 | * Copyright 2003-2005 Red Hat Inc | |
10 | * Copyright 2003-2005 Jeff Garzik | |
11 | * | |
12 | * | |
13 | * Copyright header from piix.c: | |
14 | * | |
15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer | |
16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> | |
17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> | |
18 | * | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or modify | |
21 | * it under the terms of the GNU General Public License as published by | |
22 | * the Free Software Foundation; either version 2, or (at your option) | |
23 | * any later version. | |
24 | * | |
25 | * This program is distributed in the hope that it will be useful, | |
26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
28 | * GNU General Public License for more details. | |
29 | * | |
30 | * You should have received a copy of the GNU General Public License | |
31 | * along with this program; see the file COPYING. If not, write to | |
32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | * | |
34 | * | |
35 | * libata documentation is available via 'make {ps|pdf}docs', | |
36 | * as Documentation/DocBook/libata.* | |
37 | * | |
38 | * Hardware documentation available at http://developer.intel.com/ | |
39 | * | |
d96212ed AC |
40 | * Documentation |
41 | * Publically available from Intel web site. Errata documentation | |
42 | * is also publically available. As an aide to anyone hacking on this | |
43 | * driver the list of errata that are relevant is below.going back to | |
44 | * PIIX4. Older device documentation is now a bit tricky to find. | |
45 | * | |
46 | * The chipsets all follow very much the same design. The orginal Triton | |
47 | * series chipsets do _not_ support independant device timings, but this | |
48 | * is fixed in Triton II. With the odd mobile exception the chips then | |
49 | * change little except in gaining more modes until SATA arrives. This | |
50 | * driver supports only the chips with independant timing (that is those | |
51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix | |
52 | * for the early chip drivers. | |
53 | * | |
54 | * Errata of note: | |
55 | * | |
56 | * Unfixable | |
57 | * PIIX4 errata #9 - Only on ultra obscure hw | |
58 | * ICH3 errata #13 - Not observed to affect real hw | |
59 | * by Intel | |
60 | * | |
61 | * Things we must deal with | |
62 | * PIIX4 errata #10 - BM IDE hang with non UDMA | |
63 | * (must stop/start dma to recover) | |
64 | * 440MX errata #15 - As PIIX4 errata #10 | |
65 | * PIIX4 errata #15 - Must not read control registers | |
66 | * during a PIO transfer | |
67 | * 440MX errata #13 - As PIIX4 errata #15 | |
68 | * ICH2 errata #21 - DMA mode 0 doesn't work right | |
69 | * ICH0/1 errata #55 - As ICH2 errata #21 | |
70 | * ICH2 spec c #9 - Extra operations needed to handle | |
71 | * drive hotswap [NOT YET SUPPORTED] | |
72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary | |
73 | * and must be dword aligned | |
74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 | |
75 | * | |
76 | * Should have been BIOS fixed: | |
77 | * 450NX: errata #19 - DMA hangs on old 450NX | |
78 | * 450NX: errata #20 - DMA hangs on old 450NX | |
79 | * 450NX: errata #25 - Corruption with DMA on old 450NX | |
80 | * ICH3 errata #15 - IDE deadlock under high load | |
81 | * (BIOS must set dev 31 fn 0 bit 23) | |
82 | * ICH3 errata #18 - Don't use native mode | |
1da177e4 LT |
83 | */ |
84 | ||
85 | #include <linux/kernel.h> | |
86 | #include <linux/module.h> | |
87 | #include <linux/pci.h> | |
88 | #include <linux/init.h> | |
89 | #include <linux/blkdev.h> | |
90 | #include <linux/delay.h> | |
6248e647 | 91 | #include <linux/device.h> |
1da177e4 LT |
92 | #include <scsi/scsi_host.h> |
93 | #include <linux/libata.h> | |
94 | ||
95 | #define DRV_NAME "ata_piix" | |
669a5db4 | 96 | #define DRV_VERSION "2.00ac6" |
1da177e4 LT |
97 | |
98 | enum { | |
99 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ | |
100 | ICH5_PMR = 0x90, /* port mapping register */ | |
101 | ICH5_PCS = 0x92, /* port control and status */ | |
7b6dbd68 | 102 | PIIX_SCC = 0x0A, /* sub-class code register */ |
1da177e4 | 103 | |
219e6214 | 104 | PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */ |
d4358048 | 105 | PIIX_FLAG_SCR = (1 << 26), /* SCR available */ |
ff0fc146 TH |
106 | PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */ |
107 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ | |
1da177e4 LT |
108 | |
109 | /* combined mode. if set, PATA is channel 0. | |
110 | * if clear, PATA is channel 1. | |
111 | */ | |
6a690df5 HR |
112 | PIIX_PORT_ENABLED = (1 << 0), |
113 | PIIX_PORT_PRESENT = (1 << 4), | |
1da177e4 LT |
114 | |
115 | PIIX_80C_PRI = (1 << 5) | (1 << 4), | |
116 | PIIX_80C_SEC = (1 << 7) | (1 << 6), | |
117 | ||
1d076e5b | 118 | /* controller IDs */ |
669a5db4 JG |
119 | piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */ |
120 | ich_pata_33 = 1, /* ICH up to UDMA 33 only */ | |
121 | ich_pata_66 = 2, /* ICH up to 66 Mhz */ | |
122 | ich_pata_100 = 3, /* ICH up to UDMA 100 */ | |
123 | ich_pata_133 = 4, /* ICH up to UDMA 133 */ | |
124 | ich5_sata = 5, | |
125 | esb_sata = 6, | |
126 | ich6_sata = 7, | |
127 | ich6_sata_ahci = 8, | |
128 | ich6m_sata_ahci = 9, | |
dd1dc802 JG |
129 | ich7m_sata_ahci = 10, |
130 | ich8_sata_ahci = 11, | |
85cd7251 | 131 | |
d33f58b8 TH |
132 | /* constants for mapping table */ |
133 | P0 = 0, /* port 0 */ | |
134 | P1 = 1, /* port 1 */ | |
135 | P2 = 2, /* port 2 */ | |
136 | P3 = 3, /* port 3 */ | |
137 | IDE = -1, /* IDE */ | |
138 | NA = -2, /* not avaliable */ | |
139 | RV = -3, /* reserved */ | |
140 | ||
7b6dbd68 | 141 | PIIX_AHCI_DEVICE = 6, |
1da177e4 LT |
142 | }; |
143 | ||
d33f58b8 TH |
144 | struct piix_map_db { |
145 | const u32 mask; | |
73291a1c | 146 | const u16 port_enable; |
08f12edc | 147 | const int present_shift; |
d33f58b8 TH |
148 | const int map[][4]; |
149 | }; | |
150 | ||
d96715c1 TH |
151 | struct piix_host_priv { |
152 | const int *map; | |
08f12edc | 153 | const struct piix_map_db *map_db; |
d96715c1 TH |
154 | }; |
155 | ||
1da177e4 LT |
156 | static int piix_init_one (struct pci_dev *pdev, |
157 | const struct pci_device_id *ent); | |
cca3974e | 158 | static void piix_host_stop(struct ata_host *host); |
ccc4672a | 159 | static void piix_pata_error_handler(struct ata_port *ap); |
669a5db4 | 160 | static void ich_pata_error_handler(struct ata_port *ap); |
ccc4672a | 161 | static void piix_sata_error_handler(struct ata_port *ap); |
669a5db4 JG |
162 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev); |
163 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev); | |
164 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev); | |
1da177e4 LT |
165 | |
166 | static unsigned int in_module_init = 1; | |
167 | ||
3b7d697d | 168 | static const struct pci_device_id piix_pci_tbl[] = { |
1da177e4 | 169 | #ifdef ATA_ENABLE_PATA |
669a5db4 JG |
170 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
171 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ | |
172 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
173 | { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
174 | { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
175 | /* Intel PIIX4 */ | |
176 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
177 | /* Intel PIIX4 */ | |
178 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
179 | /* Intel PIIX */ | |
180 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, | |
181 | /* Intel ICH (i810, i815, i840) UDMA 66*/ | |
182 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, | |
183 | /* Intel ICH0 : UDMA 33*/ | |
184 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, | |
185 | /* Intel ICH2M */ | |
186 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
187 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ | |
188 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
189 | /* Intel ICH3M */ | |
190 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
191 | /* Intel ICH3 (E7500/1) UDMA 100 */ | |
192 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
193 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ | |
194 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
195 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
196 | /* Intel ICH5 */ | |
197 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, | |
198 | /* C-ICH (i810E2) */ | |
199 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
85cd7251 | 200 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
669a5db4 JG |
201 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
202 | /* ICH6 (and 6) (i915) UDMA 100 */ | |
203 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
204 | /* ICH7/7-R (i945, i975) UDMA 100*/ | |
205 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 }, | |
206 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, | |
1da177e4 LT |
207 | #endif |
208 | ||
209 | /* NOTE: The following PCI ids must be kept in sync with the | |
210 | * list in drivers/pci/quirks.c. | |
211 | */ | |
212 | ||
1d076e5b | 213 | /* 82801EB (ICH5) */ |
1da177e4 | 214 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b | 215 | /* 82801EB (ICH5) */ |
1da177e4 | 216 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
1d076e5b TH |
217 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
218 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, | |
219 | /* 6300ESB pretending RAID */ | |
220 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata }, | |
221 | /* 82801FB/FW (ICH6/ICH6W) */ | |
1da177e4 | 222 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
1d076e5b | 223 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
1c24a412 | 224 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b TH |
225 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */ |
226 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci }, | |
227 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ | |
1c24a412 | 228 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b | 229 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
67083741 | 230 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7m_sata_ahci }, |
1d076e5b | 231 | /* Enterprise Southbridge 2 (where's the datasheet?) */ |
1c24a412 | 232 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci }, |
1d076e5b | 233 | /* SATA Controller 1 IDE (ICH8, no datasheet yet) */ |
08f12edc | 234 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
1d076e5b | 235 | /* SATA Controller 2 IDE (ICH8, ditto) */ |
08f12edc | 236 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
1d076e5b | 237 | /* Mobile SATA Controller IDE (ICH8M, ditto) */ |
08f12edc | 238 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci }, |
1da177e4 LT |
239 | |
240 | { } /* terminate list */ | |
241 | }; | |
242 | ||
243 | static struct pci_driver piix_pci_driver = { | |
244 | .name = DRV_NAME, | |
245 | .id_table = piix_pci_tbl, | |
246 | .probe = piix_init_one, | |
247 | .remove = ata_pci_remove_one, | |
9b847548 JA |
248 | .suspend = ata_pci_device_suspend, |
249 | .resume = ata_pci_device_resume, | |
1da177e4 LT |
250 | }; |
251 | ||
193515d5 | 252 | static struct scsi_host_template piix_sht = { |
1da177e4 LT |
253 | .module = THIS_MODULE, |
254 | .name = DRV_NAME, | |
255 | .ioctl = ata_scsi_ioctl, | |
256 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
257 | .can_queue = ATA_DEF_QUEUE, |
258 | .this_id = ATA_SHT_THIS_ID, | |
259 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
260 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
261 | .emulated = ATA_SHT_EMULATED, | |
262 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
263 | .proc_name = DRV_NAME, | |
264 | .dma_boundary = ATA_DMA_BOUNDARY, | |
265 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 266 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 267 | .bios_param = ata_std_bios_param, |
9b847548 JA |
268 | .resume = ata_scsi_device_resume, |
269 | .suspend = ata_scsi_device_suspend, | |
1da177e4 LT |
270 | }; |
271 | ||
057ace5e | 272 | static const struct ata_port_operations piix_pata_ops = { |
1da177e4 LT |
273 | .port_disable = ata_port_disable, |
274 | .set_piomode = piix_set_piomode, | |
275 | .set_dmamode = piix_set_dmamode, | |
89bad589 | 276 | .mode_filter = ata_pci_default_filter, |
1da177e4 LT |
277 | |
278 | .tf_load = ata_tf_load, | |
279 | .tf_read = ata_tf_read, | |
280 | .check_status = ata_check_status, | |
281 | .exec_command = ata_exec_command, | |
282 | .dev_select = ata_std_dev_select, | |
283 | ||
1da177e4 LT |
284 | .bmdma_setup = ata_bmdma_setup, |
285 | .bmdma_start = ata_bmdma_start, | |
286 | .bmdma_stop = ata_bmdma_stop, | |
287 | .bmdma_status = ata_bmdma_status, | |
288 | .qc_prep = ata_qc_prep, | |
289 | .qc_issue = ata_qc_issue_prot, | |
89bad589 | 290 | .data_xfer = ata_pio_data_xfer, |
1da177e4 | 291 | |
3f037db0 TH |
292 | .freeze = ata_bmdma_freeze, |
293 | .thaw = ata_bmdma_thaw, | |
ccc4672a | 294 | .error_handler = piix_pata_error_handler, |
3f037db0 | 295 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
1da177e4 LT |
296 | |
297 | .irq_handler = ata_interrupt, | |
298 | .irq_clear = ata_bmdma_irq_clear, | |
299 | ||
300 | .port_start = ata_port_start, | |
301 | .port_stop = ata_port_stop, | |
d96715c1 | 302 | .host_stop = piix_host_stop, |
1da177e4 LT |
303 | }; |
304 | ||
669a5db4 JG |
305 | static const struct ata_port_operations ich_pata_ops = { |
306 | .port_disable = ata_port_disable, | |
307 | .set_piomode = piix_set_piomode, | |
308 | .set_dmamode = ich_set_dmamode, | |
309 | .mode_filter = ata_pci_default_filter, | |
310 | ||
311 | .tf_load = ata_tf_load, | |
312 | .tf_read = ata_tf_read, | |
313 | .check_status = ata_check_status, | |
314 | .exec_command = ata_exec_command, | |
315 | .dev_select = ata_std_dev_select, | |
316 | ||
317 | .bmdma_setup = ata_bmdma_setup, | |
318 | .bmdma_start = ata_bmdma_start, | |
319 | .bmdma_stop = ata_bmdma_stop, | |
320 | .bmdma_status = ata_bmdma_status, | |
321 | .qc_prep = ata_qc_prep, | |
322 | .qc_issue = ata_qc_issue_prot, | |
323 | .data_xfer = ata_pio_data_xfer, | |
324 | ||
325 | .freeze = ata_bmdma_freeze, | |
326 | .thaw = ata_bmdma_thaw, | |
327 | .error_handler = ich_pata_error_handler, | |
328 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
329 | ||
330 | .irq_handler = ata_interrupt, | |
331 | .irq_clear = ata_bmdma_irq_clear, | |
332 | ||
333 | .port_start = ata_port_start, | |
334 | .port_stop = ata_port_stop, | |
335 | .host_stop = ata_host_stop, | |
336 | }; | |
337 | ||
057ace5e | 338 | static const struct ata_port_operations piix_sata_ops = { |
1da177e4 LT |
339 | .port_disable = ata_port_disable, |
340 | ||
341 | .tf_load = ata_tf_load, | |
342 | .tf_read = ata_tf_read, | |
343 | .check_status = ata_check_status, | |
344 | .exec_command = ata_exec_command, | |
345 | .dev_select = ata_std_dev_select, | |
346 | ||
1da177e4 LT |
347 | .bmdma_setup = ata_bmdma_setup, |
348 | .bmdma_start = ata_bmdma_start, | |
349 | .bmdma_stop = ata_bmdma_stop, | |
350 | .bmdma_status = ata_bmdma_status, | |
351 | .qc_prep = ata_qc_prep, | |
352 | .qc_issue = ata_qc_issue_prot, | |
89bad589 | 353 | .data_xfer = ata_pio_data_xfer, |
1da177e4 | 354 | |
3f037db0 TH |
355 | .freeze = ata_bmdma_freeze, |
356 | .thaw = ata_bmdma_thaw, | |
ccc4672a | 357 | .error_handler = piix_sata_error_handler, |
3f037db0 | 358 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
1da177e4 LT |
359 | |
360 | .irq_handler = ata_interrupt, | |
361 | .irq_clear = ata_bmdma_irq_clear, | |
362 | ||
363 | .port_start = ata_port_start, | |
364 | .port_stop = ata_port_stop, | |
d96715c1 | 365 | .host_stop = piix_host_stop, |
1da177e4 LT |
366 | }; |
367 | ||
d96715c1 | 368 | static const struct piix_map_db ich5_map_db = { |
d33f58b8 | 369 | .mask = 0x7, |
ea35d29e | 370 | .port_enable = 0x3, |
08f12edc | 371 | .present_shift = 4, |
d33f58b8 TH |
372 | .map = { |
373 | /* PM PS SM SS MAP */ | |
374 | { P0, NA, P1, NA }, /* 000b */ | |
375 | { P1, NA, P0, NA }, /* 001b */ | |
376 | { RV, RV, RV, RV }, | |
377 | { RV, RV, RV, RV }, | |
378 | { P0, P1, IDE, IDE }, /* 100b */ | |
379 | { P1, P0, IDE, IDE }, /* 101b */ | |
380 | { IDE, IDE, P0, P1 }, /* 110b */ | |
381 | { IDE, IDE, P1, P0 }, /* 111b */ | |
382 | }, | |
383 | }; | |
384 | ||
d96715c1 | 385 | static const struct piix_map_db ich6_map_db = { |
d33f58b8 | 386 | .mask = 0x3, |
ea35d29e | 387 | .port_enable = 0xf, |
08f12edc | 388 | .present_shift = 4, |
d33f58b8 TH |
389 | .map = { |
390 | /* PM PS SM SS MAP */ | |
79ea24e7 | 391 | { P0, P2, P1, P3 }, /* 00b */ |
d33f58b8 TH |
392 | { IDE, IDE, P1, P3 }, /* 01b */ |
393 | { P0, P2, IDE, IDE }, /* 10b */ | |
394 | { RV, RV, RV, RV }, | |
395 | }, | |
396 | }; | |
397 | ||
d96715c1 | 398 | static const struct piix_map_db ich6m_map_db = { |
d33f58b8 | 399 | .mask = 0x3, |
ea35d29e | 400 | .port_enable = 0x5, |
08f12edc | 401 | .present_shift = 4, |
d33f58b8 TH |
402 | .map = { |
403 | /* PM PS SM SS MAP */ | |
79ea24e7 | 404 | { P0, P2, RV, RV }, /* 00b */ |
d33f58b8 TH |
405 | { RV, RV, RV, RV }, |
406 | { P0, P2, IDE, IDE }, /* 10b */ | |
407 | { RV, RV, RV, RV }, | |
408 | }, | |
409 | }; | |
410 | ||
67083741 TH |
411 | static const struct piix_map_db ich7m_map_db = { |
412 | .mask = 0x3, | |
413 | .port_enable = 0x5, | |
414 | .present_shift = 4, | |
415 | ||
416 | /* Map 01b isn't specified in the doc but some notebooks use | |
417 | * it anyway. ATM, the only case spotted carries subsystem ID | |
418 | * 1025:0107. This is the only difference from ich6m. | |
419 | */ | |
420 | .map = { | |
421 | /* PM PS SM SS MAP */ | |
422 | { P0, P2, RV, RV }, /* 00b */ | |
423 | { IDE, IDE, P1, P3 }, /* 01b */ | |
424 | { P0, P2, IDE, IDE }, /* 10b */ | |
425 | { RV, RV, RV, RV }, | |
426 | }, | |
427 | }; | |
428 | ||
08f12edc JG |
429 | static const struct piix_map_db ich8_map_db = { |
430 | .mask = 0x3, | |
431 | .port_enable = 0x3, | |
432 | .present_shift = 8, | |
433 | .map = { | |
434 | /* PM PS SM SS MAP */ | |
f5beec49 | 435 | { P0, NA, P1, NA }, /* 00b (hardwired) */ |
08f12edc JG |
436 | { RV, RV, RV, RV }, |
437 | { RV, RV, RV, RV }, /* 10b (never) */ | |
438 | { RV, RV, RV, RV }, | |
439 | }, | |
440 | }; | |
441 | ||
d96715c1 TH |
442 | static const struct piix_map_db *piix_map_db_table[] = { |
443 | [ich5_sata] = &ich5_map_db, | |
444 | [esb_sata] = &ich5_map_db, | |
445 | [ich6_sata] = &ich6_map_db, | |
446 | [ich6_sata_ahci] = &ich6_map_db, | |
447 | [ich6m_sata_ahci] = &ich6m_map_db, | |
67083741 | 448 | [ich7m_sata_ahci] = &ich7m_map_db, |
08f12edc | 449 | [ich8_sata_ahci] = &ich8_map_db, |
d96715c1 TH |
450 | }; |
451 | ||
1da177e4 | 452 | static struct ata_port_info piix_port_info[] = { |
669a5db4 | 453 | /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */ |
1d076e5b TH |
454 | { |
455 | .sht = &piix_sht, | |
669a5db4 | 456 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, |
1d076e5b | 457 | .pio_mask = 0x1f, /* pio0-4 */ |
669a5db4 | 458 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
1d076e5b TH |
459 | .udma_mask = ATA_UDMA_MASK_40C, |
460 | .port_ops = &piix_pata_ops, | |
461 | }, | |
462 | ||
669a5db4 JG |
463 | /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/ |
464 | { | |
465 | .sht = &piix_sht, | |
466 | .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS, | |
467 | .pio_mask = 0x1f, /* pio 0-4 */ | |
468 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ | |
469 | .udma_mask = ATA_UDMA2, /* UDMA33 */ | |
470 | .port_ops = &ich_pata_ops, | |
471 | }, | |
472 | /* ich_pata_66: 2 ICH controllers up to 66MHz */ | |
1da177e4 LT |
473 | { |
474 | .sht = &piix_sht, | |
669a5db4 JG |
475 | .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS, |
476 | .pio_mask = 0x1f, /* pio 0-4 */ | |
477 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ | |
478 | .udma_mask = ATA_UDMA4, | |
479 | .port_ops = &ich_pata_ops, | |
480 | }, | |
85cd7251 | 481 | |
669a5db4 JG |
482 | /* ich_pata_100: 3 */ |
483 | { | |
484 | .sht = &piix_sht, | |
485 | .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR, | |
1da177e4 | 486 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 | 487 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
669a5db4 JG |
488 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
489 | .port_ops = &ich_pata_ops, | |
1da177e4 LT |
490 | }, |
491 | ||
669a5db4 JG |
492 | /* ich_pata_133: 4 ICH with full UDMA6 */ |
493 | { | |
494 | .sht = &piix_sht, | |
495 | .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR, | |
496 | .pio_mask = 0x1f, /* pio 0-4 */ | |
497 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ | |
498 | .udma_mask = ATA_UDMA6, /* UDMA133 */ | |
499 | .port_ops = &ich_pata_ops, | |
500 | }, | |
501 | ||
502 | /* ich5_sata: 5 */ | |
1da177e4 LT |
503 | { |
504 | .sht = &piix_sht, | |
cca3974e | 505 | .flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR | |
f3745a3f | 506 | PIIX_FLAG_IGNORE_PCS, |
1da177e4 LT |
507 | .pio_mask = 0x1f, /* pio0-4 */ |
508 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
509 | .udma_mask = 0x7f, /* udma0-6 */ | |
510 | .port_ops = &piix_sata_ops, | |
511 | }, | |
512 | ||
669a5db4 | 513 | /* i6300esb_sata: 6 */ |
1da177e4 LT |
514 | { |
515 | .sht = &piix_sht, | |
cca3974e | 516 | .flags = ATA_FLAG_SATA | |
219e6214 | 517 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS, |
1da177e4 | 518 | .pio_mask = 0x1f, /* pio0-4 */ |
1d076e5b TH |
519 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
520 | .udma_mask = 0x7f, /* udma0-6 */ | |
521 | .port_ops = &piix_sata_ops, | |
1da177e4 LT |
522 | }, |
523 | ||
669a5db4 | 524 | /* ich6_sata: 7 */ |
1da177e4 LT |
525 | { |
526 | .sht = &piix_sht, | |
cca3974e | 527 | .flags = ATA_FLAG_SATA | |
d33f58b8 | 528 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR, |
1da177e4 LT |
529 | .pio_mask = 0x1f, /* pio0-4 */ |
530 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
531 | .udma_mask = 0x7f, /* udma0-6 */ | |
532 | .port_ops = &piix_sata_ops, | |
533 | }, | |
534 | ||
dd1dc802 | 535 | /* ich6_sata_ahci: 8 */ |
c368ca4e JG |
536 | { |
537 | .sht = &piix_sht, | |
cca3974e | 538 | .flags = ATA_FLAG_SATA | |
d33f58b8 TH |
539 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
540 | PIIX_FLAG_AHCI, | |
c368ca4e JG |
541 | .pio_mask = 0x1f, /* pio0-4 */ |
542 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
543 | .udma_mask = 0x7f, /* udma0-6 */ | |
544 | .port_ops = &piix_sata_ops, | |
545 | }, | |
1d076e5b | 546 | |
669a5db4 | 547 | /* ich6m_sata_ahci: 9 */ |
1d076e5b TH |
548 | { |
549 | .sht = &piix_sht, | |
cca3974e | 550 | .flags = ATA_FLAG_SATA | |
d33f58b8 TH |
551 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
552 | PIIX_FLAG_AHCI, | |
1d076e5b TH |
553 | .pio_mask = 0x1f, /* pio0-4 */ |
554 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
555 | .udma_mask = 0x7f, /* udma0-6 */ | |
556 | .port_ops = &piix_sata_ops, | |
557 | }, | |
08f12edc | 558 | |
dd1dc802 | 559 | /* ich7m_sata_ahci: 10 */ |
67083741 TH |
560 | { |
561 | .sht = &piix_sht, | |
b0fea350 | 562 | .flags = ATA_FLAG_SATA | |
67083741 TH |
563 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
564 | PIIX_FLAG_AHCI, | |
565 | .pio_mask = 0x1f, /* pio0-4 */ | |
566 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
567 | .udma_mask = 0x7f, /* udma0-6 */ | |
568 | .port_ops = &piix_sata_ops, | |
569 | }, | |
570 | ||
dd1dc802 | 571 | /* ich8_sata_ahci: 11 */ |
08f12edc JG |
572 | { |
573 | .sht = &piix_sht, | |
cca3974e | 574 | .flags = ATA_FLAG_SATA | |
08f12edc JG |
575 | PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR | |
576 | PIIX_FLAG_AHCI, | |
577 | .pio_mask = 0x1f, /* pio0-4 */ | |
578 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
579 | .udma_mask = 0x7f, /* udma0-6 */ | |
580 | .port_ops = &piix_sata_ops, | |
581 | }, | |
669a5db4 | 582 | |
1da177e4 LT |
583 | }; |
584 | ||
585 | static struct pci_bits piix_enable_bits[] = { | |
586 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
587 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
588 | }; | |
589 | ||
590 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); | |
591 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); | |
592 | MODULE_LICENSE("GPL"); | |
593 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); | |
594 | MODULE_VERSION(DRV_VERSION); | |
595 | ||
9dd9c164 TH |
596 | static int force_pcs = 0; |
597 | module_param(force_pcs, int, 0444); | |
598 | MODULE_PARM_DESC(force_pcs, "force honoring or ignoring PCS to work around " | |
599 | "device mis-detection (0=default, 1=ignore PCS, 2=honor PCS)"); | |
600 | ||
1da177e4 LT |
601 | /** |
602 | * piix_pata_cbl_detect - Probe host controller cable detect info | |
603 | * @ap: Port for which cable detect info is desired | |
604 | * | |
605 | * Read 80c cable indicator from ATA PCI device's PCI config | |
606 | * register. This register is normally set by firmware (BIOS). | |
607 | * | |
608 | * LOCKING: | |
609 | * None (inherited from caller). | |
610 | */ | |
669a5db4 JG |
611 | |
612 | static void ich_pata_cbl_detect(struct ata_port *ap) | |
1da177e4 | 613 | { |
cca3974e | 614 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 LT |
615 | u8 tmp, mask; |
616 | ||
617 | /* no 80c support in host controller? */ | |
618 | if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0) | |
619 | goto cbl40; | |
620 | ||
621 | /* check BIOS cable detect results */ | |
2a88d1ac | 622 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
1da177e4 LT |
623 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
624 | if ((tmp & mask) == 0) | |
625 | goto cbl40; | |
626 | ||
627 | ap->cbl = ATA_CBL_PATA80; | |
628 | return; | |
629 | ||
630 | cbl40: | |
631 | ap->cbl = ATA_CBL_PATA40; | |
1da177e4 LT |
632 | } |
633 | ||
634 | /** | |
ccc4672a | 635 | * piix_pata_prereset - prereset for PATA host controller |
573db6b8 | 636 | * @ap: Target port |
1da177e4 | 637 | * |
573db6b8 TH |
638 | * |
639 | * LOCKING: | |
640 | * None (inherited from caller). | |
641 | */ | |
ccc4672a | 642 | static int piix_pata_prereset(struct ata_port *ap) |
1da177e4 | 643 | { |
cca3974e | 644 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 645 | |
2a88d1ac | 646 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) { |
f15a1daf | 647 | ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n"); |
ccc4672a | 648 | ap->eh_context.i.action &= ~ATA_EH_RESET_MASK; |
573db6b8 | 649 | return 0; |
1da177e4 | 650 | } |
669a5db4 | 651 | ap->cbl = ATA_CBL_PATA40; |
ccc4672a TH |
652 | return ata_std_prereset(ap); |
653 | } | |
654 | ||
655 | static void piix_pata_error_handler(struct ata_port *ap) | |
656 | { | |
657 | ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL, | |
658 | ata_std_postreset); | |
1da177e4 LT |
659 | } |
660 | ||
669a5db4 JG |
661 | |
662 | /** | |
663 | * ich_pata_prereset - prereset for PATA host controller | |
664 | * @ap: Target port | |
665 | * | |
666 | * | |
667 | * LOCKING: | |
668 | * None (inherited from caller). | |
669 | */ | |
670 | static int ich_pata_prereset(struct ata_port *ap) | |
671 | { | |
672 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
673 | ||
674 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) { | |
675 | ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n"); | |
676 | ap->eh_context.i.action &= ~ATA_EH_RESET_MASK; | |
677 | return 0; | |
678 | } | |
679 | ||
680 | ich_pata_cbl_detect(ap); | |
681 | ||
682 | return ata_std_prereset(ap); | |
683 | } | |
684 | ||
685 | static void ich_pata_error_handler(struct ata_port *ap) | |
686 | { | |
687 | ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL, | |
688 | ata_std_postreset); | |
689 | } | |
690 | ||
1da177e4 | 691 | /** |
f1a58eca | 692 | * piix_sata_present_mask - determine present mask for SATA host controller |
ccc4672a | 693 | * @ap: Target port |
1da177e4 | 694 | * |
f1a58eca TH |
695 | * Reads SATA PCI device's PCI config register Port Configuration |
696 | * and Status (PCS) to determine port and device availability. | |
1da177e4 LT |
697 | * |
698 | * LOCKING: | |
699 | * None (inherited from caller). | |
700 | * | |
701 | * RETURNS: | |
f1a58eca | 702 | * determined present_mask |
1da177e4 | 703 | */ |
f1a58eca | 704 | static unsigned int piix_sata_present_mask(struct ata_port *ap) |
1da177e4 | 705 | { |
cca3974e JG |
706 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
707 | struct piix_host_priv *hpriv = ap->host->private_data; | |
d96715c1 | 708 | const unsigned int *map = hpriv->map; |
2a88d1ac | 709 | int base = 2 * ap->port_no; |
f1a58eca | 710 | unsigned int present_mask = 0; |
d133ecab | 711 | int port, i; |
ea35d29e | 712 | u16 pcs; |
1da177e4 | 713 | |
ea35d29e | 714 | pci_read_config_word(pdev, ICH5_PCS, &pcs); |
d133ecab TH |
715 | DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base); |
716 | ||
d133ecab TH |
717 | for (i = 0; i < 2; i++) { |
718 | port = map[base + i]; | |
719 | if (port < 0) | |
720 | continue; | |
08f12edc JG |
721 | if ((ap->flags & PIIX_FLAG_IGNORE_PCS) || |
722 | (pcs & 1 << (hpriv->map_db->present_shift + port))) | |
f1a58eca | 723 | present_mask |= 1 << i; |
1da177e4 LT |
724 | } |
725 | ||
f1a58eca TH |
726 | DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n", |
727 | ap->id, pcs, present_mask); | |
d133ecab | 728 | |
f1a58eca TH |
729 | return present_mask; |
730 | } | |
731 | ||
732 | /** | |
733 | * piix_sata_softreset - reset SATA host port via ATA SRST | |
734 | * @ap: port to reset | |
735 | * @classes: resulting classes of attached devices | |
736 | * | |
737 | * Reset SATA host port via ATA SRST. On controllers with | |
738 | * reliable PCS present bits, the bits are used to determine | |
739 | * device presence. | |
740 | * | |
741 | * LOCKING: | |
742 | * Kernel thread context (may sleep) | |
743 | * | |
744 | * RETURNS: | |
745 | * 0 on success, -errno otherwise. | |
746 | */ | |
747 | static int piix_sata_softreset(struct ata_port *ap, unsigned int *classes) | |
748 | { | |
749 | unsigned int present_mask; | |
750 | int i, rc; | |
751 | ||
752 | present_mask = piix_sata_present_mask(ap); | |
753 | ||
754 | rc = ata_std_softreset(ap, classes); | |
755 | if (rc) | |
756 | return rc; | |
757 | ||
758 | for (i = 0; i < ATA_MAX_DEVICES; i++) { | |
759 | if (!(present_mask & (1 << i))) | |
760 | classes[i] = ATA_DEV_NONE; | |
1da177e4 LT |
761 | } |
762 | ||
f1a58eca | 763 | return 0; |
ccc4672a TH |
764 | } |
765 | ||
766 | static void piix_sata_error_handler(struct ata_port *ap) | |
767 | { | |
f1a58eca | 768 | ata_bmdma_drive_eh(ap, ata_std_prereset, piix_sata_softreset, NULL, |
ccc4672a | 769 | ata_std_postreset); |
1da177e4 LT |
770 | } |
771 | ||
772 | /** | |
773 | * piix_set_piomode - Initialize host controller PATA PIO timings | |
774 | * @ap: Port whose timings we are configuring | |
775 | * @adev: um | |
1da177e4 LT |
776 | * |
777 | * Set PIO mode for device, in host controller PCI config space. | |
778 | * | |
779 | * LOCKING: | |
780 | * None (inherited from caller). | |
781 | */ | |
782 | ||
783 | static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
784 | { | |
785 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
cca3974e | 786 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
1da177e4 | 787 | unsigned int is_slave = (adev->devno != 0); |
2a88d1ac | 788 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
1da177e4 LT |
789 | unsigned int slave_port = 0x44; |
790 | u16 master_data; | |
791 | u8 slave_data; | |
669a5db4 JG |
792 | u8 udma_enable; |
793 | int control = 0; | |
85cd7251 | 794 | |
669a5db4 JG |
795 | /* |
796 | * See Intel Document 298600-004 for the timing programing rules | |
797 | * for ICH controllers. | |
798 | */ | |
1da177e4 LT |
799 | |
800 | static const /* ISP RTC */ | |
801 | u8 timings[][2] = { { 0, 0 }, | |
802 | { 0, 0 }, | |
803 | { 1, 0 }, | |
804 | { 2, 1 }, | |
805 | { 2, 3 }, }; | |
806 | ||
669a5db4 JG |
807 | if (pio >= 2) |
808 | control |= 1; /* TIME1 enable */ | |
809 | if (ata_pio_need_iordy(adev)) | |
810 | control |= 2; /* IE enable */ | |
811 | ||
85cd7251 | 812 | /* Intel specifies that the PPE functionality is for disk only */ |
669a5db4 JG |
813 | if (adev->class == ATA_DEV_ATA) |
814 | control |= 4; /* PPE enable */ | |
815 | ||
1da177e4 LT |
816 | pci_read_config_word(dev, master_port, &master_data); |
817 | if (is_slave) { | |
669a5db4 | 818 | /* Enable SITRE (seperate slave timing register) */ |
1da177e4 | 819 | master_data |= 0x4000; |
669a5db4 JG |
820 | /* enable PPE1, IE1 and TIME1 as needed */ |
821 | master_data |= (control << 4); | |
1da177e4 | 822 | pci_read_config_byte(dev, slave_port, &slave_data); |
2a88d1ac | 823 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
669a5db4 JG |
824 | /* Load the timing nibble for this slave */ |
825 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
1da177e4 | 826 | } else { |
669a5db4 | 827 | /* Master keeps the bits in a different format */ |
1da177e4 | 828 | master_data &= 0xccf8; |
669a5db4 JG |
829 | /* Enable PPE, IE and TIME as appropriate */ |
830 | master_data |= control; | |
1da177e4 LT |
831 | master_data |= |
832 | (timings[pio][0] << 12) | | |
833 | (timings[pio][1] << 8); | |
834 | } | |
835 | pci_write_config_word(dev, master_port, master_data); | |
836 | if (is_slave) | |
837 | pci_write_config_byte(dev, slave_port, slave_data); | |
669a5db4 JG |
838 | |
839 | /* Ensure the UDMA bit is off - it will be turned back on if | |
840 | UDMA is selected */ | |
85cd7251 | 841 | |
669a5db4 JG |
842 | if (ap->udma_mask) { |
843 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
844 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); | |
845 | pci_write_config_byte(dev, 0x48, udma_enable); | |
846 | } | |
1da177e4 LT |
847 | } |
848 | ||
849 | /** | |
669a5db4 | 850 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
1da177e4 | 851 | * @ap: Port whose timings we are configuring |
669a5db4 | 852 | * @adev: Drive in question |
1da177e4 | 853 | * @udma: udma mode, 0 - 6 |
669a5db4 | 854 | * @is_ich: set if the chip is an ICH device |
1da177e4 LT |
855 | * |
856 | * Set UDMA mode for device, in host controller PCI config space. | |
857 | * | |
858 | * LOCKING: | |
859 | * None (inherited from caller). | |
860 | */ | |
861 | ||
669a5db4 | 862 | static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich) |
1da177e4 | 863 | { |
cca3974e | 864 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
669a5db4 JG |
865 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
866 | u16 master_data; | |
867 | u8 speed = adev->dma_mode; | |
868 | int devid = adev->devno + 2 * ap->port_no; | |
869 | u8 udma_enable; | |
85cd7251 | 870 | |
669a5db4 JG |
871 | static const /* ISP RTC */ |
872 | u8 timings[][2] = { { 0, 0 }, | |
873 | { 0, 0 }, | |
874 | { 1, 0 }, | |
875 | { 2, 1 }, | |
876 | { 2, 3 }, }; | |
877 | ||
878 | pci_read_config_word(dev, master_port, &master_data); | |
879 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
1da177e4 LT |
880 | |
881 | if (speed >= XFER_UDMA_0) { | |
669a5db4 JG |
882 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
883 | u16 udma_timing; | |
884 | u16 ideconf; | |
885 | int u_clock, u_speed; | |
85cd7251 | 886 | |
669a5db4 JG |
887 | /* |
888 | * UDMA is handled by a combination of clock switching and | |
85cd7251 JG |
889 | * selection of dividers |
890 | * | |
669a5db4 | 891 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
85cd7251 | 892 | * except UDMA0 which is 00 |
669a5db4 JG |
893 | */ |
894 | u_speed = min(2 - (udma & 1), udma); | |
895 | if (udma == 5) | |
896 | u_clock = 0x1000; /* 100Mhz */ | |
897 | else if (udma > 2) | |
898 | u_clock = 1; /* 66Mhz */ | |
899 | else | |
900 | u_clock = 0; /* 33Mhz */ | |
85cd7251 | 901 | |
669a5db4 | 902 | udma_enable |= (1 << devid); |
85cd7251 | 903 | |
669a5db4 JG |
904 | /* Load the CT/RP selection */ |
905 | pci_read_config_word(dev, 0x4A, &udma_timing); | |
906 | udma_timing &= ~(3 << (4 * devid)); | |
907 | udma_timing |= u_speed << (4 * devid); | |
908 | pci_write_config_word(dev, 0x4A, udma_timing); | |
909 | ||
85cd7251 | 910 | if (isich) { |
669a5db4 JG |
911 | /* Select a 33/66/100Mhz clock */ |
912 | pci_read_config_word(dev, 0x54, &ideconf); | |
913 | ideconf &= ~(0x1001 << devid); | |
914 | ideconf |= u_clock << devid; | |
915 | /* For ICH or later we should set bit 10 for better | |
916 | performance (WR_PingPong_En) */ | |
917 | pci_write_config_word(dev, 0x54, ideconf); | |
1da177e4 | 918 | } |
1da177e4 | 919 | } else { |
669a5db4 JG |
920 | /* |
921 | * MWDMA is driven by the PIO timings. We must also enable | |
922 | * IORDY unconditionally along with TIME1. PPE has already | |
923 | * been set when the PIO timing was set. | |
924 | */ | |
925 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
926 | unsigned int control; | |
927 | u8 slave_data; | |
928 | const unsigned int needed_pio[3] = { | |
929 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
930 | }; | |
931 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
85cd7251 | 932 | |
669a5db4 | 933 | control = 3; /* IORDY|TIME1 */ |
85cd7251 | 934 | |
669a5db4 JG |
935 | /* If the drive MWDMA is faster than it can do PIO then |
936 | we must force PIO into PIO0 */ | |
85cd7251 | 937 | |
669a5db4 JG |
938 | if (adev->pio_mode < needed_pio[mwdma]) |
939 | /* Enable DMA timing only */ | |
940 | control |= 8; /* PIO cycles in PIO0 */ | |
941 | ||
942 | if (adev->devno) { /* Slave */ | |
943 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ | |
944 | master_data |= control << 4; | |
945 | pci_read_config_byte(dev, 0x44, &slave_data); | |
946 | slave_data &= (0x0F + 0xE1 * ap->port_no); | |
947 | /* Load the matching timing */ | |
948 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
949 | pci_write_config_byte(dev, 0x44, slave_data); | |
950 | } else { /* Master */ | |
85cd7251 | 951 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
669a5db4 JG |
952 | and master timing bits */ |
953 | master_data |= control; | |
954 | master_data |= | |
955 | (timings[pio][0] << 12) | | |
956 | (timings[pio][1] << 8); | |
957 | } | |
958 | udma_enable &= ~(1 << devid); | |
959 | pci_write_config_word(dev, master_port, master_data); | |
1da177e4 | 960 | } |
669a5db4 JG |
961 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
962 | if (ap->udma_mask) | |
963 | pci_write_config_byte(dev, 0x48, udma_enable); | |
964 | } | |
965 | ||
966 | /** | |
967 | * piix_set_dmamode - Initialize host controller PATA DMA timings | |
968 | * @ap: Port whose timings we are configuring | |
969 | * @adev: um | |
970 | * | |
971 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
972 | * | |
973 | * LOCKING: | |
974 | * None (inherited from caller). | |
975 | */ | |
976 | ||
977 | static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
978 | { | |
979 | do_pata_set_dmamode(ap, adev, 0); | |
980 | } | |
981 | ||
982 | /** | |
983 | * ich_set_dmamode - Initialize host controller PATA DMA timings | |
984 | * @ap: Port whose timings we are configuring | |
985 | * @adev: um | |
986 | * | |
987 | * Set MW/UDMA mode for device, in host controller PCI config space. | |
988 | * | |
989 | * LOCKING: | |
990 | * None (inherited from caller). | |
991 | */ | |
992 | ||
993 | static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
994 | { | |
995 | do_pata_set_dmamode(ap, adev, 1); | |
1da177e4 LT |
996 | } |
997 | ||
1da177e4 LT |
998 | #define AHCI_PCI_BAR 5 |
999 | #define AHCI_GLOBAL_CTL 0x04 | |
1000 | #define AHCI_ENABLE (1 << 31) | |
1001 | static int piix_disable_ahci(struct pci_dev *pdev) | |
1002 | { | |
ea6ba10b | 1003 | void __iomem *mmio; |
1da177e4 LT |
1004 | u32 tmp; |
1005 | int rc = 0; | |
1006 | ||
1007 | /* BUG: pci_enable_device has not yet been called. This | |
1008 | * works because this device is usually set up by BIOS. | |
1009 | */ | |
1010 | ||
374b1873 JG |
1011 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
1012 | !pci_resource_len(pdev, AHCI_PCI_BAR)) | |
1da177e4 | 1013 | return 0; |
7b6dbd68 | 1014 | |
374b1873 | 1015 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
1da177e4 LT |
1016 | if (!mmio) |
1017 | return -ENOMEM; | |
7b6dbd68 | 1018 | |
1da177e4 LT |
1019 | tmp = readl(mmio + AHCI_GLOBAL_CTL); |
1020 | if (tmp & AHCI_ENABLE) { | |
1021 | tmp &= ~AHCI_ENABLE; | |
1022 | writel(tmp, mmio + AHCI_GLOBAL_CTL); | |
1023 | ||
1024 | tmp = readl(mmio + AHCI_GLOBAL_CTL); | |
1025 | if (tmp & AHCI_ENABLE) | |
1026 | rc = -EIO; | |
1027 | } | |
7b6dbd68 | 1028 | |
374b1873 | 1029 | pci_iounmap(pdev, mmio); |
1da177e4 LT |
1030 | return rc; |
1031 | } | |
1032 | ||
c621b140 AC |
1033 | /** |
1034 | * piix_check_450nx_errata - Check for problem 450NX setup | |
c893a3ae | 1035 | * @ata_dev: the PCI device to check |
2e9edbf8 | 1036 | * |
c621b140 AC |
1037 | * Check for the present of 450NX errata #19 and errata #25. If |
1038 | * they are found return an error code so we can turn off DMA | |
1039 | */ | |
1040 | ||
1041 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) | |
1042 | { | |
1043 | struct pci_dev *pdev = NULL; | |
1044 | u16 cfg; | |
1045 | u8 rev; | |
1046 | int no_piix_dma = 0; | |
2e9edbf8 | 1047 | |
c621b140 AC |
1048 | while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) |
1049 | { | |
1050 | /* Look for 450NX PXB. Check for problem configurations | |
1051 | A PCI quirk checks bit 6 already */ | |
1052 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); | |
1053 | pci_read_config_word(pdev, 0x41, &cfg); | |
1054 | /* Only on the original revision: IDE DMA can hang */ | |
31a34fe7 | 1055 | if (rev == 0x00) |
c621b140 AC |
1056 | no_piix_dma = 1; |
1057 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ | |
31a34fe7 | 1058 | else if (cfg & (1<<14) && rev < 5) |
c621b140 AC |
1059 | no_piix_dma = 2; |
1060 | } | |
31a34fe7 | 1061 | if (no_piix_dma) |
c621b140 | 1062 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
31a34fe7 | 1063 | if (no_piix_dma == 2) |
c621b140 AC |
1064 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
1065 | return no_piix_dma; | |
2e9edbf8 | 1066 | } |
c621b140 | 1067 | |
ea35d29e | 1068 | static void __devinit piix_init_pcs(struct pci_dev *pdev, |
9dd9c164 | 1069 | struct ata_port_info *pinfo, |
ea35d29e JG |
1070 | const struct piix_map_db *map_db) |
1071 | { | |
1072 | u16 pcs, new_pcs; | |
1073 | ||
1074 | pci_read_config_word(pdev, ICH5_PCS, &pcs); | |
1075 | ||
1076 | new_pcs = pcs | map_db->port_enable; | |
1077 | ||
1078 | if (new_pcs != pcs) { | |
1079 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); | |
1080 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); | |
1081 | msleep(150); | |
1082 | } | |
9dd9c164 TH |
1083 | |
1084 | if (force_pcs == 1) { | |
1085 | dev_printk(KERN_INFO, &pdev->dev, | |
1086 | "force ignoring PCS (0x%x)\n", new_pcs); | |
cca3974e JG |
1087 | pinfo[0].flags |= PIIX_FLAG_IGNORE_PCS; |
1088 | pinfo[1].flags |= PIIX_FLAG_IGNORE_PCS; | |
9dd9c164 TH |
1089 | } else if (force_pcs == 2) { |
1090 | dev_printk(KERN_INFO, &pdev->dev, | |
1091 | "force honoring PCS (0x%x)\n", new_pcs); | |
cca3974e JG |
1092 | pinfo[0].flags &= ~PIIX_FLAG_IGNORE_PCS; |
1093 | pinfo[1].flags &= ~PIIX_FLAG_IGNORE_PCS; | |
9dd9c164 | 1094 | } |
ea35d29e JG |
1095 | } |
1096 | ||
d33f58b8 | 1097 | static void __devinit piix_init_sata_map(struct pci_dev *pdev, |
d96715c1 TH |
1098 | struct ata_port_info *pinfo, |
1099 | const struct piix_map_db *map_db) | |
d33f58b8 | 1100 | { |
d96715c1 | 1101 | struct piix_host_priv *hpriv = pinfo[0].private_data; |
d33f58b8 TH |
1102 | const unsigned int *map; |
1103 | int i, invalid_map = 0; | |
1104 | u8 map_value; | |
1105 | ||
1106 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); | |
1107 | ||
1108 | map = map_db->map[map_value & map_db->mask]; | |
1109 | ||
1110 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); | |
1111 | for (i = 0; i < 4; i++) { | |
1112 | switch (map[i]) { | |
1113 | case RV: | |
1114 | invalid_map = 1; | |
1115 | printk(" XX"); | |
1116 | break; | |
1117 | ||
1118 | case NA: | |
1119 | printk(" --"); | |
1120 | break; | |
1121 | ||
1122 | case IDE: | |
1123 | WARN_ON((i & 1) || map[i + 1] != IDE); | |
669a5db4 | 1124 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
f814b75f | 1125 | pinfo[i / 2].private_data = hpriv; |
d33f58b8 TH |
1126 | i++; |
1127 | printk(" IDE IDE"); | |
1128 | break; | |
1129 | ||
1130 | default: | |
1131 | printk(" P%d", map[i]); | |
1132 | if (i & 1) | |
cca3974e | 1133 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
d33f58b8 TH |
1134 | break; |
1135 | } | |
1136 | } | |
1137 | printk(" ]\n"); | |
1138 | ||
1139 | if (invalid_map) | |
1140 | dev_printk(KERN_ERR, &pdev->dev, | |
1141 | "invalid MAP value %u\n", map_value); | |
1142 | ||
d96715c1 | 1143 | hpriv->map = map; |
08f12edc | 1144 | hpriv->map_db = map_db; |
d33f58b8 TH |
1145 | } |
1146 | ||
1da177e4 LT |
1147 | /** |
1148 | * piix_init_one - Register PIIX ATA PCI device with kernel services | |
1149 | * @pdev: PCI device to register | |
1150 | * @ent: Entry in piix_pci_tbl matching with @pdev | |
1151 | * | |
1152 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
1153 | * and then hand over control to libata, for it to do the rest. | |
1154 | * | |
1155 | * LOCKING: | |
1156 | * Inherited from PCI layer (may sleep). | |
1157 | * | |
1158 | * RETURNS: | |
1159 | * Zero on success, or -ERRNO value. | |
1160 | */ | |
1161 | ||
1162 | static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1163 | { | |
1164 | static int printed_version; | |
d33f58b8 TH |
1165 | struct ata_port_info port_info[2]; |
1166 | struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] }; | |
d96715c1 | 1167 | struct piix_host_priv *hpriv; |
cca3974e | 1168 | unsigned long port_flags; |
1da177e4 LT |
1169 | |
1170 | if (!printed_version++) | |
6248e647 JG |
1171 | dev_printk(KERN_DEBUG, &pdev->dev, |
1172 | "version " DRV_VERSION "\n"); | |
1da177e4 LT |
1173 | |
1174 | /* no hotplugging support (FIXME) */ | |
1175 | if (!in_module_init) | |
1176 | return -ENODEV; | |
1177 | ||
d96715c1 TH |
1178 | hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); |
1179 | if (!hpriv) | |
1180 | return -ENOMEM; | |
1181 | ||
d33f58b8 TH |
1182 | port_info[0] = piix_port_info[ent->driver_data]; |
1183 | port_info[1] = piix_port_info[ent->driver_data]; | |
d96715c1 TH |
1184 | port_info[0].private_data = hpriv; |
1185 | port_info[1].private_data = hpriv; | |
1da177e4 | 1186 | |
cca3974e | 1187 | port_flags = port_info[0].flags; |
ff0fc146 | 1188 | |
cca3974e | 1189 | if (port_flags & PIIX_FLAG_AHCI) { |
8a60a071 JG |
1190 | u8 tmp; |
1191 | pci_read_config_byte(pdev, PIIX_SCC, &tmp); | |
1192 | if (tmp == PIIX_AHCI_DEVICE) { | |
1193 | int rc = piix_disable_ahci(pdev); | |
1194 | if (rc) | |
1195 | return rc; | |
1196 | } | |
1da177e4 LT |
1197 | } |
1198 | ||
d33f58b8 | 1199 | /* Initialize SATA map */ |
cca3974e | 1200 | if (port_flags & ATA_FLAG_SATA) { |
d96715c1 TH |
1201 | piix_init_sata_map(pdev, port_info, |
1202 | piix_map_db_table[ent->driver_data]); | |
9dd9c164 TH |
1203 | piix_init_pcs(pdev, port_info, |
1204 | piix_map_db_table[ent->driver_data]); | |
ea35d29e | 1205 | } |
1da177e4 LT |
1206 | |
1207 | /* On ICH5, some BIOSen disable the interrupt using the | |
1208 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. | |
1209 | * On ICH6, this bit has the same effect, but only when | |
1210 | * MSI is disabled (and it is disabled, as we don't use | |
1211 | * message-signalled interrupts currently). | |
1212 | */ | |
cca3974e | 1213 | if (port_flags & PIIX_FLAG_CHECKINTR) |
a04ce0ff | 1214 | pci_intx(pdev, 1); |
1da177e4 | 1215 | |
c621b140 AC |
1216 | if (piix_check_450nx_errata(pdev)) { |
1217 | /* This writes into the master table but it does not | |
1218 | really matter for this errata as we will apply it to | |
1219 | all the PIIX devices on the board */ | |
d33f58b8 TH |
1220 | port_info[0].mwdma_mask = 0; |
1221 | port_info[0].udma_mask = 0; | |
1222 | port_info[1].mwdma_mask = 0; | |
1223 | port_info[1].udma_mask = 0; | |
c621b140 | 1224 | } |
d33f58b8 | 1225 | return ata_pci_init_one(pdev, ppinfo, 2); |
1da177e4 LT |
1226 | } |
1227 | ||
cca3974e | 1228 | static void piix_host_stop(struct ata_host *host) |
d96715c1 | 1229 | { |
cca3974e | 1230 | struct piix_host_priv *hpriv = host->private_data; |
24dd01bf | 1231 | |
cca3974e | 1232 | ata_host_stop(host); |
24dd01bf JG |
1233 | |
1234 | kfree(hpriv); | |
d96715c1 TH |
1235 | } |
1236 | ||
1da177e4 LT |
1237 | static int __init piix_init(void) |
1238 | { | |
1239 | int rc; | |
1240 | ||
b7887196 PR |
1241 | DPRINTK("pci_register_driver\n"); |
1242 | rc = pci_register_driver(&piix_pci_driver); | |
1da177e4 LT |
1243 | if (rc) |
1244 | return rc; | |
1245 | ||
1246 | in_module_init = 0; | |
1247 | ||
1248 | DPRINTK("done\n"); | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1da177e4 LT |
1252 | static void __exit piix_exit(void) |
1253 | { | |
1254 | pci_unregister_driver(&piix_pci_driver); | |
1255 | } | |
1256 | ||
1257 | module_init(piix_init); | |
1258 | module_exit(piix_exit); |