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pata_sis: Fix and clean up some timing setups
[mirror_ubuntu-artful-kernel.git] / drivers / ata / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
2c5ff671 43 * driver the list of errata that are relevant is below, going back to
d96212ed
AC		 44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
eb4a2c7f 96#define DRV_VERSION "2.11"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
d4358048 104 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 105 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
106 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
1da177e4 107
800b3996
TH		 108 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
109 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
b3362f88 110
1da177e4
LT		 111 /* combined mode. if set, PATA is channel 0.
112 * if clear, PATA is channel 1.
113 */
6a690df5
HR		 114 PIIX_PORT_ENABLED = (1 << 0),
115 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 116
117 PIIX_80C_PRI = (1 << 5) | (1 << 4),
118 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119
1d076e5b 120 /* controller IDs */
d2cdfc0d 121 piix_pata_33 = 0, /* PIIX4 at 33Mhz */
669a5db4
JG		 122 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
123 ich_pata_66 = 2, /* ICH up to 66 Mhz */
124 ich_pata_100 = 3, /* ICH up to UDMA 100 */
125 ich_pata_133 = 4, /* ICH up to UDMA 133 */
126 ich5_sata = 5,
5e56a37c
TH		 127 ich6_sata = 6,
128 ich6_sata_ahci = 7,
129 ich6m_sata_ahci = 8,
130 ich8_sata_ahci = 9,
d2cdfc0d 131 piix_pata_mwdma = 10, /* PIIX3 MWDMA only */
85cd7251 132
d33f58b8
TH		 133 /* constants for mapping table */
134 P0 = 0, /* port 0 */
135 P1 = 1, /* port 1 */
136 P2 = 2, /* port 2 */
137 P3 = 3, /* port 3 */
138 IDE = -1, /* IDE */
139 NA = -2, /* not avaliable */
140 RV = -3, /* reserved */
141
7b6dbd68 142 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 143};
144
d33f58b8
TH		 145struct piix_map_db {
146 const u32 mask;
73291a1c 147 const u16 port_enable;
d33f58b8
TH		 148 const int map[][4];
149};
150
d96715c1
TH		 151struct piix_host_priv {
152 const int *map;
153};
154
1da177e4
LT		 155static int piix_init_one (struct pci_dev *pdev,
156 const struct pci_device_id *ent);
ccc4672a 157static void piix_pata_error_handler(struct ata_port *ap);
669a5db4
JG		 158static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
159static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
160static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
eb4a2c7f 161static int ich_pata_cable_detect(struct ata_port *ap);
1da177e4
LT		 162
163static unsigned int in_module_init = 1;
164
3b7d697d 165static const struct pci_device_id piix_pci_tbl[] = {
d2cdfc0d
AC		 166 /* Intel PIIX3 for the 430HX etc */
167 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
669a5db4
JG		 168 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
169 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
170 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
669a5db4
JG		 171 /* Intel PIIX4 */
172 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
173 /* Intel PIIX4 */
174 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
175 /* Intel PIIX */
176 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
177 /* Intel ICH (i810, i815, i840) UDMA 66*/
178 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
179 /* Intel ICH0 : UDMA 33*/
180 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
181 /* Intel ICH2M */
182 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
183 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
184 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
185 /* Intel ICH3M */
186 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
187 /* Intel ICH3 (E7500/1) UDMA 100 */
188 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
190 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH5 */
193 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
194 /* C-ICH (i810E2) */
195 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
85cd7251 196 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
669a5db4
JG		 197 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 /* ICH6 (and 6) (i915) UDMA 100 */
199 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* ICH7/7-R (i945, i975) UDMA 100*/
201 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
202 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
1da177e4
LT		 203
204 /* NOTE: The following PCI ids must be kept in sync with the
205 * list in drivers/pci/quirks.c.
206 */
207
1d076e5b 208 /* 82801EB (ICH5) */
1da177e4 209 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 210 /* 82801EB (ICH5) */
1da177e4 211 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 212 /* 6300ESB (ICH5 variant with broken PCS present bits) */
5e56a37c 213 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 214 /* 6300ESB pretending RAID */
5e56a37c 215 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 216 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 217 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 218 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 219 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 220 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
221 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
222 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 223 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 224 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
c6446a4c 225 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
f98b6573 226 /* Enterprise Southbridge 2 (631xESB/632xESB) */
1c24a412 227 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
f98b6573 228 /* SATA Controller 1 IDE (ICH8) */
08f12edc 229 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 230 /* SATA Controller 2 IDE (ICH8) */
08f12edc 231 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573 232 /* Mobile SATA Controller IDE (ICH8M) */
08f12edc 233 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
f98b6573
JG		 234 /* SATA Controller IDE (ICH9) */
235 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
236 /* SATA Controller IDE (ICH9) */
237 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
238 /* SATA Controller IDE (ICH9) */
239 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
240 /* SATA Controller IDE (ICH9M) */
241 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
242 /* SATA Controller IDE (ICH9M) */
243 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
244 /* SATA Controller IDE (ICH9M) */
245 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
1da177e4
LT		 246
247 { } /* terminate list */
248};
249
250static struct pci_driver piix_pci_driver = {
251 .name = DRV_NAME,
252 .id_table = piix_pci_tbl,
253 .probe = piix_init_one,
254 .remove = ata_pci_remove_one,
438ac6d5 255#ifdef CONFIG_PM
9b847548
JA		 256 .suspend = ata_pci_device_suspend,
257 .resume = ata_pci_device_resume,
438ac6d5 258#endif
1da177e4
LT		 259};
260
193515d5 261static struct scsi_host_template piix_sht = {
1da177e4
LT		 262 .module = THIS_MODULE,
263 .name = DRV_NAME,
264 .ioctl = ata_scsi_ioctl,
265 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 266 .can_queue = ATA_DEF_QUEUE,
267 .this_id = ATA_SHT_THIS_ID,
268 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 269 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
270 .emulated = ATA_SHT_EMULATED,
271 .use_clustering = ATA_SHT_USE_CLUSTERING,
272 .proc_name = DRV_NAME,
273 .dma_boundary = ATA_DMA_BOUNDARY,
274 .slave_configure = ata_scsi_slave_config,
ccf68c34 275 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 276 .bios_param = ata_std_bios_param,
1da177e4
LT		 277};
278
057ace5e 279static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 280 .port_disable = ata_port_disable,
281 .set_piomode = piix_set_piomode,
282 .set_dmamode = piix_set_dmamode,
89bad589 283 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 284
285 .tf_load = ata_tf_load,
286 .tf_read = ata_tf_read,
287 .check_status = ata_check_status,
288 .exec_command = ata_exec_command,
289 .dev_select = ata_std_dev_select,
290
1da177e4
LT		 291 .bmdma_setup = ata_bmdma_setup,
292 .bmdma_start = ata_bmdma_start,
293 .bmdma_stop = ata_bmdma_stop,
294 .bmdma_status = ata_bmdma_status,
295 .qc_prep = ata_qc_prep,
296 .qc_issue = ata_qc_issue_prot,
0d5ff566 297 .data_xfer = ata_data_xfer,
1da177e4 298
3f037db0
TH		 299 .freeze = ata_bmdma_freeze,
300 .thaw = ata_bmdma_thaw,
ccc4672a 301 .error_handler = piix_pata_error_handler,
3f037db0 302 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 303 .cable_detect = ata_cable_40wire,
1da177e4
LT		 304
305 .irq_handler = ata_interrupt,
306 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 307 .irq_on = ata_irq_on,
308 .irq_ack = ata_irq_ack,
1da177e4
LT		 309
310 .port_start = ata_port_start,
1da177e4
LT		 311};
312
669a5db4
JG		 313static const struct ata_port_operations ich_pata_ops = {
314 .port_disable = ata_port_disable,
315 .set_piomode = piix_set_piomode,
316 .set_dmamode = ich_set_dmamode,
317 .mode_filter = ata_pci_default_filter,
318
319 .tf_load = ata_tf_load,
320 .tf_read = ata_tf_read,
321 .check_status = ata_check_status,
322 .exec_command = ata_exec_command,
323 .dev_select = ata_std_dev_select,
324
325 .bmdma_setup = ata_bmdma_setup,
326 .bmdma_start = ata_bmdma_start,
327 .bmdma_stop = ata_bmdma_stop,
328 .bmdma_status = ata_bmdma_status,
329 .qc_prep = ata_qc_prep,
330 .qc_issue = ata_qc_issue_prot,
0d5ff566 331 .data_xfer = ata_data_xfer,
669a5db4
JG		 332
333 .freeze = ata_bmdma_freeze,
334 .thaw = ata_bmdma_thaw,
eb4a2c7f 335 .error_handler = piix_pata_error_handler,
669a5db4 336 .post_internal_cmd = ata_bmdma_post_internal_cmd,
eb4a2c7f 337 .cable_detect = ich_pata_cable_detect,
669a5db4
JG		 338
339 .irq_handler = ata_interrupt,
340 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 341 .irq_on = ata_irq_on,
342 .irq_ack = ata_irq_ack,
669a5db4
JG		 343
344 .port_start = ata_port_start,
669a5db4
JG		 345};
346
057ace5e 347static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 348 .port_disable = ata_port_disable,
349
350 .tf_load = ata_tf_load,
351 .tf_read = ata_tf_read,
352 .check_status = ata_check_status,
353 .exec_command = ata_exec_command,
354 .dev_select = ata_std_dev_select,
355
1da177e4
LT		 356 .bmdma_setup = ata_bmdma_setup,
357 .bmdma_start = ata_bmdma_start,
358 .bmdma_stop = ata_bmdma_stop,
359 .bmdma_status = ata_bmdma_status,
360 .qc_prep = ata_qc_prep,
361 .qc_issue = ata_qc_issue_prot,
0d5ff566 362 .data_xfer = ata_data_xfer,
1da177e4 363
3f037db0
TH		 364 .freeze = ata_bmdma_freeze,
365 .thaw = ata_bmdma_thaw,
2f91d81d 366 .error_handler = ata_bmdma_error_handler,
3f037db0 367 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 368
369 .irq_handler = ata_interrupt,
370 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 371 .irq_on = ata_irq_on,
372 .irq_ack = ata_irq_ack,
1da177e4
LT		 373
374 .port_start = ata_port_start,
1da177e4
LT		 375};
376
d96715c1 377static const struct piix_map_db ich5_map_db = {
d33f58b8 378 .mask = 0x7,
ea35d29e 379 .port_enable = 0x3,
d33f58b8
TH		 380 .map = {
381 /* PM PS SM SS MAP */
382 { P0, NA, P1, NA }, /* 000b */
383 { P1, NA, P0, NA }, /* 001b */
384 { RV, RV, RV, RV },
385 { RV, RV, RV, RV },
386 { P0, P1, IDE, IDE }, /* 100b */
387 { P1, P0, IDE, IDE }, /* 101b */
388 { IDE, IDE, P0, P1 }, /* 110b */
389 { IDE, IDE, P1, P0 }, /* 111b */
390 },
391};
392
d96715c1 393static const struct piix_map_db ich6_map_db = {
d33f58b8 394 .mask = 0x3,
ea35d29e 395 .port_enable = 0xf,
d33f58b8
TH		 396 .map = {
397 /* PM PS SM SS MAP */
79ea24e7 398 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 399 { IDE, IDE, P1, P3 }, /* 01b */
400 { P0, P2, IDE, IDE }, /* 10b */
401 { RV, RV, RV, RV },
402 },
403};
404
d96715c1 405static const struct piix_map_db ich6m_map_db = {
d33f58b8 406 .mask = 0x3,
ea35d29e 407 .port_enable = 0x5,
67083741
TH		 408
409 /* Map 01b isn't specified in the doc but some notebooks use
c6446a4c
TH		 410 * it anyway. MAP 01b have been spotted on both ICH6M and
411 * ICH7M.
67083741
TH		 412 */
413 .map = {
414 /* PM PS SM SS MAP */
415 { P0, P2, RV, RV }, /* 00b */
416 { IDE, IDE, P1, P3 }, /* 01b */
417 { P0, P2, IDE, IDE }, /* 10b */
418 { RV, RV, RV, RV },
419 },
420};
421
08f12edc
JG		 422static const struct piix_map_db ich8_map_db = {
423 .mask = 0x3,
424 .port_enable = 0x3,
08f12edc
JG		 425 .map = {
426 /* PM PS SM SS MAP */
158f30c8 427 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
08f12edc 428 { RV, RV, RV, RV },
158f30c8 429 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
08f12edc
JG		 430 { RV, RV, RV, RV },
431 },
432};
433
d96715c1
TH		 434static const struct piix_map_db *piix_map_db_table[] = {
435 [ich5_sata] = &ich5_map_db,
d96715c1
TH		 436 [ich6_sata] = &ich6_map_db,
437 [ich6_sata_ahci] = &ich6_map_db,
438 [ich6m_sata_ahci] = &ich6m_map_db,
08f12edc 439 [ich8_sata_ahci] = &ich8_map_db,
d96715c1
TH		 440};
441
1da177e4 442static struct ata_port_info piix_port_info[] = {
d2cdfc0d 443 /* piix_pata_33: 0: PIIX4 at 33MHz */
1d076e5b
TH		 444 {
445 .sht = &piix_sht,
b3362f88 446 .flags = PIIX_PATA_FLAGS,
1d076e5b 447 .pio_mask = 0x1f, /* pio0-4 */
669a5db4 448 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1d076e5b
TH		 449 .udma_mask = ATA_UDMA_MASK_40C,
450 .port_ops = &piix_pata_ops,
451 },
452
669a5db4
JG		 453 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
454 {
455 .sht = &piix_sht,
b3362f88 456 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 457 .pio_mask = 0x1f, /* pio 0-4 */
458 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
459 .udma_mask = ATA_UDMA2, /* UDMA33 */
460 .port_ops = &ich_pata_ops,
461 },
462 /* ich_pata_66: 2 ICH controllers up to 66MHz */
1da177e4
LT		 463 {
464 .sht = &piix_sht,
b3362f88 465 .flags = PIIX_PATA_FLAGS,
669a5db4
JG		 466 .pio_mask = 0x1f, /* pio 0-4 */
467 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
468 .udma_mask = ATA_UDMA4,
469 .port_ops = &ich_pata_ops,
470 },
85cd7251 471
669a5db4
JG		 472 /* ich_pata_100: 3 */
473 {
474 .sht = &piix_sht,
b3362f88 475 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1da177e4 476 .pio_mask = 0x1f, /* pio0-4 */
1da177e4 477 .mwdma_mask = 0x06, /* mwdma1-2 */
669a5db4
JG		 478 .udma_mask = ATA_UDMA5, /* udma0-5 */
479 .port_ops = &ich_pata_ops,
1da177e4
LT		 480 },
481
669a5db4
JG		 482 /* ich_pata_133: 4 ICH with full UDMA6 */
483 {
484 .sht = &piix_sht,
b3362f88 485 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
669a5db4
JG		 486 .pio_mask = 0x1f, /* pio 0-4 */
487 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
488 .udma_mask = ATA_UDMA6, /* UDMA133 */
489 .port_ops = &ich_pata_ops,
490 },
491
492 /* ich5_sata: 5 */
1da177e4
LT		 493 {
494 .sht = &piix_sht,
228c1590 495 .flags = PIIX_SATA_FLAGS,
1da177e4
LT		 496 .pio_mask = 0x1f, /* pio0-4 */
497 .mwdma_mask = 0x07, /* mwdma0-2 */
498 .udma_mask = 0x7f, /* udma0-6 */
499 .port_ops = &piix_sata_ops,
500 },
501
5e56a37c 502 /* ich6_sata: 6 */
1da177e4
LT		 503 {
504 .sht = &piix_sht,
b3362f88 505 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR,
1da177e4
LT		 506 .pio_mask = 0x1f, /* pio0-4 */
507 .mwdma_mask = 0x07, /* mwdma0-2 */
508 .udma_mask = 0x7f, /* udma0-6 */
509 .port_ops = &piix_sata_ops,
510 },
511
5e56a37c 512 /* ich6_sata_ahci: 7 */
c368ca4e
JG		 513 {
514 .sht = &piix_sht,
b3362f88 515 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 516 PIIX_FLAG_AHCI,
c368ca4e
JG		 517 .pio_mask = 0x1f, /* pio0-4 */
518 .mwdma_mask = 0x07, /* mwdma0-2 */
519 .udma_mask = 0x7f, /* udma0-6 */
520 .port_ops = &piix_sata_ops,
521 },
1d076e5b 522
5e56a37c 523 /* ich6m_sata_ahci: 8 */
1d076e5b
TH		 524 {
525 .sht = &piix_sht,
b3362f88 526 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
d33f58b8 527 PIIX_FLAG_AHCI,
1d076e5b
TH		 528 .pio_mask = 0x1f, /* pio0-4 */
529 .mwdma_mask = 0x07, /* mwdma0-2 */
530 .udma_mask = 0x7f, /* udma0-6 */
531 .port_ops = &piix_sata_ops,
532 },
08f12edc 533
5e56a37c 534 /* ich8_sata_ahci: 9 */
08f12edc
JG		 535 {
536 .sht = &piix_sht,
b3362f88 537 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SCR |
08f12edc
JG		 538 PIIX_FLAG_AHCI,
539 .pio_mask = 0x1f, /* pio0-4 */
540 .mwdma_mask = 0x07, /* mwdma0-2 */
541 .udma_mask = 0x7f, /* udma0-6 */
542 .port_ops = &piix_sata_ops,
543 },
669a5db4 544
d2cdfc0d
AC		 545 /* piix_pata_mwdma: 10: PIIX3 MWDMA only */
546 {
547 .sht = &piix_sht,
548 .flags = PIIX_PATA_FLAGS,
549 .pio_mask = 0x1f, /* pio0-4 */
550 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
551 .port_ops = &piix_pata_ops,
552 },
1da177e4
LT		 553};
554
555static struct pci_bits piix_enable_bits[] = {
556 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
557 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
558};
559
560MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
561MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
562MODULE_LICENSE("GPL");
563MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
564MODULE_VERSION(DRV_VERSION);
565
fc085150
AC		 566struct ich_laptop {
567 u16 device;
568 u16 subvendor;
569 u16 subdevice;
570};
571
572/*
573 * List of laptops that use short cables rather than 80 wire
574 */
575
576static const struct ich_laptop ich_laptop[] = {
577 /* devid, subvendor, subdev */
578 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
babfb682 579 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
12340106 580 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
fc085150
AC		 581 /* end marker */
582 { 0, }
583};
584
1da177e4 585/**
eb4a2c7f 586 * ich_pata_cable_detect - Probe host controller cable detect info
1da177e4
LT		 587 * @ap: Port for which cable detect info is desired
588 *
589 * Read 80c cable indicator from ATA PCI device's PCI config
590 * register. This register is normally set by firmware (BIOS).
591 *
592 * LOCKING:
593 * None (inherited from caller).
594 */
669a5db4 595
eb4a2c7f 596static int ich_pata_cable_detect(struct ata_port *ap)
1da177e4 597{
cca3974e 598 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
fc085150 599 const struct ich_laptop *lap = &ich_laptop[0];
1da177e4
LT		 600 u8 tmp, mask;
601
fc085150
AC		 602 /* Check for specials - Acer Aspire 5602WLMi */
603 while (lap->device) {
604 if (lap->device == pdev->device &&
605 lap->subvendor == pdev->subsystem_vendor &&
606 lap->subdevice == pdev->subsystem_device) {
eb4a2c7f 607 return ATA_CBL_PATA40_SHORT;
fc085150
AC		 608 }
609 lap++;
610 }
611
1da177e4 612 /* check BIOS cable detect results */
2a88d1ac 613 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
1da177e4
LT		 614 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
615 if ((tmp & mask) == 0)
eb4a2c7f
AC		 616 return ATA_CBL_PATA40;
617 return ATA_CBL_PATA80;
1da177e4
LT		 618}
619
620/**
ccc4672a 621 * piix_pata_prereset - prereset for PATA host controller
573db6b8 622 * @ap: Target port
d4b2bab4 623 * @deadline: deadline jiffies for the operation
1da177e4 624 *
573db6b8
TH		 625 * LOCKING:
626 * None (inherited from caller).
627 */
d4b2bab4 628static int piix_pata_prereset(struct ata_port *ap, unsigned long deadline)
1da177e4 629{
cca3974e 630 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4 631
c961922b
AC		 632 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
633 return -ENOENT;
d4b2bab4 634 return ata_std_prereset(ap, deadline);
ccc4672a
TH		 635}
636
637static void piix_pata_error_handler(struct ata_port *ap)
638{
639 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
640 ata_std_postreset);
1da177e4
LT		 641}
642
1da177e4
LT		 643/**
644 * piix_set_piomode - Initialize host controller PATA PIO timings
645 * @ap: Port whose timings we are configuring
646 * @adev: um
1da177e4
LT		 647 *
648 * Set PIO mode for device, in host controller PCI config space.
649 *
650 * LOCKING:
651 * None (inherited from caller).
652 */
653
654static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
655{
656 unsigned int pio = adev->pio_mode - XFER_PIO_0;
cca3974e 657 struct pci_dev *dev = to_pci_dev(ap->host->dev);
1da177e4 658 unsigned int is_slave = (adev->devno != 0);
2a88d1ac 659 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
1da177e4
LT		 660 unsigned int slave_port = 0x44;
661 u16 master_data;
662 u8 slave_data;
669a5db4
JG		 663 u8 udma_enable;
664 int control = 0;
85cd7251 665
669a5db4
JG		 666 /*
667 * See Intel Document 298600-004 for the timing programing rules
668 * for ICH controllers.
669 */
1da177e4
LT		 670
671 static const /* ISP RTC */
672 u8 timings[][2] = { { 0, 0 },
673 { 0, 0 },
674 { 1, 0 },
675 { 2, 1 },
676 { 2, 3 }, };
677
669a5db4
JG		 678 if (pio >= 2)
679 control |= 1; /* TIME1 enable */
680 if (ata_pio_need_iordy(adev))
681 control |= 2; /* IE enable */
682
85cd7251 683 /* Intel specifies that the PPE functionality is for disk only */
669a5db4
JG		 684 if (adev->class == ATA_DEV_ATA)
685 control |= 4; /* PPE enable */
686
1da177e4
LT		 687 pci_read_config_word(dev, master_port, &master_data);
688 if (is_slave) {
669a5db4 689 /* Enable SITRE (seperate slave timing register) */
1da177e4 690 master_data |= 0x4000;
669a5db4
JG		 691 /* enable PPE1, IE1 and TIME1 as needed */
692 master_data |= (control << 4);
1da177e4 693 pci_read_config_byte(dev, slave_port, &slave_data);
2a88d1ac 694 slave_data &= (ap->port_no ? 0x0f : 0xf0);
669a5db4
JG		 695 /* Load the timing nibble for this slave */
696 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
1da177e4 697 } else {
669a5db4 698 /* Master keeps the bits in a different format */
1da177e4 699 master_data &= 0xccf8;
669a5db4
JG		 700 /* Enable PPE, IE and TIME as appropriate */
701 master_data |= control;
1da177e4
LT		 702 master_data |=
703 (timings[pio][0] << 12) |
704 (timings[pio][1] << 8);
705 }
706 pci_write_config_word(dev, master_port, master_data);
707 if (is_slave)
708 pci_write_config_byte(dev, slave_port, slave_data);
669a5db4
JG		 709
710 /* Ensure the UDMA bit is off - it will be turned back on if
711 UDMA is selected */
85cd7251 712
669a5db4
JG		 713 if (ap->udma_mask) {
714 pci_read_config_byte(dev, 0x48, &udma_enable);
715 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
716 pci_write_config_byte(dev, 0x48, udma_enable);
717 }
1da177e4
LT		 718}
719
720/**
669a5db4 721 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
1da177e4 722 * @ap: Port whose timings we are configuring
669a5db4 723 * @adev: Drive in question
1da177e4 724 * @udma: udma mode, 0 - 6
c32a8fd7 725 * @isich: set if the chip is an ICH device
1da177e4
LT		 726 *
727 * Set UDMA mode for device, in host controller PCI config space.
728 *
729 * LOCKING:
730 * None (inherited from caller).
731 */
732
669a5db4 733static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
1da177e4 734{
cca3974e 735 struct pci_dev *dev = to_pci_dev(ap->host->dev);
669a5db4
JG		 736 u8 master_port = ap->port_no ? 0x42 : 0x40;
737 u16 master_data;
738 u8 speed = adev->dma_mode;
739 int devid = adev->devno + 2 * ap->port_no;
dedf61db 740 u8 udma_enable = 0;
85cd7251 741
669a5db4
JG		 742 static const /* ISP RTC */
743 u8 timings[][2] = { { 0, 0 },
744 { 0, 0 },
745 { 1, 0 },
746 { 2, 1 },
747 { 2, 3 }, };
748
749 pci_read_config_word(dev, master_port, &master_data);
d2cdfc0d
AC		 750 if (ap->udma_mask)
751 pci_read_config_byte(dev, 0x48, &udma_enable);
1da177e4
LT		 752
753 if (speed >= XFER_UDMA_0) {
669a5db4
JG		 754 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
755 u16 udma_timing;
756 u16 ideconf;
757 int u_clock, u_speed;
85cd7251 758
669a5db4
JG		 759 /*
760 * UDMA is handled by a combination of clock switching and
85cd7251
JG		 761 * selection of dividers
762 *
669a5db4 763 * Handy rule: Odd modes are UDMATIMx 01, even are 02
85cd7251 764 * except UDMA0 which is 00
669a5db4
JG		 765 */
766 u_speed = min(2 - (udma & 1), udma);
767 if (udma == 5)
768 u_clock = 0x1000; /* 100Mhz */
769 else if (udma > 2)
770 u_clock = 1; /* 66Mhz */
771 else
772 u_clock = 0; /* 33Mhz */
85cd7251 773
669a5db4 774 udma_enable |= (1 << devid);
85cd7251 775
669a5db4
JG		 776 /* Load the CT/RP selection */
777 pci_read_config_word(dev, 0x4A, &udma_timing);
778 udma_timing &= ~(3 << (4 * devid));
779 udma_timing |= u_speed << (4 * devid);
780 pci_write_config_word(dev, 0x4A, udma_timing);
781
85cd7251 782 if (isich) {
669a5db4
JG		 783 /* Select a 33/66/100Mhz clock */
784 pci_read_config_word(dev, 0x54, &ideconf);
785 ideconf &= ~(0x1001 << devid);
786 ideconf |= u_clock << devid;
787 /* For ICH or later we should set bit 10 for better
788 performance (WR_PingPong_En) */
789 pci_write_config_word(dev, 0x54, ideconf);
1da177e4 790 }
1da177e4 791 } else {
669a5db4
JG		 792 /*
793 * MWDMA is driven by the PIO timings. We must also enable
794 * IORDY unconditionally along with TIME1. PPE has already
795 * been set when the PIO timing was set.
796 */
797 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
798 unsigned int control;
799 u8 slave_data;
800 const unsigned int needed_pio[3] = {
801 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
802 };
803 int pio = needed_pio[mwdma] - XFER_PIO_0;
85cd7251 804
669a5db4 805 control = 3; /* IORDY|TIME1 */
85cd7251 806
669a5db4
JG		 807 /* If the drive MWDMA is faster than it can do PIO then
808 we must force PIO into PIO0 */
85cd7251 809
669a5db4
JG		 810 if (adev->pio_mode < needed_pio[mwdma])
811 /* Enable DMA timing only */
812 control |= 8; /* PIO cycles in PIO0 */
813
814 if (adev->devno) { /* Slave */
815 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
816 master_data |= control << 4;
817 pci_read_config_byte(dev, 0x44, &slave_data);
818 slave_data &= (0x0F + 0xE1 * ap->port_no);
819 /* Load the matching timing */
820 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
821 pci_write_config_byte(dev, 0x44, slave_data);
822 } else { /* Master */
85cd7251 823 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
669a5db4
JG		 824 and master timing bits */
825 master_data |= control;
826 master_data |=
827 (timings[pio][0] << 12) |
828 (timings[pio][1] << 8);
829 }
830 udma_enable &= ~(1 << devid);
831 pci_write_config_word(dev, master_port, master_data);
1da177e4 832 }
669a5db4
JG		 833 /* Don't scribble on 0x48 if the controller does not support UDMA */
834 if (ap->udma_mask)
835 pci_write_config_byte(dev, 0x48, udma_enable);
836}
837
838/**
839 * piix_set_dmamode - Initialize host controller PATA DMA timings
840 * @ap: Port whose timings we are configuring
841 * @adev: um
842 *
843 * Set MW/UDMA mode for device, in host controller PCI config space.
844 *
845 * LOCKING:
846 * None (inherited from caller).
847 */
848
849static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
850{
851 do_pata_set_dmamode(ap, adev, 0);
852}
853
854/**
855 * ich_set_dmamode - Initialize host controller PATA DMA timings
856 * @ap: Port whose timings we are configuring
857 * @adev: um
858 *
859 * Set MW/UDMA mode for device, in host controller PCI config space.
860 *
861 * LOCKING:
862 * None (inherited from caller).
863 */
864
865static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
866{
867 do_pata_set_dmamode(ap, adev, 1);
1da177e4
LT		 868}
869
1da177e4
LT		 870#define AHCI_PCI_BAR 5
871#define AHCI_GLOBAL_CTL 0x04
872#define AHCI_ENABLE (1 << 31)
873static int piix_disable_ahci(struct pci_dev *pdev)
874{
ea6ba10b 875 void __iomem *mmio;
1da177e4
LT		 876 u32 tmp;
877 int rc = 0;
878
879 /* BUG: pci_enable_device has not yet been called. This
880 * works because this device is usually set up by BIOS.
881 */
882
374b1873
JG		 883 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
884 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 885 return 0;
7b6dbd68 886
374b1873 887 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 888 if (!mmio)
889 return -ENOMEM;
7b6dbd68 890
1da177e4
LT		 891 tmp = readl(mmio + AHCI_GLOBAL_CTL);
892 if (tmp & AHCI_ENABLE) {
893 tmp &= ~AHCI_ENABLE;
894 writel(tmp, mmio + AHCI_GLOBAL_CTL);
895
896 tmp = readl(mmio + AHCI_GLOBAL_CTL);
897 if (tmp & AHCI_ENABLE)
898 rc = -EIO;
899 }
7b6dbd68 900
374b1873 901 pci_iounmap(pdev, mmio);
1da177e4
LT		 902 return rc;
903}
904
c621b140
AC		 905/**
906 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 907 * @ata_dev: the PCI device to check
2e9edbf8 908 *
c621b140
AC		 909 * Check for the present of 450NX errata #19 and errata #25. If
910 * they are found return an error code so we can turn off DMA
911 */
912
913static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
914{
915 struct pci_dev *pdev = NULL;
916 u16 cfg;
917 u8 rev;
918 int no_piix_dma = 0;
2e9edbf8 919
c621b140
AC		 920 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
921 {
922 /* Look for 450NX PXB. Check for problem configurations
923 A PCI quirk checks bit 6 already */
924 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
925 pci_read_config_word(pdev, 0x41, &cfg);
926 /* Only on the original revision: IDE DMA can hang */
31a34fe7 927 if (rev == 0x00)
c621b140
AC		 928 no_piix_dma = 1;
929 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
31a34fe7 930 else if (cfg & (1<<14) && rev < 5)
c621b140
AC		 931 no_piix_dma = 2;
932 }
31a34fe7 933 if (no_piix_dma)
c621b140 934 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 935 if (no_piix_dma == 2)
c621b140
AC		 936 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
937 return no_piix_dma;
2e9edbf8 938}
c621b140 939
ea35d29e 940static void __devinit piix_init_pcs(struct pci_dev *pdev,
9dd9c164 941 struct ata_port_info *pinfo,
ea35d29e
JG		 942 const struct piix_map_db *map_db)
943{
944 u16 pcs, new_pcs;
945
946 pci_read_config_word(pdev, ICH5_PCS, &pcs);
947
948 new_pcs = pcs | map_db->port_enable;
949
950 if (new_pcs != pcs) {
951 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
952 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
953 msleep(150);
954 }
955}
956
d33f58b8 957static void __devinit piix_init_sata_map(struct pci_dev *pdev,
d96715c1
TH		 958 struct ata_port_info *pinfo,
959 const struct piix_map_db *map_db)
d33f58b8 960{
d96715c1 961 struct piix_host_priv *hpriv = pinfo[0].private_data;
d33f58b8
TH		 962 const unsigned int *map;
963 int i, invalid_map = 0;
964 u8 map_value;
965
966 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
967
968 map = map_db->map[map_value & map_db->mask];
969
970 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
971 for (i = 0; i < 4; i++) {
972 switch (map[i]) {
973 case RV:
974 invalid_map = 1;
975 printk(" XX");
976 break;
977
978 case NA:
979 printk(" --");
980 break;
981
982 case IDE:
983 WARN_ON((i & 1) || map[i + 1] != IDE);
669a5db4 984 pinfo[i / 2] = piix_port_info[ich_pata_100];
f814b75f 985 pinfo[i / 2].private_data = hpriv;
d33f58b8
TH		 986 i++;
987 printk(" IDE IDE");
988 break;
989
990 default:
991 printk(" P%d", map[i]);
992 if (i & 1)
cca3974e 993 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
d33f58b8
TH		 994 break;
995 }
996 }
997 printk(" ]\n");
998
999 if (invalid_map)
1000 dev_printk(KERN_ERR, &pdev->dev,
1001 "invalid MAP value %u\n", map_value);
1002
d96715c1 1003 hpriv->map = map;
d33f58b8
TH		 1004}
1005
1da177e4
LT		 1006/**
1007 * piix_init_one - Register PIIX ATA PCI device with kernel services
1008 * @pdev: PCI device to register
1009 * @ent: Entry in piix_pci_tbl matching with @pdev
1010 *
1011 * Called from kernel PCI layer. We probe for combined mode (sigh),
1012 * and then hand over control to libata, for it to do the rest.
1013 *
1014 * LOCKING:
1015 * Inherited from PCI layer (may sleep).
1016 *
1017 * RETURNS:
1018 * Zero on success, or -ERRNO value.
1019 */
1020
1021static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1022{
1023 static int printed_version;
24dc5f33 1024 struct device *dev = &pdev->dev;
d33f58b8 1025 struct ata_port_info port_info[2];
1626aeb8 1026 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
d96715c1 1027 struct piix_host_priv *hpriv;
cca3974e 1028 unsigned long port_flags;
1da177e4
LT		 1029
1030 if (!printed_version++)
6248e647
JG		 1031 dev_printk(KERN_DEBUG, &pdev->dev,
1032 "version " DRV_VERSION "\n");
1da177e4
LT		 1033
1034 /* no hotplugging support (FIXME) */
1035 if (!in_module_init)
1036 return -ENODEV;
1037
24dc5f33 1038 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
d96715c1
TH		 1039 if (!hpriv)
1040 return -ENOMEM;
1041
d33f58b8
TH		 1042 port_info[0] = piix_port_info[ent->driver_data];
1043 port_info[1] = piix_port_info[ent->driver_data];
d96715c1
TH		 1044 port_info[0].private_data = hpriv;
1045 port_info[1].private_data = hpriv;
1da177e4 1046
cca3974e 1047 port_flags = port_info[0].flags;
ff0fc146 1048
cca3974e 1049 if (port_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 1050 u8 tmp;
1051 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1052 if (tmp == PIIX_AHCI_DEVICE) {
1053 int rc = piix_disable_ahci(pdev);
1054 if (rc)
1055 return rc;
1056 }
1da177e4
LT		 1057 }
1058
d33f58b8 1059 /* Initialize SATA map */
cca3974e 1060 if (port_flags & ATA_FLAG_SATA) {
d96715c1
TH		 1061 piix_init_sata_map(pdev, port_info,
1062 piix_map_db_table[ent->driver_data]);
9dd9c164
TH		 1063 piix_init_pcs(pdev, port_info,
1064 piix_map_db_table[ent->driver_data]);
ea35d29e 1065 }
1da177e4
LT		 1066
1067 /* On ICH5, some BIOSen disable the interrupt using the
1068 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1069 * On ICH6, this bit has the same effect, but only when
1070 * MSI is disabled (and it is disabled, as we don't use
1071 * message-signalled interrupts currently).
1072 */
cca3974e 1073 if (port_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 1074 pci_intx(pdev, 1);
1da177e4 1075
c621b140
AC		 1076 if (piix_check_450nx_errata(pdev)) {
1077 /* This writes into the master table but it does not
1078 really matter for this errata as we will apply it to
1079 all the PIIX devices on the board */
d33f58b8
TH		 1080 port_info[0].mwdma_mask = 0;
1081 port_info[0].udma_mask = 0;
1082 port_info[1].mwdma_mask = 0;
1083 port_info[1].udma_mask = 0;
c621b140 1084 }
1626aeb8 1085 return ata_pci_init_one(pdev, ppi);
1da177e4
LT		 1086}
1087
1da177e4
LT		 1088static int __init piix_init(void)
1089{
1090 int rc;
1091
b7887196
PR		 1092 DPRINTK("pci_register_driver\n");
1093 rc = pci_register_driver(&piix_pci_driver);
1da177e4
LT		 1094 if (rc)
1095 return rc;
1096
1097 in_module_init = 0;
1098
1099 DPRINTK("done\n");
1100 return 0;
1101}
1102
1da177e4
LT		 1103static void __exit piix_exit(void)
1104{
1105 pci_unregister_driver(&piix_pci_driver);
1106}
1107
1108module_init(piix_init);
1109module_exit(piix_exit);
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