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libata: Fix display of sata speed
[mirror_ubuntu-artful-kernel.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e
AV		 37#include <linux/module.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
47#include "ahci.h"
65fe1f0f 48#include "libata.h"
365cfa1e
AV		 49
50static int ahci_skip_host_reset;
51int ahci_ignore_sss;
52EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
6b7ae954
TH		 60static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
365cfa1e
AV		 62static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
73static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74static int ahci_port_start(struct ata_port *ap);
75static void ahci_port_stop(struct ata_port *ap);
76static void ahci_qc_prep(struct ata_queued_cmd *qc);
77static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78static void ahci_freeze(struct ata_port *ap);
79static void ahci_thaw(struct ata_port *ap);
65fe1f0f 80static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 81static void ahci_enable_fbs(struct ata_port *ap);
82static void ahci_disable_fbs(struct ata_port *ap);
83static void ahci_pmp_attach(struct ata_port *ap);
84static void ahci_pmp_detach(struct ata_port *ap);
85static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
345347c5
YHC		 87static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
365cfa1e
AV		 89static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 92static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 93static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 94#ifdef CONFIG_PM
95static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96#endif
97static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100static void ahci_init_sw_activity(struct ata_link *link);
101
102static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
c0623166
HZ		 110static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
6e5fe5b1
HR		 115static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
365cfa1e
AV		 117
118static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
119static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
120static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
121static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 122static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
123 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 124static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 125
fad16e7a 126struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 127 &dev_attr_link_power_management_policy,
128 &dev_attr_em_message_type,
129 &dev_attr_em_message,
130 &dev_attr_ahci_host_caps,
131 &dev_attr_ahci_host_cap2,
132 &dev_attr_ahci_host_version,
133 &dev_attr_ahci_port_cmd,
c0623166 134 &dev_attr_em_buffer,
6e5fe5b1 135 &dev_attr_em_message_supported,
365cfa1e
AV		 136 NULL
137};
fad16e7a 138EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 139
fad16e7a 140struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 141 &dev_attr_sw_activity,
142 &dev_attr_unload_heads,
143 NULL
144};
fad16e7a 145EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 146
147struct ata_port_operations ahci_ops = {
148 .inherits = &sata_pmp_port_ops,
149
150 .qc_defer = ahci_pmp_qc_defer,
151 .qc_prep = ahci_qc_prep,
152 .qc_issue = ahci_qc_issue,
153 .qc_fill_rtf = ahci_qc_fill_rtf,
154
155 .freeze = ahci_freeze,
156 .thaw = ahci_thaw,
157 .softreset = ahci_softreset,
158 .hardreset = ahci_hardreset,
159 .postreset = ahci_postreset,
160 .pmp_softreset = ahci_softreset,
161 .error_handler = ahci_error_handler,
162 .post_internal_cmd = ahci_post_internal_cmd,
163 .dev_config = ahci_dev_config,
164
165 .scr_read = ahci_scr_read,
166 .scr_write = ahci_scr_write,
167 .pmp_attach = ahci_pmp_attach,
168 .pmp_detach = ahci_pmp_detach,
169
6b7ae954 170 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 171 .em_show = ahci_led_show,
172 .em_store = ahci_led_store,
173 .sw_activity_show = ahci_activity_show,
174 .sw_activity_store = ahci_activity_store,
439d7a35 175 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 176#ifdef CONFIG_PM
177 .port_suspend = ahci_port_suspend,
178 .port_resume = ahci_port_resume,
179#endif
180 .port_start = ahci_port_start,
181 .port_stop = ahci_port_stop,
182};
183EXPORT_SYMBOL_GPL(ahci_ops);
184
345347c5
YHC		 185struct ata_port_operations ahci_pmp_retry_srst_ops = {
186 .inherits = &ahci_ops,
187 .softreset = ahci_pmp_retry_softreset,
188};
189EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
190
ed08d40c 191static bool ahci_em_messages __read_mostly = true;
365cfa1e 192EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 193module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 194/* add other LED protocol types when they become supported */
195MODULE_PARM_DESC(ahci_em_messages,
008dbd61 196 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 197
ed08d40c
CL		 198/* device sleep idle timeout in ms */
199static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 200module_param(devslp_idle_timeout, int, 0644);
201MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
202
365cfa1e
AV		 203static void ahci_enable_ahci(void __iomem *mmio)
204{
205 int i;
206 u32 tmp;
207
208 /* turn on AHCI_EN */
209 tmp = readl(mmio + HOST_CTL);
210 if (tmp & HOST_AHCI_EN)
211 return;
212
213 /* Some controllers need AHCI_EN to be written multiple times.
214 * Try a few times before giving up.
215 */
216 for (i = 0; i < 5; i++) {
217 tmp |= HOST_AHCI_EN;
218 writel(tmp, mmio + HOST_CTL);
219 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
220 if (tmp & HOST_AHCI_EN)
221 return;
222 msleep(10);
223 }
224
225 WARN_ON(1);
226}
227
228static ssize_t ahci_show_host_caps(struct device *dev,
229 struct device_attribute *attr, char *buf)
230{
231 struct Scsi_Host *shost = class_to_shost(dev);
232 struct ata_port *ap = ata_shost_to_port(shost);
233 struct ahci_host_priv *hpriv = ap->host->private_data;
234
235 return sprintf(buf, "%x\n", hpriv->cap);
236}
237
238static ssize_t ahci_show_host_cap2(struct device *dev,
239 struct device_attribute *attr, char *buf)
240{
241 struct Scsi_Host *shost = class_to_shost(dev);
242 struct ata_port *ap = ata_shost_to_port(shost);
243 struct ahci_host_priv *hpriv = ap->host->private_data;
244
245 return sprintf(buf, "%x\n", hpriv->cap2);
246}
247
248static ssize_t ahci_show_host_version(struct device *dev,
249 struct device_attribute *attr, char *buf)
250{
251 struct Scsi_Host *shost = class_to_shost(dev);
252 struct ata_port *ap = ata_shost_to_port(shost);
253 struct ahci_host_priv *hpriv = ap->host->private_data;
254 void __iomem *mmio = hpriv->mmio;
255
256 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
257}
258
259static ssize_t ahci_show_port_cmd(struct device *dev,
260 struct device_attribute *attr, char *buf)
261{
262 struct Scsi_Host *shost = class_to_shost(dev);
263 struct ata_port *ap = ata_shost_to_port(shost);
264 void __iomem *port_mmio = ahci_port_base(ap);
265
266 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
267}
268
c0623166
HZ		 269static ssize_t ahci_read_em_buffer(struct device *dev,
270 struct device_attribute *attr, char *buf)
271{
272 struct Scsi_Host *shost = class_to_shost(dev);
273 struct ata_port *ap = ata_shost_to_port(shost);
274 struct ahci_host_priv *hpriv = ap->host->private_data;
275 void __iomem *mmio = hpriv->mmio;
276 void __iomem *em_mmio = mmio + hpriv->em_loc;
277 u32 em_ctl, msg;
278 unsigned long flags;
279 size_t count;
280 int i;
281
282 spin_lock_irqsave(ap->lock, flags);
283
284 em_ctl = readl(mmio + HOST_EM_CTL);
285 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
286 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
287 spin_unlock_irqrestore(ap->lock, flags);
288 return -EINVAL;
289 }
290
291 if (!(em_ctl & EM_CTL_MR)) {
292 spin_unlock_irqrestore(ap->lock, flags);
293 return -EAGAIN;
294 }
295
296 if (!(em_ctl & EM_CTL_SMB))
297 em_mmio += hpriv->em_buf_sz;
298
299 count = hpriv->em_buf_sz;
300
301 /* the count should not be larger than PAGE_SIZE */
302 if (count > PAGE_SIZE) {
303 if (printk_ratelimit())
a9a79dfe
JP		 304 ata_port_warn(ap,
305 "EM read buffer size too large: "
306 "buffer size %u, page size %lu\n",
307 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 308 count = PAGE_SIZE;
309 }
310
311 for (i = 0; i < count; i += 4) {
312 msg = readl(em_mmio + i);
313 buf[i] = msg & 0xff;
314 buf[i + 1] = (msg >> 8) & 0xff;
315 buf[i + 2] = (msg >> 16) & 0xff;
316 buf[i + 3] = (msg >> 24) & 0xff;
317 }
318
319 spin_unlock_irqrestore(ap->lock, flags);
320
321 return i;
322}
323
324static ssize_t ahci_store_em_buffer(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t size)
327{
328 struct Scsi_Host *shost = class_to_shost(dev);
329 struct ata_port *ap = ata_shost_to_port(shost);
330 struct ahci_host_priv *hpriv = ap->host->private_data;
331 void __iomem *mmio = hpriv->mmio;
332 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 333 const unsigned char *msg_buf = buf;
c0623166
HZ		 334 u32 em_ctl, msg;
335 unsigned long flags;
336 int i;
337
338 /* check size validity */
339 if (!(ap->flags & ATA_FLAG_EM) ||
340 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
341 size % 4 || size > hpriv->em_buf_sz)
342 return -EINVAL;
343
344 spin_lock_irqsave(ap->lock, flags);
345
346 em_ctl = readl(mmio + HOST_EM_CTL);
347 if (em_ctl & EM_CTL_TM) {
348 spin_unlock_irqrestore(ap->lock, flags);
349 return -EBUSY;
350 }
351
352 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 353 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
354 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 355 writel(msg, em_mmio + i);
356 }
357
358 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
359
360 spin_unlock_irqrestore(ap->lock, flags);
361
362 return size;
363}
364
6e5fe5b1
HR		 365static ssize_t ahci_show_em_supported(struct device *dev,
366 struct device_attribute *attr, char *buf)
367{
368 struct Scsi_Host *shost = class_to_shost(dev);
369 struct ata_port *ap = ata_shost_to_port(shost);
370 struct ahci_host_priv *hpriv = ap->host->private_data;
371 void __iomem *mmio = hpriv->mmio;
372 u32 em_ctl;
373
374 em_ctl = readl(mmio + HOST_EM_CTL);
375
376 return sprintf(buf, "%s%s%s%s\n",
377 em_ctl & EM_CTL_LED ? "led " : "",
378 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
379 em_ctl & EM_CTL_SES ? "ses-2 " : "",
380 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
381}
382
365cfa1e
AV		 383/**
384 * ahci_save_initial_config - Save and fixup initial config values
385 * @dev: target AHCI device
386 * @hpriv: host private area to store config values
387 * @force_port_map: force port map to a specified value
388 * @mask_port_map: mask out particular bits from port map
389 *
390 * Some registers containing configuration info might be setup by
391 * BIOS and might be cleared on reset. This function saves the
392 * initial values of those registers into @hpriv such that they
393 * can be restored after controller reset.
394 *
395 * If inconsistent, config values are fixed up by this function.
396 *
397 * LOCKING:
398 * None.
399 */
400void ahci_save_initial_config(struct device *dev,
401 struct ahci_host_priv *hpriv,
402 unsigned int force_port_map,
403 unsigned int mask_port_map)
404{
405 void __iomem *mmio = hpriv->mmio;
406 u32 cap, cap2, vers, port_map;
407 int i;
408
409 /* make sure AHCI mode is enabled before accessing CAP */
410 ahci_enable_ahci(mmio);
411
412 /* Values prefixed with saved_ are written back to host after
413 * reset. Values without are used for driver operation.
414 */
415 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
416 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
417
418 /* CAP2 register is only defined for AHCI 1.2 and later */
419 vers = readl(mmio + HOST_VERSION);
420 if ((vers >> 16) > 1 ||
421 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
422 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
423 else
424 hpriv->saved_cap2 = cap2 = 0;
425
426 /* some chips have errata preventing 64bit use */
427 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 428 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 429 cap &= ~HOST_CAP_64;
430 }
431
432 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 433 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 434 cap &= ~HOST_CAP_NCQ;
435 }
436
437 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 438 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 439 cap |= HOST_CAP_NCQ;
440 }
441
442 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 443 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 444 cap &= ~HOST_CAP_PMP;
445 }
446
447 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 448 dev_info(dev,
449 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 450 cap &= ~HOST_CAP_SNTF;
451 }
452
5f173107 453 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 454 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 455 cap |= HOST_CAP_FBS;
456 }
457
365cfa1e 458 if (force_port_map && port_map != force_port_map) {
a44fec1f
JP		 459 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
460 port_map, force_port_map);
365cfa1e
AV		 461 port_map = force_port_map;
462 }
463
464 if (mask_port_map) {
a44fec1f
JP		 465 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
466 port_map,
467 port_map & mask_port_map);
365cfa1e
AV		 468 port_map &= mask_port_map;
469 }
470
471 /* cross check port_map and cap.n_ports */
472 if (port_map) {
473 int map_ports = 0;
474
475 for (i = 0; i < AHCI_MAX_PORTS; i++)
476 if (port_map & (1 << i))
477 map_ports++;
478
479 /* If PI has more ports than n_ports, whine, clear
480 * port_map and let it be generated from n_ports.
481 */
482 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 483 dev_warn(dev,
484 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
485 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 486 port_map = 0;
487 }
488 }
489
490 /* fabricate port_map from cap.nr_ports */
491 if (!port_map) {
492 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 493 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 494
495 /* write the fixed up value to the PI register */
496 hpriv->saved_port_map = port_map;
497 }
498
499 /* record values to use during operation */
500 hpriv->cap = cap;
501 hpriv->cap2 = cap2;
502 hpriv->port_map = port_map;
503}
504EXPORT_SYMBOL_GPL(ahci_save_initial_config);
505
506/**
507 * ahci_restore_initial_config - Restore initial config
508 * @host: target ATA host
509 *
510 * Restore initial config stored by ahci_save_initial_config().
511 *
512 * LOCKING:
513 * None.
514 */
515static void ahci_restore_initial_config(struct ata_host *host)
516{
517 struct ahci_host_priv *hpriv = host->private_data;
518 void __iomem *mmio = hpriv->mmio;
519
520 writel(hpriv->saved_cap, mmio + HOST_CAP);
521 if (hpriv->saved_cap2)
522 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
523 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
524 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
525}
526
527static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
528{
529 static const int offset[] = {
530 [SCR_STATUS] = PORT_SCR_STAT,
531 [SCR_CONTROL] = PORT_SCR_CTL,
532 [SCR_ERROR] = PORT_SCR_ERR,
533 [SCR_ACTIVE] = PORT_SCR_ACT,
534 [SCR_NOTIFICATION] = PORT_SCR_NTF,
535 };
536 struct ahci_host_priv *hpriv = ap->host->private_data;
537
538 if (sc_reg < ARRAY_SIZE(offset) &&
539 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
540 return offset[sc_reg];
541 return 0;
542}
543
544static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
545{
546 void __iomem *port_mmio = ahci_port_base(link->ap);
547 int offset = ahci_scr_offset(link->ap, sc_reg);
548
549 if (offset) {
550 *val = readl(port_mmio + offset);
551 return 0;
552 }
553 return -EINVAL;
554}
555
556static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
557{
558 void __iomem *port_mmio = ahci_port_base(link->ap);
559 int offset = ahci_scr_offset(link->ap, sc_reg);
560
561 if (offset) {
562 writel(val, port_mmio + offset);
563 return 0;
564 }
565 return -EINVAL;
566}
567
568void ahci_start_engine(struct ata_port *ap)
569{
570 void __iomem *port_mmio = ahci_port_base(ap);
571 u32 tmp;
572
573 /* start DMA */
574 tmp = readl(port_mmio + PORT_CMD);
575 tmp |= PORT_CMD_START;
576 writel(tmp, port_mmio + PORT_CMD);
577 readl(port_mmio + PORT_CMD); /* flush */
578}
579EXPORT_SYMBOL_GPL(ahci_start_engine);
580
581int ahci_stop_engine(struct ata_port *ap)
582{
583 void __iomem *port_mmio = ahci_port_base(ap);
584 u32 tmp;
585
586 tmp = readl(port_mmio + PORT_CMD);
587
588 /* check if the HBA is idle */
589 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
590 return 0;
591
592 /* setting HBA to idle */
593 tmp &= ~PORT_CMD_START;
594 writel(tmp, port_mmio + PORT_CMD);
595
596 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 597 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 598 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
599 if (tmp & PORT_CMD_LIST_ON)
600 return -EIO;
601
602 return 0;
603}
604EXPORT_SYMBOL_GPL(ahci_stop_engine);
605
606static void ahci_start_fis_rx(struct ata_port *ap)
607{
608 void __iomem *port_mmio = ahci_port_base(ap);
609 struct ahci_host_priv *hpriv = ap->host->private_data;
610 struct ahci_port_priv *pp = ap->private_data;
611 u32 tmp;
612
613 /* set FIS registers */
614 if (hpriv->cap & HOST_CAP_64)
615 writel((pp->cmd_slot_dma >> 16) >> 16,
616 port_mmio + PORT_LST_ADDR_HI);
617 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
618
619 if (hpriv->cap & HOST_CAP_64)
620 writel((pp->rx_fis_dma >> 16) >> 16,
621 port_mmio + PORT_FIS_ADDR_HI);
622 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
623
624 /* enable FIS reception */
625 tmp = readl(port_mmio + PORT_CMD);
626 tmp |= PORT_CMD_FIS_RX;
627 writel(tmp, port_mmio + PORT_CMD);
628
629 /* flush */
630 readl(port_mmio + PORT_CMD);
631}
632
633static int ahci_stop_fis_rx(struct ata_port *ap)
634{
635 void __iomem *port_mmio = ahci_port_base(ap);
636 u32 tmp;
637
638 /* disable FIS reception */
639 tmp = readl(port_mmio + PORT_CMD);
640 tmp &= ~PORT_CMD_FIS_RX;
641 writel(tmp, port_mmio + PORT_CMD);
642
643 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 644 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 645 PORT_CMD_FIS_ON, 10, 1000);
646 if (tmp & PORT_CMD_FIS_ON)
647 return -EBUSY;
648
649 return 0;
650}
651
652static void ahci_power_up(struct ata_port *ap)
653{
654 struct ahci_host_priv *hpriv = ap->host->private_data;
655 void __iomem *port_mmio = ahci_port_base(ap);
656 u32 cmd;
657
658 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
659
660 /* spin up device */
661 if (hpriv->cap & HOST_CAP_SSS) {
662 cmd |= PORT_CMD_SPIN_UP;
663 writel(cmd, port_mmio + PORT_CMD);
664 }
665
666 /* wake up link */
667 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
668}
669
6b7ae954
TH		 670static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
671 unsigned int hints)
365cfa1e 672{
6b7ae954 673 struct ata_port *ap = link->ap;
365cfa1e 674 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 675 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 676 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 677
6b7ae954 678 if (policy != ATA_LPM_MAX_POWER) {
365cfa1e 679 /*
6b7ae954
TH		 680 * Disable interrupts on Phy Ready. This keeps us from
681 * getting woken up due to spurious phy ready
682 * interrupts.
365cfa1e 683 */
6b7ae954
TH		 684 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
685 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
686
687 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 688 }
689
6b7ae954
TH		 690 if (hpriv->cap & HOST_CAP_ALPM) {
691 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 692
6b7ae954
TH		 693 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
694 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
695 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 696
6b7ae954
TH		 697 writel(cmd, port_mmio + PORT_CMD);
698 readl(port_mmio + PORT_CMD);
365cfa1e 699
6b7ae954 700 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 701 ata_msleep(ap, 10);
6b7ae954
TH		 702 } else {
703 cmd |= PORT_CMD_ALPE;
704 if (policy == ATA_LPM_MIN_POWER)
705 cmd |= PORT_CMD_ASP;
365cfa1e 706
6b7ae954
TH		 707 /* write out new cmd value */
708 writel(cmd, port_mmio + PORT_CMD);
709 }
710 }
365cfa1e 711
65fe1f0f
SH		 712 /* set aggressive device sleep */
713 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
714 (hpriv->cap2 & HOST_CAP2_SADM) &&
715 (link->device->flags & ATA_DFLAG_DEVSLP)) {
716 if (policy == ATA_LPM_MIN_POWER)
717 ahci_set_aggressive_devslp(ap, true);
718 else
719 ahci_set_aggressive_devslp(ap, false);
720 }
721
6b7ae954
TH		 722 if (policy == ATA_LPM_MAX_POWER) {
723 sata_link_scr_lpm(link, policy, false);
724
725 /* turn PHYRDY IRQ back on */
726 pp->intr_mask |= PORT_IRQ_PHYRDY;
727 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
728 }
365cfa1e 729
365cfa1e
AV		 730 return 0;
731}
732
733#ifdef CONFIG_PM
734static void ahci_power_down(struct ata_port *ap)
735{
736 struct ahci_host_priv *hpriv = ap->host->private_data;
737 void __iomem *port_mmio = ahci_port_base(ap);
738 u32 cmd, scontrol;
739
740 if (!(hpriv->cap & HOST_CAP_SSS))
741 return;
742
743 /* put device into listen mode, first set PxSCTL.DET to 0 */
744 scontrol = readl(port_mmio + PORT_SCR_CTL);
745 scontrol &= ~0xf;
746 writel(scontrol, port_mmio + PORT_SCR_CTL);
747
748 /* then set PxCMD.SUD to 0 */
749 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
750 cmd &= ~PORT_CMD_SPIN_UP;
751 writel(cmd, port_mmio + PORT_CMD);
752}
753#endif
754
755static void ahci_start_port(struct ata_port *ap)
756{
66583c9f 757 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 758 struct ahci_port_priv *pp = ap->private_data;
759 struct ata_link *link;
760 struct ahci_em_priv *emp;
761 ssize_t rc;
762 int i;
763
764 /* enable FIS reception */
765 ahci_start_fis_rx(ap);
766
66583c9f
BN		 767 /* enable DMA */
768 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
769 ahci_start_engine(ap);
770
365cfa1e
AV		 771 /* turn on LEDs */
772 if (ap->flags & ATA_FLAG_EM) {
773 ata_for_each_link(link, ap, EDGE) {
774 emp = &pp->em_priv[link->pmp];
775
776 /* EM Transmit bit maybe busy during init */
777 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 778 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 779 emp->led_state,
780 4);
781 if (rc == -EBUSY)
97750ceb 782 ata_msleep(ap, 1);
365cfa1e
AV		 783 else
784 break;
785 }
786 }
787 }
788
789 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
790 ata_for_each_link(link, ap, EDGE)
791 ahci_init_sw_activity(link);
792
793}
794
795static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
796{
797 int rc;
798
799 /* disable DMA */
800 rc = ahci_stop_engine(ap);
801 if (rc) {
802 *emsg = "failed to stop engine";
803 return rc;
804 }
805
806 /* disable FIS reception */
807 rc = ahci_stop_fis_rx(ap);
808 if (rc) {
809 *emsg = "failed stop FIS RX";
810 return rc;
811 }
812
813 return 0;
814}
815
816int ahci_reset_controller(struct ata_host *host)
817{
818 struct ahci_host_priv *hpriv = host->private_data;
819 void __iomem *mmio = hpriv->mmio;
820 u32 tmp;
821
822 /* we must be in AHCI mode, before using anything
823 * AHCI-specific, such as HOST_RESET.
824 */
825 ahci_enable_ahci(mmio);
826
827 /* global controller reset */
828 if (!ahci_skip_host_reset) {
829 tmp = readl(mmio + HOST_CTL);
830 if ((tmp & HOST_RESET) == 0) {
831 writel(tmp | HOST_RESET, mmio + HOST_CTL);
832 readl(mmio + HOST_CTL); /* flush */
833 }
834
835 /*
836 * to perform host reset, OS should set HOST_RESET
837 * and poll until this bit is read to be "0".
838 * reset must complete within 1 second, or
839 * the hardware should be considered fried.
840 */
97750ceb 841 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 842 HOST_RESET, 10, 1000);
843
844 if (tmp & HOST_RESET) {
a44fec1f
JP		 845 dev_err(host->dev, "controller reset failed (0x%x)\n",
846 tmp);
365cfa1e
AV		 847 return -EIO;
848 }
849
850 /* turn on AHCI mode */
851 ahci_enable_ahci(mmio);
852
853 /* Some registers might be cleared on reset. Restore
854 * initial values.
855 */
856 ahci_restore_initial_config(host);
857 } else
a44fec1f 858 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 859
860 return 0;
861}
862EXPORT_SYMBOL_GPL(ahci_reset_controller);
863
864static void ahci_sw_activity(struct ata_link *link)
865{
866 struct ata_port *ap = link->ap;
867 struct ahci_port_priv *pp = ap->private_data;
868 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
869
870 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
871 return;
872
873 emp->activity++;
874 if (!timer_pending(&emp->timer))
875 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
876}
877
878static void ahci_sw_activity_blink(unsigned long arg)
879{
880 struct ata_link *link = (struct ata_link *)arg;
881 struct ata_port *ap = link->ap;
882 struct ahci_port_priv *pp = ap->private_data;
883 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
884 unsigned long led_message = emp->led_state;
885 u32 activity_led_state;
886 unsigned long flags;
887
888 led_message &= EM_MSG_LED_VALUE;
889 led_message |= ap->port_no | (link->pmp << 8);
890
891 /* check to see if we've had activity. If so,
892 * toggle state of LED and reset timer. If not,
893 * turn LED to desired idle state.
894 */
895 spin_lock_irqsave(ap->lock, flags);
896 if (emp->saved_activity != emp->activity) {
897 emp->saved_activity = emp->activity;
898 /* get the current LED state */
899 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
900
901 if (activity_led_state)
902 activity_led_state = 0;
903 else
904 activity_led_state = 1;
905
906 /* clear old state */
907 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
908
909 /* toggle state */
910 led_message |= (activity_led_state << 16);
911 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
912 } else {
913 /* switch to idle */
914 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
915 if (emp->blink_policy == BLINK_OFF)
916 led_message |= (1 << 16);
917 }
918 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 919 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 920}
921
922static void ahci_init_sw_activity(struct ata_link *link)
923{
924 struct ata_port *ap = link->ap;
925 struct ahci_port_priv *pp = ap->private_data;
926 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
927
928 /* init activity stats, setup timer */
929 emp->saved_activity = emp->activity = 0;
930 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
931
932 /* check our blink policy and set flag for link if it's enabled */
933 if (emp->blink_policy)
934 link->flags |= ATA_LFLAG_SW_ACTIVITY;
935}
936
937int ahci_reset_em(struct ata_host *host)
938{
939 struct ahci_host_priv *hpriv = host->private_data;
940 void __iomem *mmio = hpriv->mmio;
941 u32 em_ctl;
942
943 em_ctl = readl(mmio + HOST_EM_CTL);
944 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
945 return -EINVAL;
946
947 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
948 return 0;
949}
950EXPORT_SYMBOL_GPL(ahci_reset_em);
951
952static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
953 ssize_t size)
954{
955 struct ahci_host_priv *hpriv = ap->host->private_data;
956 struct ahci_port_priv *pp = ap->private_data;
957 void __iomem *mmio = hpriv->mmio;
958 u32 em_ctl;
959 u32 message[] = {0, 0};
960 unsigned long flags;
961 int pmp;
962 struct ahci_em_priv *emp;
963
964 /* get the slot number from the message */
965 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
966 if (pmp < EM_MAX_SLOTS)
967 emp = &pp->em_priv[pmp];
968 else
969 return -EINVAL;
970
971 spin_lock_irqsave(ap->lock, flags);
972
973 /*
974 * if we are still busy transmitting a previous message,
975 * do not allow
976 */
977 em_ctl = readl(mmio + HOST_EM_CTL);
978 if (em_ctl & EM_CTL_TM) {
979 spin_unlock_irqrestore(ap->lock, flags);
980 return -EBUSY;
981 }
982
008dbd61
HZ		 983 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
984 /*
985 * create message header - this is all zero except for
986 * the message size, which is 4 bytes.
987 */
988 message[0] |= (4 << 8);
365cfa1e 989
008dbd61
HZ		 990 /* ignore 0:4 of byte zero, fill in port info yourself */
991 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 992
008dbd61
HZ		 993 /* write message to EM_LOC */
994 writel(message[0], mmio + hpriv->em_loc);
995 writel(message[1], mmio + hpriv->em_loc+4);
996
997 /*
998 * tell hardware to transmit the message
999 */
1000 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1001 }
365cfa1e
AV		 1002
1003 /* save off new led state for port/slot */
1004 emp->led_state = state;
1005
365cfa1e
AV		 1006 spin_unlock_irqrestore(ap->lock, flags);
1007 return size;
1008}
1009
1010static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1011{
1012 struct ahci_port_priv *pp = ap->private_data;
1013 struct ata_link *link;
1014 struct ahci_em_priv *emp;
1015 int rc = 0;
1016
1017 ata_for_each_link(link, ap, EDGE) {
1018 emp = &pp->em_priv[link->pmp];
1019 rc += sprintf(buf, "%lx\n", emp->led_state);
1020 }
1021 return rc;
1022}
1023
1024static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1025 size_t size)
1026{
1027 int state;
1028 int pmp;
1029 struct ahci_port_priv *pp = ap->private_data;
1030 struct ahci_em_priv *emp;
1031
1032 state = simple_strtoul(buf, NULL, 0);
1033
1034 /* get the slot number from the message */
1035 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1036 if (pmp < EM_MAX_SLOTS)
1037 emp = &pp->em_priv[pmp];
1038 else
1039 return -EINVAL;
1040
1041 /* mask off the activity bits if we are in sw_activity
1042 * mode, user should turn off sw_activity before setting
1043 * activity led through em_message
1044 */
1045 if (emp->blink_policy)
1046 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1047
439d7a35 1048 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1049}
1050
1051static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1052{
1053 struct ata_link *link = dev->link;
1054 struct ata_port *ap = link->ap;
1055 struct ahci_port_priv *pp = ap->private_data;
1056 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1057 u32 port_led_state = emp->led_state;
1058
1059 /* save the desired Activity LED behavior */
1060 if (val == OFF) {
1061 /* clear LFLAG */
1062 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1063
1064 /* set the LED to OFF */
1065 port_led_state &= EM_MSG_LED_VALUE_OFF;
1066 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1067 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1068 } else {
1069 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1070 if (val == BLINK_OFF) {
1071 /* set LED to ON for idle */
1072 port_led_state &= EM_MSG_LED_VALUE_OFF;
1073 port_led_state |= (ap->port_no | (link->pmp << 8));
1074 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1075 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1076 }
1077 }
1078 emp->blink_policy = val;
1079 return 0;
1080}
1081
1082static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1083{
1084 struct ata_link *link = dev->link;
1085 struct ata_port *ap = link->ap;
1086 struct ahci_port_priv *pp = ap->private_data;
1087 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1088
1089 /* display the saved value of activity behavior for this
1090 * disk.
1091 */
1092 return sprintf(buf, "%d\n", emp->blink_policy);
1093}
1094
1095static void ahci_port_init(struct device *dev, struct ata_port *ap,
1096 int port_no, void __iomem *mmio,
1097 void __iomem *port_mmio)
1098{
1099 const char *emsg = NULL;
1100 int rc;
1101 u32 tmp;
1102
1103 /* make sure port is not active */
1104 rc = ahci_deinit_port(ap, &emsg);
1105 if (rc)
1106 dev_warn(dev, "%s (%d)\n", emsg, rc);
1107
1108 /* clear SError */
1109 tmp = readl(port_mmio + PORT_SCR_ERR);
1110 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1111 writel(tmp, port_mmio + PORT_SCR_ERR);
1112
1113 /* clear port IRQ */
1114 tmp = readl(port_mmio + PORT_IRQ_STAT);
1115 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1116 if (tmp)
1117 writel(tmp, port_mmio + PORT_IRQ_STAT);
1118
1119 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1120}
1121
1122void ahci_init_controller(struct ata_host *host)
1123{
1124 struct ahci_host_priv *hpriv = host->private_data;
1125 void __iomem *mmio = hpriv->mmio;
1126 int i;
1127 void __iomem *port_mmio;
1128 u32 tmp;
1129
1130 for (i = 0; i < host->n_ports; i++) {
1131 struct ata_port *ap = host->ports[i];
1132
1133 port_mmio = ahci_port_base(ap);
1134 if (ata_port_is_dummy(ap))
1135 continue;
1136
1137 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1138 }
1139
1140 tmp = readl(mmio + HOST_CTL);
1141 VPRINTK("HOST_CTL 0x%x\n", tmp);
1142 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1143 tmp = readl(mmio + HOST_CTL);
1144 VPRINTK("HOST_CTL 0x%x\n", tmp);
1145}
1146EXPORT_SYMBOL_GPL(ahci_init_controller);
1147
1148static void ahci_dev_config(struct ata_device *dev)
1149{
1150 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1151
1152 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1153 dev->max_sectors = 255;
a9a79dfe
JP		 1154 ata_dev_info(dev,
1155 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1156 }
1157}
1158
bbb4ab43 1159unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1160{
1161 void __iomem *port_mmio = ahci_port_base(ap);
1162 struct ata_taskfile tf;
1163 u32 tmp;
1164
1165 tmp = readl(port_mmio + PORT_SIG);
1166 tf.lbah = (tmp >> 24) & 0xff;
1167 tf.lbam = (tmp >> 16) & 0xff;
1168 tf.lbal = (tmp >> 8) & 0xff;
1169 tf.nsect = (tmp) & 0xff;
1170
1171 return ata_dev_classify(&tf);
1172}
bbb4ab43 1173EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1174
02cdfcf0
DM		 1175void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1176 u32 opts)
365cfa1e
AV		 1177{
1178 dma_addr_t cmd_tbl_dma;
1179
1180 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1181
1182 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1183 pp->cmd_slot[tag].status = 0;
1184 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1185 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1186}
02cdfcf0 1187EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1188
1189int ahci_kick_engine(struct ata_port *ap)
1190{
1191 void __iomem *port_mmio = ahci_port_base(ap);
1192 struct ahci_host_priv *hpriv = ap->host->private_data;
1193 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1194 u32 tmp;
1195 int busy, rc;
1196
1197 /* stop engine */
1198 rc = ahci_stop_engine(ap);
1199 if (rc)
1200 goto out_restart;
1201
1202 /* need to do CLO?
1203 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1204 */
1205 busy = status & (ATA_BUSY | ATA_DRQ);
1206 if (!busy && !sata_pmp_attached(ap)) {
1207 rc = 0;
1208 goto out_restart;
1209 }
1210
1211 if (!(hpriv->cap & HOST_CAP_CLO)) {
1212 rc = -EOPNOTSUPP;
1213 goto out_restart;
1214 }
1215
1216 /* perform CLO */
1217 tmp = readl(port_mmio + PORT_CMD);
1218 tmp |= PORT_CMD_CLO;
1219 writel(tmp, port_mmio + PORT_CMD);
1220
1221 rc = 0;
97750ceb 1222 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1223 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1224 if (tmp & PORT_CMD_CLO)
1225 rc = -EIO;
1226
1227 /* restart engine */
1228 out_restart:
1229 ahci_start_engine(ap);
1230 return rc;
1231}
1232EXPORT_SYMBOL_GPL(ahci_kick_engine);
1233
1234static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1235 struct ata_taskfile *tf, int is_cmd, u16 flags,
1236 unsigned long timeout_msec)
1237{
1238 const u32 cmd_fis_len = 5; /* five dwords */
1239 struct ahci_port_priv *pp = ap->private_data;
1240 void __iomem *port_mmio = ahci_port_base(ap);
1241 u8 *fis = pp->cmd_tbl;
1242 u32 tmp;
1243
1244 /* prep the command */
1245 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1246 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1247
1248 /* issue & wait */
1249 writel(1, port_mmio + PORT_CMD_ISSUE);
1250
1251 if (timeout_msec) {
97750ceb
TH		 1252 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1253 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1254 if (tmp & 0x1) {
1255 ahci_kick_engine(ap);
1256 return -EBUSY;
1257 }
1258 } else
1259 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1260
1261 return 0;
1262}
1263
1264int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1265 int pmp, unsigned long deadline,
1266 int (*check_ready)(struct ata_link *link))
1267{
1268 struct ata_port *ap = link->ap;
1269 struct ahci_host_priv *hpriv = ap->host->private_data;
1270 const char *reason = NULL;
1271 unsigned long now, msecs;
1272 struct ata_taskfile tf;
1273 int rc;
1274
1275 DPRINTK("ENTER\n");
1276
1277 /* prepare for SRST (AHCI-1.1 10.4.1) */
1278 rc = ahci_kick_engine(ap);
1279 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1280 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e
AV		 1281
1282 ata_tf_init(link->device, &tf);
1283
1284 /* issue the first D2H Register FIS */
1285 msecs = 0;
1286 now = jiffies;
f1f5a807 1287 if (time_after(deadline, now))
365cfa1e
AV		 1288 msecs = jiffies_to_msecs(deadline - now);
1289
1290 tf.ctl |= ATA_SRST;
1291 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1292 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1293 rc = -EIO;
1294 reason = "1st FIS failed";
1295 goto fail;
1296 }
1297
1298 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1299 ata_msleep(ap, 1);
365cfa1e
AV		 1300
1301 /* issue the second D2H Register FIS */
1302 tf.ctl &= ~ATA_SRST;
1303 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1304
1305 /* wait for link to become ready */
1306 rc = ata_wait_after_reset(link, deadline, check_ready);
1307 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1308 /*
1309 * Workaround for cases where link online status can't
1310 * be trusted. Treat device readiness timeout as link
1311 * offline.
1312 */
a9a79dfe 1313 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1314 *class = ATA_DEV_NONE;
1315 } else if (rc) {
1316 /* link occupied, -ENODEV too is an error */
1317 reason = "device not ready";
1318 goto fail;
1319 } else
1320 *class = ahci_dev_classify(ap);
1321
1322 DPRINTK("EXIT, class=%u\n", *class);
1323 return 0;
1324
1325 fail:
a9a79dfe 1326 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1327 return rc;
1328}
1329
1330int ahci_check_ready(struct ata_link *link)
1331{
1332 void __iomem *port_mmio = ahci_port_base(link->ap);
1333 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1334
1335 return ata_check_ready(status);
1336}
1337EXPORT_SYMBOL_GPL(ahci_check_ready);
1338
1339static int ahci_softreset(struct ata_link *link, unsigned int *class,
1340 unsigned long deadline)
1341{
1342 int pmp = sata_srst_pmp(link);
1343
1344 DPRINTK("ENTER\n");
1345
1346 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1347}
1348EXPORT_SYMBOL_GPL(ahci_do_softreset);
1349
345347c5
YHC		 1350static int ahci_bad_pmp_check_ready(struct ata_link *link)
1351{
1352 void __iomem *port_mmio = ahci_port_base(link->ap);
1353 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1354 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1355
1356 /*
1357 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1358 * which can save timeout delay.
1359 */
1360 if (irq_status & PORT_IRQ_BAD_PMP)
1361 return -EIO;
1362
1363 return ata_check_ready(status);
1364}
1365
1366int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1367 unsigned long deadline)
1368{
1369 struct ata_port *ap = link->ap;
1370 void __iomem *port_mmio = ahci_port_base(ap);
1371 int pmp = sata_srst_pmp(link);
1372 int rc;
1373 u32 irq_sts;
1374
1375 DPRINTK("ENTER\n");
1376
1377 rc = ahci_do_softreset(link, class, pmp, deadline,
1378 ahci_bad_pmp_check_ready);
1379
1380 /*
1381 * Soft reset fails with IPMS set when PMP is enabled but
1382 * SATA HDD/ODD is connected to SATA port, do soft reset
1383 * again to port 0.
1384 */
1385 if (rc == -EIO) {
1386 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1387 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1388 ata_link_warn(link,
345347c5
YHC		 1389 "applying PMP SRST workaround "
1390 "and retrying\n");
1391 rc = ahci_do_softreset(link, class, 0, deadline,
1392 ahci_check_ready);
1393 }
1394 }
1395
1396 return rc;
1397}
1398
365cfa1e
AV		 1399static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1400 unsigned long deadline)
1401{
1402 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1403 struct ata_port *ap = link->ap;
1404 struct ahci_port_priv *pp = ap->private_data;
1405 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1406 struct ata_taskfile tf;
1407 bool online;
1408 int rc;
1409
1410 DPRINTK("ENTER\n");
1411
1412 ahci_stop_engine(ap);
1413
1414 /* clear D2H reception area to properly wait for D2H FIS */
1415 ata_tf_init(link->device, &tf);
9bbb1b0e 1416 tf.command = ATA_BUSY;
365cfa1e
AV		 1417 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1418
1419 rc = sata_link_hardreset(link, timing, deadline, &online,
1420 ahci_check_ready);
1421
1422 ahci_start_engine(ap);
1423
1424 if (online)
1425 *class = ahci_dev_classify(ap);
1426
1427 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1428 return rc;
1429}
1430
1431static void ahci_postreset(struct ata_link *link, unsigned int *class)
1432{
1433 struct ata_port *ap = link->ap;
1434 void __iomem *port_mmio = ahci_port_base(ap);
1435 u32 new_tmp, tmp;
1436
1437 ata_std_postreset(link, class);
1438
1439 /* Make sure port's ATAPI bit is set appropriately */
1440 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1441 if (*class == ATA_DEV_ATAPI)
1442 new_tmp |= PORT_CMD_ATAPI;
1443 else
1444 new_tmp &= ~PORT_CMD_ATAPI;
1445 if (new_tmp != tmp) {
1446 writel(new_tmp, port_mmio + PORT_CMD);
1447 readl(port_mmio + PORT_CMD); /* flush */
1448 }
1449}
1450
1451static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1452{
1453 struct scatterlist *sg;
1454 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1455 unsigned int si;
1456
1457 VPRINTK("ENTER\n");
1458
1459 /*
1460 * Next, the S/G list.
1461 */
1462 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1463 dma_addr_t addr = sg_dma_address(sg);
1464 u32 sg_len = sg_dma_len(sg);
1465
1466 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1467 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1468 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1469 }
1470
1471 return si;
1472}
1473
1474static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1475{
1476 struct ata_port *ap = qc->ap;
1477 struct ahci_port_priv *pp = ap->private_data;
1478
1479 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1480 return ata_std_qc_defer(qc);
1481 else
1482 return sata_pmp_qc_defer_cmd_switch(qc);
1483}
1484
1485static void ahci_qc_prep(struct ata_queued_cmd *qc)
1486{
1487 struct ata_port *ap = qc->ap;
1488 struct ahci_port_priv *pp = ap->private_data;
1489 int is_atapi = ata_is_atapi(qc->tf.protocol);
1490 void *cmd_tbl;
1491 u32 opts;
1492 const u32 cmd_fis_len = 5; /* five dwords */
1493 unsigned int n_elem;
1494
1495 /*
1496 * Fill in command table information. First, the header,
1497 * a SATA Register - Host to Device command FIS.
1498 */
1499 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1500
1501 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1502 if (is_atapi) {
1503 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1504 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1505 }
1506
1507 n_elem = 0;
1508 if (qc->flags & ATA_QCFLAG_DMAMAP)
1509 n_elem = ahci_fill_sg(qc, cmd_tbl);
1510
1511 /*
1512 * Fill in command slot information.
1513 */
1514 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1515 if (qc->tf.flags & ATA_TFLAG_WRITE)
1516 opts |= AHCI_CMD_WRITE;
1517 if (is_atapi)
1518 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1519
1520 ahci_fill_cmd_slot(pp, qc->tag, opts);
1521}
1522
1523static void ahci_fbs_dec_intr(struct ata_port *ap)
1524{
1525 struct ahci_port_priv *pp = ap->private_data;
1526 void __iomem *port_mmio = ahci_port_base(ap);
1527 u32 fbs = readl(port_mmio + PORT_FBS);
1528 int retries = 3;
1529
1530 DPRINTK("ENTER\n");
1531 BUG_ON(!pp->fbs_enabled);
1532
1533 /* time to wait for DEC is not specified by AHCI spec,
1534 * add a retry loop for safety.
1535 */
1536 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1537 fbs = readl(port_mmio + PORT_FBS);
1538 while ((fbs & PORT_FBS_DEC) && retries--) {
1539 udelay(1);
1540 fbs = readl(port_mmio + PORT_FBS);
1541 }
1542
1543 if (fbs & PORT_FBS_DEC)
a44fec1f 1544 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1545}
1546
1547static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1548{
1549 struct ahci_host_priv *hpriv = ap->host->private_data;
1550 struct ahci_port_priv *pp = ap->private_data;
1551 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1552 struct ata_link *link = NULL;
1553 struct ata_queued_cmd *active_qc;
1554 struct ata_eh_info *active_ehi;
1555 bool fbs_need_dec = false;
1556 u32 serror;
1557
1558 /* determine active link with error */
1559 if (pp->fbs_enabled) {
1560 void __iomem *port_mmio = ahci_port_base(ap);
1561 u32 fbs = readl(port_mmio + PORT_FBS);
1562 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1563
912b9ac6 1564 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1565 link = &ap->pmp_link[pmp];
1566 fbs_need_dec = true;
1567 }
1568
1569 } else
1570 ata_for_each_link(link, ap, EDGE)
1571 if (ata_link_active(link))
1572 break;
1573
1574 if (!link)
1575 link = &ap->link;
1576
1577 active_qc = ata_qc_from_tag(ap, link->active_tag);
1578 active_ehi = &link->eh_info;
1579
1580 /* record irq stat */
1581 ata_ehi_clear_desc(host_ehi);
1582 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1583
1584 /* AHCI needs SError cleared; otherwise, it might lock up */
1585 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1586 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1587 host_ehi->serror |= serror;
1588
1589 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1590 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1591 irq_stat &= ~PORT_IRQ_IF_ERR;
1592
1593 if (irq_stat & PORT_IRQ_TF_ERR) {
1594 /* If qc is active, charge it; otherwise, the active
1595 * link. There's no active qc on NCQ errors. It will
1596 * be determined by EH by reading log page 10h.
1597 */
1598 if (active_qc)
1599 active_qc->err_mask |= AC_ERR_DEV;
1600 else
1601 active_ehi->err_mask |= AC_ERR_DEV;
1602
1603 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1604 host_ehi->serror &= ~SERR_INTERNAL;
1605 }
1606
1607 if (irq_stat & PORT_IRQ_UNK_FIS) {
1608 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1609
1610 active_ehi->err_mask |= AC_ERR_HSM;
1611 active_ehi->action |= ATA_EH_RESET;
1612 ata_ehi_push_desc(active_ehi,
1613 "unknown FIS %08x %08x %08x %08x" ,
1614 unk[0], unk[1], unk[2], unk[3]);
1615 }
1616
1617 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1618 active_ehi->err_mask |= AC_ERR_HSM;
1619 active_ehi->action |= ATA_EH_RESET;
1620 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1621 }
1622
1623 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1624 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1625 host_ehi->action |= ATA_EH_RESET;
1626 ata_ehi_push_desc(host_ehi, "host bus error");
1627 }
1628
1629 if (irq_stat & PORT_IRQ_IF_ERR) {
1630 if (fbs_need_dec)
1631 active_ehi->err_mask |= AC_ERR_DEV;
1632 else {
1633 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1634 host_ehi->action |= ATA_EH_RESET;
1635 }
1636
1637 ata_ehi_push_desc(host_ehi, "interface fatal error");
1638 }
1639
1640 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1641 ata_ehi_hotplugged(host_ehi);
1642 ata_ehi_push_desc(host_ehi, "%s",
1643 irq_stat & PORT_IRQ_CONNECT ?
1644 "connection status changed" : "PHY RDY changed");
1645 }
1646
1647 /* okay, let's hand over to EH */
1648
1649 if (irq_stat & PORT_IRQ_FREEZE)
1650 ata_port_freeze(ap);
1651 else if (fbs_need_dec) {
1652 ata_link_abort(link);
1653 ahci_fbs_dec_intr(ap);
1654 } else
1655 ata_port_abort(ap);
1656}
1657
5ca72c4f
AG		 1658static void ahci_handle_port_interrupt(struct ata_port *ap,
1659 void __iomem *port_mmio, u32 status)
365cfa1e 1660{
365cfa1e
AV		 1661 struct ata_eh_info *ehi = &ap->link.eh_info;
1662 struct ahci_port_priv *pp = ap->private_data;
1663 struct ahci_host_priv *hpriv = ap->host->private_data;
1664 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1665 u32 qc_active = 0;
365cfa1e
AV		 1666 int rc;
1667
365cfa1e
AV		 1668 /* ignore BAD_PMP while resetting */
1669 if (unlikely(resetting))
1670 status &= ~PORT_IRQ_BAD_PMP;
1671
6b7ae954
TH		 1672 /* if LPM is enabled, PHYRDY doesn't mean anything */
1673 if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
365cfa1e 1674 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1675 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1676 }
1677
1678 if (unlikely(status & PORT_IRQ_ERROR)) {
1679 ahci_error_intr(ap, status);
1680 return;
1681 }
1682
1683 if (status & PORT_IRQ_SDB_FIS) {
1684 /* If SNotification is available, leave notification
1685 * handling to sata_async_notification(). If not,
1686 * emulate it by snooping SDB FIS RX area.
1687 *
1688 * Snooping FIS RX area is probably cheaper than
1689 * poking SNotification but some constrollers which
1690 * implement SNotification, ICH9 for example, don't
1691 * store AN SDB FIS into receive area.
1692 */
1693 if (hpriv->cap & HOST_CAP_SNTF)
1694 sata_async_notification(ap);
1695 else {
1696 /* If the 'N' bit in word 0 of the FIS is set,
1697 * we just received asynchronous notification.
1698 * Tell libata about it.
1699 *
1700 * Lack of SNotification should not appear in
1701 * ahci 1.2, so the workaround is unnecessary
1702 * when FBS is enabled.
1703 */
1704 if (pp->fbs_enabled)
1705 WARN_ON_ONCE(1);
1706 else {
1707 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1708 u32 f0 = le32_to_cpu(f[0]);
1709 if (f0 & (1 << 15))
1710 sata_async_notification(ap);
1711 }
1712 }
1713 }
1714
1715 /* pp->active_link is not reliable once FBS is enabled, both
1716 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1717 * NCQ and non-NCQ commands may be in flight at the same time.
1718 */
1719 if (pp->fbs_enabled) {
1720 if (ap->qc_active) {
1721 qc_active = readl(port_mmio + PORT_SCR_ACT);
1722 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1723 }
1724 } else {
1725 /* pp->active_link is valid iff any command is in flight */
1726 if (ap->qc_active && pp->active_link->sactive)
1727 qc_active = readl(port_mmio + PORT_SCR_ACT);
1728 else
1729 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1730 }
1731
1732
1733 rc = ata_qc_complete_multiple(ap, qc_active);
1734
1735 /* while resetting, invalid completions are expected */
1736 if (unlikely(rc < 0 && !resetting)) {
1737 ehi->err_mask |= AC_ERR_HSM;
1738 ehi->action |= ATA_EH_RESET;
1739 ata_port_freeze(ap);
1740 }
1741}
1742
5ca72c4f
AG		 1743void ahci_port_intr(struct ata_port *ap)
1744{
1745 void __iomem *port_mmio = ahci_port_base(ap);
1746 u32 status;
1747
1748 status = readl(port_mmio + PORT_IRQ_STAT);
1749 writel(status, port_mmio + PORT_IRQ_STAT);
1750
1751 ahci_handle_port_interrupt(ap, port_mmio, status);
1752}
1753
1754irqreturn_t ahci_thread_fn(int irq, void *dev_instance)
1755{
1756 struct ata_port *ap = dev_instance;
1757 struct ahci_port_priv *pp = ap->private_data;
1758 void __iomem *port_mmio = ahci_port_base(ap);
1759 unsigned long flags;
1760 u32 status;
1761
1762 spin_lock_irqsave(&ap->host->lock, flags);
1763 status = pp->intr_status;
1764 if (status)
1765 pp->intr_status = 0;
1766 spin_unlock_irqrestore(&ap->host->lock, flags);
1767
1768 spin_lock_bh(ap->lock);
1769 ahci_handle_port_interrupt(ap, port_mmio, status);
1770 spin_unlock_bh(ap->lock);
1771
1772 return IRQ_HANDLED;
1773}
1774EXPORT_SYMBOL_GPL(ahci_thread_fn);
1775
1776void ahci_hw_port_interrupt(struct ata_port *ap)
1777{
1778 void __iomem *port_mmio = ahci_port_base(ap);
1779 struct ahci_port_priv *pp = ap->private_data;
1780 u32 status;
1781
1782 status = readl(port_mmio + PORT_IRQ_STAT);
1783 writel(status, port_mmio + PORT_IRQ_STAT);
1784
1785 pp->intr_status |= status;
1786}
1787
1788irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance)
1789{
1790 struct ata_port *ap_this = dev_instance;
1791 struct ahci_port_priv *pp = ap_this->private_data;
1792 struct ata_host *host = ap_this->host;
1793 struct ahci_host_priv *hpriv = host->private_data;
1794 void __iomem *mmio = hpriv->mmio;
1795 unsigned int i;
1796 u32 irq_stat, irq_masked;
1797
1798 VPRINTK("ENTER\n");
1799
1800 spin_lock(&host->lock);
1801
1802 irq_stat = readl(mmio + HOST_IRQ_STAT);
1803
1804 if (!irq_stat) {
1805 u32 status = pp->intr_status;
1806
1807 spin_unlock(&host->lock);
1808
1809 VPRINTK("EXIT\n");
1810
1811 return status ? IRQ_WAKE_THREAD : IRQ_NONE;
1812 }
1813
1814 irq_masked = irq_stat & hpriv->port_map;
1815
1816 for (i = 0; i < host->n_ports; i++) {
1817 struct ata_port *ap;
1818
1819 if (!(irq_masked & (1 << i)))
1820 continue;
1821
1822 ap = host->ports[i];
1823 if (ap) {
1824 ahci_hw_port_interrupt(ap);
1825 VPRINTK("port %u\n", i);
1826 } else {
1827 VPRINTK("port %u (no irq)\n", i);
1828 if (ata_ratelimit())
1829 dev_warn(host->dev,
1830 "interrupt on disabled port %u\n", i);
1831 }
1832 }
1833
1834 writel(irq_stat, mmio + HOST_IRQ_STAT);
1835
1836 spin_unlock(&host->lock);
1837
1838 VPRINTK("EXIT\n");
1839
1840 return IRQ_WAKE_THREAD;
1841}
1842EXPORT_SYMBOL_GPL(ahci_hw_interrupt);
1843
365cfa1e
AV		 1844irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1845{
1846 struct ata_host *host = dev_instance;
1847 struct ahci_host_priv *hpriv;
1848 unsigned int i, handled = 0;
1849 void __iomem *mmio;
1850 u32 irq_stat, irq_masked;
1851
1852 VPRINTK("ENTER\n");
1853
1854 hpriv = host->private_data;
1855 mmio = hpriv->mmio;
1856
1857 /* sigh. 0xffffffff is a valid return from h/w */
1858 irq_stat = readl(mmio + HOST_IRQ_STAT);
1859 if (!irq_stat)
1860 return IRQ_NONE;
1861
1862 irq_masked = irq_stat & hpriv->port_map;
1863
1864 spin_lock(&host->lock);
1865
1866 for (i = 0; i < host->n_ports; i++) {
1867 struct ata_port *ap;
1868
1869 if (!(irq_masked & (1 << i)))
1870 continue;
1871
1872 ap = host->ports[i];
1873 if (ap) {
1874 ahci_port_intr(ap);
1875 VPRINTK("port %u\n", i);
1876 } else {
1877 VPRINTK("port %u (no irq)\n", i);
1878 if (ata_ratelimit())
a44fec1f
JP		 1879 dev_warn(host->dev,
1880 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1881 }
1882
1883 handled = 1;
1884 }
1885
1886 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1887 * it should be cleared after all the port events are cleared;
1888 * otherwise, it will raise a spurious interrupt after each
1889 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1890 * information.
1891 *
1892 * Also, use the unmasked value to clear interrupt as spurious
1893 * pending event on a dummy port might cause screaming IRQ.
1894 */
1895 writel(irq_stat, mmio + HOST_IRQ_STAT);
1896
1897 spin_unlock(&host->lock);
1898
1899 VPRINTK("EXIT\n");
1900
1901 return IRQ_RETVAL(handled);
1902}
1903EXPORT_SYMBOL_GPL(ahci_interrupt);
1904
1905static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1906{
1907 struct ata_port *ap = qc->ap;
1908 void __iomem *port_mmio = ahci_port_base(ap);
1909 struct ahci_port_priv *pp = ap->private_data;
1910
1911 /* Keep track of the currently active link. It will be used
1912 * in completion path to determine whether NCQ phase is in
1913 * progress.
1914 */
1915 pp->active_link = qc->dev->link;
1916
1917 if (qc->tf.protocol == ATA_PROT_NCQ)
1918 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1919
1920 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1921 u32 fbs = readl(port_mmio + PORT_FBS);
1922 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1923 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1924 writel(fbs, port_mmio + PORT_FBS);
1925 pp->fbs_last_dev = qc->dev->link->pmp;
1926 }
1927
1928 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1929
1930 ahci_sw_activity(qc->dev->link);
1931
1932 return 0;
1933}
1934
1935static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1936{
1937 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 1938 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 1939
1940 if (pp->fbs_enabled)
6ad60195
TH		 1941 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1942
1943 /*
1944 * After a successful execution of an ATA PIO data-in command,
1945 * the device doesn't send D2H Reg FIS to update the TF and
1946 * the host should take TF and E_Status from the preceding PIO
1947 * Setup FIS.
1948 */
1949 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1950 !(qc->flags & ATA_QCFLAG_FAILED)) {
1951 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1952 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1953 } else
1954 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 1955
365cfa1e
AV		 1956 return true;
1957}
1958
1959static void ahci_freeze(struct ata_port *ap)
1960{
1961 void __iomem *port_mmio = ahci_port_base(ap);
1962
1963 /* turn IRQ off */
1964 writel(0, port_mmio + PORT_IRQ_MASK);
1965}
1966
1967static void ahci_thaw(struct ata_port *ap)
1968{
1969 struct ahci_host_priv *hpriv = ap->host->private_data;
1970 void __iomem *mmio = hpriv->mmio;
1971 void __iomem *port_mmio = ahci_port_base(ap);
1972 u32 tmp;
1973 struct ahci_port_priv *pp = ap->private_data;
1974
1975 /* clear IRQ */
1976 tmp = readl(port_mmio + PORT_IRQ_STAT);
1977 writel(tmp, port_mmio + PORT_IRQ_STAT);
1978 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1979
1980 /* turn IRQ back on */
1981 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1982}
1983
8b789d89 1984void ahci_error_handler(struct ata_port *ap)
365cfa1e
AV		 1985{
1986 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1987 /* restart engine */
1988 ahci_stop_engine(ap);
1989 ahci_start_engine(ap);
1990 }
1991
1992 sata_pmp_error_handler(ap);
0ee71952
TH		 1993
1994 if (!ata_dev_enabled(ap->link.device))
1995 ahci_stop_engine(ap);
365cfa1e 1996}
8b789d89 1997EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 1998
1999static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2000{
2001 struct ata_port *ap = qc->ap;
2002
2003 /* make DMA engine forget about the failed command */
2004 if (qc->flags & ATA_QCFLAG_FAILED)
2005 ahci_kick_engine(ap);
2006}
2007
65fe1f0f
SH		 2008static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2009{
2010 void __iomem *port_mmio = ahci_port_base(ap);
2011 struct ata_device *dev = ap->link.device;
2012 u32 devslp, dm, dito, mdat, deto;
2013 int rc;
2014 unsigned int err_mask;
2015
2016 devslp = readl(port_mmio + PORT_DEVSLP);
2017 if (!(devslp & PORT_DEVSLP_DSP)) {
2018 dev_err(ap->host->dev, "port does not support device sleep\n");
2019 return;
2020 }
2021
2022 /* disable device sleep */
2023 if (!sleep) {
2024 if (devslp & PORT_DEVSLP_ADSE) {
2025 writel(devslp & ~PORT_DEVSLP_ADSE,
2026 port_mmio + PORT_DEVSLP);
2027 err_mask = ata_dev_set_feature(dev,
2028 SETFEATURES_SATA_DISABLE,
2029 SATA_DEVSLP);
2030 if (err_mask && err_mask != AC_ERR_DEV)
2031 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2032 }
2033 return;
2034 }
2035
2036 /* device sleep was already enabled */
2037 if (devslp & PORT_DEVSLP_ADSE)
2038 return;
2039
2040 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2041 rc = ahci_stop_engine(ap);
2042 if (rc)
2043 return;
2044
2045 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2046 dito = devslp_idle_timeout / (dm + 1);
2047 if (dito > 0x3ff)
2048 dito = 0x3ff;
2049
2050 /* Use the nominal value 10 ms if the read MDAT is zero,
2051 * the nominal value of DETO is 20 ms.
2052 */
803739d2 2053 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2054 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2055 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2056 ATA_LOG_DEVSLP_MDAT_MASK;
2057 if (!mdat)
2058 mdat = 10;
803739d2 2059 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2060 if (!deto)
2061 deto = 20;
2062 } else {
2063 mdat = 10;
2064 deto = 20;
2065 }
2066
2067 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2068 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2069 (deto << PORT_DEVSLP_DETO_OFFSET) |
2070 PORT_DEVSLP_ADSE);
2071 writel(devslp, port_mmio + PORT_DEVSLP);
2072
2073 ahci_start_engine(ap);
2074
2075 /* enable device sleep feature for the drive */
2076 err_mask = ata_dev_set_feature(dev,
2077 SETFEATURES_SATA_ENABLE,
2078 SATA_DEVSLP);
2079 if (err_mask && err_mask != AC_ERR_DEV)
2080 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2081}
2082
365cfa1e
AV		 2083static void ahci_enable_fbs(struct ata_port *ap)
2084{
2085 struct ahci_port_priv *pp = ap->private_data;
2086 void __iomem *port_mmio = ahci_port_base(ap);
2087 u32 fbs;
2088 int rc;
2089
2090 if (!pp->fbs_supported)
2091 return;
2092
2093 fbs = readl(port_mmio + PORT_FBS);
2094 if (fbs & PORT_FBS_EN) {
2095 pp->fbs_enabled = true;
2096 pp->fbs_last_dev = -1; /* initialization */
2097 return;
2098 }
2099
2100 rc = ahci_stop_engine(ap);
2101 if (rc)
2102 return;
2103
2104 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2105 fbs = readl(port_mmio + PORT_FBS);
2106 if (fbs & PORT_FBS_EN) {
a44fec1f 2107 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2108 pp->fbs_enabled = true;
2109 pp->fbs_last_dev = -1; /* initialization */
2110 } else
a44fec1f 2111 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e
AV		 2112
2113 ahci_start_engine(ap);
2114}
2115
2116static void ahci_disable_fbs(struct ata_port *ap)
2117{
2118 struct ahci_port_priv *pp = ap->private_data;
2119 void __iomem *port_mmio = ahci_port_base(ap);
2120 u32 fbs;
2121 int rc;
2122
2123 if (!pp->fbs_supported)
2124 return;
2125
2126 fbs = readl(port_mmio + PORT_FBS);
2127 if ((fbs & PORT_FBS_EN) == 0) {
2128 pp->fbs_enabled = false;
2129 return;
2130 }
2131
2132 rc = ahci_stop_engine(ap);
2133 if (rc)
2134 return;
2135
2136 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2137 fbs = readl(port_mmio + PORT_FBS);
2138 if (fbs & PORT_FBS_EN)
a44fec1f 2139 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2140 else {
a44fec1f 2141 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2142 pp->fbs_enabled = false;
2143 }
2144
2145 ahci_start_engine(ap);
2146}
2147
2148static void ahci_pmp_attach(struct ata_port *ap)
2149{
2150 void __iomem *port_mmio = ahci_port_base(ap);
2151 struct ahci_port_priv *pp = ap->private_data;
2152 u32 cmd;
2153
2154 cmd = readl(port_mmio + PORT_CMD);
2155 cmd |= PORT_CMD_PMP;
2156 writel(cmd, port_mmio + PORT_CMD);
2157
2158 ahci_enable_fbs(ap);
2159
2160 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2161
2162 /*
2163 * We must not change the port interrupt mask register if the
2164 * port is marked frozen, the value in pp->intr_mask will be
2165 * restored later when the port is thawed.
2166 *
2167 * Note that during initialization, the port is marked as
2168 * frozen since the irq handler is not yet registered.
2169 */
2170 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2171 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2172}
2173
2174static void ahci_pmp_detach(struct ata_port *ap)
2175{
2176 void __iomem *port_mmio = ahci_port_base(ap);
2177 struct ahci_port_priv *pp = ap->private_data;
2178 u32 cmd;
2179
2180 ahci_disable_fbs(ap);
2181
2182 cmd = readl(port_mmio + PORT_CMD);
2183 cmd &= ~PORT_CMD_PMP;
2184 writel(cmd, port_mmio + PORT_CMD);
2185
2186 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2187
2188 /* see comment above in ahci_pmp_attach() */
2189 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2190 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2191}
2192
02cdfcf0 2193int ahci_port_resume(struct ata_port *ap)
365cfa1e
AV		 2194{
2195 ahci_power_up(ap);
2196 ahci_start_port(ap);
2197
2198 if (sata_pmp_attached(ap))
2199 ahci_pmp_attach(ap);
2200 else
2201 ahci_pmp_detach(ap);
2202
2203 return 0;
2204}
02cdfcf0 2205EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2206
2207#ifdef CONFIG_PM
2208static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2209{
2210 const char *emsg = NULL;
2211 int rc;
2212
2213 rc = ahci_deinit_port(ap, &emsg);
2214 if (rc == 0)
2215 ahci_power_down(ap);
2216 else {
a9a79dfe 2217 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2218 ata_port_freeze(ap);
365cfa1e
AV		 2219 }
2220
2221 return rc;
2222}
2223#endif
2224
2225static int ahci_port_start(struct ata_port *ap)
2226{
2227 struct ahci_host_priv *hpriv = ap->host->private_data;
2228 struct device *dev = ap->host->dev;
2229 struct ahci_port_priv *pp;
2230 void *mem;
2231 dma_addr_t mem_dma;
2232 size_t dma_sz, rx_fis_sz;
2233
2234 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2235 if (!pp)
2236 return -ENOMEM;
2237
b29900e6
AG		 2238 if (ap->host->n_ports > 1) {
2239 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2240 if (!pp->irq_desc) {
2241 devm_kfree(dev, pp);
2242 return -ENOMEM;
2243 }
2244 snprintf(pp->irq_desc, 8,
2245 "%s%d", dev_driver_string(dev), ap->port_no);
2246 }
2247
365cfa1e
AV		 2248 /* check FBS capability */
2249 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2250 void __iomem *port_mmio = ahci_port_base(ap);
2251 u32 cmd = readl(port_mmio + PORT_CMD);
2252 if (cmd & PORT_CMD_FBSCP)
2253 pp->fbs_supported = true;
5f173107 2254 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2255 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2256 ap->port_no);
5f173107
TH		 2257 pp->fbs_supported = true;
2258 } else
a44fec1f
JP		 2259 dev_warn(dev, "port %d is not capable of FBS\n",
2260 ap->port_no);
365cfa1e
AV		 2261 }
2262
2263 if (pp->fbs_supported) {
2264 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2265 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2266 } else {
2267 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2268 rx_fis_sz = AHCI_RX_FIS_SZ;
2269 }
2270
2271 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2272 if (!mem)
2273 return -ENOMEM;
2274 memset(mem, 0, dma_sz);
2275
2276 /*
2277 * First item in chunk of DMA memory: 32-slot command table,
2278 * 32 bytes each in size
2279 */
2280 pp->cmd_slot = mem;
2281 pp->cmd_slot_dma = mem_dma;
2282
2283 mem += AHCI_CMD_SLOT_SZ;
2284 mem_dma += AHCI_CMD_SLOT_SZ;
2285
2286 /*
2287 * Second item: Received-FIS area
2288 */
2289 pp->rx_fis = mem;
2290 pp->rx_fis_dma = mem_dma;
2291
2292 mem += rx_fis_sz;
2293 mem_dma += rx_fis_sz;
2294
2295 /*
2296 * Third item: data area for storing a single command
2297 * and its scatter-gather table
2298 */
2299 pp->cmd_tbl = mem;
2300 pp->cmd_tbl_dma = mem_dma;
2301
2302 /*
2303 * Save off initial list of interrupts to be enabled.
2304 * This could be changed later
2305 */
2306 pp->intr_mask = DEF_PORT_IRQ;
2307
5ca72c4f
AG		 2308 /*
2309 * Switch to per-port locking in case each port has its own MSI vector.
2310 */
2311 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) {
2312 spin_lock_init(&pp->lock);
2313 ap->lock = &pp->lock;
2314 }
2315
365cfa1e
AV		 2316 ap->private_data = pp;
2317
2318 /* engage engines, captain */
2319 return ahci_port_resume(ap);
2320}
2321
2322static void ahci_port_stop(struct ata_port *ap)
2323{
2324 const char *emsg = NULL;
2325 int rc;
2326
2327 /* de-initialize port */
2328 rc = ahci_deinit_port(ap, &emsg);
2329 if (rc)
a9a79dfe 2330 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
365cfa1e
AV		 2331}
2332
2333void ahci_print_info(struct ata_host *host, const char *scc_s)
2334{
2335 struct ahci_host_priv *hpriv = host->private_data;
2336 void __iomem *mmio = hpriv->mmio;
2337 u32 vers, cap, cap2, impl, speed;
2338 const char *speed_s;
2339
2340 vers = readl(mmio + HOST_VERSION);
2341 cap = hpriv->cap;
2342 cap2 = hpriv->cap2;
2343 impl = hpriv->port_map;
2344
2345 speed = (cap >> 20) & 0xf;
2346 if (speed == 1)
2347 speed_s = "1.5";
2348 else if (speed == 2)
2349 speed_s = "3";
2350 else if (speed == 3)
2351 speed_s = "6";
2352 else
2353 speed_s = "?";
2354
2355 dev_info(host->dev,
2356 "AHCI %02x%02x.%02x%02x "
2357 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2358 ,
2359
2360 (vers >> 24) & 0xff,
2361 (vers >> 16) & 0xff,
2362 (vers >> 8) & 0xff,
2363 vers & 0xff,
2364
2365 ((cap >> 8) & 0x1f) + 1,
2366 (cap & 0x1f) + 1,
2367 speed_s,
2368 impl,
2369 scc_s);
2370
2371 dev_info(host->dev,
2372 "flags: "
2373 "%s%s%s%s%s%s%s"
2374 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2375 "%s%s%s%s%s%s%s"
2376 "%s%s\n"
365cfa1e
AV		 2377 ,
2378
2379 cap & HOST_CAP_64 ? "64bit " : "",
2380 cap & HOST_CAP_NCQ ? "ncq " : "",
2381 cap & HOST_CAP_SNTF ? "sntf " : "",
2382 cap & HOST_CAP_MPS ? "ilck " : "",
2383 cap & HOST_CAP_SSS ? "stag " : "",
2384 cap & HOST_CAP_ALPM ? "pm " : "",
2385 cap & HOST_CAP_LED ? "led " : "",
2386 cap & HOST_CAP_CLO ? "clo " : "",
2387 cap & HOST_CAP_ONLY ? "only " : "",
2388 cap & HOST_CAP_PMP ? "pmp " : "",
2389 cap & HOST_CAP_FBS ? "fbs " : "",
2390 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2391 cap & HOST_CAP_SSC ? "slum " : "",
2392 cap & HOST_CAP_PART ? "part " : "",
2393 cap & HOST_CAP_CCC ? "ccc " : "",
2394 cap & HOST_CAP_EMS ? "ems " : "",
2395 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2396 cap2 & HOST_CAP2_DESO ? "deso " : "",
2397 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2398 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2399 cap2 & HOST_CAP2_APST ? "apst " : "",
2400 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2401 cap2 & HOST_CAP2_BOH ? "boh " : ""
2402 );
2403}
2404EXPORT_SYMBOL_GPL(ahci_print_info);
2405
2406void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2407 struct ata_port_info *pi)
2408{
2409 u8 messages;
2410 void __iomem *mmio = hpriv->mmio;
2411 u32 em_loc = readl(mmio + HOST_EM_LOC);
2412 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2413
2414 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2415 return;
2416
2417 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2418
008dbd61 2419 if (messages) {
365cfa1e
AV		 2420 /* store em_loc */
2421 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2422 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2423 hpriv->em_msg_type = messages;
365cfa1e
AV		 2424 pi->flags |= ATA_FLAG_EM;
2425 if (!(em_ctl & EM_CTL_ALHD))
2426 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2427 }
2428}
2429EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2430
2431MODULE_AUTHOR("Jeff Garzik");
2432MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2433MODULE_LICENSE("GPL");
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