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libahci: Allow drivers to override stop_engine
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
9bb9a39c 27 * as Documentation/driver-api/libata.rst
365cfa1e
AV		 28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e 37#include <linux/module.h>
365cfa1e
AV		 38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
d684a90d 46#include <linux/pci.h>
365cfa1e 47#include "ahci.h"
65fe1f0f 48#include "libata.h"
365cfa1e
AV		 49
50static int ahci_skip_host_reset;
51int ahci_ignore_sss;
52EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
6b7ae954
TH		 60static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
365cfa1e
AV		 62static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
65fe1f0f 79static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 80static void ahci_enable_fbs(struct ata_port *ap);
81static void ahci_disable_fbs(struct ata_port *ap);
82static void ahci_pmp_attach(struct ata_port *ap);
83static void ahci_pmp_detach(struct ata_port *ap);
84static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
345347c5
YHC		 86static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
365cfa1e
AV		 88static int ahci_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 91static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 92static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 93#ifdef CONFIG_PM
94static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
95#endif
96static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
97static ssize_t ahci_activity_store(struct ata_device *dev,
98 enum sw_activity val);
99static void ahci_init_sw_activity(struct ata_link *link);
100
101static ssize_t ahci_show_host_caps(struct device *dev,
102 struct device_attribute *attr, char *buf);
103static ssize_t ahci_show_host_cap2(struct device *dev,
104 struct device_attribute *attr, char *buf);
105static ssize_t ahci_show_host_version(struct device *dev,
106 struct device_attribute *attr, char *buf);
107static ssize_t ahci_show_port_cmd(struct device *dev,
108 struct device_attribute *attr, char *buf);
c0623166
HZ		 109static ssize_t ahci_read_em_buffer(struct device *dev,
110 struct device_attribute *attr, char *buf);
111static ssize_t ahci_store_em_buffer(struct device *dev,
112 struct device_attribute *attr,
113 const char *buf, size_t size);
6e5fe5b1
HR		 114static ssize_t ahci_show_em_supported(struct device *dev,
115 struct device_attribute *attr, char *buf);
f070d671 116static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
365cfa1e
AV		 117
118static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
119static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
120static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
121static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 122static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
123 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 124static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 125
fad16e7a 126struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 127 &dev_attr_link_power_management_policy,
128 &dev_attr_em_message_type,
129 &dev_attr_em_message,
130 &dev_attr_ahci_host_caps,
131 &dev_attr_ahci_host_cap2,
132 &dev_attr_ahci_host_version,
133 &dev_attr_ahci_port_cmd,
c0623166 134 &dev_attr_em_buffer,
6e5fe5b1 135 &dev_attr_em_message_supported,
365cfa1e
AV		 136 NULL
137};
fad16e7a 138EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 139
fad16e7a 140struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 141 &dev_attr_sw_activity,
142 &dev_attr_unload_heads,
84f95243 143 &dev_attr_ncq_prio_enable,
365cfa1e
AV		 144 NULL
145};
fad16e7a 146EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 147
148struct ata_port_operations ahci_ops = {
149 .inherits = &sata_pmp_port_ops,
150
151 .qc_defer = ahci_pmp_qc_defer,
152 .qc_prep = ahci_qc_prep,
153 .qc_issue = ahci_qc_issue,
154 .qc_fill_rtf = ahci_qc_fill_rtf,
155
156 .freeze = ahci_freeze,
157 .thaw = ahci_thaw,
158 .softreset = ahci_softreset,
159 .hardreset = ahci_hardreset,
160 .postreset = ahci_postreset,
161 .pmp_softreset = ahci_softreset,
162 .error_handler = ahci_error_handler,
163 .post_internal_cmd = ahci_post_internal_cmd,
164 .dev_config = ahci_dev_config,
165
166 .scr_read = ahci_scr_read,
167 .scr_write = ahci_scr_write,
168 .pmp_attach = ahci_pmp_attach,
169 .pmp_detach = ahci_pmp_detach,
170
6b7ae954 171 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 172 .em_show = ahci_led_show,
173 .em_store = ahci_led_store,
174 .sw_activity_show = ahci_activity_show,
175 .sw_activity_store = ahci_activity_store,
439d7a35 176 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 177#ifdef CONFIG_PM
178 .port_suspend = ahci_port_suspend,
179 .port_resume = ahci_port_resume,
180#endif
181 .port_start = ahci_port_start,
182 .port_stop = ahci_port_stop,
183};
184EXPORT_SYMBOL_GPL(ahci_ops);
185
345347c5
YHC		 186struct ata_port_operations ahci_pmp_retry_srst_ops = {
187 .inherits = &ahci_ops,
188 .softreset = ahci_pmp_retry_softreset,
189};
190EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
191
ed08d40c 192static bool ahci_em_messages __read_mostly = true;
365cfa1e 193EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 194module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 195/* add other LED protocol types when they become supported */
196MODULE_PARM_DESC(ahci_em_messages,
008dbd61 197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 198
ed08d40c
CL		 199/* device sleep idle timeout in ms */
200static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 201module_param(devslp_idle_timeout, int, 0644);
202MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
203
365cfa1e
AV		 204static void ahci_enable_ahci(void __iomem *mmio)
205{
206 int i;
207 u32 tmp;
208
209 /* turn on AHCI_EN */
210 tmp = readl(mmio + HOST_CTL);
211 if (tmp & HOST_AHCI_EN)
212 return;
213
214 /* Some controllers need AHCI_EN to be written multiple times.
215 * Try a few times before giving up.
216 */
217 for (i = 0; i < 5; i++) {
218 tmp |= HOST_AHCI_EN;
219 writel(tmp, mmio + HOST_CTL);
220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
221 if (tmp & HOST_AHCI_EN)
222 return;
223 msleep(10);
224 }
225
226 WARN_ON(1);
227}
228
bb03c640
MW		 229/**
230 * ahci_rpm_get_port - Make sure the port is powered on
231 * @ap: Port to power on
232 *
233 * Whenever there is need to access the AHCI host registers outside of
234 * normal execution paths, call this function to make sure the host is
235 * actually powered on.
236 */
237static int ahci_rpm_get_port(struct ata_port *ap)
238{
239 return pm_runtime_get_sync(ap->dev);
240}
241
242/**
243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
244 * @ap: Port to power down
245 *
246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
247 * if it has no more active users.
248 */
249static void ahci_rpm_put_port(struct ata_port *ap)
250{
251 pm_runtime_put(ap->dev);
252}
253
365cfa1e
AV		 254static ssize_t ahci_show_host_caps(struct device *dev,
255 struct device_attribute *attr, char *buf)
256{
257 struct Scsi_Host *shost = class_to_shost(dev);
258 struct ata_port *ap = ata_shost_to_port(shost);
259 struct ahci_host_priv *hpriv = ap->host->private_data;
260
261 return sprintf(buf, "%x\n", hpriv->cap);
262}
263
264static ssize_t ahci_show_host_cap2(struct device *dev,
265 struct device_attribute *attr, char *buf)
266{
267 struct Scsi_Host *shost = class_to_shost(dev);
268 struct ata_port *ap = ata_shost_to_port(shost);
269 struct ahci_host_priv *hpriv = ap->host->private_data;
270
271 return sprintf(buf, "%x\n", hpriv->cap2);
272}
273
274static ssize_t ahci_show_host_version(struct device *dev,
275 struct device_attribute *attr, char *buf)
276{
277 struct Scsi_Host *shost = class_to_shost(dev);
278 struct ata_port *ap = ata_shost_to_port(shost);
279 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 280
8ea909cb 281 return sprintf(buf, "%x\n", hpriv->version);
365cfa1e
AV		 282}
283
284static ssize_t ahci_show_port_cmd(struct device *dev,
285 struct device_attribute *attr, char *buf)
286{
287 struct Scsi_Host *shost = class_to_shost(dev);
288 struct ata_port *ap = ata_shost_to_port(shost);
289 void __iomem *port_mmio = ahci_port_base(ap);
bb03c640 290 ssize_t ret;
365cfa1e 291
bb03c640
MW		 292 ahci_rpm_get_port(ap);
293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
294 ahci_rpm_put_port(ap);
295
296 return ret;
365cfa1e
AV		 297}
298
c0623166
HZ		 299static ssize_t ahci_read_em_buffer(struct device *dev,
300 struct device_attribute *attr, char *buf)
301{
302 struct Scsi_Host *shost = class_to_shost(dev);
303 struct ata_port *ap = ata_shost_to_port(shost);
304 struct ahci_host_priv *hpriv = ap->host->private_data;
305 void __iomem *mmio = hpriv->mmio;
306 void __iomem *em_mmio = mmio + hpriv->em_loc;
307 u32 em_ctl, msg;
308 unsigned long flags;
309 size_t count;
310 int i;
311
bb03c640 312 ahci_rpm_get_port(ap);
c0623166
HZ		 313 spin_lock_irqsave(ap->lock, flags);
314
315 em_ctl = readl(mmio + HOST_EM_CTL);
316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
318 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 319 ahci_rpm_put_port(ap);
c0623166
HZ		 320 return -EINVAL;
321 }
322
323 if (!(em_ctl & EM_CTL_MR)) {
324 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 325 ahci_rpm_put_port(ap);
c0623166
HZ		 326 return -EAGAIN;
327 }
328
329 if (!(em_ctl & EM_CTL_SMB))
330 em_mmio += hpriv->em_buf_sz;
331
332 count = hpriv->em_buf_sz;
333
334 /* the count should not be larger than PAGE_SIZE */
335 if (count > PAGE_SIZE) {
336 if (printk_ratelimit())
a9a79dfe
JP		 337 ata_port_warn(ap,
338 "EM read buffer size too large: "
339 "buffer size %u, page size %lu\n",
340 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 341 count = PAGE_SIZE;
342 }
343
344 for (i = 0; i < count; i += 4) {
345 msg = readl(em_mmio + i);
346 buf[i] = msg & 0xff;
347 buf[i + 1] = (msg >> 8) & 0xff;
348 buf[i + 2] = (msg >> 16) & 0xff;
349 buf[i + 3] = (msg >> 24) & 0xff;
350 }
351
352 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 353 ahci_rpm_put_port(ap);
c0623166
HZ		 354
355 return i;
356}
357
358static ssize_t ahci_store_em_buffer(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf, size_t size)
361{
362 struct Scsi_Host *shost = class_to_shost(dev);
363 struct ata_port *ap = ata_shost_to_port(shost);
364 struct ahci_host_priv *hpriv = ap->host->private_data;
365 void __iomem *mmio = hpriv->mmio;
366 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 367 const unsigned char *msg_buf = buf;
c0623166
HZ		 368 u32 em_ctl, msg;
369 unsigned long flags;
370 int i;
371
372 /* check size validity */
373 if (!(ap->flags & ATA_FLAG_EM) ||
374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
375 size % 4 || size > hpriv->em_buf_sz)
376 return -EINVAL;
377
bb03c640 378 ahci_rpm_get_port(ap);
c0623166
HZ		 379 spin_lock_irqsave(ap->lock, flags);
380
381 em_ctl = readl(mmio + HOST_EM_CTL);
382 if (em_ctl & EM_CTL_TM) {
383 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 384 ahci_rpm_put_port(ap);
c0623166
HZ		 385 return -EBUSY;
386 }
387
388 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 389 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 391 writel(msg, em_mmio + i);
392 }
393
394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
395
396 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 397 ahci_rpm_put_port(ap);
c0623166
HZ		 398
399 return size;
400}
401
6e5fe5b1
HR		 402static ssize_t ahci_show_em_supported(struct device *dev,
403 struct device_attribute *attr, char *buf)
404{
405 struct Scsi_Host *shost = class_to_shost(dev);
406 struct ata_port *ap = ata_shost_to_port(shost);
407 struct ahci_host_priv *hpriv = ap->host->private_data;
408 void __iomem *mmio = hpriv->mmio;
409 u32 em_ctl;
410
bb03c640 411 ahci_rpm_get_port(ap);
6e5fe5b1 412 em_ctl = readl(mmio + HOST_EM_CTL);
bb03c640 413 ahci_rpm_put_port(ap);
6e5fe5b1
HR		 414
415 return sprintf(buf, "%s%s%s%s\n",
416 em_ctl & EM_CTL_LED ? "led " : "",
417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
418 em_ctl & EM_CTL_SES ? "ses-2 " : "",
419 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
420}
421
365cfa1e
AV		 422/**
423 * ahci_save_initial_config - Save and fixup initial config values
424 * @dev: target AHCI device
425 * @hpriv: host private area to store config values
365cfa1e
AV		 426 *
427 * Some registers containing configuration info might be setup by
428 * BIOS and might be cleared on reset. This function saves the
429 * initial values of those registers into @hpriv such that they
430 * can be restored after controller reset.
431 *
432 * If inconsistent, config values are fixed up by this function.
433 *
039ece38
HG		 434 * If it is not set already this function sets hpriv->start_engine to
435 * ahci_start_engine.
436 *
365cfa1e
AV		 437 * LOCKING:
438 * None.
439 */
725c7b57 440void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
365cfa1e
AV		 441{
442 void __iomem *mmio = hpriv->mmio;
443 u32 cap, cap2, vers, port_map;
444 int i;
445
446 /* make sure AHCI mode is enabled before accessing CAP */
447 ahci_enable_ahci(mmio);
448
449 /* Values prefixed with saved_ are written back to host after
450 * reset. Values without are used for driver operation.
451 */
452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
454
455 /* CAP2 register is only defined for AHCI 1.2 and later */
456 vers = readl(mmio + HOST_VERSION);
457 if ((vers >> 16) > 1 ||
458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
460 else
461 hpriv->saved_cap2 = cap2 = 0;
462
463 /* some chips have errata preventing 64bit use */
464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 466 cap &= ~HOST_CAP_64;
467 }
468
469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 471 cap &= ~HOST_CAP_NCQ;
472 }
473
474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 476 cap |= HOST_CAP_NCQ;
477 }
478
479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 481 cap &= ~HOST_CAP_PMP;
482 }
483
484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 485 dev_info(dev,
486 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 487 cap &= ~HOST_CAP_SNTF;
488 }
489
0cf4a7d6
JP		 490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
491 dev_info(dev,
492 "controller can't do DEVSLP, turning off\n");
493 cap2 &= ~HOST_CAP2_SDS;
494 cap2 &= ~HOST_CAP2_SADM;
495 }
496
5f173107 497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 499 cap |= HOST_CAP_FBS;
500 }
501
888d91a0
KW		 502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
504 cap &= ~HOST_CAP_FBS;
505 }
506
ef0da1bf
DB		 507 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
508 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
509 cap |= HOST_CAP_ALPM;
510 }
511
725c7b57 512 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
a44fec1f 513 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
725c7b57
AT		 514 port_map, hpriv->force_port_map);
515 port_map = hpriv->force_port_map;
2fd0f46c 516 hpriv->saved_port_map = port_map;
365cfa1e
AV		 517 }
518
725c7b57 519 if (hpriv->mask_port_map) {
a44fec1f
JP		 520 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
521 port_map,
725c7b57
AT		 522 port_map & hpriv->mask_port_map);
523 port_map &= hpriv->mask_port_map;
365cfa1e
AV		 524 }
525
526 /* cross check port_map and cap.n_ports */
527 if (port_map) {
528 int map_ports = 0;
529
530 for (i = 0; i < AHCI_MAX_PORTS; i++)
531 if (port_map & (1 << i))
532 map_ports++;
533
534 /* If PI has more ports than n_ports, whine, clear
535 * port_map and let it be generated from n_ports.
536 */
537 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 538 dev_warn(dev,
539 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
540 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 541 port_map = 0;
542 }
543 }
544
566d1827
TH		 545 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
546 if (!port_map && vers < 0x10300) {
365cfa1e 547 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 548 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 549
550 /* write the fixed up value to the PI register */
551 hpriv->saved_port_map = port_map;
552 }
553
554 /* record values to use during operation */
555 hpriv->cap = cap;
556 hpriv->cap2 = cap2;
8ea909cb 557 hpriv->version = readl(mmio + HOST_VERSION);
365cfa1e 558 hpriv->port_map = port_map;
039ece38
HG		 559
560 if (!hpriv->start_engine)
561 hpriv->start_engine = ahci_start_engine;
f070d671 562
76ff34cf
EW		 563 if (!hpriv->stop_engine)
564 hpriv->stop_engine = ahci_stop_engine;
565
f070d671 566 if (!hpriv->irq_handler)
d867b95f 567 hpriv->irq_handler = ahci_single_level_irq_intr;
365cfa1e
AV		 568}
569EXPORT_SYMBOL_GPL(ahci_save_initial_config);
570
571/**
572 * ahci_restore_initial_config - Restore initial config
573 * @host: target ATA host
574 *
575 * Restore initial config stored by ahci_save_initial_config().
576 *
577 * LOCKING:
578 * None.
579 */
580static void ahci_restore_initial_config(struct ata_host *host)
581{
582 struct ahci_host_priv *hpriv = host->private_data;
583 void __iomem *mmio = hpriv->mmio;
584
585 writel(hpriv->saved_cap, mmio + HOST_CAP);
586 if (hpriv->saved_cap2)
587 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
588 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
589 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
590}
591
592static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
593{
594 static const int offset[] = {
595 [SCR_STATUS] = PORT_SCR_STAT,
596 [SCR_CONTROL] = PORT_SCR_CTL,
597 [SCR_ERROR] = PORT_SCR_ERR,
598 [SCR_ACTIVE] = PORT_SCR_ACT,
599 [SCR_NOTIFICATION] = PORT_SCR_NTF,
600 };
601 struct ahci_host_priv *hpriv = ap->host->private_data;
602
603 if (sc_reg < ARRAY_SIZE(offset) &&
604 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
605 return offset[sc_reg];
606 return 0;
607}
608
609static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
610{
611 void __iomem *port_mmio = ahci_port_base(link->ap);
612 int offset = ahci_scr_offset(link->ap, sc_reg);
613
614 if (offset) {
615 *val = readl(port_mmio + offset);
616 return 0;
617 }
618 return -EINVAL;
619}
620
621static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
622{
623 void __iomem *port_mmio = ahci_port_base(link->ap);
624 int offset = ahci_scr_offset(link->ap, sc_reg);
625
626 if (offset) {
627 writel(val, port_mmio + offset);
628 return 0;
629 }
630 return -EINVAL;
631}
632
633void ahci_start_engine(struct ata_port *ap)
634{
635 void __iomem *port_mmio = ahci_port_base(ap);
636 u32 tmp;
637
638 /* start DMA */
639 tmp = readl(port_mmio + PORT_CMD);
640 tmp |= PORT_CMD_START;
641 writel(tmp, port_mmio + PORT_CMD);
642 readl(port_mmio + PORT_CMD); /* flush */
643}
644EXPORT_SYMBOL_GPL(ahci_start_engine);
645
646int ahci_stop_engine(struct ata_port *ap)
647{
648 void __iomem *port_mmio = ahci_port_base(ap);
fb329633 649 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 650 u32 tmp;
651
fb329633
DP		 652 /*
653 * On some controllers, stopping a port's DMA engine while the port
654 * is in ALPM state (partial or slumber) results in failures on
655 * subsequent DMA engine starts. For those controllers, put the
656 * port back in active state before stopping its DMA engine.
657 */
658 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
659 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
660 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
661 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
662 return -EIO;
663 }
664
365cfa1e
AV		 665 tmp = readl(port_mmio + PORT_CMD);
666
667 /* check if the HBA is idle */
668 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
669 return 0;
670
671 /* setting HBA to idle */
672 tmp &= ~PORT_CMD_START;
673 writel(tmp, port_mmio + PORT_CMD);
674
675 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 676 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 677 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
678 if (tmp & PORT_CMD_LIST_ON)
679 return -EIO;
680
681 return 0;
682}
683EXPORT_SYMBOL_GPL(ahci_stop_engine);
684
39e0ee99 685void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 686{
687 void __iomem *port_mmio = ahci_port_base(ap);
688 struct ahci_host_priv *hpriv = ap->host->private_data;
689 struct ahci_port_priv *pp = ap->private_data;
690 u32 tmp;
691
692 /* set FIS registers */
693 if (hpriv->cap & HOST_CAP_64)
694 writel((pp->cmd_slot_dma >> 16) >> 16,
695 port_mmio + PORT_LST_ADDR_HI);
696 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
697
698 if (hpriv->cap & HOST_CAP_64)
699 writel((pp->rx_fis_dma >> 16) >> 16,
700 port_mmio + PORT_FIS_ADDR_HI);
701 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
702
703 /* enable FIS reception */
704 tmp = readl(port_mmio + PORT_CMD);
705 tmp |= PORT_CMD_FIS_RX;
706 writel(tmp, port_mmio + PORT_CMD);
707
708 /* flush */
709 readl(port_mmio + PORT_CMD);
710}
39e0ee99 711EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 712
713static int ahci_stop_fis_rx(struct ata_port *ap)
714{
715 void __iomem *port_mmio = ahci_port_base(ap);
716 u32 tmp;
717
718 /* disable FIS reception */
719 tmp = readl(port_mmio + PORT_CMD);
720 tmp &= ~PORT_CMD_FIS_RX;
721 writel(tmp, port_mmio + PORT_CMD);
722
723 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 724 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 725 PORT_CMD_FIS_ON, 10, 1000);
726 if (tmp & PORT_CMD_FIS_ON)
727 return -EBUSY;
728
729 return 0;
730}
731
732static void ahci_power_up(struct ata_port *ap)
733{
734 struct ahci_host_priv *hpriv = ap->host->private_data;
735 void __iomem *port_mmio = ahci_port_base(ap);
736 u32 cmd;
737
738 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
739
740 /* spin up device */
741 if (hpriv->cap & HOST_CAP_SSS) {
742 cmd |= PORT_CMD_SPIN_UP;
743 writel(cmd, port_mmio + PORT_CMD);
744 }
745
746 /* wake up link */
747 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
748}
749
6b7ae954
TH		 750static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
751 unsigned int hints)
365cfa1e 752{
6b7ae954 753 struct ata_port *ap = link->ap;
365cfa1e 754 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 755 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 756 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 757
6b7ae954 758 if (policy != ATA_LPM_MAX_POWER) {
fb329633
DP		 759 /* wakeup flag only applies to the max power policy */
760 hints &= ~ATA_LPM_WAKE_ONLY;
761
365cfa1e 762 /*
6b7ae954
TH		 763 * Disable interrupts on Phy Ready. This keeps us from
764 * getting woken up due to spurious phy ready
765 * interrupts.
365cfa1e 766 */
6b7ae954
TH		 767 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
768 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
769
770 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 771 }
772
6b7ae954
TH		 773 if (hpriv->cap & HOST_CAP_ALPM) {
774 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 775
6b7ae954 776 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
fb329633
DP		 777 if (!(hints & ATA_LPM_WAKE_ONLY))
778 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
6b7ae954 779 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 780
6b7ae954
TH		 781 writel(cmd, port_mmio + PORT_CMD);
782 readl(port_mmio + PORT_CMD);
365cfa1e 783
6b7ae954 784 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 785 ata_msleep(ap, 10);
fb329633
DP		 786
787 if (hints & ATA_LPM_WAKE_ONLY)
788 return 0;
6b7ae954
TH		 789 } else {
790 cmd |= PORT_CMD_ALPE;
791 if (policy == ATA_LPM_MIN_POWER)
792 cmd |= PORT_CMD_ASP;
365cfa1e 793
6b7ae954
TH		 794 /* write out new cmd value */
795 writel(cmd, port_mmio + PORT_CMD);
796 }
797 }
365cfa1e 798
65fe1f0f
SH		 799 /* set aggressive device sleep */
800 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
801 (hpriv->cap2 & HOST_CAP2_SADM) &&
802 (link->device->flags & ATA_DFLAG_DEVSLP)) {
803 if (policy == ATA_LPM_MIN_POWER)
804 ahci_set_aggressive_devslp(ap, true);
805 else
806 ahci_set_aggressive_devslp(ap, false);
807 }
808
6b7ae954
TH		 809 if (policy == ATA_LPM_MAX_POWER) {
810 sata_link_scr_lpm(link, policy, false);
811
812 /* turn PHYRDY IRQ back on */
813 pp->intr_mask |= PORT_IRQ_PHYRDY;
814 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
815 }
365cfa1e 816
365cfa1e
AV		 817 return 0;
818}
819
820#ifdef CONFIG_PM
821static void ahci_power_down(struct ata_port *ap)
822{
823 struct ahci_host_priv *hpriv = ap->host->private_data;
824 void __iomem *port_mmio = ahci_port_base(ap);
825 u32 cmd, scontrol;
826
827 if (!(hpriv->cap & HOST_CAP_SSS))
828 return;
829
830 /* put device into listen mode, first set PxSCTL.DET to 0 */
831 scontrol = readl(port_mmio + PORT_SCR_CTL);
832 scontrol &= ~0xf;
833 writel(scontrol, port_mmio + PORT_SCR_CTL);
834
835 /* then set PxCMD.SUD to 0 */
836 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
837 cmd &= ~PORT_CMD_SPIN_UP;
838 writel(cmd, port_mmio + PORT_CMD);
839}
840#endif
841
842static void ahci_start_port(struct ata_port *ap)
843{
66583c9f 844 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 845 struct ahci_port_priv *pp = ap->private_data;
846 struct ata_link *link;
847 struct ahci_em_priv *emp;
848 ssize_t rc;
849 int i;
850
851 /* enable FIS reception */
852 ahci_start_fis_rx(ap);
853
66583c9f
BN		 854 /* enable DMA */
855 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 856 hpriv->start_engine(ap);
66583c9f 857
365cfa1e
AV		 858 /* turn on LEDs */
859 if (ap->flags & ATA_FLAG_EM) {
860 ata_for_each_link(link, ap, EDGE) {
861 emp = &pp->em_priv[link->pmp];
862
863 /* EM Transmit bit maybe busy during init */
864 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 865 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 866 emp->led_state,
867 4);
fa070ee6
LD		 868 /*
869 * If busy, give a breather but do not
870 * release EH ownership by using msleep()
871 * instead of ata_msleep(). EM Transmit
872 * bit is busy for the whole host and
873 * releasing ownership will cause other
874 * ports to fail the same way.
875 */
365cfa1e 876 if (rc == -EBUSY)
fa070ee6 877 msleep(1);
365cfa1e
AV		 878 else
879 break;
880 }
881 }
882 }
883
884 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
885 ata_for_each_link(link, ap, EDGE)
886 ahci_init_sw_activity(link);
887
888}
889
890static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
891{
892 int rc;
76ff34cf 893 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 894
895 /* disable DMA */
76ff34cf 896 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 897 if (rc) {
898 *emsg = "failed to stop engine";
899 return rc;
900 }
901
902 /* disable FIS reception */
903 rc = ahci_stop_fis_rx(ap);
904 if (rc) {
905 *emsg = "failed stop FIS RX";
906 return rc;
907 }
908
909 return 0;
910}
911
912int ahci_reset_controller(struct ata_host *host)
913{
914 struct ahci_host_priv *hpriv = host->private_data;
915 void __iomem *mmio = hpriv->mmio;
916 u32 tmp;
917
918 /* we must be in AHCI mode, before using anything
919 * AHCI-specific, such as HOST_RESET.
920 */
921 ahci_enable_ahci(mmio);
922
923 /* global controller reset */
924 if (!ahci_skip_host_reset) {
925 tmp = readl(mmio + HOST_CTL);
926 if ((tmp & HOST_RESET) == 0) {
927 writel(tmp | HOST_RESET, mmio + HOST_CTL);
928 readl(mmio + HOST_CTL); /* flush */
929 }
930
931 /*
932 * to perform host reset, OS should set HOST_RESET
933 * and poll until this bit is read to be "0".
934 * reset must complete within 1 second, or
935 * the hardware should be considered fried.
936 */
97750ceb 937 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 938 HOST_RESET, 10, 1000);
939
940 if (tmp & HOST_RESET) {
a44fec1f
JP		 941 dev_err(host->dev, "controller reset failed (0x%x)\n",
942 tmp);
365cfa1e
AV		 943 return -EIO;
944 }
945
946 /* turn on AHCI mode */
947 ahci_enable_ahci(mmio);
948
949 /* Some registers might be cleared on reset. Restore
950 * initial values.
951 */
7fab72f8
DB		 952 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
953 ahci_restore_initial_config(host);
365cfa1e 954 } else
a44fec1f 955 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 956
957 return 0;
958}
959EXPORT_SYMBOL_GPL(ahci_reset_controller);
960
961static void ahci_sw_activity(struct ata_link *link)
962{
963 struct ata_port *ap = link->ap;
964 struct ahci_port_priv *pp = ap->private_data;
965 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
966
967 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
968 return;
969
970 emp->activity++;
971 if (!timer_pending(&emp->timer))
972 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
973}
974
1843594c 975static void ahci_sw_activity_blink(struct timer_list *t)
365cfa1e 976{
1843594c
KC		 977 struct ahci_em_priv *emp = from_timer(emp, t, timer);
978 struct ata_link *link = emp->link;
365cfa1e 979 struct ata_port *ap = link->ap;
1843594c 980
365cfa1e
AV		 981 unsigned long led_message = emp->led_state;
982 u32 activity_led_state;
983 unsigned long flags;
984
985 led_message &= EM_MSG_LED_VALUE;
986 led_message |= ap->port_no | (link->pmp << 8);
987
988 /* check to see if we've had activity. If so,
989 * toggle state of LED and reset timer. If not,
990 * turn LED to desired idle state.
991 */
992 spin_lock_irqsave(ap->lock, flags);
993 if (emp->saved_activity != emp->activity) {
994 emp->saved_activity = emp->activity;
995 /* get the current LED state */
996 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
997
998 if (activity_led_state)
999 activity_led_state = 0;
1000 else
1001 activity_led_state = 1;
1002
1003 /* clear old state */
1004 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1005
1006 /* toggle state */
1007 led_message |= (activity_led_state << 16);
1008 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1009 } else {
1010 /* switch to idle */
1011 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1012 if (emp->blink_policy == BLINK_OFF)
1013 led_message |= (1 << 16);
1014 }
1015 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 1016 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 1017}
1018
1019static void ahci_init_sw_activity(struct ata_link *link)
1020{
1021 struct ata_port *ap = link->ap;
1022 struct ahci_port_priv *pp = ap->private_data;
1023 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1024
1025 /* init activity stats, setup timer */
1026 emp->saved_activity = emp->activity = 0;
1843594c
KC		 1027 emp->link = link;
1028 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
365cfa1e
AV		 1029
1030 /* check our blink policy and set flag for link if it's enabled */
1031 if (emp->blink_policy)
1032 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1033}
1034
1035int ahci_reset_em(struct ata_host *host)
1036{
1037 struct ahci_host_priv *hpriv = host->private_data;
1038 void __iomem *mmio = hpriv->mmio;
1039 u32 em_ctl;
1040
1041 em_ctl = readl(mmio + HOST_EM_CTL);
1042 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1043 return -EINVAL;
1044
1045 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1046 return 0;
1047}
1048EXPORT_SYMBOL_GPL(ahci_reset_em);
1049
1050static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1051 ssize_t size)
1052{
1053 struct ahci_host_priv *hpriv = ap->host->private_data;
1054 struct ahci_port_priv *pp = ap->private_data;
1055 void __iomem *mmio = hpriv->mmio;
1056 u32 em_ctl;
1057 u32 message[] = {0, 0};
1058 unsigned long flags;
1059 int pmp;
1060 struct ahci_em_priv *emp;
1061
1062 /* get the slot number from the message */
1063 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1064 if (pmp < EM_MAX_SLOTS)
1065 emp = &pp->em_priv[pmp];
1066 else
1067 return -EINVAL;
1068
bb03c640 1069 ahci_rpm_get_port(ap);
365cfa1e
AV		 1070 spin_lock_irqsave(ap->lock, flags);
1071
1072 /*
1073 * if we are still busy transmitting a previous message,
1074 * do not allow
1075 */
1076 em_ctl = readl(mmio + HOST_EM_CTL);
1077 if (em_ctl & EM_CTL_TM) {
1078 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 1079 ahci_rpm_put_port(ap);
365cfa1e
AV		 1080 return -EBUSY;
1081 }
1082
008dbd61
HZ		 1083 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1084 /*
1085 * create message header - this is all zero except for
1086 * the message size, which is 4 bytes.
1087 */
1088 message[0] |= (4 << 8);
365cfa1e 1089
008dbd61
HZ		 1090 /* ignore 0:4 of byte zero, fill in port info yourself */
1091 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1092
008dbd61
HZ		 1093 /* write message to EM_LOC */
1094 writel(message[0], mmio + hpriv->em_loc);
1095 writel(message[1], mmio + hpriv->em_loc+4);
1096
1097 /*
1098 * tell hardware to transmit the message
1099 */
1100 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1101 }
365cfa1e
AV		 1102
1103 /* save off new led state for port/slot */
1104 emp->led_state = state;
1105
365cfa1e 1106 spin_unlock_irqrestore(ap->lock, flags);
bb03c640
MW		 1107 ahci_rpm_put_port(ap);
1108
365cfa1e
AV		 1109 return size;
1110}
1111
1112static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1113{
1114 struct ahci_port_priv *pp = ap->private_data;
1115 struct ata_link *link;
1116 struct ahci_em_priv *emp;
1117 int rc = 0;
1118
1119 ata_for_each_link(link, ap, EDGE) {
1120 emp = &pp->em_priv[link->pmp];
1121 rc += sprintf(buf, "%lx\n", emp->led_state);
1122 }
1123 return rc;
1124}
1125
1126static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1127 size_t size)
1128{
b2a52b6a 1129 unsigned int state;
365cfa1e
AV		 1130 int pmp;
1131 struct ahci_port_priv *pp = ap->private_data;
1132 struct ahci_em_priv *emp;
1133
b2a52b6a
DY		 1134 if (kstrtouint(buf, 0, &state) < 0)
1135 return -EINVAL;
365cfa1e
AV		 1136
1137 /* get the slot number from the message */
1138 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1139 if (pmp < EM_MAX_SLOTS)
1140 emp = &pp->em_priv[pmp];
1141 else
1142 return -EINVAL;
1143
1144 /* mask off the activity bits if we are in sw_activity
1145 * mode, user should turn off sw_activity before setting
1146 * activity led through em_message
1147 */
1148 if (emp->blink_policy)
1149 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1150
439d7a35 1151 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1152}
1153
1154static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1155{
1156 struct ata_link *link = dev->link;
1157 struct ata_port *ap = link->ap;
1158 struct ahci_port_priv *pp = ap->private_data;
1159 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1160 u32 port_led_state = emp->led_state;
1161
1162 /* save the desired Activity LED behavior */
1163 if (val == OFF) {
1164 /* clear LFLAG */
1165 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1166
1167 /* set the LED to OFF */
1168 port_led_state &= EM_MSG_LED_VALUE_OFF;
1169 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1170 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1171 } else {
1172 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1173 if (val == BLINK_OFF) {
1174 /* set LED to ON for idle */
1175 port_led_state &= EM_MSG_LED_VALUE_OFF;
1176 port_led_state |= (ap->port_no | (link->pmp << 8));
1177 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1178 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1179 }
1180 }
1181 emp->blink_policy = val;
1182 return 0;
1183}
1184
1185static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1186{
1187 struct ata_link *link = dev->link;
1188 struct ata_port *ap = link->ap;
1189 struct ahci_port_priv *pp = ap->private_data;
1190 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1191
1192 /* display the saved value of activity behavior for this
1193 * disk.
1194 */
1195 return sprintf(buf, "%d\n", emp->blink_policy);
1196}
1197
1198static void ahci_port_init(struct device *dev, struct ata_port *ap,
1199 int port_no, void __iomem *mmio,
1200 void __iomem *port_mmio)
1201{
8a3e33cf 1202 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1203 const char *emsg = NULL;
1204 int rc;
1205 u32 tmp;
1206
1207 /* make sure port is not active */
1208 rc = ahci_deinit_port(ap, &emsg);
1209 if (rc)
1210 dev_warn(dev, "%s (%d)\n", emsg, rc);
1211
1212 /* clear SError */
1213 tmp = readl(port_mmio + PORT_SCR_ERR);
1214 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1215 writel(tmp, port_mmio + PORT_SCR_ERR);
1216
1217 /* clear port IRQ */
1218 tmp = readl(port_mmio + PORT_IRQ_STAT);
1219 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1220 if (tmp)
1221 writel(tmp, port_mmio + PORT_IRQ_STAT);
1222
1223 writel(1 << port_no, mmio + HOST_IRQ_STAT);
8a3e33cf
ML		 1224
1225 /* mark esata ports */
1226 tmp = readl(port_mmio + PORT_CMD);
dc8b4afc 1227 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
8a3e33cf 1228 ap->pflags |= ATA_PFLAG_EXTERNAL;
365cfa1e
AV		 1229}
1230
1231void ahci_init_controller(struct ata_host *host)
1232{
1233 struct ahci_host_priv *hpriv = host->private_data;
1234 void __iomem *mmio = hpriv->mmio;
1235 int i;
1236 void __iomem *port_mmio;
1237 u32 tmp;
1238
1239 for (i = 0; i < host->n_ports; i++) {
1240 struct ata_port *ap = host->ports[i];
1241
1242 port_mmio = ahci_port_base(ap);
1243 if (ata_port_is_dummy(ap))
1244 continue;
1245
1246 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1247 }
1248
1249 tmp = readl(mmio + HOST_CTL);
1250 VPRINTK("HOST_CTL 0x%x\n", tmp);
1251 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1252 tmp = readl(mmio + HOST_CTL);
1253 VPRINTK("HOST_CTL 0x%x\n", tmp);
1254}
1255EXPORT_SYMBOL_GPL(ahci_init_controller);
1256
1257static void ahci_dev_config(struct ata_device *dev)
1258{
1259 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1260
1261 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1262 dev->max_sectors = 255;
a9a79dfe
JP		 1263 ata_dev_info(dev,
1264 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1265 }
1266}
1267
bbb4ab43 1268unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1269{
1270 void __iomem *port_mmio = ahci_port_base(ap);
1271 struct ata_taskfile tf;
1272 u32 tmp;
1273
1274 tmp = readl(port_mmio + PORT_SIG);
1275 tf.lbah = (tmp >> 24) & 0xff;
1276 tf.lbam = (tmp >> 16) & 0xff;
1277 tf.lbal = (tmp >> 8) & 0xff;
1278 tf.nsect = (tmp) & 0xff;
1279
1280 return ata_dev_classify(&tf);
1281}
bbb4ab43 1282EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1283
02cdfcf0
DM		 1284void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1285 u32 opts)
365cfa1e
AV		 1286{
1287 dma_addr_t cmd_tbl_dma;
1288
1289 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1290
1291 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1292 pp->cmd_slot[tag].status = 0;
1293 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1294 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1295}
02cdfcf0 1296EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1297
1298int ahci_kick_engine(struct ata_port *ap)
1299{
1300 void __iomem *port_mmio = ahci_port_base(ap);
1301 struct ahci_host_priv *hpriv = ap->host->private_data;
1302 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1303 u32 tmp;
1304 int busy, rc;
1305
1306 /* stop engine */
76ff34cf 1307 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 1308 if (rc)
1309 goto out_restart;
1310
1311 /* need to do CLO?
1312 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1313 */
1314 busy = status & (ATA_BUSY | ATA_DRQ);
1315 if (!busy && !sata_pmp_attached(ap)) {
1316 rc = 0;
1317 goto out_restart;
1318 }
1319
1320 if (!(hpriv->cap & HOST_CAP_CLO)) {
1321 rc = -EOPNOTSUPP;
1322 goto out_restart;
1323 }
1324
1325 /* perform CLO */
1326 tmp = readl(port_mmio + PORT_CMD);
1327 tmp |= PORT_CMD_CLO;
1328 writel(tmp, port_mmio + PORT_CMD);
1329
1330 rc = 0;
97750ceb 1331 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1332 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1333 if (tmp & PORT_CMD_CLO)
1334 rc = -EIO;
1335
1336 /* restart engine */
1337 out_restart:
039ece38 1338 hpriv->start_engine(ap);
365cfa1e
AV		 1339 return rc;
1340}
1341EXPORT_SYMBOL_GPL(ahci_kick_engine);
1342
1343static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1344 struct ata_taskfile *tf, int is_cmd, u16 flags,
1345 unsigned long timeout_msec)
1346{
1347 const u32 cmd_fis_len = 5; /* five dwords */
1348 struct ahci_port_priv *pp = ap->private_data;
1349 void __iomem *port_mmio = ahci_port_base(ap);
1350 u8 *fis = pp->cmd_tbl;
1351 u32 tmp;
1352
1353 /* prep the command */
1354 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1355 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1356
023113d2
XY		 1357 /* set port value for softreset of Port Multiplier */
1358 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1359 tmp = readl(port_mmio + PORT_FBS);
1360 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1361 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1362 writel(tmp, port_mmio + PORT_FBS);
1363 pp->fbs_last_dev = pmp;
1364 }
1365
365cfa1e
AV		 1366 /* issue & wait */
1367 writel(1, port_mmio + PORT_CMD_ISSUE);
1368
1369 if (timeout_msec) {
97750ceb
TH		 1370 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1371 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1372 if (tmp & 0x1) {
1373 ahci_kick_engine(ap);
1374 return -EBUSY;
1375 }
1376 } else
1377 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1378
1379 return 0;
1380}
1381
1382int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1383 int pmp, unsigned long deadline,
1384 int (*check_ready)(struct ata_link *link))
1385{
1386 struct ata_port *ap = link->ap;
1387 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1388 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1389 const char *reason = NULL;
1390 unsigned long now, msecs;
1391 struct ata_taskfile tf;
89dafa20 1392 bool fbs_disabled = false;
365cfa1e
AV		 1393 int rc;
1394
1395 DPRINTK("ENTER\n");
1396
1397 /* prepare for SRST (AHCI-1.1 10.4.1) */
1398 rc = ahci_kick_engine(ap);
1399 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1400 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1401
89dafa20 1402 /*
1403 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1404 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1405 * that is attached to port multiplier.
1406 */
1407 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1408 ahci_disable_fbs(ap);
1409 fbs_disabled = true;
1410 }
1411
365cfa1e
AV		 1412 ata_tf_init(link->device, &tf);
1413
08fc4756 1414 /* issue the first H2D Register FIS */
365cfa1e
AV		 1415 msecs = 0;
1416 now = jiffies;
f1f5a807 1417 if (time_after(deadline, now))
365cfa1e
AV		 1418 msecs = jiffies_to_msecs(deadline - now);
1419
1420 tf.ctl |= ATA_SRST;
1421 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1422 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1423 rc = -EIO;
1424 reason = "1st FIS failed";
1425 goto fail;
1426 }
1427
1428 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1429 ata_msleep(ap, 1);
365cfa1e 1430
08fc4756 1431 /* issue the second H2D Register FIS */
365cfa1e
AV		 1432 tf.ctl &= ~ATA_SRST;
1433 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1434
1435 /* wait for link to become ready */
1436 rc = ata_wait_after_reset(link, deadline, check_ready);
1437 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1438 /*
1439 * Workaround for cases where link online status can't
1440 * be trusted. Treat device readiness timeout as link
1441 * offline.
1442 */
a9a79dfe 1443 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1444 *class = ATA_DEV_NONE;
1445 } else if (rc) {
1446 /* link occupied, -ENODEV too is an error */
1447 reason = "device not ready";
1448 goto fail;
1449 } else
1450 *class = ahci_dev_classify(ap);
1451
89dafa20 1452 /* re-enable FBS if disabled before */
1453 if (fbs_disabled)
1454 ahci_enable_fbs(ap);
1455
365cfa1e
AV		 1456 DPRINTK("EXIT, class=%u\n", *class);
1457 return 0;
1458
1459 fail:
a9a79dfe 1460 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1461 return rc;
1462}
1463
1464int ahci_check_ready(struct ata_link *link)
1465{
1466 void __iomem *port_mmio = ahci_port_base(link->ap);
1467 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1468
1469 return ata_check_ready(status);
1470}
1471EXPORT_SYMBOL_GPL(ahci_check_ready);
1472
1473static int ahci_softreset(struct ata_link *link, unsigned int *class,
1474 unsigned long deadline)
1475{
1476 int pmp = sata_srst_pmp(link);
1477
1478 DPRINTK("ENTER\n");
1479
1480 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1481}
1482EXPORT_SYMBOL_GPL(ahci_do_softreset);
1483
345347c5
YHC		 1484static int ahci_bad_pmp_check_ready(struct ata_link *link)
1485{
1486 void __iomem *port_mmio = ahci_port_base(link->ap);
1487 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1488 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1489
1490 /*
1491 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1492 * which can save timeout delay.
1493 */
1494 if (irq_status & PORT_IRQ_BAD_PMP)
1495 return -EIO;
1496
1497 return ata_check_ready(status);
1498}
1499
35186d05
DY		 1500static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1501 unsigned long deadline)
345347c5
YHC		 1502{
1503 struct ata_port *ap = link->ap;
1504 void __iomem *port_mmio = ahci_port_base(ap);
1505 int pmp = sata_srst_pmp(link);
1506 int rc;
1507 u32 irq_sts;
1508
1509 DPRINTK("ENTER\n");
1510
1511 rc = ahci_do_softreset(link, class, pmp, deadline,
1512 ahci_bad_pmp_check_ready);
1513
1514 /*
1515 * Soft reset fails with IPMS set when PMP is enabled but
1516 * SATA HDD/ODD is connected to SATA port, do soft reset
1517 * again to port 0.
1518 */
1519 if (rc == -EIO) {
1520 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1521 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1522 ata_link_warn(link,
345347c5
YHC		 1523 "applying PMP SRST workaround "
1524 "and retrying\n");
1525 rc = ahci_do_softreset(link, class, 0, deadline,
1526 ahci_check_ready);
1527 }
1528 }
1529
1530 return rc;
1531}
1532
d436501e
BG		 1533int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1534 unsigned long deadline, bool *online)
365cfa1e
AV		 1535{
1536 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1537 struct ata_port *ap = link->ap;
1538 struct ahci_port_priv *pp = ap->private_data;
039ece38 1539 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1540 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1541 struct ata_taskfile tf;
365cfa1e
AV		 1542 int rc;
1543
1544 DPRINTK("ENTER\n");
1545
76ff34cf 1546 hpriv->stop_engine(ap);
365cfa1e
AV		 1547
1548 /* clear D2H reception area to properly wait for D2H FIS */
1549 ata_tf_init(link->device, &tf);
9bbb1b0e 1550 tf.command = ATA_BUSY;
365cfa1e
AV		 1551 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1552
d436501e 1553 rc = sata_link_hardreset(link, timing, deadline, online,
365cfa1e
AV		 1554 ahci_check_ready);
1555
039ece38 1556 hpriv->start_engine(ap);
365cfa1e 1557
d436501e 1558 if (*online)
365cfa1e
AV		 1559 *class = ahci_dev_classify(ap);
1560
1561 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1562 return rc;
1563}
d436501e
BG		 1564EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1565
1566static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1567 unsigned long deadline)
1568{
1569 bool online;
1570
1571 return ahci_do_hardreset(link, class, deadline, &online);
1572}
365cfa1e
AV		 1573
1574static void ahci_postreset(struct ata_link *link, unsigned int *class)
1575{
1576 struct ata_port *ap = link->ap;
1577 void __iomem *port_mmio = ahci_port_base(ap);
1578 u32 new_tmp, tmp;
1579
1580 ata_std_postreset(link, class);
1581
1582 /* Make sure port's ATAPI bit is set appropriately */
1583 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1584 if (*class == ATA_DEV_ATAPI)
1585 new_tmp |= PORT_CMD_ATAPI;
1586 else
1587 new_tmp &= ~PORT_CMD_ATAPI;
1588 if (new_tmp != tmp) {
1589 writel(new_tmp, port_mmio + PORT_CMD);
1590 readl(port_mmio + PORT_CMD); /* flush */
1591 }
1592}
1593
1594static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1595{
1596 struct scatterlist *sg;
1597 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1598 unsigned int si;
1599
1600 VPRINTK("ENTER\n");
1601
1602 /*
1603 * Next, the S/G list.
1604 */
1605 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1606 dma_addr_t addr = sg_dma_address(sg);
1607 u32 sg_len = sg_dma_len(sg);
1608
1609 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1610 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1611 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1612 }
1613
1614 return si;
1615}
1616
1617static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1618{
1619 struct ata_port *ap = qc->ap;
1620 struct ahci_port_priv *pp = ap->private_data;
1621
1622 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1623 return ata_std_qc_defer(qc);
1624 else
1625 return sata_pmp_qc_defer_cmd_switch(qc);
1626}
1627
1628static void ahci_qc_prep(struct ata_queued_cmd *qc)
1629{
1630 struct ata_port *ap = qc->ap;
1631 struct ahci_port_priv *pp = ap->private_data;
1632 int is_atapi = ata_is_atapi(qc->tf.protocol);
1633 void *cmd_tbl;
1634 u32 opts;
1635 const u32 cmd_fis_len = 5; /* five dwords */
1636 unsigned int n_elem;
1637
1638 /*
1639 * Fill in command table information. First, the header,
1640 * a SATA Register - Host to Device command FIS.
1641 */
1642 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1643
1644 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1645 if (is_atapi) {
1646 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1647 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1648 }
1649
1650 n_elem = 0;
1651 if (qc->flags & ATA_QCFLAG_DMAMAP)
1652 n_elem = ahci_fill_sg(qc, cmd_tbl);
1653
1654 /*
1655 * Fill in command slot information.
1656 */
1657 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1658 if (qc->tf.flags & ATA_TFLAG_WRITE)
1659 opts |= AHCI_CMD_WRITE;
1660 if (is_atapi)
1661 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1662
1663 ahci_fill_cmd_slot(pp, qc->tag, opts);
1664}
1665
1666static void ahci_fbs_dec_intr(struct ata_port *ap)
1667{
1668 struct ahci_port_priv *pp = ap->private_data;
1669 void __iomem *port_mmio = ahci_port_base(ap);
1670 u32 fbs = readl(port_mmio + PORT_FBS);
1671 int retries = 3;
1672
1673 DPRINTK("ENTER\n");
1674 BUG_ON(!pp->fbs_enabled);
1675
1676 /* time to wait for DEC is not specified by AHCI spec,
1677 * add a retry loop for safety.
1678 */
1679 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1680 fbs = readl(port_mmio + PORT_FBS);
1681 while ((fbs & PORT_FBS_DEC) && retries--) {
1682 udelay(1);
1683 fbs = readl(port_mmio + PORT_FBS);
1684 }
1685
1686 if (fbs & PORT_FBS_DEC)
a44fec1f 1687 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1688}
1689
1690static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1691{
1692 struct ahci_host_priv *hpriv = ap->host->private_data;
1693 struct ahci_port_priv *pp = ap->private_data;
1694 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1695 struct ata_link *link = NULL;
1696 struct ata_queued_cmd *active_qc;
1697 struct ata_eh_info *active_ehi;
1698 bool fbs_need_dec = false;
1699 u32 serror;
1700
1701 /* determine active link with error */
1702 if (pp->fbs_enabled) {
1703 void __iomem *port_mmio = ahci_port_base(ap);
1704 u32 fbs = readl(port_mmio + PORT_FBS);
1705 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1706
912b9ac6 1707 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1708 link = &ap->pmp_link[pmp];
1709 fbs_need_dec = true;
1710 }
1711
1712 } else
1713 ata_for_each_link(link, ap, EDGE)
1714 if (ata_link_active(link))
1715 break;
1716
1717 if (!link)
1718 link = &ap->link;
1719
1720 active_qc = ata_qc_from_tag(ap, link->active_tag);
1721 active_ehi = &link->eh_info;
1722
1723 /* record irq stat */
1724 ata_ehi_clear_desc(host_ehi);
1725 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1726
1727 /* AHCI needs SError cleared; otherwise, it might lock up */
1728 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1729 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1730 host_ehi->serror |= serror;
1731
1732 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1733 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1734 irq_stat &= ~PORT_IRQ_IF_ERR;
1735
1736 if (irq_stat & PORT_IRQ_TF_ERR) {
1737 /* If qc is active, charge it; otherwise, the active
1738 * link. There's no active qc on NCQ errors. It will
1739 * be determined by EH by reading log page 10h.
1740 */
1741 if (active_qc)
1742 active_qc->err_mask |= AC_ERR_DEV;
1743 else
1744 active_ehi->err_mask |= AC_ERR_DEV;
1745
1746 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1747 host_ehi->serror &= ~SERR_INTERNAL;
1748 }
1749
1750 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1751 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1752
1753 active_ehi->err_mask |= AC_ERR_HSM;
1754 active_ehi->action |= ATA_EH_RESET;
1755 ata_ehi_push_desc(active_ehi,
1756 "unknown FIS %08x %08x %08x %08x" ,
1757 unk[0], unk[1], unk[2], unk[3]);
1758 }
1759
1760 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1761 active_ehi->err_mask |= AC_ERR_HSM;
1762 active_ehi->action |= ATA_EH_RESET;
1763 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1764 }
1765
1766 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1767 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1768 host_ehi->action |= ATA_EH_RESET;
1769 ata_ehi_push_desc(host_ehi, "host bus error");
1770 }
1771
1772 if (irq_stat & PORT_IRQ_IF_ERR) {
1773 if (fbs_need_dec)
1774 active_ehi->err_mask |= AC_ERR_DEV;
1775 else {
1776 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1777 host_ehi->action |= ATA_EH_RESET;
1778 }
1779
1780 ata_ehi_push_desc(host_ehi, "interface fatal error");
1781 }
1782
1783 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1784 ata_ehi_hotplugged(host_ehi);
1785 ata_ehi_push_desc(host_ehi, "%s",
1786 irq_stat & PORT_IRQ_CONNECT ?
1787 "connection status changed" : "PHY RDY changed");
1788 }
1789
1790 /* okay, let's hand over to EH */
1791
1792 if (irq_stat & PORT_IRQ_FREEZE)
1793 ata_port_freeze(ap);
1794 else if (fbs_need_dec) {
1795 ata_link_abort(link);
1796 ahci_fbs_dec_intr(ap);
1797 } else
1798 ata_port_abort(ap);
1799}
1800
5ca72c4f
AG		 1801static void ahci_handle_port_interrupt(struct ata_port *ap,
1802 void __iomem *port_mmio, u32 status)
365cfa1e 1803{
365cfa1e
AV		 1804 struct ata_eh_info *ehi = &ap->link.eh_info;
1805 struct ahci_port_priv *pp = ap->private_data;
1806 struct ahci_host_priv *hpriv = ap->host->private_data;
1807 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1808 u32 qc_active = 0;
365cfa1e
AV		 1809 int rc;
1810
365cfa1e
AV		 1811 /* ignore BAD_PMP while resetting */
1812 if (unlikely(resetting))
1813 status &= ~PORT_IRQ_BAD_PMP;
1814
8393b811 1815 if (sata_lpm_ignore_phy_events(&ap->link)) {
365cfa1e 1816 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1817 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1818 }
1819
1820 if (unlikely(status & PORT_IRQ_ERROR)) {
1821 ahci_error_intr(ap, status);
1822 return;
1823 }
1824
1825 if (status & PORT_IRQ_SDB_FIS) {
1826 /* If SNotification is available, leave notification
1827 * handling to sata_async_notification(). If not,
1828 * emulate it by snooping SDB FIS RX area.
1829 *
1830 * Snooping FIS RX area is probably cheaper than
1831 * poking SNotification but some constrollers which
1832 * implement SNotification, ICH9 for example, don't
1833 * store AN SDB FIS into receive area.
1834 */
1835 if (hpriv->cap & HOST_CAP_SNTF)
1836 sata_async_notification(ap);
1837 else {
1838 /* If the 'N' bit in word 0 of the FIS is set,
1839 * we just received asynchronous notification.
1840 * Tell libata about it.
1841 *
1842 * Lack of SNotification should not appear in
1843 * ahci 1.2, so the workaround is unnecessary
1844 * when FBS is enabled.
1845 */
1846 if (pp->fbs_enabled)
1847 WARN_ON_ONCE(1);
1848 else {
1849 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1850 u32 f0 = le32_to_cpu(f[0]);
1851 if (f0 & (1 << 15))
1852 sata_async_notification(ap);
1853 }
1854 }
1855 }
1856
1857 /* pp->active_link is not reliable once FBS is enabled, both
1858 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1859 * NCQ and non-NCQ commands may be in flight at the same time.
1860 */
1861 if (pp->fbs_enabled) {
1862 if (ap->qc_active) {
1863 qc_active = readl(port_mmio + PORT_SCR_ACT);
1864 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1865 }
1866 } else {
1867 /* pp->active_link is valid iff any command is in flight */
1868 if (ap->qc_active && pp->active_link->sactive)
1869 qc_active = readl(port_mmio + PORT_SCR_ACT);
1870 else
1871 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1872 }
1873
1874
1875 rc = ata_qc_complete_multiple(ap, qc_active);
1876
1877 /* while resetting, invalid completions are expected */
1878 if (unlikely(rc < 0 && !resetting)) {
1879 ehi->err_mask |= AC_ERR_HSM;
1880 ehi->action |= ATA_EH_RESET;
1881 ata_port_freeze(ap);
1882 }
1883}
1884
7865f83f 1885static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1886{
1887 void __iomem *port_mmio = ahci_port_base(ap);
1888 u32 status;
1889
1890 status = readl(port_mmio + PORT_IRQ_STAT);
1891 writel(status, port_mmio + PORT_IRQ_STAT);
1892
7865f83f 1893 ahci_handle_port_interrupt(ap, port_mmio, status);
5ca72c4f
AG		 1894}
1895
a6b7fb76 1896static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
5ca72c4f
AG		 1897{
1898 struct ata_port *ap = dev_instance;
5ca72c4f 1899 void __iomem *port_mmio = ahci_port_base(ap);
5ca72c4f
AG		 1900 u32 status;
1901
5ca72c4f
AG		 1902 VPRINTK("ENTER\n");
1903
227dfb4d
AG		 1904 status = readl(port_mmio + PORT_IRQ_STAT);
1905 writel(status, port_mmio + PORT_IRQ_STAT);
5ca72c4f 1906
a6b7fb76
DW		 1907 spin_lock(ap->lock);
1908 ahci_handle_port_interrupt(ap, port_mmio, status);
1909 spin_unlock(ap->lock);
5ca72c4f
AG		 1910
1911 VPRINTK("EXIT\n");
1912
a6b7fb76 1913 return IRQ_HANDLED;
5ca72c4f 1914}
5ca72c4f 1915
f070d671 1916u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
365cfa1e 1917{
365cfa1e 1918 unsigned int i, handled = 0;
03e83cbd 1919
365cfa1e
AV		 1920 for (i = 0; i < host->n_ports; i++) {
1921 struct ata_port *ap;
1922
1923 if (!(irq_masked & (1 << i)))
1924 continue;
1925
1926 ap = host->ports[i];
1927 if (ap) {
7865f83f 1928 ahci_port_intr(ap);
365cfa1e
AV		 1929 VPRINTK("port %u\n", i);
1930 } else {
1931 VPRINTK("port %u (no irq)\n", i);
1932 if (ata_ratelimit())
a44fec1f
JP		 1933 dev_warn(host->dev,
1934 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1935 }
1936
1937 handled = 1;
1938 }
1939
a129db89
ST		 1940 return handled;
1941}
f070d671 1942EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
a129db89
ST		 1943
1944static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1945{
1946 struct ata_host *host = dev_instance;
1947 struct ahci_host_priv *hpriv;
1948 unsigned int rc = 0;
1949 void __iomem *mmio;
1950 u32 irq_stat, irq_masked;
1951
1952 VPRINTK("ENTER\n");
1953
1954 hpriv = host->private_data;
1955 mmio = hpriv->mmio;
1956
1957 /* sigh. 0xffffffff is a valid return from h/w */
1958 irq_stat = readl(mmio + HOST_IRQ_STAT);
1959 if (!irq_stat)
1960 return IRQ_NONE;
1961
1962 irq_masked = irq_stat & hpriv->port_map;
1963
1964 spin_lock(&host->lock);
1965
1966 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e
AV		 1967
1968 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1969 * it should be cleared after all the port events are cleared;
1970 * otherwise, it will raise a spurious interrupt after each
1971 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1972 * information.
1973 *
1974 * Also, use the unmasked value to clear interrupt as spurious
1975 * pending event on a dummy port might cause screaming IRQ.
1976 */
1977 writel(irq_stat, mmio + HOST_IRQ_STAT);
1978
03e83cbd
TH		 1979 spin_unlock(&host->lock);
1980
365cfa1e
AV		 1981 VPRINTK("EXIT\n");
1982
a129db89 1983 return IRQ_RETVAL(rc);
365cfa1e 1984}
365cfa1e 1985
39e0ee99 1986unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1987{
1988 struct ata_port *ap = qc->ap;
1989 void __iomem *port_mmio = ahci_port_base(ap);
1990 struct ahci_port_priv *pp = ap->private_data;
1991
1992 /* Keep track of the currently active link. It will be used
1993 * in completion path to determine whether NCQ phase is in
1994 * progress.
1995 */
1996 pp->active_link = qc->dev->link;
1997
179b310a 1998 if (ata_is_ncq(qc->tf.protocol))
365cfa1e
AV		 1999 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2000
2001 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2002 u32 fbs = readl(port_mmio + PORT_FBS);
2003 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2004 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2005 writel(fbs, port_mmio + PORT_FBS);
2006 pp->fbs_last_dev = qc->dev->link->pmp;
2007 }
2008
2009 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2010
2011 ahci_sw_activity(qc->dev->link);
2012
2013 return 0;
2014}
39e0ee99 2015EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 2016
2017static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2018{
2019 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 2020 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 2021
2022 if (pp->fbs_enabled)
6ad60195
TH		 2023 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2024
2025 /*
2026 * After a successful execution of an ATA PIO data-in command,
2027 * the device doesn't send D2H Reg FIS to update the TF and
2028 * the host should take TF and E_Status from the preceding PIO
2029 * Setup FIS.
2030 */
2031 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2032 !(qc->flags & ATA_QCFLAG_FAILED)) {
2033 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2034 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2035 } else
2036 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 2037
365cfa1e
AV		 2038 return true;
2039}
2040
2041static void ahci_freeze(struct ata_port *ap)
2042{
2043 void __iomem *port_mmio = ahci_port_base(ap);
2044
2045 /* turn IRQ off */
2046 writel(0, port_mmio + PORT_IRQ_MASK);
2047}
2048
2049static void ahci_thaw(struct ata_port *ap)
2050{
2051 struct ahci_host_priv *hpriv = ap->host->private_data;
2052 void __iomem *mmio = hpriv->mmio;
2053 void __iomem *port_mmio = ahci_port_base(ap);
2054 u32 tmp;
2055 struct ahci_port_priv *pp = ap->private_data;
2056
2057 /* clear IRQ */
2058 tmp = readl(port_mmio + PORT_IRQ_STAT);
2059 writel(tmp, port_mmio + PORT_IRQ_STAT);
2060 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2061
2062 /* turn IRQ back on */
2063 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2064}
2065
8b789d89 2066void ahci_error_handler(struct ata_port *ap)
365cfa1e 2067{
039ece38
HG		 2068 struct ahci_host_priv *hpriv = ap->host->private_data;
2069
365cfa1e
AV		 2070 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2071 /* restart engine */
76ff34cf 2072 hpriv->stop_engine(ap);
039ece38 2073 hpriv->start_engine(ap);
365cfa1e
AV		 2074 }
2075
2076 sata_pmp_error_handler(ap);
0ee71952
TH		 2077
2078 if (!ata_dev_enabled(ap->link.device))
76ff34cf 2079 hpriv->stop_engine(ap);
365cfa1e 2080}
8b789d89 2081EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2082
2083static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2084{
2085 struct ata_port *ap = qc->ap;
2086
2087 /* make DMA engine forget about the failed command */
2088 if (qc->flags & ATA_QCFLAG_FAILED)
2089 ahci_kick_engine(ap);
2090}
2091
65fe1f0f
SH		 2092static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2093{
039ece38 2094 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2095 void __iomem *port_mmio = ahci_port_base(ap);
2096 struct ata_device *dev = ap->link.device;
2097 u32 devslp, dm, dito, mdat, deto;
2098 int rc;
2099 unsigned int err_mask;
2100
2101 devslp = readl(port_mmio + PORT_DEVSLP);
2102 if (!(devslp & PORT_DEVSLP_DSP)) {
95bbbe9a 2103 dev_info(ap->host->dev, "port does not support device sleep\n");
65fe1f0f
SH		 2104 return;
2105 }
2106
2107 /* disable device sleep */
2108 if (!sleep) {
2109 if (devslp & PORT_DEVSLP_ADSE) {
2110 writel(devslp & ~PORT_DEVSLP_ADSE,
2111 port_mmio + PORT_DEVSLP);
2112 err_mask = ata_dev_set_feature(dev,
2113 SETFEATURES_SATA_DISABLE,
2114 SATA_DEVSLP);
2115 if (err_mask && err_mask != AC_ERR_DEV)
2116 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2117 }
2118 return;
2119 }
2120
2121 /* device sleep was already enabled */
2122 if (devslp & PORT_DEVSLP_ADSE)
2123 return;
2124
2125 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
76ff34cf 2126 rc = hpriv->stop_engine(ap);
65fe1f0f
SH		 2127 if (rc)
2128 return;
2129
2130 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2131 dito = devslp_idle_timeout / (dm + 1);
2132 if (dito > 0x3ff)
2133 dito = 0x3ff;
2134
2135 /* Use the nominal value 10 ms if the read MDAT is zero,
2136 * the nominal value of DETO is 20 ms.
2137 */
803739d2 2138 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2139 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2140 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2141 ATA_LOG_DEVSLP_MDAT_MASK;
2142 if (!mdat)
2143 mdat = 10;
803739d2 2144 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2145 if (!deto)
2146 deto = 20;
2147 } else {
2148 mdat = 10;
2149 deto = 20;
2150 }
2151
2152 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2153 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2154 (deto << PORT_DEVSLP_DETO_OFFSET) |
2155 PORT_DEVSLP_ADSE);
2156 writel(devslp, port_mmio + PORT_DEVSLP);
2157
039ece38 2158 hpriv->start_engine(ap);
65fe1f0f
SH		 2159
2160 /* enable device sleep feature for the drive */
2161 err_mask = ata_dev_set_feature(dev,
2162 SETFEATURES_SATA_ENABLE,
2163 SATA_DEVSLP);
2164 if (err_mask && err_mask != AC_ERR_DEV)
2165 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2166}
2167
365cfa1e
AV		 2168static void ahci_enable_fbs(struct ata_port *ap)
2169{
039ece38 2170 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2171 struct ahci_port_priv *pp = ap->private_data;
2172 void __iomem *port_mmio = ahci_port_base(ap);
2173 u32 fbs;
2174 int rc;
2175
2176 if (!pp->fbs_supported)
2177 return;
2178
2179 fbs = readl(port_mmio + PORT_FBS);
2180 if (fbs & PORT_FBS_EN) {
2181 pp->fbs_enabled = true;
2182 pp->fbs_last_dev = -1; /* initialization */
2183 return;
2184 }
2185
76ff34cf 2186 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 2187 if (rc)
2188 return;
2189
2190 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2191 fbs = readl(port_mmio + PORT_FBS);
2192 if (fbs & PORT_FBS_EN) {
a44fec1f 2193 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2194 pp->fbs_enabled = true;
2195 pp->fbs_last_dev = -1; /* initialization */
2196 } else
a44fec1f 2197 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2198
039ece38 2199 hpriv->start_engine(ap);
365cfa1e
AV		 2200}
2201
2202static void ahci_disable_fbs(struct ata_port *ap)
2203{
039ece38 2204 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2205 struct ahci_port_priv *pp = ap->private_data;
2206 void __iomem *port_mmio = ahci_port_base(ap);
2207 u32 fbs;
2208 int rc;
2209
2210 if (!pp->fbs_supported)
2211 return;
2212
2213 fbs = readl(port_mmio + PORT_FBS);
2214 if ((fbs & PORT_FBS_EN) == 0) {
2215 pp->fbs_enabled = false;
2216 return;
2217 }
2218
76ff34cf 2219 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 2220 if (rc)
2221 return;
2222
2223 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2224 fbs = readl(port_mmio + PORT_FBS);
2225 if (fbs & PORT_FBS_EN)
a44fec1f 2226 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2227 else {
a44fec1f 2228 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2229 pp->fbs_enabled = false;
2230 }
2231
039ece38 2232 hpriv->start_engine(ap);
365cfa1e
AV		 2233}
2234
2235static void ahci_pmp_attach(struct ata_port *ap)
2236{
2237 void __iomem *port_mmio = ahci_port_base(ap);
2238 struct ahci_port_priv *pp = ap->private_data;
2239 u32 cmd;
2240
2241 cmd = readl(port_mmio + PORT_CMD);
2242 cmd |= PORT_CMD_PMP;
2243 writel(cmd, port_mmio + PORT_CMD);
2244
2245 ahci_enable_fbs(ap);
2246
2247 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2248
2249 /*
2250 * We must not change the port interrupt mask register if the
2251 * port is marked frozen, the value in pp->intr_mask will be
2252 * restored later when the port is thawed.
2253 *
2254 * Note that during initialization, the port is marked as
2255 * frozen since the irq handler is not yet registered.
2256 */
2257 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2258 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2259}
2260
2261static void ahci_pmp_detach(struct ata_port *ap)
2262{
2263 void __iomem *port_mmio = ahci_port_base(ap);
2264 struct ahci_port_priv *pp = ap->private_data;
2265 u32 cmd;
2266
2267 ahci_disable_fbs(ap);
2268
2269 cmd = readl(port_mmio + PORT_CMD);
2270 cmd &= ~PORT_CMD_PMP;
2271 writel(cmd, port_mmio + PORT_CMD);
2272
2273 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2274
2275 /* see comment above in ahci_pmp_attach() */
2276 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2277 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2278}
2279
02cdfcf0 2280int ahci_port_resume(struct ata_port *ap)
365cfa1e 2281{
bb03c640
MW		 2282 ahci_rpm_get_port(ap);
2283
365cfa1e
AV		 2284 ahci_power_up(ap);
2285 ahci_start_port(ap);
2286
2287 if (sata_pmp_attached(ap))
2288 ahci_pmp_attach(ap);
2289 else
2290 ahci_pmp_detach(ap);
2291
2292 return 0;
2293}
02cdfcf0 2294EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2295
2296#ifdef CONFIG_PM
2297static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2298{
2299 const char *emsg = NULL;
2300 int rc;
2301
2302 rc = ahci_deinit_port(ap, &emsg);
2303 if (rc == 0)
2304 ahci_power_down(ap);
2305 else {
a9a79dfe 2306 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2307 ata_port_freeze(ap);
365cfa1e
AV		 2308 }
2309
bb03c640 2310 ahci_rpm_put_port(ap);
365cfa1e
AV		 2311 return rc;
2312}
2313#endif
2314
2315static int ahci_port_start(struct ata_port *ap)
2316{
2317 struct ahci_host_priv *hpriv = ap->host->private_data;
2318 struct device *dev = ap->host->dev;
2319 struct ahci_port_priv *pp;
2320 void *mem;
2321 dma_addr_t mem_dma;
2322 size_t dma_sz, rx_fis_sz;
2323
2324 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2325 if (!pp)
2326 return -ENOMEM;
2327
b29900e6
AG		 2328 if (ap->host->n_ports > 1) {
2329 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2330 if (!pp->irq_desc) {
2331 devm_kfree(dev, pp);
2332 return -ENOMEM;
2333 }
2334 snprintf(pp->irq_desc, 8,
2335 "%s%d", dev_driver_string(dev), ap->port_no);
2336 }
2337
365cfa1e
AV		 2338 /* check FBS capability */
2339 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2340 void __iomem *port_mmio = ahci_port_base(ap);
2341 u32 cmd = readl(port_mmio + PORT_CMD);
2342 if (cmd & PORT_CMD_FBSCP)
2343 pp->fbs_supported = true;
5f173107 2344 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2345 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2346 ap->port_no);
5f173107
TH		 2347 pp->fbs_supported = true;
2348 } else
a44fec1f
JP		 2349 dev_warn(dev, "port %d is not capable of FBS\n",
2350 ap->port_no);
365cfa1e
AV		 2351 }
2352
2353 if (pp->fbs_supported) {
2354 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2355 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2356 } else {
2357 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2358 rx_fis_sz = AHCI_RX_FIS_SZ;
2359 }
2360
2361 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2362 if (!mem)
2363 return -ENOMEM;
2364 memset(mem, 0, dma_sz);
2365
2366 /*
2367 * First item in chunk of DMA memory: 32-slot command table,
2368 * 32 bytes each in size
2369 */
2370 pp->cmd_slot = mem;
2371 pp->cmd_slot_dma = mem_dma;
2372
2373 mem += AHCI_CMD_SLOT_SZ;
2374 mem_dma += AHCI_CMD_SLOT_SZ;
2375
2376 /*
2377 * Second item: Received-FIS area
2378 */
2379 pp->rx_fis = mem;
2380 pp->rx_fis_dma = mem_dma;
2381
2382 mem += rx_fis_sz;
2383 mem_dma += rx_fis_sz;
2384
2385 /*
2386 * Third item: data area for storing a single command
2387 * and its scatter-gather table
2388 */
2389 pp->cmd_tbl = mem;
2390 pp->cmd_tbl_dma = mem_dma;
2391
2392 /*
2393 * Save off initial list of interrupts to be enabled.
2394 * This could be changed later
2395 */
2396 pp->intr_mask = DEF_PORT_IRQ;
2397
7865f83f
TH		 2398 /*
2399 * Switch to per-port locking in case each port has its own MSI vector.
2400 */
0b9e2988 2401 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
7865f83f
TH		 2402 spin_lock_init(&pp->lock);
2403 ap->lock = &pp->lock;
2404 }
5ca72c4f 2405
365cfa1e
AV		 2406 ap->private_data = pp;
2407
2408 /* engage engines, captain */
2409 return ahci_port_resume(ap);
2410}
2411
2412static void ahci_port_stop(struct ata_port *ap)
2413{
2414 const char *emsg = NULL;
0516900a
PR		 2415 struct ahci_host_priv *hpriv = ap->host->private_data;
2416 void __iomem *host_mmio = hpriv->mmio;
365cfa1e
AV		 2417 int rc;
2418
2419 /* de-initialize port */
2420 rc = ahci_deinit_port(ap, &emsg);
2421 if (rc)
a9a79dfe 2422 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
0516900a
PR		 2423
2424 /*
2425 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2426 * re-enabling INTx.
2427 */
2428 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
365cfa1e
AV		 2429}
2430
2431void ahci_print_info(struct ata_host *host, const char *scc_s)
2432{
2433 struct ahci_host_priv *hpriv = host->private_data;
365cfa1e
AV		 2434 u32 vers, cap, cap2, impl, speed;
2435 const char *speed_s;
2436
8ea909cb 2437 vers = hpriv->version;
365cfa1e
AV		 2438 cap = hpriv->cap;
2439 cap2 = hpriv->cap2;
2440 impl = hpriv->port_map;
2441
2442 speed = (cap >> 20) & 0xf;
2443 if (speed == 1)
2444 speed_s = "1.5";
2445 else if (speed == 2)
2446 speed_s = "3";
2447 else if (speed == 3)
2448 speed_s = "6";
2449 else
2450 speed_s = "?";
2451
2452 dev_info(host->dev,
2453 "AHCI %02x%02x.%02x%02x "
2454 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2455 ,
2456
2457 (vers >> 24) & 0xff,
2458 (vers >> 16) & 0xff,
2459 (vers >> 8) & 0xff,
2460 vers & 0xff,
2461
2462 ((cap >> 8) & 0x1f) + 1,
2463 (cap & 0x1f) + 1,
2464 speed_s,
2465 impl,
2466 scc_s);
2467
2468 dev_info(host->dev,
2469 "flags: "
2470 "%s%s%s%s%s%s%s"
2471 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2472 "%s%s%s%s%s%s%s"
2473 "%s%s\n"
365cfa1e
AV		 2474 ,
2475
2476 cap & HOST_CAP_64 ? "64bit " : "",
2477 cap & HOST_CAP_NCQ ? "ncq " : "",
2478 cap & HOST_CAP_SNTF ? "sntf " : "",
2479 cap & HOST_CAP_MPS ? "ilck " : "",
2480 cap & HOST_CAP_SSS ? "stag " : "",
2481 cap & HOST_CAP_ALPM ? "pm " : "",
2482 cap & HOST_CAP_LED ? "led " : "",
2483 cap & HOST_CAP_CLO ? "clo " : "",
2484 cap & HOST_CAP_ONLY ? "only " : "",
2485 cap & HOST_CAP_PMP ? "pmp " : "",
2486 cap & HOST_CAP_FBS ? "fbs " : "",
2487 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2488 cap & HOST_CAP_SSC ? "slum " : "",
2489 cap & HOST_CAP_PART ? "part " : "",
2490 cap & HOST_CAP_CCC ? "ccc " : "",
2491 cap & HOST_CAP_EMS ? "ems " : "",
2492 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2493 cap2 & HOST_CAP2_DESO ? "deso " : "",
2494 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2495 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2496 cap2 & HOST_CAP2_APST ? "apst " : "",
2497 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2498 cap2 & HOST_CAP2_BOH ? "boh " : ""
2499 );
2500}
2501EXPORT_SYMBOL_GPL(ahci_print_info);
2502
2503void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2504 struct ata_port_info *pi)
2505{
2506 u8 messages;
2507 void __iomem *mmio = hpriv->mmio;
2508 u32 em_loc = readl(mmio + HOST_EM_LOC);
2509 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2510
2511 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2512 return;
2513
2514 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2515
008dbd61 2516 if (messages) {
365cfa1e
AV		 2517 /* store em_loc */
2518 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2519 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2520 hpriv->em_msg_type = messages;
365cfa1e
AV		 2521 pi->flags |= ATA_FLAG_EM;
2522 if (!(em_ctl & EM_CTL_ALHD))
2523 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2524 }
2525}
2526EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2527
d684a90d 2528static int ahci_host_activate_multi_irqs(struct ata_host *host,
d1028e2f 2529 struct scsi_host_template *sht)
1c62854f 2530{
d684a90d 2531 struct ahci_host_priv *hpriv = host->private_data;
1c62854f
AG		 2532 int i, rc;
2533
2534 rc = ata_host_start(host);
2535 if (rc)
2536 return rc;
21bfd1aa
RR		 2537 /*
2538 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2539 * allocated. That is one MSI per port, starting from @irq.
2540 */
1c62854f
AG		 2541 for (i = 0; i < host->n_ports; i++) {
2542 struct ahci_port_priv *pp = host->ports[i]->private_data;
0b9e2988 2543 int irq = hpriv->get_irq_vector(host, i);
1c62854f
AG		 2544
2545 /* Do not receive interrupts sent by dummy ports */
2546 if (!pp) {
9b4b3f6a 2547 disable_irq(irq);
1c62854f
AG		 2548 continue;
2549 }
2550
a6b7fb76
DW		 2551 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2552 0, pp->irq_desc, host->ports[i]);
2553
1c62854f 2554 if (rc)
0a142b26 2555 return rc;
d684a90d 2556 ata_port_desc(host->ports[i], "irq %d", irq);
0a142b26 2557 }
d684a90d 2558
0a142b26 2559 return ata_host_register(host, sht);
1c62854f 2560}
d1028e2f
AG		 2561
2562/**
2563 * ahci_host_activate - start AHCI host, request IRQs and register it
2564 * @host: target ATA host
d1028e2f
AG		 2565 * @sht: scsi_host_template to use when registering the host
2566 *
d1028e2f
AG		 2567 * LOCKING:
2568 * Inherited from calling layer (may sleep).
2569 *
2570 * RETURNS:
2571 * 0 on success, -errno otherwise.
2572 */
21bfd1aa 2573int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
d1028e2f
AG		 2574{
2575 struct ahci_host_priv *hpriv = host->private_data;
21bfd1aa 2576 int irq = hpriv->irq;
d1028e2f
AG		 2577 int rc;
2578
0b9e2988 2579 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
f070d671 2580 if (hpriv->irq_handler)
d991c872
SE		 2581 dev_warn(host->dev,
2582 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
0b9e2988
CH		 2583 if (!hpriv->get_irq_vector) {
2584 dev_err(host->dev,
2585 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2586 return -EIO;
2587 }
f070d671 2588
d684a90d 2589 rc = ahci_host_activate_multi_irqs(host, sht);
f070d671
ST		 2590 } else {
2591 rc = ata_host_activate(host, irq, hpriv->irq_handler,
7865f83f 2592 IRQF_SHARED, sht);
f070d671
ST		 2593 }
2594
2595
d1028e2f
AG		 2596 return rc;
2597}
1c62854f
AG		 2598EXPORT_SYMBOL_GPL(ahci_host_activate);
2599
365cfa1e
AV		 2600MODULE_AUTHOR("Jeff Garzik");
2601MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2602MODULE_LICENSE("GPL");
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