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libahci: Fix possible Spectre-v1 pmp indexing in ahci_led_store()
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
8c3d3d4b 4 * Maintained by: Tejun Heo <tj@kernel.org>
365cfa1e
AV		 5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
9bb9a39c 27 * as Documentation/driver-api/libata.rst
365cfa1e
AV		 28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
fbaf666b 36#include <linux/gfp.h>
365cfa1e 37#include <linux/module.h>
dec6104e 38#include <linux/nospec.h>
365cfa1e
AV		 39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/dma-mapping.h>
43#include <linux/device.h>
44#include <scsi/scsi_host.h>
45#include <scsi/scsi_cmnd.h>
46#include <linux/libata.h>
d684a90d 47#include <linux/pci.h>
365cfa1e 48#include "ahci.h"
65fe1f0f 49#include "libata.h"
365cfa1e
AV		 50
51static int ahci_skip_host_reset;
52int ahci_ignore_sss;
53EXPORT_SYMBOL_GPL(ahci_ignore_sss);
54
55module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
56MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
57
58module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
59MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
60
6b7ae954
TH		 61static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
62 unsigned hints);
365cfa1e
AV		 63static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
64static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
65 size_t size);
66static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
67 ssize_t size);
68
69
70
71static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
72static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
365cfa1e
AV		 73static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74static int ahci_port_start(struct ata_port *ap);
75static void ahci_port_stop(struct ata_port *ap);
76static void ahci_qc_prep(struct ata_queued_cmd *qc);
77static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78static void ahci_freeze(struct ata_port *ap);
79static void ahci_thaw(struct ata_port *ap);
65fe1f0f 80static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
365cfa1e
AV		 81static void ahci_enable_fbs(struct ata_port *ap);
82static void ahci_disable_fbs(struct ata_port *ap);
83static void ahci_pmp_attach(struct ata_port *ap);
84static void ahci_pmp_detach(struct ata_port *ap);
85static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
345347c5
YHC		 87static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
365cfa1e
AV		 89static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91static void ahci_postreset(struct ata_link *link, unsigned int *class);
365cfa1e 92static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
365cfa1e 93static void ahci_dev_config(struct ata_device *dev);
365cfa1e
AV		 94#ifdef CONFIG_PM
95static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96#endif
97static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100static void ahci_init_sw_activity(struct ata_link *link);
101
102static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
c0623166
HZ		 110static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
6e5fe5b1
HR		 115static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
f070d671 117static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
365cfa1e
AV		 118
119static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
c0623166
HZ		 123static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
6e5fe5b1 125static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
365cfa1e 126
fad16e7a 127struct device_attribute *ahci_shost_attrs[] = {
365cfa1e
AV		 128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
c0623166 135 &dev_attr_em_buffer,
6e5fe5b1 136 &dev_attr_em_message_supported,
365cfa1e
AV		 137 NULL
138};
fad16e7a 139EXPORT_SYMBOL_GPL(ahci_shost_attrs);
365cfa1e 140
fad16e7a 141struct device_attribute *ahci_sdev_attrs[] = {
365cfa1e
AV		 142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
84f95243 144 &dev_attr_ncq_prio_enable,
365cfa1e
AV		 145 NULL
146};
fad16e7a 147EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
365cfa1e
AV		 148
149struct ata_port_operations ahci_ops = {
150 .inherits = &sata_pmp_port_ops,
151
152 .qc_defer = ahci_pmp_qc_defer,
153 .qc_prep = ahci_qc_prep,
154 .qc_issue = ahci_qc_issue,
155 .qc_fill_rtf = ahci_qc_fill_rtf,
156
157 .freeze = ahci_freeze,
158 .thaw = ahci_thaw,
159 .softreset = ahci_softreset,
160 .hardreset = ahci_hardreset,
161 .postreset = ahci_postreset,
162 .pmp_softreset = ahci_softreset,
163 .error_handler = ahci_error_handler,
164 .post_internal_cmd = ahci_post_internal_cmd,
165 .dev_config = ahci_dev_config,
166
167 .scr_read = ahci_scr_read,
168 .scr_write = ahci_scr_write,
169 .pmp_attach = ahci_pmp_attach,
170 .pmp_detach = ahci_pmp_detach,
171
6b7ae954 172 .set_lpm = ahci_set_lpm,
365cfa1e
AV		 173 .em_show = ahci_led_show,
174 .em_store = ahci_led_store,
175 .sw_activity_show = ahci_activity_show,
176 .sw_activity_store = ahci_activity_store,
439d7a35 177 .transmit_led_message = ahci_transmit_led_message,
365cfa1e
AV		 178#ifdef CONFIG_PM
179 .port_suspend = ahci_port_suspend,
180 .port_resume = ahci_port_resume,
181#endif
182 .port_start = ahci_port_start,
183 .port_stop = ahci_port_stop,
184};
185EXPORT_SYMBOL_GPL(ahci_ops);
186
345347c5
YHC		 187struct ata_port_operations ahci_pmp_retry_srst_ops = {
188 .inherits = &ahci_ops,
189 .softreset = ahci_pmp_retry_softreset,
190};
191EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192
ed08d40c 193static bool ahci_em_messages __read_mostly = true;
365cfa1e 194EXPORT_SYMBOL_GPL(ahci_em_messages);
ed08d40c 195module_param(ahci_em_messages, bool, 0444);
365cfa1e
AV		 196/* add other LED protocol types when they become supported */
197MODULE_PARM_DESC(ahci_em_messages,
008dbd61 198 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
365cfa1e 199
ed08d40c
CL		 200/* device sleep idle timeout in ms */
201static int devslp_idle_timeout __read_mostly = 1000;
65fe1f0f
SH		 202module_param(devslp_idle_timeout, int, 0644);
203MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
204
365cfa1e
AV		 205static void ahci_enable_ahci(void __iomem *mmio)
206{
207 int i;
208 u32 tmp;
209
210 /* turn on AHCI_EN */
211 tmp = readl(mmio + HOST_CTL);
212 if (tmp & HOST_AHCI_EN)
213 return;
214
215 /* Some controllers need AHCI_EN to be written multiple times.
216 * Try a few times before giving up.
217 */
218 for (i = 0; i < 5; i++) {
219 tmp |= HOST_AHCI_EN;
220 writel(tmp, mmio + HOST_CTL);
221 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
222 if (tmp & HOST_AHCI_EN)
223 return;
224 msleep(10);
225 }
226
227 WARN_ON(1);
228}
229
bb03c640
MW		 230/**
231 * ahci_rpm_get_port - Make sure the port is powered on
232 * @ap: Port to power on
233 *
234 * Whenever there is need to access the AHCI host registers outside of
235 * normal execution paths, call this function to make sure the host is
236 * actually powered on.
237 */
238static int ahci_rpm_get_port(struct ata_port *ap)
239{
240 return pm_runtime_get_sync(ap->dev);
241}
242
243/**
244 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
245 * @ap: Port to power down
246 *
247 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
248 * if it has no more active users.
249 */
250static void ahci_rpm_put_port(struct ata_port *ap)
251{
252 pm_runtime_put(ap->dev);
253}
254
365cfa1e
AV		 255static ssize_t ahci_show_host_caps(struct device *dev,
256 struct device_attribute *attr, char *buf)
257{
258 struct Scsi_Host *shost = class_to_shost(dev);
259 struct ata_port *ap = ata_shost_to_port(shost);
260 struct ahci_host_priv *hpriv = ap->host->private_data;
261
262 return sprintf(buf, "%x\n", hpriv->cap);
263}
264
265static ssize_t ahci_show_host_cap2(struct device *dev,
266 struct device_attribute *attr, char *buf)
267{
268 struct Scsi_Host *shost = class_to_shost(dev);
269 struct ata_port *ap = ata_shost_to_port(shost);
270 struct ahci_host_priv *hpriv = ap->host->private_data;
271
272 return sprintf(buf, "%x\n", hpriv->cap2);
273}
274
275static ssize_t ahci_show_host_version(struct device *dev,
276 struct device_attribute *attr, char *buf)
277{
278 struct Scsi_Host *shost = class_to_shost(dev);
279 struct ata_port *ap = ata_shost_to_port(shost);
280 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 281
8ea909cb 282 return sprintf(buf, "%x\n", hpriv->version);
365cfa1e
AV		 283}
284
285static ssize_t ahci_show_port_cmd(struct device *dev,
286 struct device_attribute *attr, char *buf)
287{
288 struct Scsi_Host *shost = class_to_shost(dev);
289 struct ata_port *ap = ata_shost_to_port(shost);
290 void __iomem *port_mmio = ahci_port_base(ap);
bb03c640 291 ssize_t ret;
365cfa1e 292
bb03c640
MW		 293 ahci_rpm_get_port(ap);
294 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
295 ahci_rpm_put_port(ap);
296
297 return ret;
365cfa1e
AV		 298}
299
c0623166
HZ		 300static ssize_t ahci_read_em_buffer(struct device *dev,
301 struct device_attribute *attr, char *buf)
302{
303 struct Scsi_Host *shost = class_to_shost(dev);
304 struct ata_port *ap = ata_shost_to_port(shost);
305 struct ahci_host_priv *hpriv = ap->host->private_data;
306 void __iomem *mmio = hpriv->mmio;
307 void __iomem *em_mmio = mmio + hpriv->em_loc;
308 u32 em_ctl, msg;
309 unsigned long flags;
310 size_t count;
311 int i;
312
bb03c640 313 ahci_rpm_get_port(ap);
c0623166
HZ		 314 spin_lock_irqsave(ap->lock, flags);
315
316 em_ctl = readl(mmio + HOST_EM_CTL);
317 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
318 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
319 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 320 ahci_rpm_put_port(ap);
c0623166
HZ		 321 return -EINVAL;
322 }
323
324 if (!(em_ctl & EM_CTL_MR)) {
325 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 326 ahci_rpm_put_port(ap);
c0623166
HZ		 327 return -EAGAIN;
328 }
329
330 if (!(em_ctl & EM_CTL_SMB))
331 em_mmio += hpriv->em_buf_sz;
332
333 count = hpriv->em_buf_sz;
334
335 /* the count should not be larger than PAGE_SIZE */
336 if (count > PAGE_SIZE) {
337 if (printk_ratelimit())
a9a79dfe
JP		 338 ata_port_warn(ap,
339 "EM read buffer size too large: "
340 "buffer size %u, page size %lu\n",
341 hpriv->em_buf_sz, PAGE_SIZE);
c0623166
HZ		 342 count = PAGE_SIZE;
343 }
344
345 for (i = 0; i < count; i += 4) {
346 msg = readl(em_mmio + i);
347 buf[i] = msg & 0xff;
348 buf[i + 1] = (msg >> 8) & 0xff;
349 buf[i + 2] = (msg >> 16) & 0xff;
350 buf[i + 3] = (msg >> 24) & 0xff;
351 }
352
353 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 354 ahci_rpm_put_port(ap);
c0623166
HZ		 355
356 return i;
357}
358
359static ssize_t ahci_store_em_buffer(struct device *dev,
360 struct device_attribute *attr,
361 const char *buf, size_t size)
362{
363 struct Scsi_Host *shost = class_to_shost(dev);
364 struct ata_port *ap = ata_shost_to_port(shost);
365 struct ahci_host_priv *hpriv = ap->host->private_data;
366 void __iomem *mmio = hpriv->mmio;
367 void __iomem *em_mmio = mmio + hpriv->em_loc;
f9ce889b 368 const unsigned char *msg_buf = buf;
c0623166
HZ		 369 u32 em_ctl, msg;
370 unsigned long flags;
371 int i;
372
373 /* check size validity */
374 if (!(ap->flags & ATA_FLAG_EM) ||
375 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
376 size % 4 || size > hpriv->em_buf_sz)
377 return -EINVAL;
378
bb03c640 379 ahci_rpm_get_port(ap);
c0623166
HZ		 380 spin_lock_irqsave(ap->lock, flags);
381
382 em_ctl = readl(mmio + HOST_EM_CTL);
383 if (em_ctl & EM_CTL_TM) {
384 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 385 ahci_rpm_put_port(ap);
c0623166
HZ		 386 return -EBUSY;
387 }
388
389 for (i = 0; i < size; i += 4) {
f9ce889b
HZ		 390 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
391 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
c0623166
HZ		 392 writel(msg, em_mmio + i);
393 }
394
395 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
396
397 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 398 ahci_rpm_put_port(ap);
c0623166
HZ		 399
400 return size;
401}
402
6e5fe5b1
HR		 403static ssize_t ahci_show_em_supported(struct device *dev,
404 struct device_attribute *attr, char *buf)
405{
406 struct Scsi_Host *shost = class_to_shost(dev);
407 struct ata_port *ap = ata_shost_to_port(shost);
408 struct ahci_host_priv *hpriv = ap->host->private_data;
409 void __iomem *mmio = hpriv->mmio;
410 u32 em_ctl;
411
bb03c640 412 ahci_rpm_get_port(ap);
6e5fe5b1 413 em_ctl = readl(mmio + HOST_EM_CTL);
bb03c640 414 ahci_rpm_put_port(ap);
6e5fe5b1
HR		 415
416 return sprintf(buf, "%s%s%s%s\n",
417 em_ctl & EM_CTL_LED ? "led " : "",
418 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
419 em_ctl & EM_CTL_SES ? "ses-2 " : "",
420 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
421}
422
365cfa1e
AV		 423/**
424 * ahci_save_initial_config - Save and fixup initial config values
425 * @dev: target AHCI device
426 * @hpriv: host private area to store config values
365cfa1e
AV		 427 *
428 * Some registers containing configuration info might be setup by
429 * BIOS and might be cleared on reset. This function saves the
430 * initial values of those registers into @hpriv such that they
431 * can be restored after controller reset.
432 *
433 * If inconsistent, config values are fixed up by this function.
434 *
039ece38
HG		 435 * If it is not set already this function sets hpriv->start_engine to
436 * ahci_start_engine.
437 *
365cfa1e
AV		 438 * LOCKING:
439 * None.
440 */
725c7b57 441void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
365cfa1e
AV		 442{
443 void __iomem *mmio = hpriv->mmio;
444 u32 cap, cap2, vers, port_map;
445 int i;
446
447 /* make sure AHCI mode is enabled before accessing CAP */
448 ahci_enable_ahci(mmio);
449
450 /* Values prefixed with saved_ are written back to host after
451 * reset. Values without are used for driver operation.
452 */
453 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
454 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
455
456 /* CAP2 register is only defined for AHCI 1.2 and later */
457 vers = readl(mmio + HOST_VERSION);
458 if ((vers >> 16) > 1 ||
459 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
460 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
461 else
462 hpriv->saved_cap2 = cap2 = 0;
463
464 /* some chips have errata preventing 64bit use */
465 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
a44fec1f 466 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
365cfa1e
AV		 467 cap &= ~HOST_CAP_64;
468 }
469
470 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
a44fec1f 471 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
365cfa1e
AV		 472 cap &= ~HOST_CAP_NCQ;
473 }
474
475 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
a44fec1f 476 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
365cfa1e
AV		 477 cap |= HOST_CAP_NCQ;
478 }
479
480 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
a44fec1f 481 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
365cfa1e
AV		 482 cap &= ~HOST_CAP_PMP;
483 }
484
485 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
a44fec1f
JP		 486 dev_info(dev,
487 "controller can't do SNTF, turning off CAP_SNTF\n");
365cfa1e
AV		 488 cap &= ~HOST_CAP_SNTF;
489 }
490
0cf4a7d6
JP		 491 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
492 dev_info(dev,
493 "controller can't do DEVSLP, turning off\n");
494 cap2 &= ~HOST_CAP2_SDS;
495 cap2 &= ~HOST_CAP2_SADM;
496 }
497
5f173107 498 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
a44fec1f 499 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
5f173107
TH		 500 cap |= HOST_CAP_FBS;
501 }
502
888d91a0
KW		 503 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
504 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
505 cap &= ~HOST_CAP_FBS;
506 }
507
ef0da1bf
DB		 508 if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
509 dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
510 cap |= HOST_CAP_ALPM;
511 }
512
725c7b57 513 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
a44fec1f 514 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
725c7b57
AT		 515 port_map, hpriv->force_port_map);
516 port_map = hpriv->force_port_map;
2fd0f46c 517 hpriv->saved_port_map = port_map;
365cfa1e
AV		 518 }
519
725c7b57 520 if (hpriv->mask_port_map) {
a44fec1f
JP		 521 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
522 port_map,
725c7b57
AT		 523 port_map & hpriv->mask_port_map);
524 port_map &= hpriv->mask_port_map;
365cfa1e
AV		 525 }
526
527 /* cross check port_map and cap.n_ports */
528 if (port_map) {
529 int map_ports = 0;
530
531 for (i = 0; i < AHCI_MAX_PORTS; i++)
532 if (port_map & (1 << i))
533 map_ports++;
534
535 /* If PI has more ports than n_ports, whine, clear
536 * port_map and let it be generated from n_ports.
537 */
538 if (map_ports > ahci_nr_ports(cap)) {
a44fec1f
JP		 539 dev_warn(dev,
540 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
541 port_map, ahci_nr_ports(cap));
365cfa1e
AV		 542 port_map = 0;
543 }
544 }
545
566d1827
TH		 546 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
547 if (!port_map && vers < 0x10300) {
365cfa1e 548 port_map = (1 << ahci_nr_ports(cap)) - 1;
a44fec1f 549 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
365cfa1e
AV		 550
551 /* write the fixed up value to the PI register */
552 hpriv->saved_port_map = port_map;
553 }
554
555 /* record values to use during operation */
556 hpriv->cap = cap;
557 hpriv->cap2 = cap2;
8ea909cb 558 hpriv->version = readl(mmio + HOST_VERSION);
365cfa1e 559 hpriv->port_map = port_map;
039ece38
HG		 560
561 if (!hpriv->start_engine)
562 hpriv->start_engine = ahci_start_engine;
f070d671 563
76ff34cf
EW		 564 if (!hpriv->stop_engine)
565 hpriv->stop_engine = ahci_stop_engine;
566
f070d671 567 if (!hpriv->irq_handler)
d867b95f 568 hpriv->irq_handler = ahci_single_level_irq_intr;
365cfa1e
AV		 569}
570EXPORT_SYMBOL_GPL(ahci_save_initial_config);
571
572/**
573 * ahci_restore_initial_config - Restore initial config
574 * @host: target ATA host
575 *
576 * Restore initial config stored by ahci_save_initial_config().
577 *
578 * LOCKING:
579 * None.
580 */
581static void ahci_restore_initial_config(struct ata_host *host)
582{
583 struct ahci_host_priv *hpriv = host->private_data;
584 void __iomem *mmio = hpriv->mmio;
585
586 writel(hpriv->saved_cap, mmio + HOST_CAP);
587 if (hpriv->saved_cap2)
588 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
589 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
590 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
591}
592
593static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
594{
595 static const int offset[] = {
596 [SCR_STATUS] = PORT_SCR_STAT,
597 [SCR_CONTROL] = PORT_SCR_CTL,
598 [SCR_ERROR] = PORT_SCR_ERR,
599 [SCR_ACTIVE] = PORT_SCR_ACT,
600 [SCR_NOTIFICATION] = PORT_SCR_NTF,
601 };
602 struct ahci_host_priv *hpriv = ap->host->private_data;
603
604 if (sc_reg < ARRAY_SIZE(offset) &&
605 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
606 return offset[sc_reg];
607 return 0;
608}
609
610static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
611{
612 void __iomem *port_mmio = ahci_port_base(link->ap);
613 int offset = ahci_scr_offset(link->ap, sc_reg);
614
615 if (offset) {
616 *val = readl(port_mmio + offset);
617 return 0;
618 }
619 return -EINVAL;
620}
621
622static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
623{
624 void __iomem *port_mmio = ahci_port_base(link->ap);
625 int offset = ahci_scr_offset(link->ap, sc_reg);
626
627 if (offset) {
628 writel(val, port_mmio + offset);
629 return 0;
630 }
631 return -EINVAL;
632}
633
634void ahci_start_engine(struct ata_port *ap)
635{
636 void __iomem *port_mmio = ahci_port_base(ap);
637 u32 tmp;
638
639 /* start DMA */
640 tmp = readl(port_mmio + PORT_CMD);
641 tmp |= PORT_CMD_START;
642 writel(tmp, port_mmio + PORT_CMD);
643 readl(port_mmio + PORT_CMD); /* flush */
644}
645EXPORT_SYMBOL_GPL(ahci_start_engine);
646
647int ahci_stop_engine(struct ata_port *ap)
648{
649 void __iomem *port_mmio = ahci_port_base(ap);
fb329633 650 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 651 u32 tmp;
652
fb329633
DP		 653 /*
654 * On some controllers, stopping a port's DMA engine while the port
655 * is in ALPM state (partial or slumber) results in failures on
656 * subsequent DMA engine starts. For those controllers, put the
657 * port back in active state before stopping its DMA engine.
658 */
659 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
660 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
661 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
662 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
663 return -EIO;
664 }
665
365cfa1e
AV		 666 tmp = readl(port_mmio + PORT_CMD);
667
668 /* check if the HBA is idle */
669 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
670 return 0;
671
672 /* setting HBA to idle */
673 tmp &= ~PORT_CMD_START;
674 writel(tmp, port_mmio + PORT_CMD);
675
676 /* wait for engine to stop. This could be as long as 500 msec */
97750ceb 677 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 678 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
679 if (tmp & PORT_CMD_LIST_ON)
680 return -EIO;
681
682 return 0;
683}
684EXPORT_SYMBOL_GPL(ahci_stop_engine);
685
39e0ee99 686void ahci_start_fis_rx(struct ata_port *ap)
365cfa1e
AV		 687{
688 void __iomem *port_mmio = ahci_port_base(ap);
689 struct ahci_host_priv *hpriv = ap->host->private_data;
690 struct ahci_port_priv *pp = ap->private_data;
691 u32 tmp;
692
693 /* set FIS registers */
694 if (hpriv->cap & HOST_CAP_64)
695 writel((pp->cmd_slot_dma >> 16) >> 16,
696 port_mmio + PORT_LST_ADDR_HI);
697 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
698
699 if (hpriv->cap & HOST_CAP_64)
700 writel((pp->rx_fis_dma >> 16) >> 16,
701 port_mmio + PORT_FIS_ADDR_HI);
702 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
703
704 /* enable FIS reception */
705 tmp = readl(port_mmio + PORT_CMD);
706 tmp |= PORT_CMD_FIS_RX;
707 writel(tmp, port_mmio + PORT_CMD);
708
709 /* flush */
710 readl(port_mmio + PORT_CMD);
711}
39e0ee99 712EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
365cfa1e
AV		 713
714static int ahci_stop_fis_rx(struct ata_port *ap)
715{
716 void __iomem *port_mmio = ahci_port_base(ap);
717 u32 tmp;
718
719 /* disable FIS reception */
720 tmp = readl(port_mmio + PORT_CMD);
721 tmp &= ~PORT_CMD_FIS_RX;
722 writel(tmp, port_mmio + PORT_CMD);
723
724 /* wait for completion, spec says 500ms, give it 1000 */
97750ceb 725 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
365cfa1e
AV		 726 PORT_CMD_FIS_ON, 10, 1000);
727 if (tmp & PORT_CMD_FIS_ON)
728 return -EBUSY;
729
730 return 0;
731}
732
733static void ahci_power_up(struct ata_port *ap)
734{
735 struct ahci_host_priv *hpriv = ap->host->private_data;
736 void __iomem *port_mmio = ahci_port_base(ap);
737 u32 cmd;
738
739 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
740
741 /* spin up device */
742 if (hpriv->cap & HOST_CAP_SSS) {
743 cmd |= PORT_CMD_SPIN_UP;
744 writel(cmd, port_mmio + PORT_CMD);
745 }
746
747 /* wake up link */
748 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
749}
750
6b7ae954
TH		 751static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
752 unsigned int hints)
365cfa1e 753{
6b7ae954 754 struct ata_port *ap = link->ap;
365cfa1e 755 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e 756 struct ahci_port_priv *pp = ap->private_data;
365cfa1e 757 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 758
6b7ae954 759 if (policy != ATA_LPM_MAX_POWER) {
fb329633
DP		 760 /* wakeup flag only applies to the max power policy */
761 hints &= ~ATA_LPM_WAKE_ONLY;
762
365cfa1e 763 /*
6b7ae954
TH		 764 * Disable interrupts on Phy Ready. This keeps us from
765 * getting woken up due to spurious phy ready
766 * interrupts.
365cfa1e 767 */
6b7ae954
TH		 768 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
769 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
770
771 sata_link_scr_lpm(link, policy, false);
365cfa1e
AV		 772 }
773
6b7ae954
TH		 774 if (hpriv->cap & HOST_CAP_ALPM) {
775 u32 cmd = readl(port_mmio + PORT_CMD);
365cfa1e 776
6b7ae954 777 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
fb329633
DP		 778 if (!(hints & ATA_LPM_WAKE_ONLY))
779 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
6b7ae954 780 cmd |= PORT_CMD_ICC_ACTIVE;
365cfa1e 781
6b7ae954
TH		 782 writel(cmd, port_mmio + PORT_CMD);
783 readl(port_mmio + PORT_CMD);
365cfa1e 784
6b7ae954 785 /* wait 10ms to be sure we've come out of LPM state */
97750ceb 786 ata_msleep(ap, 10);
fb329633
DP		 787
788 if (hints & ATA_LPM_WAKE_ONLY)
789 return 0;
6b7ae954
TH		 790 } else {
791 cmd |= PORT_CMD_ALPE;
792 if (policy == ATA_LPM_MIN_POWER)
793 cmd |= PORT_CMD_ASP;
82544793
SP		 794 else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
795 cmd &= ~PORT_CMD_ASP;
365cfa1e 796
6b7ae954
TH		 797 /* write out new cmd value */
798 writel(cmd, port_mmio + PORT_CMD);
799 }
800 }
365cfa1e 801
65fe1f0f
SH		 802 /* set aggressive device sleep */
803 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
804 (hpriv->cap2 & HOST_CAP2_SADM) &&
805 (link->device->flags & ATA_DFLAG_DEVSLP)) {
82544793
SP		 806 if (policy == ATA_LPM_MIN_POWER ||
807 policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
65fe1f0f
SH		 808 ahci_set_aggressive_devslp(ap, true);
809 else
810 ahci_set_aggressive_devslp(ap, false);
811 }
812
6b7ae954
TH		 813 if (policy == ATA_LPM_MAX_POWER) {
814 sata_link_scr_lpm(link, policy, false);
815
816 /* turn PHYRDY IRQ back on */
817 pp->intr_mask |= PORT_IRQ_PHYRDY;
818 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
819 }
365cfa1e 820
365cfa1e
AV		 821 return 0;
822}
823
824#ifdef CONFIG_PM
825static void ahci_power_down(struct ata_port *ap)
826{
827 struct ahci_host_priv *hpriv = ap->host->private_data;
828 void __iomem *port_mmio = ahci_port_base(ap);
829 u32 cmd, scontrol;
830
831 if (!(hpriv->cap & HOST_CAP_SSS))
832 return;
833
834 /* put device into listen mode, first set PxSCTL.DET to 0 */
835 scontrol = readl(port_mmio + PORT_SCR_CTL);
836 scontrol &= ~0xf;
837 writel(scontrol, port_mmio + PORT_SCR_CTL);
838
839 /* then set PxCMD.SUD to 0 */
840 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
841 cmd &= ~PORT_CMD_SPIN_UP;
842 writel(cmd, port_mmio + PORT_CMD);
843}
844#endif
845
846static void ahci_start_port(struct ata_port *ap)
847{
66583c9f 848 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 849 struct ahci_port_priv *pp = ap->private_data;
850 struct ata_link *link;
851 struct ahci_em_priv *emp;
852 ssize_t rc;
853 int i;
854
855 /* enable FIS reception */
856 ahci_start_fis_rx(ap);
857
66583c9f
BN		 858 /* enable DMA */
859 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
039ece38 860 hpriv->start_engine(ap);
66583c9f 861
365cfa1e
AV		 862 /* turn on LEDs */
863 if (ap->flags & ATA_FLAG_EM) {
864 ata_for_each_link(link, ap, EDGE) {
865 emp = &pp->em_priv[link->pmp];
866
867 /* EM Transmit bit maybe busy during init */
868 for (i = 0; i < EM_MAX_RETRY; i++) {
439d7a35 869 rc = ap->ops->transmit_led_message(ap,
365cfa1e
AV		 870 emp->led_state,
871 4);
fa070ee6
LD		 872 /*
873 * If busy, give a breather but do not
874 * release EH ownership by using msleep()
875 * instead of ata_msleep(). EM Transmit
876 * bit is busy for the whole host and
877 * releasing ownership will cause other
878 * ports to fail the same way.
879 */
365cfa1e 880 if (rc == -EBUSY)
fa070ee6 881 msleep(1);
365cfa1e
AV		 882 else
883 break;
884 }
885 }
886 }
887
888 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
889 ata_for_each_link(link, ap, EDGE)
890 ahci_init_sw_activity(link);
891
892}
893
894static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
895{
896 int rc;
76ff34cf 897 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 898
899 /* disable DMA */
76ff34cf 900 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 901 if (rc) {
902 *emsg = "failed to stop engine";
903 return rc;
904 }
905
906 /* disable FIS reception */
907 rc = ahci_stop_fis_rx(ap);
908 if (rc) {
909 *emsg = "failed stop FIS RX";
910 return rc;
911 }
912
913 return 0;
914}
915
916int ahci_reset_controller(struct ata_host *host)
917{
918 struct ahci_host_priv *hpriv = host->private_data;
919 void __iomem *mmio = hpriv->mmio;
920 u32 tmp;
921
922 /* we must be in AHCI mode, before using anything
923 * AHCI-specific, such as HOST_RESET.
924 */
925 ahci_enable_ahci(mmio);
926
927 /* global controller reset */
928 if (!ahci_skip_host_reset) {
929 tmp = readl(mmio + HOST_CTL);
930 if ((tmp & HOST_RESET) == 0) {
931 writel(tmp | HOST_RESET, mmio + HOST_CTL);
932 readl(mmio + HOST_CTL); /* flush */
933 }
934
935 /*
936 * to perform host reset, OS should set HOST_RESET
937 * and poll until this bit is read to be "0".
938 * reset must complete within 1 second, or
939 * the hardware should be considered fried.
940 */
97750ceb 941 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
365cfa1e
AV		 942 HOST_RESET, 10, 1000);
943
944 if (tmp & HOST_RESET) {
a44fec1f
JP		 945 dev_err(host->dev, "controller reset failed (0x%x)\n",
946 tmp);
365cfa1e
AV		 947 return -EIO;
948 }
949
950 /* turn on AHCI mode */
951 ahci_enable_ahci(mmio);
952
953 /* Some registers might be cleared on reset. Restore
954 * initial values.
955 */
7fab72f8
DB		 956 if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
957 ahci_restore_initial_config(host);
365cfa1e 958 } else
a44fec1f 959 dev_info(host->dev, "skipping global host reset\n");
365cfa1e
AV		 960
961 return 0;
962}
963EXPORT_SYMBOL_GPL(ahci_reset_controller);
964
965static void ahci_sw_activity(struct ata_link *link)
966{
967 struct ata_port *ap = link->ap;
968 struct ahci_port_priv *pp = ap->private_data;
969 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
970
971 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
972 return;
973
974 emp->activity++;
975 if (!timer_pending(&emp->timer))
976 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
977}
978
1843594c 979static void ahci_sw_activity_blink(struct timer_list *t)
365cfa1e 980{
1843594c
KC		 981 struct ahci_em_priv *emp = from_timer(emp, t, timer);
982 struct ata_link *link = emp->link;
365cfa1e 983 struct ata_port *ap = link->ap;
1843594c 984
365cfa1e
AV		 985 unsigned long led_message = emp->led_state;
986 u32 activity_led_state;
987 unsigned long flags;
988
989 led_message &= EM_MSG_LED_VALUE;
990 led_message |= ap->port_no | (link->pmp << 8);
991
992 /* check to see if we've had activity. If so,
993 * toggle state of LED and reset timer. If not,
994 * turn LED to desired idle state.
995 */
996 spin_lock_irqsave(ap->lock, flags);
997 if (emp->saved_activity != emp->activity) {
998 emp->saved_activity = emp->activity;
999 /* get the current LED state */
1000 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1001
1002 if (activity_led_state)
1003 activity_led_state = 0;
1004 else
1005 activity_led_state = 1;
1006
1007 /* clear old state */
1008 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1009
1010 /* toggle state */
1011 led_message |= (activity_led_state << 16);
1012 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1013 } else {
1014 /* switch to idle */
1015 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1016 if (emp->blink_policy == BLINK_OFF)
1017 led_message |= (1 << 16);
1018 }
1019 spin_unlock_irqrestore(ap->lock, flags);
439d7a35 1020 ap->ops->transmit_led_message(ap, led_message, 4);
365cfa1e
AV		 1021}
1022
1023static void ahci_init_sw_activity(struct ata_link *link)
1024{
1025 struct ata_port *ap = link->ap;
1026 struct ahci_port_priv *pp = ap->private_data;
1027 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1028
1029 /* init activity stats, setup timer */
1030 emp->saved_activity = emp->activity = 0;
1843594c
KC		 1031 emp->link = link;
1032 timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
365cfa1e
AV		 1033
1034 /* check our blink policy and set flag for link if it's enabled */
1035 if (emp->blink_policy)
1036 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1037}
1038
1039int ahci_reset_em(struct ata_host *host)
1040{
1041 struct ahci_host_priv *hpriv = host->private_data;
1042 void __iomem *mmio = hpriv->mmio;
1043 u32 em_ctl;
1044
1045 em_ctl = readl(mmio + HOST_EM_CTL);
1046 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1047 return -EINVAL;
1048
1049 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1050 return 0;
1051}
1052EXPORT_SYMBOL_GPL(ahci_reset_em);
1053
1054static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1055 ssize_t size)
1056{
1057 struct ahci_host_priv *hpriv = ap->host->private_data;
1058 struct ahci_port_priv *pp = ap->private_data;
1059 void __iomem *mmio = hpriv->mmio;
1060 u32 em_ctl;
1061 u32 message[] = {0, 0};
1062 unsigned long flags;
1063 int pmp;
1064 struct ahci_em_priv *emp;
1065
1066 /* get the slot number from the message */
1067 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1068 if (pmp < EM_MAX_SLOTS)
1069 emp = &pp->em_priv[pmp];
1070 else
1071 return -EINVAL;
1072
bb03c640 1073 ahci_rpm_get_port(ap);
365cfa1e
AV		 1074 spin_lock_irqsave(ap->lock, flags);
1075
1076 /*
1077 * if we are still busy transmitting a previous message,
1078 * do not allow
1079 */
1080 em_ctl = readl(mmio + HOST_EM_CTL);
1081 if (em_ctl & EM_CTL_TM) {
1082 spin_unlock_irqrestore(ap->lock, flags);
bb03c640 1083 ahci_rpm_put_port(ap);
365cfa1e
AV		 1084 return -EBUSY;
1085 }
1086
008dbd61
HZ		 1087 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1088 /*
1089 * create message header - this is all zero except for
1090 * the message size, which is 4 bytes.
1091 */
1092 message[0] |= (4 << 8);
365cfa1e 1093
008dbd61
HZ		 1094 /* ignore 0:4 of byte zero, fill in port info yourself */
1095 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
365cfa1e 1096
008dbd61
HZ		 1097 /* write message to EM_LOC */
1098 writel(message[0], mmio + hpriv->em_loc);
1099 writel(message[1], mmio + hpriv->em_loc+4);
1100
1101 /*
1102 * tell hardware to transmit the message
1103 */
1104 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1105 }
365cfa1e
AV		 1106
1107 /* save off new led state for port/slot */
1108 emp->led_state = state;
1109
365cfa1e 1110 spin_unlock_irqrestore(ap->lock, flags);
bb03c640
MW		 1111 ahci_rpm_put_port(ap);
1112
365cfa1e
AV		 1113 return size;
1114}
1115
1116static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1117{
1118 struct ahci_port_priv *pp = ap->private_data;
1119 struct ata_link *link;
1120 struct ahci_em_priv *emp;
1121 int rc = 0;
1122
1123 ata_for_each_link(link, ap, EDGE) {
1124 emp = &pp->em_priv[link->pmp];
1125 rc += sprintf(buf, "%lx\n", emp->led_state);
1126 }
1127 return rc;
1128}
1129
1130static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1131 size_t size)
1132{
b2a52b6a 1133 unsigned int state;
365cfa1e
AV		 1134 int pmp;
1135 struct ahci_port_priv *pp = ap->private_data;
1136 struct ahci_em_priv *emp;
1137
b2a52b6a
DY		 1138 if (kstrtouint(buf, 0, &state) < 0)
1139 return -EINVAL;
365cfa1e
AV		 1140
1141 /* get the slot number from the message */
1142 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
dec6104e
JG		 1143 if (pmp < EM_MAX_SLOTS) {
1144 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
365cfa1e 1145 emp = &pp->em_priv[pmp];
dec6104e 1146 } else {
365cfa1e 1147 return -EINVAL;
dec6104e 1148 }
365cfa1e
AV		 1149
1150 /* mask off the activity bits if we are in sw_activity
1151 * mode, user should turn off sw_activity before setting
1152 * activity led through em_message
1153 */
1154 if (emp->blink_policy)
1155 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1156
439d7a35 1157 return ap->ops->transmit_led_message(ap, state, size);
365cfa1e
AV		 1158}
1159
1160static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1161{
1162 struct ata_link *link = dev->link;
1163 struct ata_port *ap = link->ap;
1164 struct ahci_port_priv *pp = ap->private_data;
1165 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1166 u32 port_led_state = emp->led_state;
1167
1168 /* save the desired Activity LED behavior */
1169 if (val == OFF) {
1170 /* clear LFLAG */
1171 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1172
1173 /* set the LED to OFF */
1174 port_led_state &= EM_MSG_LED_VALUE_OFF;
1175 port_led_state |= (ap->port_no | (link->pmp << 8));
439d7a35 1176 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1177 } else {
1178 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1179 if (val == BLINK_OFF) {
1180 /* set LED to ON for idle */
1181 port_led_state &= EM_MSG_LED_VALUE_OFF;
1182 port_led_state |= (ap->port_no | (link->pmp << 8));
1183 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
439d7a35 1184 ap->ops->transmit_led_message(ap, port_led_state, 4);
365cfa1e
AV		 1185 }
1186 }
1187 emp->blink_policy = val;
1188 return 0;
1189}
1190
1191static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1192{
1193 struct ata_link *link = dev->link;
1194 struct ata_port *ap = link->ap;
1195 struct ahci_port_priv *pp = ap->private_data;
1196 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1197
1198 /* display the saved value of activity behavior for this
1199 * disk.
1200 */
1201 return sprintf(buf, "%d\n", emp->blink_policy);
1202}
1203
1204static void ahci_port_init(struct device *dev, struct ata_port *ap,
1205 int port_no, void __iomem *mmio,
1206 void __iomem *port_mmio)
1207{
8a3e33cf 1208 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1209 const char *emsg = NULL;
1210 int rc;
1211 u32 tmp;
1212
1213 /* make sure port is not active */
1214 rc = ahci_deinit_port(ap, &emsg);
1215 if (rc)
1216 dev_warn(dev, "%s (%d)\n", emsg, rc);
1217
1218 /* clear SError */
1219 tmp = readl(port_mmio + PORT_SCR_ERR);
1220 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1221 writel(tmp, port_mmio + PORT_SCR_ERR);
1222
1223 /* clear port IRQ */
1224 tmp = readl(port_mmio + PORT_IRQ_STAT);
1225 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1226 if (tmp)
1227 writel(tmp, port_mmio + PORT_IRQ_STAT);
1228
1229 writel(1 << port_no, mmio + HOST_IRQ_STAT);
8a3e33cf
ML		 1230
1231 /* mark esata ports */
1232 tmp = readl(port_mmio + PORT_CMD);
dc8b4afc 1233 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
8a3e33cf 1234 ap->pflags |= ATA_PFLAG_EXTERNAL;
365cfa1e
AV		 1235}
1236
1237void ahci_init_controller(struct ata_host *host)
1238{
1239 struct ahci_host_priv *hpriv = host->private_data;
1240 void __iomem *mmio = hpriv->mmio;
1241 int i;
1242 void __iomem *port_mmio;
1243 u32 tmp;
1244
1245 for (i = 0; i < host->n_ports; i++) {
1246 struct ata_port *ap = host->ports[i];
1247
1248 port_mmio = ahci_port_base(ap);
1249 if (ata_port_is_dummy(ap))
1250 continue;
1251
1252 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1253 }
1254
1255 tmp = readl(mmio + HOST_CTL);
1256 VPRINTK("HOST_CTL 0x%x\n", tmp);
1257 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1258 tmp = readl(mmio + HOST_CTL);
1259 VPRINTK("HOST_CTL 0x%x\n", tmp);
1260}
1261EXPORT_SYMBOL_GPL(ahci_init_controller);
1262
1263static void ahci_dev_config(struct ata_device *dev)
1264{
1265 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1266
1267 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1268 dev->max_sectors = 255;
a9a79dfe
JP		 1269 ata_dev_info(dev,
1270 "SB600 AHCI: limiting to 255 sectors per cmd\n");
365cfa1e
AV		 1271 }
1272}
1273
bbb4ab43 1274unsigned int ahci_dev_classify(struct ata_port *ap)
365cfa1e
AV		 1275{
1276 void __iomem *port_mmio = ahci_port_base(ap);
1277 struct ata_taskfile tf;
1278 u32 tmp;
1279
1280 tmp = readl(port_mmio + PORT_SIG);
1281 tf.lbah = (tmp >> 24) & 0xff;
1282 tf.lbam = (tmp >> 16) & 0xff;
1283 tf.lbal = (tmp >> 8) & 0xff;
1284 tf.nsect = (tmp) & 0xff;
1285
1286 return ata_dev_classify(&tf);
1287}
bbb4ab43 1288EXPORT_SYMBOL_GPL(ahci_dev_classify);
365cfa1e 1289
02cdfcf0
DM		 1290void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1291 u32 opts)
365cfa1e
AV		 1292{
1293 dma_addr_t cmd_tbl_dma;
1294
1295 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1296
1297 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1298 pp->cmd_slot[tag].status = 0;
1299 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1300 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1301}
02cdfcf0 1302EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
365cfa1e
AV		 1303
1304int ahci_kick_engine(struct ata_port *ap)
1305{
1306 void __iomem *port_mmio = ahci_port_base(ap);
1307 struct ahci_host_priv *hpriv = ap->host->private_data;
1308 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1309 u32 tmp;
1310 int busy, rc;
1311
1312 /* stop engine */
76ff34cf 1313 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 1314 if (rc)
1315 goto out_restart;
1316
1317 /* need to do CLO?
1318 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1319 */
1320 busy = status & (ATA_BUSY | ATA_DRQ);
1321 if (!busy && !sata_pmp_attached(ap)) {
1322 rc = 0;
1323 goto out_restart;
1324 }
1325
1326 if (!(hpriv->cap & HOST_CAP_CLO)) {
1327 rc = -EOPNOTSUPP;
1328 goto out_restart;
1329 }
1330
1331 /* perform CLO */
1332 tmp = readl(port_mmio + PORT_CMD);
1333 tmp |= PORT_CMD_CLO;
1334 writel(tmp, port_mmio + PORT_CMD);
1335
1336 rc = 0;
97750ceb 1337 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
365cfa1e
AV		 1338 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1339 if (tmp & PORT_CMD_CLO)
1340 rc = -EIO;
1341
1342 /* restart engine */
1343 out_restart:
039ece38 1344 hpriv->start_engine(ap);
365cfa1e
AV		 1345 return rc;
1346}
1347EXPORT_SYMBOL_GPL(ahci_kick_engine);
1348
1349static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1350 struct ata_taskfile *tf, int is_cmd, u16 flags,
1351 unsigned long timeout_msec)
1352{
1353 const u32 cmd_fis_len = 5; /* five dwords */
1354 struct ahci_port_priv *pp = ap->private_data;
1355 void __iomem *port_mmio = ahci_port_base(ap);
1356 u8 *fis = pp->cmd_tbl;
1357 u32 tmp;
1358
1359 /* prep the command */
1360 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1361 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1362
023113d2
XY		 1363 /* set port value for softreset of Port Multiplier */
1364 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1365 tmp = readl(port_mmio + PORT_FBS);
1366 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1367 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1368 writel(tmp, port_mmio + PORT_FBS);
1369 pp->fbs_last_dev = pmp;
1370 }
1371
365cfa1e
AV		 1372 /* issue & wait */
1373 writel(1, port_mmio + PORT_CMD_ISSUE);
1374
1375 if (timeout_msec) {
97750ceb
TH		 1376 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1377 0x1, 0x1, 1, timeout_msec);
365cfa1e
AV		 1378 if (tmp & 0x1) {
1379 ahci_kick_engine(ap);
1380 return -EBUSY;
1381 }
1382 } else
1383 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1384
1385 return 0;
1386}
1387
1388int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1389 int pmp, unsigned long deadline,
1390 int (*check_ready)(struct ata_link *link))
1391{
1392 struct ata_port *ap = link->ap;
1393 struct ahci_host_priv *hpriv = ap->host->private_data;
89dafa20 1394 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 1395 const char *reason = NULL;
1396 unsigned long now, msecs;
1397 struct ata_taskfile tf;
89dafa20 1398 bool fbs_disabled = false;
365cfa1e
AV		 1399 int rc;
1400
1401 DPRINTK("ENTER\n");
1402
1403 /* prepare for SRST (AHCI-1.1 10.4.1) */
1404 rc = ahci_kick_engine(ap);
1405 if (rc && rc != -EOPNOTSUPP)
a9a79dfe 1406 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
365cfa1e 1407
89dafa20 1408 /*
1409 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1410 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1411 * that is attached to port multiplier.
1412 */
1413 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1414 ahci_disable_fbs(ap);
1415 fbs_disabled = true;
1416 }
1417
365cfa1e
AV		 1418 ata_tf_init(link->device, &tf);
1419
08fc4756 1420 /* issue the first H2D Register FIS */
365cfa1e
AV		 1421 msecs = 0;
1422 now = jiffies;
f1f5a807 1423 if (time_after(deadline, now))
365cfa1e
AV		 1424 msecs = jiffies_to_msecs(deadline - now);
1425
1426 tf.ctl |= ATA_SRST;
1427 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1428 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1429 rc = -EIO;
1430 reason = "1st FIS failed";
1431 goto fail;
1432 }
1433
1434 /* spec says at least 5us, but be generous and sleep for 1ms */
97750ceb 1435 ata_msleep(ap, 1);
365cfa1e 1436
08fc4756 1437 /* issue the second H2D Register FIS */
365cfa1e
AV		 1438 tf.ctl &= ~ATA_SRST;
1439 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1440
1441 /* wait for link to become ready */
1442 rc = ata_wait_after_reset(link, deadline, check_ready);
1443 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1444 /*
1445 * Workaround for cases where link online status can't
1446 * be trusted. Treat device readiness timeout as link
1447 * offline.
1448 */
a9a79dfe 1449 ata_link_info(link, "device not ready, treating as offline\n");
365cfa1e
AV		 1450 *class = ATA_DEV_NONE;
1451 } else if (rc) {
1452 /* link occupied, -ENODEV too is an error */
1453 reason = "device not ready";
1454 goto fail;
1455 } else
1456 *class = ahci_dev_classify(ap);
1457
89dafa20 1458 /* re-enable FBS if disabled before */
1459 if (fbs_disabled)
1460 ahci_enable_fbs(ap);
1461
365cfa1e
AV		 1462 DPRINTK("EXIT, class=%u\n", *class);
1463 return 0;
1464
1465 fail:
a9a79dfe 1466 ata_link_err(link, "softreset failed (%s)\n", reason);
365cfa1e
AV		 1467 return rc;
1468}
1469
1470int ahci_check_ready(struct ata_link *link)
1471{
1472 void __iomem *port_mmio = ahci_port_base(link->ap);
1473 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1474
1475 return ata_check_ready(status);
1476}
1477EXPORT_SYMBOL_GPL(ahci_check_ready);
1478
1479static int ahci_softreset(struct ata_link *link, unsigned int *class,
1480 unsigned long deadline)
1481{
1482 int pmp = sata_srst_pmp(link);
1483
1484 DPRINTK("ENTER\n");
1485
1486 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1487}
1488EXPORT_SYMBOL_GPL(ahci_do_softreset);
1489
345347c5
YHC		 1490static int ahci_bad_pmp_check_ready(struct ata_link *link)
1491{
1492 void __iomem *port_mmio = ahci_port_base(link->ap);
1493 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1494 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1495
1496 /*
1497 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1498 * which can save timeout delay.
1499 */
1500 if (irq_status & PORT_IRQ_BAD_PMP)
1501 return -EIO;
1502
1503 return ata_check_ready(status);
1504}
1505
35186d05
DY		 1506static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1507 unsigned long deadline)
345347c5
YHC		 1508{
1509 struct ata_port *ap = link->ap;
1510 void __iomem *port_mmio = ahci_port_base(ap);
1511 int pmp = sata_srst_pmp(link);
1512 int rc;
1513 u32 irq_sts;
1514
1515 DPRINTK("ENTER\n");
1516
1517 rc = ahci_do_softreset(link, class, pmp, deadline,
1518 ahci_bad_pmp_check_ready);
1519
1520 /*
1521 * Soft reset fails with IPMS set when PMP is enabled but
1522 * SATA HDD/ODD is connected to SATA port, do soft reset
1523 * again to port 0.
1524 */
1525 if (rc == -EIO) {
1526 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1527 if (irq_sts & PORT_IRQ_BAD_PMP) {
39f80acb 1528 ata_link_warn(link,
345347c5
YHC		 1529 "applying PMP SRST workaround "
1530 "and retrying\n");
1531 rc = ahci_do_softreset(link, class, 0, deadline,
1532 ahci_check_ready);
1533 }
1534 }
1535
1536 return rc;
1537}
1538
d436501e
BG		 1539int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1540 unsigned long deadline, bool *online)
365cfa1e
AV		 1541{
1542 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1543 struct ata_port *ap = link->ap;
1544 struct ahci_port_priv *pp = ap->private_data;
039ece38 1545 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 1546 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1547 struct ata_taskfile tf;
365cfa1e
AV		 1548 int rc;
1549
1550 DPRINTK("ENTER\n");
1551
76ff34cf 1552 hpriv->stop_engine(ap);
365cfa1e
AV		 1553
1554 /* clear D2H reception area to properly wait for D2H FIS */
1555 ata_tf_init(link->device, &tf);
9bbb1b0e 1556 tf.command = ATA_BUSY;
365cfa1e
AV		 1557 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1558
d436501e 1559 rc = sata_link_hardreset(link, timing, deadline, online,
365cfa1e
AV		 1560 ahci_check_ready);
1561
039ece38 1562 hpriv->start_engine(ap);
365cfa1e 1563
d436501e 1564 if (*online)
365cfa1e
AV		 1565 *class = ahci_dev_classify(ap);
1566
1567 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1568 return rc;
1569}
d436501e
BG		 1570EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1571
1572static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1573 unsigned long deadline)
1574{
1575 bool online;
1576
1577 return ahci_do_hardreset(link, class, deadline, &online);
1578}
365cfa1e
AV		 1579
1580static void ahci_postreset(struct ata_link *link, unsigned int *class)
1581{
1582 struct ata_port *ap = link->ap;
1583 void __iomem *port_mmio = ahci_port_base(ap);
1584 u32 new_tmp, tmp;
1585
1586 ata_std_postreset(link, class);
1587
1588 /* Make sure port's ATAPI bit is set appropriately */
1589 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1590 if (*class == ATA_DEV_ATAPI)
1591 new_tmp |= PORT_CMD_ATAPI;
1592 else
1593 new_tmp &= ~PORT_CMD_ATAPI;
1594 if (new_tmp != tmp) {
1595 writel(new_tmp, port_mmio + PORT_CMD);
1596 readl(port_mmio + PORT_CMD); /* flush */
1597 }
1598}
1599
1600static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1601{
1602 struct scatterlist *sg;
1603 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1604 unsigned int si;
1605
1606 VPRINTK("ENTER\n");
1607
1608 /*
1609 * Next, the S/G list.
1610 */
1611 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1612 dma_addr_t addr = sg_dma_address(sg);
1613 u32 sg_len = sg_dma_len(sg);
1614
1615 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1616 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1617 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1618 }
1619
1620 return si;
1621}
1622
1623static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1624{
1625 struct ata_port *ap = qc->ap;
1626 struct ahci_port_priv *pp = ap->private_data;
1627
1628 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1629 return ata_std_qc_defer(qc);
1630 else
1631 return sata_pmp_qc_defer_cmd_switch(qc);
1632}
1633
1634static void ahci_qc_prep(struct ata_queued_cmd *qc)
1635{
1636 struct ata_port *ap = qc->ap;
1637 struct ahci_port_priv *pp = ap->private_data;
1638 int is_atapi = ata_is_atapi(qc->tf.protocol);
1639 void *cmd_tbl;
1640 u32 opts;
1641 const u32 cmd_fis_len = 5; /* five dwords */
1642 unsigned int n_elem;
1643
1644 /*
1645 * Fill in command table information. First, the header,
1646 * a SATA Register - Host to Device command FIS.
1647 */
1648 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1649
1650 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1651 if (is_atapi) {
1652 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1653 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1654 }
1655
1656 n_elem = 0;
1657 if (qc->flags & ATA_QCFLAG_DMAMAP)
1658 n_elem = ahci_fill_sg(qc, cmd_tbl);
1659
1660 /*
1661 * Fill in command slot information.
1662 */
1663 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1664 if (qc->tf.flags & ATA_TFLAG_WRITE)
1665 opts |= AHCI_CMD_WRITE;
1666 if (is_atapi)
1667 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1668
1669 ahci_fill_cmd_slot(pp, qc->tag, opts);
1670}
1671
1672static void ahci_fbs_dec_intr(struct ata_port *ap)
1673{
1674 struct ahci_port_priv *pp = ap->private_data;
1675 void __iomem *port_mmio = ahci_port_base(ap);
1676 u32 fbs = readl(port_mmio + PORT_FBS);
1677 int retries = 3;
1678
1679 DPRINTK("ENTER\n");
1680 BUG_ON(!pp->fbs_enabled);
1681
1682 /* time to wait for DEC is not specified by AHCI spec,
1683 * add a retry loop for safety.
1684 */
1685 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1686 fbs = readl(port_mmio + PORT_FBS);
1687 while ((fbs & PORT_FBS_DEC) && retries--) {
1688 udelay(1);
1689 fbs = readl(port_mmio + PORT_FBS);
1690 }
1691
1692 if (fbs & PORT_FBS_DEC)
a44fec1f 1693 dev_err(ap->host->dev, "failed to clear device error\n");
365cfa1e
AV		 1694}
1695
1696static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1697{
1698 struct ahci_host_priv *hpriv = ap->host->private_data;
1699 struct ahci_port_priv *pp = ap->private_data;
1700 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1701 struct ata_link *link = NULL;
1702 struct ata_queued_cmd *active_qc;
1703 struct ata_eh_info *active_ehi;
1704 bool fbs_need_dec = false;
1705 u32 serror;
1706
1707 /* determine active link with error */
1708 if (pp->fbs_enabled) {
1709 void __iomem *port_mmio = ahci_port_base(ap);
1710 u32 fbs = readl(port_mmio + PORT_FBS);
1711 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1712
912b9ac6 1713 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
365cfa1e
AV		 1714 link = &ap->pmp_link[pmp];
1715 fbs_need_dec = true;
1716 }
1717
1718 } else
1719 ata_for_each_link(link, ap, EDGE)
1720 if (ata_link_active(link))
1721 break;
1722
1723 if (!link)
1724 link = &ap->link;
1725
1726 active_qc = ata_qc_from_tag(ap, link->active_tag);
1727 active_ehi = &link->eh_info;
1728
1729 /* record irq stat */
1730 ata_ehi_clear_desc(host_ehi);
1731 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1732
1733 /* AHCI needs SError cleared; otherwise, it might lock up */
1734 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1735 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1736 host_ehi->serror |= serror;
1737
1738 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1739 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1740 irq_stat &= ~PORT_IRQ_IF_ERR;
1741
1742 if (irq_stat & PORT_IRQ_TF_ERR) {
1743 /* If qc is active, charge it; otherwise, the active
1744 * link. There's no active qc on NCQ errors. It will
1745 * be determined by EH by reading log page 10h.
1746 */
1747 if (active_qc)
1748 active_qc->err_mask |= AC_ERR_DEV;
1749 else
1750 active_ehi->err_mask |= AC_ERR_DEV;
1751
1752 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1753 host_ehi->serror &= ~SERR_INTERNAL;
1754 }
1755
1756 if (irq_stat & PORT_IRQ_UNK_FIS) {
d5185d65 1757 u32 *unk = pp->rx_fis + RX_FIS_UNK;
365cfa1e
AV		 1758
1759 active_ehi->err_mask |= AC_ERR_HSM;
1760 active_ehi->action |= ATA_EH_RESET;
1761 ata_ehi_push_desc(active_ehi,
1762 "unknown FIS %08x %08x %08x %08x" ,
1763 unk[0], unk[1], unk[2], unk[3]);
1764 }
1765
1766 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1767 active_ehi->err_mask |= AC_ERR_HSM;
1768 active_ehi->action |= ATA_EH_RESET;
1769 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1770 }
1771
1772 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1773 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1774 host_ehi->action |= ATA_EH_RESET;
1775 ata_ehi_push_desc(host_ehi, "host bus error");
1776 }
1777
1778 if (irq_stat & PORT_IRQ_IF_ERR) {
1779 if (fbs_need_dec)
1780 active_ehi->err_mask |= AC_ERR_DEV;
1781 else {
1782 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1783 host_ehi->action |= ATA_EH_RESET;
1784 }
1785
1786 ata_ehi_push_desc(host_ehi, "interface fatal error");
1787 }
1788
1789 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1790 ata_ehi_hotplugged(host_ehi);
1791 ata_ehi_push_desc(host_ehi, "%s",
1792 irq_stat & PORT_IRQ_CONNECT ?
1793 "connection status changed" : "PHY RDY changed");
1794 }
1795
1796 /* okay, let's hand over to EH */
1797
1798 if (irq_stat & PORT_IRQ_FREEZE)
1799 ata_port_freeze(ap);
1800 else if (fbs_need_dec) {
1801 ata_link_abort(link);
1802 ahci_fbs_dec_intr(ap);
1803 } else
1804 ata_port_abort(ap);
1805}
1806
5ca72c4f
AG		 1807static void ahci_handle_port_interrupt(struct ata_port *ap,
1808 void __iomem *port_mmio, u32 status)
365cfa1e 1809{
365cfa1e
AV		 1810 struct ata_eh_info *ehi = &ap->link.eh_info;
1811 struct ahci_port_priv *pp = ap->private_data;
1812 struct ahci_host_priv *hpriv = ap->host->private_data;
1813 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
5ca72c4f 1814 u32 qc_active = 0;
365cfa1e
AV		 1815 int rc;
1816
365cfa1e
AV		 1817 /* ignore BAD_PMP while resetting */
1818 if (unlikely(resetting))
1819 status &= ~PORT_IRQ_BAD_PMP;
1820
8393b811 1821 if (sata_lpm_ignore_phy_events(&ap->link)) {
365cfa1e 1822 status &= ~PORT_IRQ_PHYRDY;
6b7ae954 1823 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
365cfa1e
AV		 1824 }
1825
1826 if (unlikely(status & PORT_IRQ_ERROR)) {
1827 ahci_error_intr(ap, status);
1828 return;
1829 }
1830
1831 if (status & PORT_IRQ_SDB_FIS) {
1832 /* If SNotification is available, leave notification
1833 * handling to sata_async_notification(). If not,
1834 * emulate it by snooping SDB FIS RX area.
1835 *
1836 * Snooping FIS RX area is probably cheaper than
1837 * poking SNotification but some constrollers which
1838 * implement SNotification, ICH9 for example, don't
1839 * store AN SDB FIS into receive area.
1840 */
1841 if (hpriv->cap & HOST_CAP_SNTF)
1842 sata_async_notification(ap);
1843 else {
1844 /* If the 'N' bit in word 0 of the FIS is set,
1845 * we just received asynchronous notification.
1846 * Tell libata about it.
1847 *
1848 * Lack of SNotification should not appear in
1849 * ahci 1.2, so the workaround is unnecessary
1850 * when FBS is enabled.
1851 */
1852 if (pp->fbs_enabled)
1853 WARN_ON_ONCE(1);
1854 else {
1855 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1856 u32 f0 = le32_to_cpu(f[0]);
1857 if (f0 & (1 << 15))
1858 sata_async_notification(ap);
1859 }
1860 }
1861 }
1862
1863 /* pp->active_link is not reliable once FBS is enabled, both
1864 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1865 * NCQ and non-NCQ commands may be in flight at the same time.
1866 */
1867 if (pp->fbs_enabled) {
1868 if (ap->qc_active) {
1869 qc_active = readl(port_mmio + PORT_SCR_ACT);
1870 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1871 }
1872 } else {
1873 /* pp->active_link is valid iff any command is in flight */
1874 if (ap->qc_active && pp->active_link->sactive)
1875 qc_active = readl(port_mmio + PORT_SCR_ACT);
1876 else
1877 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1878 }
1879
1880
1881 rc = ata_qc_complete_multiple(ap, qc_active);
1882
1883 /* while resetting, invalid completions are expected */
1884 if (unlikely(rc < 0 && !resetting)) {
1885 ehi->err_mask |= AC_ERR_HSM;
1886 ehi->action |= ATA_EH_RESET;
1887 ata_port_freeze(ap);
1888 }
1889}
1890
7865f83f 1891static void ahci_port_intr(struct ata_port *ap)
5ca72c4f
AG		 1892{
1893 void __iomem *port_mmio = ahci_port_base(ap);
1894 u32 status;
1895
1896 status = readl(port_mmio + PORT_IRQ_STAT);
1897 writel(status, port_mmio + PORT_IRQ_STAT);
1898
7865f83f 1899 ahci_handle_port_interrupt(ap, port_mmio, status);
5ca72c4f
AG		 1900}
1901
a6b7fb76 1902static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
5ca72c4f
AG		 1903{
1904 struct ata_port *ap = dev_instance;
5ca72c4f 1905 void __iomem *port_mmio = ahci_port_base(ap);
5ca72c4f
AG		 1906 u32 status;
1907
5ca72c4f
AG		 1908 VPRINTK("ENTER\n");
1909
227dfb4d
AG		 1910 status = readl(port_mmio + PORT_IRQ_STAT);
1911 writel(status, port_mmio + PORT_IRQ_STAT);
5ca72c4f 1912
a6b7fb76
DW		 1913 spin_lock(ap->lock);
1914 ahci_handle_port_interrupt(ap, port_mmio, status);
1915 spin_unlock(ap->lock);
5ca72c4f
AG		 1916
1917 VPRINTK("EXIT\n");
1918
a6b7fb76 1919 return IRQ_HANDLED;
5ca72c4f 1920}
5ca72c4f 1921
f070d671 1922u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
365cfa1e 1923{
365cfa1e 1924 unsigned int i, handled = 0;
03e83cbd 1925
365cfa1e
AV		 1926 for (i = 0; i < host->n_ports; i++) {
1927 struct ata_port *ap;
1928
1929 if (!(irq_masked & (1 << i)))
1930 continue;
1931
1932 ap = host->ports[i];
1933 if (ap) {
7865f83f 1934 ahci_port_intr(ap);
365cfa1e
AV		 1935 VPRINTK("port %u\n", i);
1936 } else {
1937 VPRINTK("port %u (no irq)\n", i);
1938 if (ata_ratelimit())
a44fec1f
JP		 1939 dev_warn(host->dev,
1940 "interrupt on disabled port %u\n", i);
365cfa1e
AV		 1941 }
1942
1943 handled = 1;
1944 }
1945
a129db89
ST		 1946 return handled;
1947}
f070d671 1948EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
a129db89
ST		 1949
1950static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1951{
1952 struct ata_host *host = dev_instance;
1953 struct ahci_host_priv *hpriv;
1954 unsigned int rc = 0;
1955 void __iomem *mmio;
1956 u32 irq_stat, irq_masked;
1957
1958 VPRINTK("ENTER\n");
1959
1960 hpriv = host->private_data;
1961 mmio = hpriv->mmio;
1962
1963 /* sigh. 0xffffffff is a valid return from h/w */
1964 irq_stat = readl(mmio + HOST_IRQ_STAT);
1965 if (!irq_stat)
1966 return IRQ_NONE;
1967
1968 irq_masked = irq_stat & hpriv->port_map;
1969
1970 spin_lock(&host->lock);
1971
1972 rc = ahci_handle_port_intr(host, irq_masked);
365cfa1e
AV		 1973
1974 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1975 * it should be cleared after all the port events are cleared;
1976 * otherwise, it will raise a spurious interrupt after each
1977 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1978 * information.
1979 *
1980 * Also, use the unmasked value to clear interrupt as spurious
1981 * pending event on a dummy port might cause screaming IRQ.
1982 */
1983 writel(irq_stat, mmio + HOST_IRQ_STAT);
1984
03e83cbd
TH		 1985 spin_unlock(&host->lock);
1986
365cfa1e
AV		 1987 VPRINTK("EXIT\n");
1988
a129db89 1989 return IRQ_RETVAL(rc);
365cfa1e 1990}
365cfa1e 1991
39e0ee99 1992unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
365cfa1e
AV		 1993{
1994 struct ata_port *ap = qc->ap;
1995 void __iomem *port_mmio = ahci_port_base(ap);
1996 struct ahci_port_priv *pp = ap->private_data;
1997
1998 /* Keep track of the currently active link. It will be used
1999 * in completion path to determine whether NCQ phase is in
2000 * progress.
2001 */
2002 pp->active_link = qc->dev->link;
2003
179b310a 2004 if (ata_is_ncq(qc->tf.protocol))
365cfa1e
AV		 2005 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2006
2007 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2008 u32 fbs = readl(port_mmio + PORT_FBS);
2009 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2010 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2011 writel(fbs, port_mmio + PORT_FBS);
2012 pp->fbs_last_dev = qc->dev->link->pmp;
2013 }
2014
2015 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2016
2017 ahci_sw_activity(qc->dev->link);
2018
2019 return 0;
2020}
39e0ee99 2021EXPORT_SYMBOL_GPL(ahci_qc_issue);
365cfa1e
AV		 2022
2023static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2024{
2025 struct ahci_port_priv *pp = qc->ap->private_data;
6ad60195 2026 u8 *rx_fis = pp->rx_fis;
365cfa1e
AV		 2027
2028 if (pp->fbs_enabled)
6ad60195
TH		 2029 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2030
2031 /*
2032 * After a successful execution of an ATA PIO data-in command,
2033 * the device doesn't send D2H Reg FIS to update the TF and
2034 * the host should take TF and E_Status from the preceding PIO
2035 * Setup FIS.
2036 */
2037 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2038 !(qc->flags & ATA_QCFLAG_FAILED)) {
2039 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2040 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2041 } else
2042 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
365cfa1e 2043
365cfa1e
AV		 2044 return true;
2045}
2046
2047static void ahci_freeze(struct ata_port *ap)
2048{
2049 void __iomem *port_mmio = ahci_port_base(ap);
2050
2051 /* turn IRQ off */
2052 writel(0, port_mmio + PORT_IRQ_MASK);
2053}
2054
2055static void ahci_thaw(struct ata_port *ap)
2056{
2057 struct ahci_host_priv *hpriv = ap->host->private_data;
2058 void __iomem *mmio = hpriv->mmio;
2059 void __iomem *port_mmio = ahci_port_base(ap);
2060 u32 tmp;
2061 struct ahci_port_priv *pp = ap->private_data;
2062
2063 /* clear IRQ */
2064 tmp = readl(port_mmio + PORT_IRQ_STAT);
2065 writel(tmp, port_mmio + PORT_IRQ_STAT);
2066 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2067
2068 /* turn IRQ back on */
2069 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2070}
2071
8b789d89 2072void ahci_error_handler(struct ata_port *ap)
365cfa1e 2073{
039ece38
HG		 2074 struct ahci_host_priv *hpriv = ap->host->private_data;
2075
365cfa1e
AV		 2076 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2077 /* restart engine */
76ff34cf 2078 hpriv->stop_engine(ap);
039ece38 2079 hpriv->start_engine(ap);
365cfa1e
AV		 2080 }
2081
2082 sata_pmp_error_handler(ap);
0ee71952
TH		 2083
2084 if (!ata_dev_enabled(ap->link.device))
76ff34cf 2085 hpriv->stop_engine(ap);
365cfa1e 2086}
8b789d89 2087EXPORT_SYMBOL_GPL(ahci_error_handler);
365cfa1e
AV		 2088
2089static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2090{
2091 struct ata_port *ap = qc->ap;
2092
2093 /* make DMA engine forget about the failed command */
2094 if (qc->flags & ATA_QCFLAG_FAILED)
2095 ahci_kick_engine(ap);
2096}
2097
65fe1f0f
SH		 2098static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2099{
039ece38 2100 struct ahci_host_priv *hpriv = ap->host->private_data;
65fe1f0f
SH		 2101 void __iomem *port_mmio = ahci_port_base(ap);
2102 struct ata_device *dev = ap->link.device;
5c67e679 2103 u32 devslp, dm, dito, mdat, deto, dito_conf;
65fe1f0f
SH		 2104 int rc;
2105 unsigned int err_mask;
2106
2107 devslp = readl(port_mmio + PORT_DEVSLP);
2108 if (!(devslp & PORT_DEVSLP_DSP)) {
95bbbe9a 2109 dev_info(ap->host->dev, "port does not support device sleep\n");
65fe1f0f
SH		 2110 return;
2111 }
2112
2113 /* disable device sleep */
2114 if (!sleep) {
2115 if (devslp & PORT_DEVSLP_ADSE) {
2116 writel(devslp & ~PORT_DEVSLP_ADSE,
2117 port_mmio + PORT_DEVSLP);
2118 err_mask = ata_dev_set_feature(dev,
2119 SETFEATURES_SATA_DISABLE,
2120 SATA_DEVSLP);
2121 if (err_mask && err_mask != AC_ERR_DEV)
2122 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2123 }
2124 return;
2125 }
2126
5c67e679
SP		 2127 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2128 dito = devslp_idle_timeout / (dm + 1);
2129 if (dito > 0x3ff)
2130 dito = 0x3ff;
2131
2132 dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2133
2134 /* device sleep was already enabled and same dito */
2135 if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
65fe1f0f
SH		 2136 return;
2137
2138 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
76ff34cf 2139 rc = hpriv->stop_engine(ap);
65fe1f0f
SH		 2140 if (rc)
2141 return;
2142
65fe1f0f
SH		 2143 /* Use the nominal value 10 ms if the read MDAT is zero,
2144 * the nominal value of DETO is 20 ms.
2145 */
803739d2 2146 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
65fe1f0f 2147 ATA_LOG_DEVSLP_VALID_MASK) {
803739d2 2148 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
65fe1f0f
SH		 2149 ATA_LOG_DEVSLP_MDAT_MASK;
2150 if (!mdat)
2151 mdat = 10;
803739d2 2152 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
65fe1f0f
SH		 2153 if (!deto)
2154 deto = 20;
2155 } else {
2156 mdat = 10;
2157 deto = 20;
2158 }
2159
b9e4c350
SP		 2160 /* Make dito, mdat, deto bits to 0s */
2161 devslp &= ~GENMASK_ULL(24, 2);
65fe1f0f
SH		 2162 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2163 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2164 (deto << PORT_DEVSLP_DETO_OFFSET) |
2165 PORT_DEVSLP_ADSE);
2166 writel(devslp, port_mmio + PORT_DEVSLP);
2167
039ece38 2168 hpriv->start_engine(ap);
65fe1f0f
SH		 2169
2170 /* enable device sleep feature for the drive */
2171 err_mask = ata_dev_set_feature(dev,
2172 SETFEATURES_SATA_ENABLE,
2173 SATA_DEVSLP);
2174 if (err_mask && err_mask != AC_ERR_DEV)
2175 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2176}
2177
365cfa1e
AV		 2178static void ahci_enable_fbs(struct ata_port *ap)
2179{
039ece38 2180 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2181 struct ahci_port_priv *pp = ap->private_data;
2182 void __iomem *port_mmio = ahci_port_base(ap);
2183 u32 fbs;
2184 int rc;
2185
2186 if (!pp->fbs_supported)
2187 return;
2188
2189 fbs = readl(port_mmio + PORT_FBS);
2190 if (fbs & PORT_FBS_EN) {
2191 pp->fbs_enabled = true;
2192 pp->fbs_last_dev = -1; /* initialization */
2193 return;
2194 }
2195
76ff34cf 2196 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 2197 if (rc)
2198 return;
2199
2200 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2201 fbs = readl(port_mmio + PORT_FBS);
2202 if (fbs & PORT_FBS_EN) {
a44fec1f 2203 dev_info(ap->host->dev, "FBS is enabled\n");
365cfa1e
AV		 2204 pp->fbs_enabled = true;
2205 pp->fbs_last_dev = -1; /* initialization */
2206 } else
a44fec1f 2207 dev_err(ap->host->dev, "Failed to enable FBS\n");
365cfa1e 2208
039ece38 2209 hpriv->start_engine(ap);
365cfa1e
AV		 2210}
2211
2212static void ahci_disable_fbs(struct ata_port *ap)
2213{
039ece38 2214 struct ahci_host_priv *hpriv = ap->host->private_data;
365cfa1e
AV		 2215 struct ahci_port_priv *pp = ap->private_data;
2216 void __iomem *port_mmio = ahci_port_base(ap);
2217 u32 fbs;
2218 int rc;
2219
2220 if (!pp->fbs_supported)
2221 return;
2222
2223 fbs = readl(port_mmio + PORT_FBS);
2224 if ((fbs & PORT_FBS_EN) == 0) {
2225 pp->fbs_enabled = false;
2226 return;
2227 }
2228
76ff34cf 2229 rc = hpriv->stop_engine(ap);
365cfa1e
AV		 2230 if (rc)
2231 return;
2232
2233 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2234 fbs = readl(port_mmio + PORT_FBS);
2235 if (fbs & PORT_FBS_EN)
a44fec1f 2236 dev_err(ap->host->dev, "Failed to disable FBS\n");
365cfa1e 2237 else {
a44fec1f 2238 dev_info(ap->host->dev, "FBS is disabled\n");
365cfa1e
AV		 2239 pp->fbs_enabled = false;
2240 }
2241
039ece38 2242 hpriv->start_engine(ap);
365cfa1e
AV		 2243}
2244
2245static void ahci_pmp_attach(struct ata_port *ap)
2246{
2247 void __iomem *port_mmio = ahci_port_base(ap);
2248 struct ahci_port_priv *pp = ap->private_data;
2249 u32 cmd;
2250
2251 cmd = readl(port_mmio + PORT_CMD);
2252 cmd |= PORT_CMD_PMP;
2253 writel(cmd, port_mmio + PORT_CMD);
2254
2255 ahci_enable_fbs(ap);
2256
2257 pp->intr_mask |= PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2258
2259 /*
2260 * We must not change the port interrupt mask register if the
2261 * port is marked frozen, the value in pp->intr_mask will be
2262 * restored later when the port is thawed.
2263 *
2264 * Note that during initialization, the port is marked as
2265 * frozen since the irq handler is not yet registered.
2266 */
2267 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2268 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2269}
2270
2271static void ahci_pmp_detach(struct ata_port *ap)
2272{
2273 void __iomem *port_mmio = ahci_port_base(ap);
2274 struct ahci_port_priv *pp = ap->private_data;
2275 u32 cmd;
2276
2277 ahci_disable_fbs(ap);
2278
2279 cmd = readl(port_mmio + PORT_CMD);
2280 cmd &= ~PORT_CMD_PMP;
2281 writel(cmd, port_mmio + PORT_CMD);
2282
2283 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
7b3a24c5
MB		 2284
2285 /* see comment above in ahci_pmp_attach() */
2286 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2287 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
365cfa1e
AV		 2288}
2289
02cdfcf0 2290int ahci_port_resume(struct ata_port *ap)
365cfa1e 2291{
bb03c640
MW		 2292 ahci_rpm_get_port(ap);
2293
365cfa1e
AV		 2294 ahci_power_up(ap);
2295 ahci_start_port(ap);
2296
2297 if (sata_pmp_attached(ap))
2298 ahci_pmp_attach(ap);
2299 else
2300 ahci_pmp_detach(ap);
2301
2302 return 0;
2303}
02cdfcf0 2304EXPORT_SYMBOL_GPL(ahci_port_resume);
365cfa1e
AV		 2305
2306#ifdef CONFIG_PM
2307static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2308{
2309 const char *emsg = NULL;
2310 int rc;
2311
2312 rc = ahci_deinit_port(ap, &emsg);
2313 if (rc == 0)
2314 ahci_power_down(ap);
2315 else {
a9a79dfe 2316 ata_port_err(ap, "%s (%d)\n", emsg, rc);
7faa33da 2317 ata_port_freeze(ap);
365cfa1e
AV		 2318 }
2319
bb03c640 2320 ahci_rpm_put_port(ap);
365cfa1e
AV		 2321 return rc;
2322}
2323#endif
2324
2325static int ahci_port_start(struct ata_port *ap)
2326{
2327 struct ahci_host_priv *hpriv = ap->host->private_data;
2328 struct device *dev = ap->host->dev;
2329 struct ahci_port_priv *pp;
2330 void *mem;
2331 dma_addr_t mem_dma;
2332 size_t dma_sz, rx_fis_sz;
2333
2334 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2335 if (!pp)
2336 return -ENOMEM;
2337
b29900e6
AG		 2338 if (ap->host->n_ports > 1) {
2339 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2340 if (!pp->irq_desc) {
2341 devm_kfree(dev, pp);
2342 return -ENOMEM;
2343 }
2344 snprintf(pp->irq_desc, 8,
2345 "%s%d", dev_driver_string(dev), ap->port_no);
2346 }
2347
365cfa1e
AV		 2348 /* check FBS capability */
2349 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2350 void __iomem *port_mmio = ahci_port_base(ap);
2351 u32 cmd = readl(port_mmio + PORT_CMD);
2352 if (cmd & PORT_CMD_FBSCP)
2353 pp->fbs_supported = true;
5f173107 2354 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
a44fec1f
JP		 2355 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2356 ap->port_no);
5f173107
TH		 2357 pp->fbs_supported = true;
2358 } else
a44fec1f
JP		 2359 dev_warn(dev, "port %d is not capable of FBS\n",
2360 ap->port_no);
365cfa1e
AV		 2361 }
2362
2363 if (pp->fbs_supported) {
2364 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2365 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2366 } else {
2367 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2368 rx_fis_sz = AHCI_RX_FIS_SZ;
2369 }
2370
2371 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2372 if (!mem)
2373 return -ENOMEM;
2374 memset(mem, 0, dma_sz);
2375
2376 /*
2377 * First item in chunk of DMA memory: 32-slot command table,
2378 * 32 bytes each in size
2379 */
2380 pp->cmd_slot = mem;
2381 pp->cmd_slot_dma = mem_dma;
2382
2383 mem += AHCI_CMD_SLOT_SZ;
2384 mem_dma += AHCI_CMD_SLOT_SZ;
2385
2386 /*
2387 * Second item: Received-FIS area
2388 */
2389 pp->rx_fis = mem;
2390 pp->rx_fis_dma = mem_dma;
2391
2392 mem += rx_fis_sz;
2393 mem_dma += rx_fis_sz;
2394
2395 /*
2396 * Third item: data area for storing a single command
2397 * and its scatter-gather table
2398 */
2399 pp->cmd_tbl = mem;
2400 pp->cmd_tbl_dma = mem_dma;
2401
2402 /*
2403 * Save off initial list of interrupts to be enabled.
2404 * This could be changed later
2405 */
2406 pp->intr_mask = DEF_PORT_IRQ;
2407
7865f83f
TH		 2408 /*
2409 * Switch to per-port locking in case each port has its own MSI vector.
2410 */
0b9e2988 2411 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
7865f83f
TH		 2412 spin_lock_init(&pp->lock);
2413 ap->lock = &pp->lock;
2414 }
5ca72c4f 2415
365cfa1e
AV		 2416 ap->private_data = pp;
2417
2418 /* engage engines, captain */
2419 return ahci_port_resume(ap);
2420}
2421
2422static void ahci_port_stop(struct ata_port *ap)
2423{
2424 const char *emsg = NULL;
0516900a
PR		 2425 struct ahci_host_priv *hpriv = ap->host->private_data;
2426 void __iomem *host_mmio = hpriv->mmio;
365cfa1e
AV		 2427 int rc;
2428
2429 /* de-initialize port */
2430 rc = ahci_deinit_port(ap, &emsg);
2431 if (rc)
a9a79dfe 2432 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
0516900a
PR		 2433
2434 /*
2435 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2436 * re-enabling INTx.
2437 */
2438 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
365cfa1e
AV		 2439}
2440
2441void ahci_print_info(struct ata_host *host, const char *scc_s)
2442{
2443 struct ahci_host_priv *hpriv = host->private_data;
365cfa1e
AV		 2444 u32 vers, cap, cap2, impl, speed;
2445 const char *speed_s;
2446
8ea909cb 2447 vers = hpriv->version;
365cfa1e
AV		 2448 cap = hpriv->cap;
2449 cap2 = hpriv->cap2;
2450 impl = hpriv->port_map;
2451
2452 speed = (cap >> 20) & 0xf;
2453 if (speed == 1)
2454 speed_s = "1.5";
2455 else if (speed == 2)
2456 speed_s = "3";
2457 else if (speed == 3)
2458 speed_s = "6";
2459 else
2460 speed_s = "?";
2461
2462 dev_info(host->dev,
2463 "AHCI %02x%02x.%02x%02x "
2464 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2465 ,
2466
2467 (vers >> 24) & 0xff,
2468 (vers >> 16) & 0xff,
2469 (vers >> 8) & 0xff,
2470 vers & 0xff,
2471
2472 ((cap >> 8) & 0x1f) + 1,
2473 (cap & 0x1f) + 1,
2474 speed_s,
2475 impl,
2476 scc_s);
2477
2478 dev_info(host->dev,
2479 "flags: "
2480 "%s%s%s%s%s%s%s"
2481 "%s%s%s%s%s%s%s"
65fe1f0f
SH		 2482 "%s%s%s%s%s%s%s"
2483 "%s%s\n"
365cfa1e
AV		 2484 ,
2485
2486 cap & HOST_CAP_64 ? "64bit " : "",
2487 cap & HOST_CAP_NCQ ? "ncq " : "",
2488 cap & HOST_CAP_SNTF ? "sntf " : "",
2489 cap & HOST_CAP_MPS ? "ilck " : "",
2490 cap & HOST_CAP_SSS ? "stag " : "",
2491 cap & HOST_CAP_ALPM ? "pm " : "",
2492 cap & HOST_CAP_LED ? "led " : "",
2493 cap & HOST_CAP_CLO ? "clo " : "",
2494 cap & HOST_CAP_ONLY ? "only " : "",
2495 cap & HOST_CAP_PMP ? "pmp " : "",
2496 cap & HOST_CAP_FBS ? "fbs " : "",
2497 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2498 cap & HOST_CAP_SSC ? "slum " : "",
2499 cap & HOST_CAP_PART ? "part " : "",
2500 cap & HOST_CAP_CCC ? "ccc " : "",
2501 cap & HOST_CAP_EMS ? "ems " : "",
2502 cap & HOST_CAP_SXS ? "sxs " : "",
65fe1f0f
SH		 2503 cap2 & HOST_CAP2_DESO ? "deso " : "",
2504 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2505 cap2 & HOST_CAP2_SDS ? "sds " : "",
365cfa1e
AV		 2506 cap2 & HOST_CAP2_APST ? "apst " : "",
2507 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2508 cap2 & HOST_CAP2_BOH ? "boh " : ""
2509 );
2510}
2511EXPORT_SYMBOL_GPL(ahci_print_info);
2512
2513void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2514 struct ata_port_info *pi)
2515{
2516 u8 messages;
2517 void __iomem *mmio = hpriv->mmio;
2518 u32 em_loc = readl(mmio + HOST_EM_LOC);
2519 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2520
2521 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2522 return;
2523
2524 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2525
008dbd61 2526 if (messages) {
365cfa1e
AV		 2527 /* store em_loc */
2528 hpriv->em_loc = ((em_loc >> 16) * 4);
c0623166 2529 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
008dbd61 2530 hpriv->em_msg_type = messages;
365cfa1e
AV		 2531 pi->flags |= ATA_FLAG_EM;
2532 if (!(em_ctl & EM_CTL_ALHD))
2533 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2534 }
2535}
2536EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2537
d684a90d 2538static int ahci_host_activate_multi_irqs(struct ata_host *host,
d1028e2f 2539 struct scsi_host_template *sht)
1c62854f 2540{
d684a90d 2541 struct ahci_host_priv *hpriv = host->private_data;
1c62854f
AG		 2542 int i, rc;
2543
2544 rc = ata_host_start(host);
2545 if (rc)
2546 return rc;
21bfd1aa
RR		 2547 /*
2548 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2549 * allocated. That is one MSI per port, starting from @irq.
2550 */
1c62854f
AG		 2551 for (i = 0; i < host->n_ports; i++) {
2552 struct ahci_port_priv *pp = host->ports[i]->private_data;
0b9e2988 2553 int irq = hpriv->get_irq_vector(host, i);
1c62854f
AG		 2554
2555 /* Do not receive interrupts sent by dummy ports */
2556 if (!pp) {
9b4b3f6a 2557 disable_irq(irq);
1c62854f
AG		 2558 continue;
2559 }
2560
a6b7fb76
DW		 2561 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2562 0, pp->irq_desc, host->ports[i]);
2563
1c62854f 2564 if (rc)
0a142b26 2565 return rc;
d684a90d 2566 ata_port_desc(host->ports[i], "irq %d", irq);
0a142b26 2567 }
d684a90d 2568
0a142b26 2569 return ata_host_register(host, sht);
1c62854f 2570}
d1028e2f
AG		 2571
2572/**
2573 * ahci_host_activate - start AHCI host, request IRQs and register it
2574 * @host: target ATA host
d1028e2f
AG		 2575 * @sht: scsi_host_template to use when registering the host
2576 *
d1028e2f
AG		 2577 * LOCKING:
2578 * Inherited from calling layer (may sleep).
2579 *
2580 * RETURNS:
2581 * 0 on success, -errno otherwise.
2582 */
21bfd1aa 2583int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
d1028e2f
AG		 2584{
2585 struct ahci_host_priv *hpriv = host->private_data;
21bfd1aa 2586 int irq = hpriv->irq;
d1028e2f
AG		 2587 int rc;
2588
0b9e2988 2589 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
f070d671 2590 if (hpriv->irq_handler)
d991c872
SE		 2591 dev_warn(host->dev,
2592 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
0b9e2988
CH		 2593 if (!hpriv->get_irq_vector) {
2594 dev_err(host->dev,
2595 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2596 return -EIO;
2597 }
f070d671 2598
d684a90d 2599 rc = ahci_host_activate_multi_irqs(host, sht);
f070d671
ST		 2600 } else {
2601 rc = ata_host_activate(host, irq, hpriv->irq_handler,
7865f83f 2602 IRQF_SHARED, sht);
f070d671
ST		 2603 }
2604
2605
d1028e2f
AG		 2606 return rc;
2607}
1c62854f
AG		 2608EXPORT_SYMBOL_GPL(ahci_host_activate);
2609
365cfa1e
AV		 2610MODULE_AUTHOR("Jeff Garzik");
2611MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2612MODULE_LICENSE("GPL");
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