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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
624d5c51 | 38 | #include <linux/highmem.h> |
1fdffbce JG |
39 | |
40 | #include "libata.h" | |
41 | ||
624d5c51 TH |
42 | const struct ata_port_operations ata_sff_port_ops = { |
43 | .inherits = &ata_base_port_ops, | |
44 | ||
9363c382 TH |
45 | .qc_prep = ata_sff_qc_prep, |
46 | .qc_issue = ata_sff_qc_issue, | |
47 | ||
48 | .freeze = ata_sff_freeze, | |
49 | .thaw = ata_sff_thaw, | |
0aa1113d | 50 | .prereset = ata_sff_prereset, |
9363c382 | 51 | .softreset = ata_sff_softreset, |
57c9efdf | 52 | .hardreset = sata_sff_hardreset, |
203c75b8 | 53 | .postreset = ata_sff_postreset, |
9363c382 TH |
54 | .error_handler = ata_sff_error_handler, |
55 | .post_internal_cmd = ata_sff_post_internal_cmd, | |
56 | ||
5682ed33 TH |
57 | .sff_dev_select = ata_sff_dev_select, |
58 | .sff_check_status = ata_sff_check_status, | |
59 | .sff_tf_load = ata_sff_tf_load, | |
60 | .sff_tf_read = ata_sff_tf_read, | |
61 | .sff_exec_command = ata_sff_exec_command, | |
62 | .sff_data_xfer = ata_sff_data_xfer, | |
63 | .sff_irq_on = ata_sff_irq_on, | |
288623a0 | 64 | .sff_irq_clear = ata_sff_irq_clear, |
624d5c51 TH |
65 | |
66 | .port_start = ata_sff_port_start, | |
67 | }; | |
68 | ||
69 | const struct ata_port_operations ata_bmdma_port_ops = { | |
70 | .inherits = &ata_sff_port_ops, | |
71 | ||
9363c382 | 72 | .mode_filter = ata_bmdma_mode_filter, |
624d5c51 TH |
73 | |
74 | .bmdma_setup = ata_bmdma_setup, | |
75 | .bmdma_start = ata_bmdma_start, | |
76 | .bmdma_stop = ata_bmdma_stop, | |
77 | .bmdma_status = ata_bmdma_status, | |
624d5c51 TH |
78 | }; |
79 | ||
80 | /** | |
81 | * ata_fill_sg - Fill PCI IDE PRD table | |
82 | * @qc: Metadata associated with taskfile to be transferred | |
83 | * | |
84 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
85 | * associated with the current disk command. | |
86 | * | |
87 | * LOCKING: | |
88 | * spin_lock_irqsave(host lock) | |
89 | * | |
90 | */ | |
91 | static void ata_fill_sg(struct ata_queued_cmd *qc) | |
92 | { | |
93 | struct ata_port *ap = qc->ap; | |
94 | struct scatterlist *sg; | |
95 | unsigned int si, pi; | |
96 | ||
97 | pi = 0; | |
98 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
99 | u32 addr, offset; | |
100 | u32 sg_len, len; | |
101 | ||
102 | /* determine if physical DMA addr spans 64K boundary. | |
103 | * Note h/w doesn't support 64-bit, so we unconditionally | |
104 | * truncate dma_addr_t to u32. | |
105 | */ | |
106 | addr = (u32) sg_dma_address(sg); | |
107 | sg_len = sg_dma_len(sg); | |
108 | ||
109 | while (sg_len) { | |
110 | offset = addr & 0xffff; | |
111 | len = sg_len; | |
112 | if ((offset + sg_len) > 0x10000) | |
113 | len = 0x10000 - offset; | |
114 | ||
115 | ap->prd[pi].addr = cpu_to_le32(addr); | |
116 | ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
117 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
118 | ||
119 | pi++; | |
120 | sg_len -= len; | |
121 | addr += len; | |
122 | } | |
123 | } | |
124 | ||
125 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
126 | } | |
127 | ||
128 | /** | |
129 | * ata_fill_sg_dumb - Fill PCI IDE PRD table | |
130 | * @qc: Metadata associated with taskfile to be transferred | |
131 | * | |
132 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
133 | * associated with the current disk command. Perform the fill | |
134 | * so that we avoid writing any length 64K records for | |
135 | * controllers that don't follow the spec. | |
136 | * | |
137 | * LOCKING: | |
138 | * spin_lock_irqsave(host lock) | |
139 | * | |
140 | */ | |
141 | static void ata_fill_sg_dumb(struct ata_queued_cmd *qc) | |
142 | { | |
143 | struct ata_port *ap = qc->ap; | |
144 | struct scatterlist *sg; | |
145 | unsigned int si, pi; | |
146 | ||
147 | pi = 0; | |
148 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
149 | u32 addr, offset; | |
150 | u32 sg_len, len, blen; | |
151 | ||
152 | /* determine if physical DMA addr spans 64K boundary. | |
153 | * Note h/w doesn't support 64-bit, so we unconditionally | |
154 | * truncate dma_addr_t to u32. | |
155 | */ | |
156 | addr = (u32) sg_dma_address(sg); | |
157 | sg_len = sg_dma_len(sg); | |
158 | ||
159 | while (sg_len) { | |
160 | offset = addr & 0xffff; | |
161 | len = sg_len; | |
162 | if ((offset + sg_len) > 0x10000) | |
163 | len = 0x10000 - offset; | |
164 | ||
165 | blen = len & 0xffff; | |
166 | ap->prd[pi].addr = cpu_to_le32(addr); | |
167 | if (blen == 0) { | |
168 | /* Some PATA chipsets like the CS5530 can't | |
169 | cope with 0x0000 meaning 64K as the spec says */ | |
170 | ap->prd[pi].flags_len = cpu_to_le32(0x8000); | |
171 | blen = 0x8000; | |
172 | ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000); | |
173 | } | |
174 | ap->prd[pi].flags_len = cpu_to_le32(blen); | |
175 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
176 | ||
177 | pi++; | |
178 | sg_len -= len; | |
179 | addr += len; | |
180 | } | |
181 | } | |
182 | ||
183 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
184 | } | |
185 | ||
186 | /** | |
9363c382 | 187 | * ata_sff_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
188 | * @qc: Metadata associated with taskfile to be prepared |
189 | * | |
190 | * Prepare ATA taskfile for submission. | |
191 | * | |
192 | * LOCKING: | |
193 | * spin_lock_irqsave(host lock) | |
194 | */ | |
9363c382 | 195 | void ata_sff_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
196 | { |
197 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
198 | return; | |
199 | ||
200 | ata_fill_sg(qc); | |
201 | } | |
202 | ||
203 | /** | |
9363c382 | 204 | * ata_sff_dumb_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
205 | * @qc: Metadata associated with taskfile to be prepared |
206 | * | |
207 | * Prepare ATA taskfile for submission. | |
208 | * | |
209 | * LOCKING: | |
210 | * spin_lock_irqsave(host lock) | |
211 | */ | |
9363c382 | 212 | void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
213 | { |
214 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
215 | return; | |
216 | ||
217 | ata_fill_sg_dumb(qc); | |
218 | } | |
219 | ||
272f7884 | 220 | /** |
9363c382 | 221 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
222 | * @ap: port where the device is |
223 | * | |
224 | * Reads ATA taskfile status register for currently-selected device | |
225 | * and return its value. This also clears pending interrupts | |
226 | * from this device | |
227 | * | |
228 | * LOCKING: | |
229 | * Inherited from caller. | |
230 | */ | |
9363c382 | 231 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
232 | { |
233 | return ioread8(ap->ioaddr.status_addr); | |
234 | } | |
235 | ||
236 | /** | |
9363c382 | 237 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
238 | * @ap: port where the device is |
239 | * | |
240 | * Reads ATA taskfile alternate status register for | |
241 | * currently-selected device and return its value. | |
242 | * | |
243 | * Note: may NOT be used as the check_altstatus() entry in | |
244 | * ata_port_operations. | |
245 | * | |
246 | * LOCKING: | |
247 | * Inherited from caller. | |
248 | */ | |
9363c382 | 249 | u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 250 | { |
5682ed33 TH |
251 | if (ap->ops->sff_check_altstatus) |
252 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
253 | |
254 | return ioread8(ap->ioaddr.altstatus_addr); | |
255 | } | |
256 | ||
257 | /** | |
9363c382 | 258 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 TH |
259 | * @ap: port containing status register to be polled |
260 | * @tmout_pat: impatience timeout | |
261 | * @tmout: overall timeout | |
262 | * | |
263 | * Sleep until ATA Status register bit BSY clears, | |
264 | * or a timeout occurs. | |
265 | * | |
266 | * LOCKING: | |
267 | * Kernel thread context (may sleep). | |
268 | * | |
269 | * RETURNS: | |
270 | * 0 on success, -errno otherwise. | |
271 | */ | |
9363c382 TH |
272 | int ata_sff_busy_sleep(struct ata_port *ap, |
273 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
274 | { |
275 | unsigned long timer_start, timeout; | |
276 | u8 status; | |
277 | ||
9363c382 | 278 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 TH |
279 | timer_start = jiffies; |
280 | timeout = timer_start + tmout_pat; | |
281 | while (status != 0xff && (status & ATA_BUSY) && | |
282 | time_before(jiffies, timeout)) { | |
283 | msleep(50); | |
9363c382 | 284 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
285 | } |
286 | ||
287 | if (status != 0xff && (status & ATA_BUSY)) | |
288 | ata_port_printk(ap, KERN_WARNING, | |
289 | "port is slow to respond, please be patient " | |
290 | "(Status 0x%x)\n", status); | |
291 | ||
292 | timeout = timer_start + tmout; | |
293 | while (status != 0xff && (status & ATA_BUSY) && | |
294 | time_before(jiffies, timeout)) { | |
295 | msleep(50); | |
5682ed33 | 296 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
297 | } |
298 | ||
299 | if (status == 0xff) | |
300 | return -ENODEV; | |
301 | ||
302 | if (status & ATA_BUSY) { | |
303 | ata_port_printk(ap, KERN_ERR, "port failed to respond " | |
304 | "(%lu secs, Status 0x%x)\n", | |
305 | tmout / HZ, status); | |
306 | return -EBUSY; | |
307 | } | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
aa2731ad TH |
312 | static int ata_sff_check_ready(struct ata_link *link) |
313 | { | |
314 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
315 | ||
316 | if (!(status & ATA_BUSY)) | |
317 | return 1; | |
318 | if (status == 0xff) | |
319 | return -ENODEV; | |
320 | return 0; | |
321 | } | |
322 | ||
624d5c51 | 323 | /** |
9363c382 | 324 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 325 | * @link: SFF link to wait ready status for |
624d5c51 TH |
326 | * @deadline: deadline jiffies for the operation |
327 | * | |
328 | * Sleep until ATA Status register bit BSY clears, or timeout | |
329 | * occurs. | |
330 | * | |
331 | * LOCKING: | |
332 | * Kernel thread context (may sleep). | |
333 | * | |
334 | * RETURNS: | |
335 | * 0 on success, -errno otherwise. | |
336 | */ | |
705e76be | 337 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 338 | { |
aa2731ad | 339 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 TH |
340 | } |
341 | ||
342 | /** | |
9363c382 | 343 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
344 | * @ap: ATA channel to manipulate |
345 | * @device: ATA device (numbered from zero) to select | |
346 | * | |
347 | * Use the method defined in the ATA specification to | |
348 | * make either device 0, or device 1, active on the | |
349 | * ATA channel. Works with both PIO and MMIO. | |
350 | * | |
351 | * May be used as the dev_select() entry in ata_port_operations. | |
352 | * | |
353 | * LOCKING: | |
354 | * caller. | |
355 | */ | |
9363c382 | 356 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
357 | { |
358 | u8 tmp; | |
359 | ||
360 | if (device == 0) | |
361 | tmp = ATA_DEVICE_OBS; | |
362 | else | |
363 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
364 | ||
365 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 366 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 TH |
367 | } |
368 | ||
369 | /** | |
370 | * ata_dev_select - Select device 0/1 on ATA bus | |
371 | * @ap: ATA channel to manipulate | |
372 | * @device: ATA device (numbered from zero) to select | |
373 | * @wait: non-zero to wait for Status register BSY bit to clear | |
374 | * @can_sleep: non-zero if context allows sleeping | |
375 | * | |
376 | * Use the method defined in the ATA specification to | |
377 | * make either device 0, or device 1, active on the | |
378 | * ATA channel. | |
379 | * | |
9363c382 TH |
380 | * This is a high-level version of ata_sff_dev_select(), which |
381 | * additionally provides the services of inserting the proper | |
382 | * pauses and status polling, where needed. | |
624d5c51 TH |
383 | * |
384 | * LOCKING: | |
385 | * caller. | |
386 | */ | |
387 | void ata_dev_select(struct ata_port *ap, unsigned int device, | |
388 | unsigned int wait, unsigned int can_sleep) | |
389 | { | |
390 | if (ata_msg_probe(ap)) | |
391 | ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, " | |
392 | "device %u, wait %u\n", device, wait); | |
393 | ||
394 | if (wait) | |
395 | ata_wait_idle(ap); | |
396 | ||
5682ed33 | 397 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
398 | |
399 | if (wait) { | |
400 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
401 | msleep(150); | |
402 | ata_wait_idle(ap); | |
403 | } | |
404 | } | |
405 | ||
406 | /** | |
9363c382 | 407 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
408 | * @ap: Port on which interrupts are enabled. |
409 | * | |
410 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
411 | * wait for idle, clear any pending interrupts. | |
412 | * | |
413 | * LOCKING: | |
414 | * Inherited from caller. | |
415 | */ | |
9363c382 | 416 | u8 ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
417 | { |
418 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
419 | u8 tmp; | |
420 | ||
421 | ap->ctl &= ~ATA_NIEN; | |
422 | ap->last_ctl = ap->ctl; | |
423 | ||
424 | if (ioaddr->ctl_addr) | |
425 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
426 | tmp = ata_wait_idle(ap); | |
427 | ||
5682ed33 | 428 | ap->ops->sff_irq_clear(ap); |
624d5c51 TH |
429 | |
430 | return tmp; | |
431 | } | |
432 | ||
433 | /** | |
9363c382 | 434 | * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt. |
624d5c51 TH |
435 | * @ap: Port associated with this ATA transaction. |
436 | * | |
437 | * Clear interrupt and error flags in DMA status register. | |
438 | * | |
439 | * May be used as the irq_clear() entry in ata_port_operations. | |
440 | * | |
441 | * LOCKING: | |
442 | * spin_lock_irqsave(host lock) | |
443 | */ | |
9363c382 | 444 | void ata_sff_irq_clear(struct ata_port *ap) |
624d5c51 TH |
445 | { |
446 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
447 | ||
448 | if (!mmio) | |
449 | return; | |
450 | ||
451 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
452 | } | |
453 | ||
454 | /** | |
9363c382 | 455 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
456 | * @ap: Port to which output is sent |
457 | * @tf: ATA taskfile register set | |
458 | * | |
459 | * Outputs ATA taskfile to standard ATA host controller. | |
460 | * | |
461 | * LOCKING: | |
462 | * Inherited from caller. | |
463 | */ | |
9363c382 | 464 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
465 | { |
466 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
467 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
468 | ||
469 | if (tf->ctl != ap->last_ctl) { | |
470 | if (ioaddr->ctl_addr) | |
471 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
472 | ap->last_ctl = tf->ctl; | |
473 | ata_wait_idle(ap); | |
474 | } | |
475 | ||
476 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
477 | WARN_ON(!ioaddr->ctl_addr); | |
478 | iowrite8(tf->hob_feature, ioaddr->feature_addr); | |
479 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
480 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
481 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
482 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
483 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
484 | tf->hob_feature, | |
485 | tf->hob_nsect, | |
486 | tf->hob_lbal, | |
487 | tf->hob_lbam, | |
488 | tf->hob_lbah); | |
489 | } | |
490 | ||
491 | if (is_addr) { | |
492 | iowrite8(tf->feature, ioaddr->feature_addr); | |
493 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
494 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
495 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
496 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
497 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
498 | tf->feature, | |
499 | tf->nsect, | |
500 | tf->lbal, | |
501 | tf->lbam, | |
502 | tf->lbah); | |
503 | } | |
504 | ||
505 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
506 | iowrite8(tf->device, ioaddr->device_addr); | |
507 | VPRINTK("device 0x%X\n", tf->device); | |
508 | } | |
509 | ||
510 | ata_wait_idle(ap); | |
511 | } | |
512 | ||
513 | /** | |
9363c382 | 514 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
515 | * @ap: Port from which input is read |
516 | * @tf: ATA taskfile register set for storing input | |
517 | * | |
518 | * Reads ATA taskfile registers for currently-selected device | |
519 | * into @tf. Assumes the device has a fully SFF compliant task file | |
520 | * layout and behaviour. If you device does not (eg has a different | |
521 | * status method) then you will need to provide a replacement tf_read | |
522 | * | |
523 | * LOCKING: | |
524 | * Inherited from caller. | |
525 | */ | |
9363c382 | 526 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
527 | { |
528 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
529 | ||
9363c382 | 530 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
531 | tf->feature = ioread8(ioaddr->error_addr); |
532 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
533 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
534 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
535 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
536 | tf->device = ioread8(ioaddr->device_addr); | |
537 | ||
538 | if (tf->flags & ATA_TFLAG_LBA48) { | |
539 | if (likely(ioaddr->ctl_addr)) { | |
540 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
541 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
542 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
543 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
544 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
545 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
546 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
547 | ap->last_ctl = tf->ctl; | |
548 | } else | |
549 | WARN_ON(1); | |
550 | } | |
551 | } | |
552 | ||
553 | /** | |
9363c382 | 554 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
555 | * @ap: port to which command is being issued |
556 | * @tf: ATA taskfile register set | |
557 | * | |
558 | * Issues ATA command, with proper synchronization with interrupt | |
559 | * handler / other threads. | |
560 | * | |
561 | * LOCKING: | |
562 | * spin_lock_irqsave(host lock) | |
563 | */ | |
9363c382 | 564 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
565 | { |
566 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
567 | ||
568 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 569 | ata_sff_pause(ap); |
624d5c51 TH |
570 | } |
571 | ||
572 | /** | |
573 | * ata_tf_to_host - issue ATA taskfile to host controller | |
574 | * @ap: port to which command is being issued | |
575 | * @tf: ATA taskfile register set | |
576 | * | |
577 | * Issues ATA taskfile register set to ATA host controller, | |
578 | * with proper synchronization with interrupt handler and | |
579 | * other threads. | |
580 | * | |
581 | * LOCKING: | |
582 | * spin_lock_irqsave(host lock) | |
583 | */ | |
584 | static inline void ata_tf_to_host(struct ata_port *ap, | |
585 | const struct ata_taskfile *tf) | |
586 | { | |
5682ed33 TH |
587 | ap->ops->sff_tf_load(ap, tf); |
588 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
589 | } |
590 | ||
591 | /** | |
9363c382 | 592 | * ata_sff_data_xfer - Transfer data by PIO |
624d5c51 TH |
593 | * @dev: device to target |
594 | * @buf: data buffer | |
595 | * @buflen: buffer length | |
596 | * @rw: read/write | |
597 | * | |
598 | * Transfer data from/to the device data register by PIO. | |
599 | * | |
600 | * LOCKING: | |
601 | * Inherited from caller. | |
602 | * | |
603 | * RETURNS: | |
604 | * Bytes consumed. | |
605 | */ | |
9363c382 TH |
606 | unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, |
607 | unsigned int buflen, int rw) | |
624d5c51 TH |
608 | { |
609 | struct ata_port *ap = dev->link->ap; | |
610 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
611 | unsigned int words = buflen >> 1; | |
612 | ||
613 | /* Transfer multiple of 2 bytes */ | |
614 | if (rw == READ) | |
615 | ioread16_rep(data_addr, buf, words); | |
616 | else | |
617 | iowrite16_rep(data_addr, buf, words); | |
618 | ||
619 | /* Transfer trailing 1 byte, if any. */ | |
620 | if (unlikely(buflen & 0x01)) { | |
621 | __le16 align_buf[1] = { 0 }; | |
622 | unsigned char *trailing_buf = buf + buflen - 1; | |
623 | ||
624 | if (rw == READ) { | |
625 | align_buf[0] = cpu_to_le16(ioread16(data_addr)); | |
626 | memcpy(trailing_buf, align_buf, 1); | |
627 | } else { | |
628 | memcpy(align_buf, trailing_buf, 1); | |
629 | iowrite16(le16_to_cpu(align_buf[0]), data_addr); | |
630 | } | |
631 | words++; | |
632 | } | |
633 | ||
634 | return words << 1; | |
635 | } | |
636 | ||
637 | /** | |
9363c382 | 638 | * ata_sff_data_xfer_noirq - Transfer data by PIO |
624d5c51 TH |
639 | * @dev: device to target |
640 | * @buf: data buffer | |
641 | * @buflen: buffer length | |
642 | * @rw: read/write | |
643 | * | |
644 | * Transfer data from/to the device data register by PIO. Do the | |
645 | * transfer with interrupts disabled. | |
646 | * | |
647 | * LOCKING: | |
648 | * Inherited from caller. | |
649 | * | |
650 | * RETURNS: | |
651 | * Bytes consumed. | |
652 | */ | |
9363c382 TH |
653 | unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, |
654 | unsigned int buflen, int rw) | |
624d5c51 TH |
655 | { |
656 | unsigned long flags; | |
657 | unsigned int consumed; | |
658 | ||
659 | local_irq_save(flags); | |
9363c382 | 660 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); |
624d5c51 TH |
661 | local_irq_restore(flags); |
662 | ||
663 | return consumed; | |
664 | } | |
665 | ||
666 | /** | |
667 | * ata_pio_sector - Transfer a sector of data. | |
668 | * @qc: Command on going | |
669 | * | |
670 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
671 | * | |
672 | * LOCKING: | |
673 | * Inherited from caller. | |
674 | */ | |
675 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
676 | { | |
677 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
678 | struct ata_port *ap = qc->ap; | |
679 | struct page *page; | |
680 | unsigned int offset; | |
681 | unsigned char *buf; | |
682 | ||
683 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
684 | ap->hsm_task_state = HSM_ST_LAST; | |
685 | ||
686 | page = sg_page(qc->cursg); | |
687 | offset = qc->cursg->offset + qc->cursg_ofs; | |
688 | ||
689 | /* get the current page and offset */ | |
690 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
691 | offset %= PAGE_SIZE; | |
692 | ||
693 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
694 | ||
695 | if (PageHighMem(page)) { | |
696 | unsigned long flags; | |
697 | ||
698 | /* FIXME: use a bounce buffer */ | |
699 | local_irq_save(flags); | |
700 | buf = kmap_atomic(page, KM_IRQ0); | |
701 | ||
702 | /* do the actual data transfer */ | |
5682ed33 TH |
703 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
704 | do_write); | |
624d5c51 TH |
705 | |
706 | kunmap_atomic(buf, KM_IRQ0); | |
707 | local_irq_restore(flags); | |
708 | } else { | |
709 | buf = page_address(page); | |
5682ed33 TH |
710 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
711 | do_write); | |
624d5c51 TH |
712 | } |
713 | ||
714 | qc->curbytes += qc->sect_size; | |
715 | qc->cursg_ofs += qc->sect_size; | |
716 | ||
717 | if (qc->cursg_ofs == qc->cursg->length) { | |
718 | qc->cursg = sg_next(qc->cursg); | |
719 | qc->cursg_ofs = 0; | |
720 | } | |
721 | } | |
722 | ||
723 | /** | |
724 | * ata_pio_sectors - Transfer one or many sectors. | |
725 | * @qc: Command on going | |
726 | * | |
727 | * Transfer one or many sectors of data from/to the | |
728 | * ATA device for the DRQ request. | |
729 | * | |
730 | * LOCKING: | |
731 | * Inherited from caller. | |
732 | */ | |
733 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
734 | { | |
735 | if (is_multi_taskfile(&qc->tf)) { | |
736 | /* READ/WRITE MULTIPLE */ | |
737 | unsigned int nsect; | |
738 | ||
739 | WARN_ON(qc->dev->multi_count == 0); | |
740 | ||
741 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
742 | qc->dev->multi_count); | |
743 | while (nsect--) | |
744 | ata_pio_sector(qc); | |
745 | } else | |
746 | ata_pio_sector(qc); | |
747 | ||
9363c382 | 748 | ata_sff_altstatus(qc->ap); /* flush */ |
624d5c51 TH |
749 | } |
750 | ||
751 | /** | |
752 | * atapi_send_cdb - Write CDB bytes to hardware | |
753 | * @ap: Port to which ATAPI device is attached. | |
754 | * @qc: Taskfile currently active | |
755 | * | |
756 | * When device has indicated its readiness to accept | |
757 | * a CDB, this function is called. Send the CDB. | |
758 | * | |
759 | * LOCKING: | |
760 | * caller. | |
761 | */ | |
762 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
763 | { | |
764 | /* send SCSI cdb */ | |
765 | DPRINTK("send cdb\n"); | |
766 | WARN_ON(qc->dev->cdb_len < 12); | |
767 | ||
5682ed33 | 768 | ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); |
9363c382 | 769 | ata_sff_altstatus(ap); /* flush */ |
624d5c51 TH |
770 | |
771 | switch (qc->tf.protocol) { | |
772 | case ATAPI_PROT_PIO: | |
773 | ap->hsm_task_state = HSM_ST; | |
774 | break; | |
775 | case ATAPI_PROT_NODATA: | |
776 | ap->hsm_task_state = HSM_ST_LAST; | |
777 | break; | |
778 | case ATAPI_PROT_DMA: | |
779 | ap->hsm_task_state = HSM_ST_LAST; | |
780 | /* initiate bmdma */ | |
781 | ap->ops->bmdma_start(qc); | |
782 | break; | |
783 | } | |
784 | } | |
785 | ||
786 | /** | |
787 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
788 | * @qc: Command on going | |
789 | * @bytes: number of bytes | |
790 | * | |
791 | * Transfer Transfer data from/to the ATAPI device. | |
792 | * | |
793 | * LOCKING: | |
794 | * Inherited from caller. | |
795 | * | |
796 | */ | |
797 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
798 | { | |
799 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
800 | struct ata_port *ap = qc->ap; | |
801 | struct ata_device *dev = qc->dev; | |
802 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
803 | struct scatterlist *sg; | |
804 | struct page *page; | |
805 | unsigned char *buf; | |
806 | unsigned int offset, count, consumed; | |
807 | ||
808 | next_sg: | |
809 | sg = qc->cursg; | |
810 | if (unlikely(!sg)) { | |
811 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
812 | "buf=%u cur=%u bytes=%u", | |
813 | qc->nbytes, qc->curbytes, bytes); | |
814 | return -1; | |
815 | } | |
816 | ||
817 | page = sg_page(sg); | |
818 | offset = sg->offset + qc->cursg_ofs; | |
819 | ||
820 | /* get the current page and offset */ | |
821 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
822 | offset %= PAGE_SIZE; | |
823 | ||
824 | /* don't overrun current sg */ | |
825 | count = min(sg->length - qc->cursg_ofs, bytes); | |
826 | ||
827 | /* don't cross page boundaries */ | |
828 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
829 | ||
830 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
831 | ||
832 | if (PageHighMem(page)) { | |
833 | unsigned long flags; | |
834 | ||
835 | /* FIXME: use bounce buffer */ | |
836 | local_irq_save(flags); | |
837 | buf = kmap_atomic(page, KM_IRQ0); | |
838 | ||
839 | /* do the actual data transfer */ | |
5682ed33 | 840 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); |
624d5c51 TH |
841 | |
842 | kunmap_atomic(buf, KM_IRQ0); | |
843 | local_irq_restore(flags); | |
844 | } else { | |
845 | buf = page_address(page); | |
5682ed33 | 846 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); |
624d5c51 TH |
847 | } |
848 | ||
849 | bytes -= min(bytes, consumed); | |
850 | qc->curbytes += count; | |
851 | qc->cursg_ofs += count; | |
852 | ||
853 | if (qc->cursg_ofs == sg->length) { | |
854 | qc->cursg = sg_next(qc->cursg); | |
855 | qc->cursg_ofs = 0; | |
856 | } | |
857 | ||
858 | /* consumed can be larger than count only for the last transfer */ | |
859 | WARN_ON(qc->cursg && count != consumed); | |
860 | ||
861 | if (bytes) | |
862 | goto next_sg; | |
863 | return 0; | |
864 | } | |
865 | ||
866 | /** | |
867 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
868 | * @qc: Command on going | |
869 | * | |
870 | * Transfer Transfer data from/to the ATAPI device. | |
871 | * | |
872 | * LOCKING: | |
873 | * Inherited from caller. | |
874 | */ | |
875 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
876 | { | |
877 | struct ata_port *ap = qc->ap; | |
878 | struct ata_device *dev = qc->dev; | |
879 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
880 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
881 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
882 | ||
883 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
884 | * here to save some kernel stack usage. | |
885 | * For normal completion, qc->result_tf is not relevant. For | |
886 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
887 | * So, the correctness of qc->result_tf is not affected. | |
888 | */ | |
5682ed33 | 889 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
890 | ireason = qc->result_tf.nsect; |
891 | bc_lo = qc->result_tf.lbam; | |
892 | bc_hi = qc->result_tf.lbah; | |
893 | bytes = (bc_hi << 8) | bc_lo; | |
894 | ||
895 | /* shall be cleared to zero, indicating xfer of data */ | |
896 | if (unlikely(ireason & (1 << 0))) | |
897 | goto atapi_check; | |
898 | ||
899 | /* make sure transfer direction matches expected */ | |
900 | i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; | |
901 | if (unlikely(do_write != i_write)) | |
902 | goto atapi_check; | |
903 | ||
904 | if (unlikely(!bytes)) | |
905 | goto atapi_check; | |
906 | ||
907 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
908 | ||
909 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
910 | goto err_out; | |
9363c382 | 911 | ata_sff_altstatus(ap); /* flush */ |
624d5c51 TH |
912 | |
913 | return; | |
914 | ||
915 | atapi_check: | |
916 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
917 | ireason, bytes); | |
918 | err_out: | |
919 | qc->err_mask |= AC_ERR_HSM; | |
920 | ap->hsm_task_state = HSM_ST_ERR; | |
921 | } | |
922 | ||
923 | /** | |
924 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
925 | * @ap: the target ata_port | |
926 | * @qc: qc on going | |
927 | * | |
928 | * RETURNS: | |
929 | * 1 if ok in workqueue, 0 otherwise. | |
930 | */ | |
931 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc) | |
932 | { | |
933 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
934 | return 1; | |
935 | ||
936 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
937 | if (qc->tf.protocol == ATA_PROT_PIO && | |
938 | (qc->tf.flags & ATA_TFLAG_WRITE)) | |
939 | return 1; | |
940 | ||
941 | if (ata_is_atapi(qc->tf.protocol) && | |
942 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
943 | return 1; | |
944 | } | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
949 | /** | |
950 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
951 | * @qc: Command to complete | |
952 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
953 | * | |
954 | * Finish @qc which is running on standard HSM. | |
955 | * | |
956 | * LOCKING: | |
957 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
958 | * Otherwise, none on entry and grabs host lock. | |
959 | */ | |
960 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
961 | { | |
962 | struct ata_port *ap = qc->ap; | |
963 | unsigned long flags; | |
964 | ||
965 | if (ap->ops->error_handler) { | |
966 | if (in_wq) { | |
967 | spin_lock_irqsave(ap->lock, flags); | |
968 | ||
969 | /* EH might have kicked in while host lock is | |
970 | * released. | |
971 | */ | |
972 | qc = ata_qc_from_tag(ap, qc->tag); | |
973 | if (qc) { | |
974 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
5682ed33 | 975 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
976 | ata_qc_complete(qc); |
977 | } else | |
978 | ata_port_freeze(ap); | |
979 | } | |
980 | ||
981 | spin_unlock_irqrestore(ap->lock, flags); | |
982 | } else { | |
983 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
984 | ata_qc_complete(qc); | |
985 | else | |
986 | ata_port_freeze(ap); | |
987 | } | |
988 | } else { | |
989 | if (in_wq) { | |
990 | spin_lock_irqsave(ap->lock, flags); | |
5682ed33 | 991 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
992 | ata_qc_complete(qc); |
993 | spin_unlock_irqrestore(ap->lock, flags); | |
994 | } else | |
995 | ata_qc_complete(qc); | |
996 | } | |
997 | } | |
998 | ||
999 | /** | |
9363c382 | 1000 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
1001 | * @ap: the target ata_port |
1002 | * @qc: qc on going | |
1003 | * @status: current device status | |
1004 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1005 | * | |
1006 | * RETURNS: | |
1007 | * 1 when poll next status needed, 0 otherwise. | |
1008 | */ | |
9363c382 TH |
1009 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
1010 | u8 status, int in_wq) | |
624d5c51 TH |
1011 | { |
1012 | unsigned long flags = 0; | |
1013 | int poll_next; | |
1014 | ||
1015 | WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0); | |
1016 | ||
9363c382 | 1017 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
1018 | * like DMA polling into the workqueue. Notice that |
1019 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
1020 | */ | |
1021 | WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc)); | |
1022 | ||
1023 | fsm_start: | |
1024 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
1025 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
1026 | ||
1027 | switch (ap->hsm_task_state) { | |
1028 | case HSM_ST_FIRST: | |
1029 | /* Send first data block or PACKET CDB */ | |
1030 | ||
1031 | /* If polling, we will stay in the work queue after | |
1032 | * sending the data. Otherwise, interrupt handler | |
1033 | * takes over after sending the data. | |
1034 | */ | |
1035 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
1036 | ||
1037 | /* check device status */ | |
1038 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1039 | /* handle BSY=0, DRQ=0 as error */ | |
1040 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1041 | /* device stops HSM for abort/error */ | |
1042 | qc->err_mask |= AC_ERR_DEV; | |
1043 | else | |
1044 | /* HSM violation. Let EH handle this */ | |
1045 | qc->err_mask |= AC_ERR_HSM; | |
1046 | ||
1047 | ap->hsm_task_state = HSM_ST_ERR; | |
1048 | goto fsm_start; | |
1049 | } | |
1050 | ||
1051 | /* Device should not ask for data transfer (DRQ=1) | |
1052 | * when it finds something wrong. | |
1053 | * We ignore DRQ here and stop the HSM by | |
1054 | * changing hsm_task_state to HSM_ST_ERR and | |
1055 | * let the EH abort the command or reset the device. | |
1056 | */ | |
1057 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1058 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1059 | * when doing the next command (mostly request sense). | |
1060 | * We ignore ERR here to workaround and proceed sending | |
1061 | * the CDB. | |
1062 | */ | |
1063 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
1064 | ata_port_printk(ap, KERN_WARNING, | |
1065 | "DRQ=1 with device error, " | |
1066 | "dev_stat 0x%X\n", status); | |
1067 | qc->err_mask |= AC_ERR_HSM; | |
1068 | ap->hsm_task_state = HSM_ST_ERR; | |
1069 | goto fsm_start; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | /* Send the CDB (atapi) or the first data block (ata pio out). | |
1074 | * During the state transition, interrupt handler shouldn't | |
1075 | * be invoked before the data transfer is complete and | |
1076 | * hsm_task_state is changed. Hence, the following locking. | |
1077 | */ | |
1078 | if (in_wq) | |
1079 | spin_lock_irqsave(ap->lock, flags); | |
1080 | ||
1081 | if (qc->tf.protocol == ATA_PROT_PIO) { | |
1082 | /* PIO data out protocol. | |
1083 | * send first data block. | |
1084 | */ | |
1085 | ||
1086 | /* ata_pio_sectors() might change the state | |
1087 | * to HSM_ST_LAST. so, the state is changed here | |
1088 | * before ata_pio_sectors(). | |
1089 | */ | |
1090 | ap->hsm_task_state = HSM_ST; | |
1091 | ata_pio_sectors(qc); | |
1092 | } else | |
1093 | /* send CDB */ | |
1094 | atapi_send_cdb(ap, qc); | |
1095 | ||
1096 | if (in_wq) | |
1097 | spin_unlock_irqrestore(ap->lock, flags); | |
1098 | ||
1099 | /* if polling, ata_pio_task() handles the rest. | |
1100 | * otherwise, interrupt handler takes over from here. | |
1101 | */ | |
1102 | break; | |
1103 | ||
1104 | case HSM_ST: | |
1105 | /* complete command or read/write the data register */ | |
1106 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1107 | /* ATAPI PIO protocol */ | |
1108 | if ((status & ATA_DRQ) == 0) { | |
1109 | /* No more data to transfer or device error. | |
1110 | * Device error will be tagged in HSM_ST_LAST. | |
1111 | */ | |
1112 | ap->hsm_task_state = HSM_ST_LAST; | |
1113 | goto fsm_start; | |
1114 | } | |
1115 | ||
1116 | /* Device should not ask for data transfer (DRQ=1) | |
1117 | * when it finds something wrong. | |
1118 | * We ignore DRQ here and stop the HSM by | |
1119 | * changing hsm_task_state to HSM_ST_ERR and | |
1120 | * let the EH abort the command or reset the device. | |
1121 | */ | |
1122 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1123 | ata_port_printk(ap, KERN_WARNING, "DRQ=1 with " | |
1124 | "device error, dev_stat 0x%X\n", | |
1125 | status); | |
1126 | qc->err_mask |= AC_ERR_HSM; | |
1127 | ap->hsm_task_state = HSM_ST_ERR; | |
1128 | goto fsm_start; | |
1129 | } | |
1130 | ||
1131 | atapi_pio_bytes(qc); | |
1132 | ||
1133 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1134 | /* bad ireason reported by device */ | |
1135 | goto fsm_start; | |
1136 | ||
1137 | } else { | |
1138 | /* ATA PIO protocol */ | |
1139 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1140 | /* handle BSY=0, DRQ=0 as error */ | |
1141 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1142 | /* device stops HSM for abort/error */ | |
1143 | qc->err_mask |= AC_ERR_DEV; | |
1144 | else | |
1145 | /* HSM violation. Let EH handle this. | |
1146 | * Phantom devices also trigger this | |
1147 | * condition. Mark hint. | |
1148 | */ | |
1149 | qc->err_mask |= AC_ERR_HSM | | |
1150 | AC_ERR_NODEV_HINT; | |
1151 | ||
1152 | ap->hsm_task_state = HSM_ST_ERR; | |
1153 | goto fsm_start; | |
1154 | } | |
1155 | ||
1156 | /* For PIO reads, some devices may ask for | |
1157 | * data transfer (DRQ=1) alone with ERR=1. | |
1158 | * We respect DRQ here and transfer one | |
1159 | * block of junk data before changing the | |
1160 | * hsm_task_state to HSM_ST_ERR. | |
1161 | * | |
1162 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1163 | * sense since the data block has been | |
1164 | * transferred to the device. | |
1165 | */ | |
1166 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1167 | /* data might be corrputed */ | |
1168 | qc->err_mask |= AC_ERR_DEV; | |
1169 | ||
1170 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1171 | ata_pio_sectors(qc); | |
1172 | status = ata_wait_idle(ap); | |
1173 | } | |
1174 | ||
1175 | if (status & (ATA_BUSY | ATA_DRQ)) | |
1176 | qc->err_mask |= AC_ERR_HSM; | |
1177 | ||
1178 | /* ata_pio_sectors() might change the | |
1179 | * state to HSM_ST_LAST. so, the state | |
1180 | * is changed after ata_pio_sectors(). | |
1181 | */ | |
1182 | ap->hsm_task_state = HSM_ST_ERR; | |
1183 | goto fsm_start; | |
1184 | } | |
1185 | ||
1186 | ata_pio_sectors(qc); | |
1187 | ||
1188 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1189 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1190 | /* all data read */ | |
1191 | status = ata_wait_idle(ap); | |
1192 | goto fsm_start; | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | poll_next = 1; | |
1197 | break; | |
1198 | ||
1199 | case HSM_ST_LAST: | |
1200 | if (unlikely(!ata_ok(status))) { | |
1201 | qc->err_mask |= __ac_err_mask(status); | |
1202 | ap->hsm_task_state = HSM_ST_ERR; | |
1203 | goto fsm_start; | |
1204 | } | |
1205 | ||
1206 | /* no more data to transfer */ | |
1207 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1208 | ap->print_id, qc->dev->devno, status); | |
1209 | ||
1210 | WARN_ON(qc->err_mask); | |
1211 | ||
1212 | ap->hsm_task_state = HSM_ST_IDLE; | |
1213 | ||
1214 | /* complete taskfile transaction */ | |
1215 | ata_hsm_qc_complete(qc, in_wq); | |
1216 | ||
1217 | poll_next = 0; | |
1218 | break; | |
1219 | ||
1220 | case HSM_ST_ERR: | |
1221 | /* make sure qc->err_mask is available to | |
1222 | * know what's wrong and recover | |
1223 | */ | |
1224 | WARN_ON(qc->err_mask == 0); | |
1225 | ||
1226 | ap->hsm_task_state = HSM_ST_IDLE; | |
1227 | ||
1228 | /* complete taskfile transaction */ | |
1229 | ata_hsm_qc_complete(qc, in_wq); | |
1230 | ||
1231 | poll_next = 0; | |
1232 | break; | |
1233 | default: | |
1234 | poll_next = 0; | |
1235 | BUG(); | |
1236 | } | |
1237 | ||
1238 | return poll_next; | |
1239 | } | |
1240 | ||
1241 | void ata_pio_task(struct work_struct *work) | |
1242 | { | |
1243 | struct ata_port *ap = | |
1244 | container_of(work, struct ata_port, port_task.work); | |
1245 | struct ata_queued_cmd *qc = ap->port_task_data; | |
1246 | u8 status; | |
1247 | int poll_next; | |
1248 | ||
1249 | fsm_start: | |
1250 | WARN_ON(ap->hsm_task_state == HSM_ST_IDLE); | |
1251 | ||
1252 | /* | |
1253 | * This is purely heuristic. This is a fast path. | |
1254 | * Sometimes when we enter, BSY will be cleared in | |
1255 | * a chk-status or two. If not, the drive is probably seeking | |
1256 | * or something. Snooze for a couple msecs, then | |
1257 | * chk-status again. If still busy, queue delayed work. | |
1258 | */ | |
9363c382 | 1259 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 TH |
1260 | if (status & ATA_BUSY) { |
1261 | msleep(2); | |
9363c382 | 1262 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 TH |
1263 | if (status & ATA_BUSY) { |
1264 | ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE); | |
1265 | return; | |
1266 | } | |
1267 | } | |
1268 | ||
1269 | /* move the HSM */ | |
9363c382 | 1270 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1271 | |
1272 | /* another command or interrupt handler | |
1273 | * may be running at this point. | |
1274 | */ | |
1275 | if (poll_next) | |
1276 | goto fsm_start; | |
1277 | } | |
1278 | ||
1279 | /** | |
9363c382 | 1280 | * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner |
624d5c51 TH |
1281 | * @qc: command to issue to device |
1282 | * | |
1283 | * Using various libata functions and hooks, this function | |
1284 | * starts an ATA command. ATA commands are grouped into | |
1285 | * classes called "protocols", and issuing each type of protocol | |
1286 | * is slightly different. | |
1287 | * | |
1288 | * May be used as the qc_issue() entry in ata_port_operations. | |
1289 | * | |
1290 | * LOCKING: | |
1291 | * spin_lock_irqsave(host lock) | |
1292 | * | |
1293 | * RETURNS: | |
1294 | * Zero on success, AC_ERR_* mask on failure | |
1295 | */ | |
9363c382 | 1296 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1297 | { |
1298 | struct ata_port *ap = qc->ap; | |
1299 | ||
1300 | /* Use polling pio if the LLD doesn't handle | |
1301 | * interrupt driven pio and atapi CDB interrupt. | |
1302 | */ | |
1303 | if (ap->flags & ATA_FLAG_PIO_POLLING) { | |
1304 | switch (qc->tf.protocol) { | |
1305 | case ATA_PROT_PIO: | |
1306 | case ATA_PROT_NODATA: | |
1307 | case ATAPI_PROT_PIO: | |
1308 | case ATAPI_PROT_NODATA: | |
1309 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
1310 | break; | |
1311 | case ATAPI_PROT_DMA: | |
1312 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
1313 | /* see ata_dma_blacklisted() */ | |
1314 | BUG(); | |
1315 | break; | |
1316 | default: | |
1317 | break; | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | /* select the device */ | |
1322 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1323 | ||
1324 | /* start the command */ | |
1325 | switch (qc->tf.protocol) { | |
1326 | case ATA_PROT_NODATA: | |
1327 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1328 | ata_qc_set_polling(qc); | |
1329 | ||
1330 | ata_tf_to_host(ap, &qc->tf); | |
1331 | ap->hsm_task_state = HSM_ST_LAST; | |
1332 | ||
1333 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1334 | ata_pio_queue_task(ap, qc, 0); | |
1335 | ||
1336 | break; | |
1337 | ||
1338 | case ATA_PROT_DMA: | |
1339 | WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); | |
1340 | ||
5682ed33 | 1341 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1342 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1343 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
1344 | ap->hsm_task_state = HSM_ST_LAST; | |
1345 | break; | |
1346 | ||
1347 | case ATA_PROT_PIO: | |
1348 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1349 | ata_qc_set_polling(qc); | |
1350 | ||
1351 | ata_tf_to_host(ap, &qc->tf); | |
1352 | ||
1353 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1354 | /* PIO data out protocol */ | |
1355 | ap->hsm_task_state = HSM_ST_FIRST; | |
1356 | ata_pio_queue_task(ap, qc, 0); | |
1357 | ||
1358 | /* always send first data block using | |
1359 | * the ata_pio_task() codepath. | |
1360 | */ | |
1361 | } else { | |
1362 | /* PIO data in protocol */ | |
1363 | ap->hsm_task_state = HSM_ST; | |
1364 | ||
1365 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1366 | ata_pio_queue_task(ap, qc, 0); | |
1367 | ||
1368 | /* if polling, ata_pio_task() handles the rest. | |
1369 | * otherwise, interrupt handler takes over from here. | |
1370 | */ | |
1371 | } | |
1372 | ||
1373 | break; | |
1374 | ||
1375 | case ATAPI_PROT_PIO: | |
1376 | case ATAPI_PROT_NODATA: | |
1377 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1378 | ata_qc_set_polling(qc); | |
1379 | ||
1380 | ata_tf_to_host(ap, &qc->tf); | |
1381 | ||
1382 | ap->hsm_task_state = HSM_ST_FIRST; | |
1383 | ||
1384 | /* send cdb by polling if no cdb interrupt */ | |
1385 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1386 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
1387 | ata_pio_queue_task(ap, qc, 0); | |
1388 | break; | |
1389 | ||
1390 | case ATAPI_PROT_DMA: | |
1391 | WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); | |
1392 | ||
5682ed33 | 1393 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1394 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1395 | ap->hsm_task_state = HSM_ST_FIRST; | |
1396 | ||
1397 | /* send cdb by polling if no cdb interrupt */ | |
1398 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1399 | ata_pio_queue_task(ap, qc, 0); | |
1400 | break; | |
1401 | ||
1402 | default: | |
1403 | WARN_ON(1); | |
1404 | return AC_ERR_SYSTEM; | |
1405 | } | |
1406 | ||
1407 | return 0; | |
1408 | } | |
1409 | ||
22183bf5 TH |
1410 | /** |
1411 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1412 | * @qc: qc to fill result TF for | |
1413 | * | |
1414 | * @qc is finished and result TF needs to be filled. Fill it | |
1415 | * using ->sff_tf_read. | |
1416 | * | |
1417 | * LOCKING: | |
1418 | * spin_lock_irqsave(host lock) | |
1419 | * | |
1420 | * RETURNS: | |
1421 | * true indicating that result TF is successfully filled. | |
1422 | */ | |
1423 | bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) | |
1424 | { | |
1425 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
1426 | return true; | |
1427 | } | |
1428 | ||
624d5c51 | 1429 | /** |
9363c382 | 1430 | * ata_sff_host_intr - Handle host interrupt for given (port, task) |
624d5c51 TH |
1431 | * @ap: Port on which interrupt arrived (possibly...) |
1432 | * @qc: Taskfile currently active in engine | |
1433 | * | |
1434 | * Handle host interrupt for given queued command. Currently, | |
1435 | * only DMA interrupts are handled. All other commands are | |
1436 | * handled via polling with interrupts disabled (nIEN bit). | |
1437 | * | |
1438 | * LOCKING: | |
1439 | * spin_lock_irqsave(host lock) | |
1440 | * | |
1441 | * RETURNS: | |
1442 | * One if interrupt was handled, zero if not (shared irq). | |
1443 | */ | |
9363c382 TH |
1444 | inline unsigned int ata_sff_host_intr(struct ata_port *ap, |
1445 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
1446 | { |
1447 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
1448 | u8 status, host_stat = 0; | |
1449 | ||
1450 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1451 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1452 | ||
1453 | /* Check whether we are expecting interrupt in this state */ | |
1454 | switch (ap->hsm_task_state) { | |
1455 | case HSM_ST_FIRST: | |
1456 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1457 | * at this state when ready to receive CDB. | |
1458 | */ | |
1459 | ||
1460 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1461 | * The flag was turned on only for atapi devices. No | |
1462 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1463 | */ | |
1464 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1465 | goto idle_irq; | |
1466 | break; | |
1467 | case HSM_ST_LAST: | |
1468 | if (qc->tf.protocol == ATA_PROT_DMA || | |
1469 | qc->tf.protocol == ATAPI_PROT_DMA) { | |
1470 | /* check status of DMA engine */ | |
1471 | host_stat = ap->ops->bmdma_status(ap); | |
1472 | VPRINTK("ata%u: host_stat 0x%X\n", | |
1473 | ap->print_id, host_stat); | |
1474 | ||
1475 | /* if it's not our irq... */ | |
1476 | if (!(host_stat & ATA_DMA_INTR)) | |
1477 | goto idle_irq; | |
1478 | ||
1479 | /* before we do anything else, clear DMA-Start bit */ | |
1480 | ap->ops->bmdma_stop(qc); | |
1481 | ||
1482 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
1483 | /* error when transfering data to/from memory */ | |
1484 | qc->err_mask |= AC_ERR_HOST_BUS; | |
1485 | ap->hsm_task_state = HSM_ST_ERR; | |
1486 | } | |
1487 | } | |
1488 | break; | |
1489 | case HSM_ST: | |
1490 | break; | |
1491 | default: | |
1492 | goto idle_irq; | |
1493 | } | |
1494 | ||
1495 | /* check altstatus */ | |
9363c382 | 1496 | status = ata_sff_altstatus(ap); |
624d5c51 TH |
1497 | if (status & ATA_BUSY) |
1498 | goto idle_irq; | |
1499 | ||
1500 | /* check main status, clearing INTRQ */ | |
5682ed33 | 1501 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
1502 | if (unlikely(status & ATA_BUSY)) |
1503 | goto idle_irq; | |
1504 | ||
1505 | /* ack bmdma irq events */ | |
5682ed33 | 1506 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1507 | |
9363c382 | 1508 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 TH |
1509 | |
1510 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || | |
1511 | qc->tf.protocol == ATAPI_PROT_DMA)) | |
1512 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
1513 | ||
1514 | return 1; /* irq handled */ | |
1515 | ||
1516 | idle_irq: | |
1517 | ap->stats.idle_irq++; | |
1518 | ||
1519 | #ifdef ATA_IRQ_TRAP | |
1520 | if ((ap->stats.idle_irq % 1000) == 0) { | |
5682ed33 TH |
1521 | ap->ops->sff_check_status(ap); |
1522 | ap->ops->sff_irq_clear(ap); | |
624d5c51 TH |
1523 | ata_port_printk(ap, KERN_WARNING, "irq trap\n"); |
1524 | return 1; | |
1525 | } | |
1526 | #endif | |
1527 | return 0; /* irq not handled */ | |
1528 | } | |
1529 | ||
1530 | /** | |
9363c382 | 1531 | * ata_sff_interrupt - Default ATA host interrupt handler |
624d5c51 TH |
1532 | * @irq: irq line (unused) |
1533 | * @dev_instance: pointer to our ata_host information structure | |
1534 | * | |
1535 | * Default interrupt handler for PCI IDE devices. Calls | |
9363c382 | 1536 | * ata_sff_host_intr() for each port that is not disabled. |
624d5c51 TH |
1537 | * |
1538 | * LOCKING: | |
1539 | * Obtains host lock during operation. | |
1540 | * | |
1541 | * RETURNS: | |
1542 | * IRQ_NONE or IRQ_HANDLED. | |
1543 | */ | |
9363c382 | 1544 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) |
624d5c51 TH |
1545 | { |
1546 | struct ata_host *host = dev_instance; | |
1547 | unsigned int i; | |
1548 | unsigned int handled = 0; | |
1549 | unsigned long flags; | |
1550 | ||
1551 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1552 | spin_lock_irqsave(&host->lock, flags); | |
1553 | ||
1554 | for (i = 0; i < host->n_ports; i++) { | |
1555 | struct ata_port *ap; | |
1556 | ||
1557 | ap = host->ports[i]; | |
1558 | if (ap && | |
1559 | !(ap->flags & ATA_FLAG_DISABLED)) { | |
1560 | struct ata_queued_cmd *qc; | |
1561 | ||
1562 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
1563 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && | |
1564 | (qc->flags & ATA_QCFLAG_ACTIVE)) | |
9363c382 | 1565 | handled |= ata_sff_host_intr(ap, qc); |
624d5c51 TH |
1566 | } |
1567 | } | |
1568 | ||
1569 | spin_unlock_irqrestore(&host->lock, flags); | |
1570 | ||
1571 | return IRQ_RETVAL(handled); | |
1572 | } | |
1573 | ||
1574 | /** | |
9363c382 | 1575 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1576 | * @ap: port to freeze |
1577 | * | |
1578 | * Freeze BMDMA controller port. | |
1579 | * | |
1580 | * LOCKING: | |
1581 | * Inherited from caller. | |
1582 | */ | |
9363c382 | 1583 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 TH |
1584 | { |
1585 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
1586 | ||
1587 | ap->ctl |= ATA_NIEN; | |
1588 | ap->last_ctl = ap->ctl; | |
1589 | ||
1590 | if (ioaddr->ctl_addr) | |
1591 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1592 | ||
1593 | /* Under certain circumstances, some controllers raise IRQ on | |
1594 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1595 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1596 | */ | |
5682ed33 | 1597 | ap->ops->sff_check_status(ap); |
624d5c51 | 1598 | |
5682ed33 | 1599 | ap->ops->sff_irq_clear(ap); |
624d5c51 TH |
1600 | } |
1601 | ||
1602 | /** | |
9363c382 | 1603 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1604 | * @ap: port to thaw |
1605 | * | |
9363c382 | 1606 | * Thaw SFF controller port. |
624d5c51 TH |
1607 | * |
1608 | * LOCKING: | |
1609 | * Inherited from caller. | |
1610 | */ | |
9363c382 | 1611 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1612 | { |
624d5c51 | 1613 | /* clear & re-enable interrupts */ |
5682ed33 TH |
1614 | ap->ops->sff_check_status(ap); |
1615 | ap->ops->sff_irq_clear(ap); | |
1616 | ap->ops->sff_irq_on(ap); | |
272f7884 TH |
1617 | } |
1618 | ||
0aa1113d TH |
1619 | /** |
1620 | * ata_sff_prereset - prepare SFF link for reset | |
1621 | * @link: SFF link to be reset | |
1622 | * @deadline: deadline jiffies for the operation | |
1623 | * | |
1624 | * SFF link @link is about to be reset. Initialize it. It first | |
1625 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1626 | * being softreset. | |
1627 | * | |
1628 | * LOCKING: | |
1629 | * Kernel thread context (may sleep) | |
1630 | * | |
1631 | * RETURNS: | |
1632 | * 0 on success, -errno otherwise. | |
1633 | */ | |
1634 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1635 | { | |
0aa1113d TH |
1636 | struct ata_eh_context *ehc = &link->eh_context; |
1637 | int rc; | |
1638 | ||
1639 | rc = ata_std_prereset(link, deadline); | |
1640 | if (rc) | |
1641 | return rc; | |
1642 | ||
1643 | /* if we're about to do hardreset, nothing more to do */ | |
1644 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1645 | return 0; | |
1646 | ||
1647 | /* wait for !BSY if we don't know that no device is attached */ | |
1648 | if (!ata_link_offline(link)) { | |
705e76be | 1649 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d TH |
1650 | if (rc && rc != -ENODEV) { |
1651 | ata_link_printk(link, KERN_WARNING, "device not ready " | |
1652 | "(errno=%d), forcing hardreset\n", rc); | |
1653 | ehc->i.action |= ATA_EH_HARDRESET; | |
1654 | } | |
1655 | } | |
1656 | ||
1657 | return 0; | |
1658 | } | |
1659 | ||
90088bb4 | 1660 | /** |
624d5c51 TH |
1661 | * ata_devchk - PATA device presence detection |
1662 | * @ap: ATA channel to examine | |
1663 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1664 | * |
624d5c51 TH |
1665 | * This technique was originally described in |
1666 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1667 | * later found its way into the ATA/ATAPI spec. | |
1668 | * | |
1669 | * Write a pattern to the ATA shadow registers, | |
1670 | * and if a device is present, it will respond by | |
1671 | * correctly storing and echoing back the | |
1672 | * ATA shadow register contents. | |
90088bb4 TH |
1673 | * |
1674 | * LOCKING: | |
624d5c51 | 1675 | * caller. |
90088bb4 | 1676 | */ |
624d5c51 | 1677 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1678 | { |
1679 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1680 | u8 nsect, lbal; |
90088bb4 | 1681 | |
5682ed33 | 1682 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1683 | |
624d5c51 TH |
1684 | iowrite8(0x55, ioaddr->nsect_addr); |
1685 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1686 | |
624d5c51 TH |
1687 | iowrite8(0xaa, ioaddr->nsect_addr); |
1688 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1689 | |
624d5c51 TH |
1690 | iowrite8(0x55, ioaddr->nsect_addr); |
1691 | iowrite8(0xaa, ioaddr->lbal_addr); | |
1692 | ||
1693 | nsect = ioread8(ioaddr->nsect_addr); | |
1694 | lbal = ioread8(ioaddr->lbal_addr); | |
1695 | ||
1696 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
1697 | return 1; /* we found a device */ | |
1698 | ||
1699 | return 0; /* nothing found */ | |
90088bb4 TH |
1700 | } |
1701 | ||
272f7884 | 1702 | /** |
9363c382 | 1703 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
1704 | * @dev: ATA device to classify (starting at zero) |
1705 | * @present: device seems present | |
1706 | * @r_err: Value of error register on completion | |
272f7884 | 1707 | * |
624d5c51 TH |
1708 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
1709 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
1710 | * shadow registers, indicating the results of device detection | |
1711 | * and diagnostics. | |
272f7884 | 1712 | * |
624d5c51 TH |
1713 | * Select the ATA device, and read the values from the ATA shadow |
1714 | * registers. Then parse according to the Error register value, | |
1715 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
1716 | * |
1717 | * LOCKING: | |
624d5c51 TH |
1718 | * caller. |
1719 | * | |
1720 | * RETURNS: | |
1721 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 1722 | */ |
9363c382 | 1723 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 1724 | u8 *r_err) |
272f7884 | 1725 | { |
624d5c51 TH |
1726 | struct ata_port *ap = dev->link->ap; |
1727 | struct ata_taskfile tf; | |
1728 | unsigned int class; | |
1729 | u8 err; | |
1730 | ||
5682ed33 | 1731 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
1732 | |
1733 | memset(&tf, 0, sizeof(tf)); | |
1734 | ||
5682ed33 | 1735 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
1736 | err = tf.feature; |
1737 | if (r_err) | |
1738 | *r_err = err; | |
1739 | ||
1740 | /* see if device passed diags: continue and warn later */ | |
1741 | if (err == 0) | |
1742 | /* diagnostic fail : do nothing _YET_ */ | |
1743 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
1744 | else if (err == 1) | |
1745 | /* do nothing */ ; | |
1746 | else if ((dev->devno == 0) && (err == 0x81)) | |
1747 | /* do nothing */ ; | |
1748 | else | |
1749 | return ATA_DEV_NONE; | |
272f7884 | 1750 | |
624d5c51 TH |
1751 | /* determine if device is ATA or ATAPI */ |
1752 | class = ata_dev_classify(&tf); | |
272f7884 | 1753 | |
624d5c51 TH |
1754 | if (class == ATA_DEV_UNKNOWN) { |
1755 | /* If the device failed diagnostic, it's likely to | |
1756 | * have reported incorrect device signature too. | |
1757 | * Assume ATA device if the device seems present but | |
1758 | * device signature is invalid with diagnostic | |
1759 | * failure. | |
1760 | */ | |
1761 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
1762 | class = ATA_DEV_ATA; | |
1763 | else | |
1764 | class = ATA_DEV_NONE; | |
5682ed33 TH |
1765 | } else if ((class == ATA_DEV_ATA) && |
1766 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
1767 | class = ATA_DEV_NONE; |
1768 | ||
1769 | return class; | |
272f7884 TH |
1770 | } |
1771 | ||
705e76be TH |
1772 | /** |
1773 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
1774 | * @link: SFF link which is just reset | |
1775 | * @devmask: mask of present devices | |
1776 | * @deadline: deadline jiffies for the operation | |
1777 | * | |
1778 | * Wait devices attached to SFF @link to become ready after | |
1779 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
1780 | * status register too early. | |
1781 | * | |
1782 | * LOCKING: | |
1783 | * Kernel thread context (may sleep). | |
1784 | * | |
1785 | * RETURNS: | |
1786 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
1787 | * don't seem to exist. -errno on other errors. | |
1788 | */ | |
1789 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
1790 | unsigned long deadline) | |
1fdffbce | 1791 | { |
705e76be | 1792 | struct ata_port *ap = link->ap; |
1fdffbce | 1793 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
1794 | unsigned int dev0 = devmask & (1 << 0); |
1795 | unsigned int dev1 = devmask & (1 << 1); | |
1796 | int rc, ret = 0; | |
1fdffbce | 1797 | |
705e76be TH |
1798 | msleep(ATA_WAIT_AFTER_RESET_MSECS); |
1799 | ||
1800 | /* always check readiness of the master device */ | |
1801 | rc = ata_sff_wait_ready(link, deadline); | |
1802 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
1803 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 1804 | */ |
705e76be TH |
1805 | if (rc) |
1806 | return rc; | |
1fdffbce | 1807 | |
624d5c51 TH |
1808 | /* if device 1 was found in ata_devchk, wait for register |
1809 | * access briefly, then wait for BSY to clear. | |
1810 | */ | |
1811 | if (dev1) { | |
1812 | int i; | |
1fdffbce | 1813 | |
5682ed33 | 1814 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 1815 | |
624d5c51 TH |
1816 | /* Wait for register access. Some ATAPI devices fail |
1817 | * to set nsect/lbal after reset, so don't waste too | |
1818 | * much time on it. We're gonna wait for !BSY anyway. | |
1819 | */ | |
1820 | for (i = 0; i < 2; i++) { | |
1821 | u8 nsect, lbal; | |
1822 | ||
1823 | nsect = ioread8(ioaddr->nsect_addr); | |
1824 | lbal = ioread8(ioaddr->lbal_addr); | |
1825 | if ((nsect == 1) && (lbal == 1)) | |
1826 | break; | |
1827 | msleep(50); /* give drive a breather */ | |
1828 | } | |
1829 | ||
705e76be | 1830 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
1831 | if (rc) { |
1832 | if (rc != -ENODEV) | |
1833 | return rc; | |
1834 | ret = rc; | |
1835 | } | |
1fdffbce JG |
1836 | } |
1837 | ||
624d5c51 | 1838 | /* is all this really necessary? */ |
5682ed33 | 1839 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 1840 | if (dev1) |
5682ed33 | 1841 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 1842 | if (dev0) |
5682ed33 | 1843 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1844 | |
1845 | return ret; | |
1fdffbce JG |
1846 | } |
1847 | ||
624d5c51 TH |
1848 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
1849 | unsigned long deadline) | |
2cc432ee | 1850 | { |
624d5c51 | 1851 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 1852 | |
624d5c51 TH |
1853 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
1854 | ||
1855 | /* software reset. causes dev0 to be selected */ | |
1856 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1857 | udelay(20); /* FIXME: flush */ | |
1858 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
1859 | udelay(20); /* FIXME: flush */ | |
1860 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1861 | ||
705e76be TH |
1862 | /* wait the port to become ready */ |
1863 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
1864 | } |
1865 | ||
6d97dbd7 | 1866 | /** |
9363c382 | 1867 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
1868 | * @link: ATA link to reset |
1869 | * @classes: resulting classes of attached devices | |
1870 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1871 | * |
624d5c51 | 1872 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
1873 | * |
1874 | * LOCKING: | |
624d5c51 TH |
1875 | * Kernel thread context (may sleep) |
1876 | * | |
1877 | * RETURNS: | |
1878 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 1879 | */ |
9363c382 | 1880 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 1881 | unsigned long deadline) |
6d97dbd7 | 1882 | { |
624d5c51 TH |
1883 | struct ata_port *ap = link->ap; |
1884 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
1885 | unsigned int devmask = 0; | |
1886 | int rc; | |
1887 | u8 err; | |
6d97dbd7 | 1888 | |
624d5c51 | 1889 | DPRINTK("ENTER\n"); |
6d97dbd7 | 1890 | |
624d5c51 TH |
1891 | if (ata_link_offline(link)) { |
1892 | classes[0] = ATA_DEV_NONE; | |
1893 | goto out; | |
1894 | } | |
0f0a3ad3 | 1895 | |
624d5c51 TH |
1896 | /* determine if device 0/1 are present */ |
1897 | if (ata_devchk(ap, 0)) | |
1898 | devmask |= (1 << 0); | |
1899 | if (slave_possible && ata_devchk(ap, 1)) | |
1900 | devmask |= (1 << 1); | |
1901 | ||
1902 | /* select device 0 again */ | |
5682ed33 | 1903 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1904 | |
1905 | /* issue bus reset */ | |
1906 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
1907 | rc = ata_bus_softreset(ap, devmask, deadline); | |
1908 | /* if link is occupied, -ENODEV too is an error */ | |
1909 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
1910 | ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); | |
1911 | return rc; | |
1912 | } | |
0f0a3ad3 | 1913 | |
624d5c51 | 1914 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 1915 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
1916 | devmask & (1 << 0), &err); |
1917 | if (slave_possible && err != 0x81) | |
9363c382 | 1918 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
1919 | devmask & (1 << 1), &err); |
1920 | ||
1921 | out: | |
1922 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); | |
1923 | return 0; | |
6d97dbd7 TH |
1924 | } |
1925 | ||
1926 | /** | |
9363c382 | 1927 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
1928 | * @link: link to reset |
1929 | * @class: resulting class of attached device | |
1930 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1931 | * |
624d5c51 TH |
1932 | * SATA phy-reset host port using DET bits of SControl register, |
1933 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
1934 | * |
1935 | * LOCKING: | |
624d5c51 TH |
1936 | * Kernel thread context (may sleep) |
1937 | * | |
1938 | * RETURNS: | |
1939 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 1940 | */ |
9363c382 | 1941 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 1942 | unsigned long deadline) |
6d97dbd7 | 1943 | { |
9dadd45b TH |
1944 | struct ata_eh_context *ehc = &link->eh_context; |
1945 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
1946 | bool online; | |
624d5c51 TH |
1947 | int rc; |
1948 | ||
9dadd45b TH |
1949 | rc = sata_link_hardreset(link, timing, deadline, &online, |
1950 | ata_sff_check_ready); | |
9dadd45b TH |
1951 | if (online) |
1952 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 TH |
1953 | |
1954 | DPRINTK("EXIT, class=%u\n", *class); | |
9dadd45b | 1955 | return rc; |
6d97dbd7 TH |
1956 | } |
1957 | ||
203c75b8 TH |
1958 | /** |
1959 | * ata_sff_postreset - SFF postreset callback | |
1960 | * @link: the target SFF ata_link | |
1961 | * @classes: classes of attached devices | |
1962 | * | |
1963 | * This function is invoked after a successful reset. It first | |
1964 | * calls ata_std_postreset() and performs SFF specific postreset | |
1965 | * processing. | |
1966 | * | |
1967 | * LOCKING: | |
1968 | * Kernel thread context (may sleep) | |
1969 | */ | |
1970 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
1971 | { | |
1972 | struct ata_port *ap = link->ap; | |
1973 | ||
1974 | ata_std_postreset(link, classes); | |
1975 | ||
1976 | /* is double-select really necessary? */ | |
1977 | if (classes[0] != ATA_DEV_NONE) | |
1978 | ap->ops->sff_dev_select(ap, 1); | |
1979 | if (classes[1] != ATA_DEV_NONE) | |
1980 | ap->ops->sff_dev_select(ap, 0); | |
1981 | ||
1982 | /* bail out if no device is present */ | |
1983 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
1984 | DPRINTK("EXIT, no device\n"); | |
1985 | return; | |
1986 | } | |
1987 | ||
1988 | /* set up device control */ | |
1989 | if (ap->ioaddr.ctl_addr) | |
1990 | iowrite8(ap->ctl, ap->ioaddr.ctl_addr); | |
1991 | } | |
1992 | ||
6d97dbd7 | 1993 | /** |
9363c382 | 1994 | * ata_sff_error_handler - Stock error handler for BMDMA controller |
6d97dbd7 | 1995 | * @ap: port to handle error for |
6d97dbd7 | 1996 | * |
9363c382 | 1997 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
1998 | * PATA and SATA controllers. Many controllers should be able to |
1999 | * use this EH as-is or with some added handling before and | |
2000 | * after. | |
2001 | * | |
6d97dbd7 TH |
2002 | * LOCKING: |
2003 | * Kernel thread context (may sleep) | |
2004 | */ | |
9363c382 | 2005 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2006 | { |
a1efdaba TH |
2007 | ata_reset_fn_t softreset = ap->ops->softreset; |
2008 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2009 | struct ata_queued_cmd *qc; |
2010 | unsigned long flags; | |
2011 | int thaw = 0; | |
2012 | ||
9af5c9c9 | 2013 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2014 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2015 | qc = NULL; | |
2016 | ||
2017 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 2018 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2019 | |
6d97dbd7 TH |
2020 | ap->hsm_task_state = HSM_ST_IDLE; |
2021 | ||
ed82f964 TH |
2022 | if (ap->ioaddr.bmdma_addr && |
2023 | qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 2024 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
2025 | u8 host_stat; |
2026 | ||
fbbb262d | 2027 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 2028 | |
6d97dbd7 TH |
2029 | /* BMDMA controllers indicate host bus error by |
2030 | * setting DMA_ERR bit and timing out. As it wasn't | |
2031 | * really a timeout event, adjust error mask and | |
2032 | * cancel frozen state. | |
2033 | */ | |
18d90deb | 2034 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { |
6d97dbd7 TH |
2035 | qc->err_mask = AC_ERR_HOST_BUS; |
2036 | thaw = 1; | |
2037 | } | |
2038 | ||
2039 | ap->ops->bmdma_stop(qc); | |
2040 | } | |
2041 | ||
9363c382 | 2042 | ata_sff_altstatus(ap); |
5682ed33 TH |
2043 | ap->ops->sff_check_status(ap); |
2044 | ap->ops->sff_irq_clear(ap); | |
6d97dbd7 | 2045 | |
ba6a1308 | 2046 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
2047 | |
2048 | if (thaw) | |
2049 | ata_eh_thaw_port(ap); | |
2050 | ||
2051 | /* PIO and DMA engines have been stopped, perform recovery */ | |
6d97dbd7 | 2052 | |
57c9efdf TH |
2053 | /* Ignore ata_sff_softreset if ctl isn't accessible and |
2054 | * built-in hardresets if SCR access isn't available. | |
a1efdaba | 2055 | */ |
9363c382 | 2056 | if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) |
a1efdaba | 2057 | softreset = NULL; |
57c9efdf | 2058 | if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link)) |
a1efdaba | 2059 | hardreset = NULL; |
6d97dbd7 | 2060 | |
a1efdaba TH |
2061 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2062 | ap->ops->postreset); | |
6d97dbd7 TH |
2063 | } |
2064 | ||
2065 | /** | |
9363c382 | 2066 | * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller |
6d97dbd7 TH |
2067 | * @qc: internal command to clean up |
2068 | * | |
2069 | * LOCKING: | |
2070 | * Kernel thread context (may sleep) | |
2071 | */ | |
9363c382 | 2072 | void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc) |
6d97dbd7 | 2073 | { |
61dd08c6 AC |
2074 | if (qc->ap->ioaddr.bmdma_addr) |
2075 | ata_bmdma_stop(qc); | |
6d97dbd7 TH |
2076 | } |
2077 | ||
d92e74d3 AC |
2078 | /** |
2079 | * ata_sff_port_start - Set port up for dma. | |
2080 | * @ap: Port to initialize | |
2081 | * | |
2082 | * Called just after data structures for each port are | |
2083 | * initialized. Allocates space for PRD table if the device | |
2084 | * is DMA capable SFF. | |
2085 | * | |
2086 | * May be used as the port_start() entry in ata_port_operations. | |
2087 | * | |
2088 | * LOCKING: | |
2089 | * Inherited from caller. | |
2090 | */ | |
d92e74d3 AC |
2091 | int ata_sff_port_start(struct ata_port *ap) |
2092 | { | |
2093 | if (ap->ioaddr.bmdma_addr) | |
2094 | return ata_port_start(ap); | |
2095 | return 0; | |
2096 | } | |
2097 | ||
624d5c51 | 2098 | /** |
9363c382 | 2099 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2100 | * @ioaddr: IO address structure to be initialized |
2101 | * | |
2102 | * Utility function which initializes data_addr, error_addr, | |
2103 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2104 | * device_addr, status_addr, and command_addr to standard offsets | |
2105 | * relative to cmd_addr. | |
2106 | * | |
2107 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2108 | */ | |
9363c382 | 2109 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2110 | { |
2111 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2112 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2113 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2114 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2115 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2116 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2117 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2118 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2119 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2120 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2121 | } | |
2122 | ||
9363c382 TH |
2123 | unsigned long ata_bmdma_mode_filter(struct ata_device *adev, |
2124 | unsigned long xfer_mask) | |
071ce34d TH |
2125 | { |
2126 | /* Filter out DMA modes if the device has been configured by | |
2127 | the BIOS as PIO only */ | |
2128 | ||
2129 | if (adev->link->ap->ioaddr.bmdma_addr == NULL) | |
2130 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
2131 | return xfer_mask; | |
2132 | } | |
2133 | ||
272f7884 TH |
2134 | /** |
2135 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2136 | * @qc: Info associated with this ATA transaction. | |
2137 | * | |
2138 | * LOCKING: | |
2139 | * spin_lock_irqsave(host lock) | |
2140 | */ | |
2141 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2142 | { | |
2143 | struct ata_port *ap = qc->ap; | |
2144 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2145 | u8 dmactl; | |
2146 | ||
2147 | /* load PRD table addr. */ | |
2148 | mb(); /* make sure PRD table writes are visible to controller */ | |
2149 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | |
2150 | ||
2151 | /* specify data direction, triple-check start bit is clear */ | |
2152 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2153 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2154 | if (!rw) | |
2155 | dmactl |= ATA_DMA_WR; | |
2156 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2157 | ||
2158 | /* issue r/w command */ | |
5682ed33 | 2159 | ap->ops->sff_exec_command(ap, &qc->tf); |
272f7884 TH |
2160 | } |
2161 | ||
2162 | /** | |
2163 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2164 | * @qc: Info associated with this ATA transaction. | |
2165 | * | |
2166 | * LOCKING: | |
2167 | * spin_lock_irqsave(host lock) | |
2168 | */ | |
2169 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2170 | { | |
2171 | struct ata_port *ap = qc->ap; | |
2172 | u8 dmactl; | |
2173 | ||
2174 | /* start host DMA transaction */ | |
2175 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2176 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2177 | ||
2178 | /* Strictly, one may wish to issue an ioread8() here, to | |
2179 | * flush the mmio write. However, control also passes | |
2180 | * to the hardware at this point, and it will interrupt | |
2181 | * us when we are to resume control. So, in effect, | |
2182 | * we don't care when the mmio write flushes. | |
2183 | * Further, a read of the DMA status register _immediately_ | |
2184 | * following the write may not be what certain flaky hardware | |
2185 | * is expected, so I think it is best to not add a readb() | |
2186 | * without first all the MMIO ATA cards/mobos. | |
2187 | * Or maybe I'm just being paranoid. | |
2188 | * | |
2189 | * FIXME: The posting of this write means I/O starts are | |
2190 | * unneccessarily delayed for MMIO | |
2191 | */ | |
2192 | } | |
2193 | ||
2194 | /** | |
2195 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
2196 | * @qc: Command we are ending DMA for | |
2197 | * | |
2198 | * Clears the ATA_DMA_START flag in the dma control register | |
2199 | * | |
2200 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
2201 | * | |
2202 | * LOCKING: | |
2203 | * spin_lock_irqsave(host lock) | |
2204 | */ | |
2205 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
2206 | { | |
2207 | struct ata_port *ap = qc->ap; | |
2208 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2209 | ||
2210 | /* clear start/stop bit */ | |
2211 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
2212 | mmio + ATA_DMA_CMD); | |
2213 | ||
2214 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
9363c382 | 2215 | ata_sff_altstatus(ap); /* dummy read */ |
272f7884 TH |
2216 | } |
2217 | ||
2218 | /** | |
2219 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
2220 | * @ap: Port associated with this ATA transaction. | |
2221 | * | |
2222 | * Read and return BMDMA status register. | |
2223 | * | |
2224 | * May be used as the bmdma_status() entry in ata_port_operations. | |
2225 | * | |
2226 | * LOCKING: | |
2227 | * spin_lock_irqsave(host lock) | |
2228 | */ | |
2229 | u8 ata_bmdma_status(struct ata_port *ap) | |
2230 | { | |
2231 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
2232 | } | |
2233 | ||
2234 | /** | |
624d5c51 TH |
2235 | * ata_bus_reset - reset host port and associated ATA channel |
2236 | * @ap: port to reset | |
2237 | * | |
2238 | * This is typically the first time we actually start issuing | |
2239 | * commands to the ATA channel. We wait for BSY to clear, then | |
2240 | * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its | |
2241 | * result. Determine what devices, if any, are on the channel | |
2242 | * by looking at the device 0/1 error register. Look at the signature | |
2243 | * stored in each device's taskfile registers, to determine if | |
2244 | * the device is ATA or ATAPI. | |
2245 | * | |
2246 | * LOCKING: | |
2247 | * PCI/etc. bus probe sem. | |
2248 | * Obtains host lock. | |
2249 | * | |
2250 | * SIDE EFFECTS: | |
2251 | * Sets ATA_FLAG_DISABLED if bus reset fails. | |
2252 | * | |
2253 | * DEPRECATED: | |
2254 | * This function is only for drivers which still use old EH and | |
2255 | * will be removed soon. | |
272f7884 | 2256 | */ |
624d5c51 | 2257 | void ata_bus_reset(struct ata_port *ap) |
272f7884 | 2258 | { |
624d5c51 TH |
2259 | struct ata_device *device = ap->link.device; |
2260 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
2261 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
2262 | u8 err; | |
2263 | unsigned int dev0, dev1 = 0, devmask = 0; | |
2264 | int rc; | |
2265 | ||
2266 | DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no); | |
2267 | ||
2268 | /* determine if device 0/1 are present */ | |
2269 | if (ap->flags & ATA_FLAG_SATA_RESET) | |
2270 | dev0 = 1; | |
2271 | else { | |
2272 | dev0 = ata_devchk(ap, 0); | |
2273 | if (slave_possible) | |
2274 | dev1 = ata_devchk(ap, 1); | |
2275 | } | |
2276 | ||
2277 | if (dev0) | |
2278 | devmask |= (1 << 0); | |
2279 | if (dev1) | |
2280 | devmask |= (1 << 1); | |
2281 | ||
2282 | /* select device 0 again */ | |
5682ed33 | 2283 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2284 | |
2285 | /* issue bus reset */ | |
2286 | if (ap->flags & ATA_FLAG_SRST) { | |
2287 | rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ); | |
2288 | if (rc && rc != -ENODEV) | |
2289 | goto err_out; | |
2290 | } | |
2291 | ||
2292 | /* | |
2293 | * determine by signature whether we have ATA or ATAPI devices | |
2294 | */ | |
9363c382 | 2295 | device[0].class = ata_sff_dev_classify(&device[0], dev0, &err); |
624d5c51 | 2296 | if ((slave_possible) && (err != 0x81)) |
9363c382 | 2297 | device[1].class = ata_sff_dev_classify(&device[1], dev1, &err); |
624d5c51 TH |
2298 | |
2299 | /* is double-select really necessary? */ | |
2300 | if (device[1].class != ATA_DEV_NONE) | |
5682ed33 | 2301 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 2302 | if (device[0].class != ATA_DEV_NONE) |
5682ed33 | 2303 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2304 | |
2305 | /* if no devices were detected, disable this port */ | |
2306 | if ((device[0].class == ATA_DEV_NONE) && | |
2307 | (device[1].class == ATA_DEV_NONE)) | |
2308 | goto err_out; | |
2309 | ||
2310 | if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { | |
2311 | /* set up device control for ATA_FLAG_SATA_RESET */ | |
2312 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
2313 | } | |
2314 | ||
2315 | DPRINTK("EXIT\n"); | |
2316 | return; | |
2317 | ||
2318 | err_out: | |
2319 | ata_port_printk(ap, KERN_ERR, "disabling port\n"); | |
2320 | ata_port_disable(ap); | |
2321 | ||
2322 | DPRINTK("EXIT\n"); | |
272f7884 TH |
2323 | } |
2324 | ||
1fdffbce | 2325 | #ifdef CONFIG_PCI |
4112e16a | 2326 | |
272f7884 | 2327 | /** |
9363c382 | 2328 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex |
272f7884 TH |
2329 | * @pdev: PCI device |
2330 | * | |
2331 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2332 | * enter non simplex mode. This implements the necessary logic to | |
2333 | * perform the task on such devices. Calling it on other devices will | |
2334 | * have -undefined- behaviour. | |
2335 | */ | |
9363c382 | 2336 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) |
4112e16a | 2337 | { |
272f7884 TH |
2338 | unsigned long bmdma = pci_resource_start(pdev, 4); |
2339 | u8 simplex; | |
a84471fe | 2340 | |
272f7884 TH |
2341 | if (bmdma == 0) |
2342 | return -ENOENT; | |
2343 | ||
2344 | simplex = inb(bmdma + 0x02); | |
2345 | outb(simplex & 0x60, bmdma + 0x02); | |
2346 | simplex = inb(bmdma + 0x02); | |
2347 | if (simplex & 0x80) | |
2348 | return -EOPNOTSUPP; | |
2349 | return 0; | |
2350 | } | |
2351 | ||
0f834de3 | 2352 | /** |
9363c382 | 2353 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host |
0f834de3 TH |
2354 | * @host: target ATA host |
2355 | * | |
2356 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
2357 | * | |
2358 | * LOCKING: | |
2359 | * Inherited from calling layer (may sleep). | |
2360 | * | |
2361 | * RETURNS: | |
2362 | * 0 on success, -errno otherwise. | |
2363 | */ | |
9363c382 | 2364 | int ata_pci_bmdma_init(struct ata_host *host) |
1fdffbce | 2365 | { |
0f834de3 TH |
2366 | struct device *gdev = host->dev; |
2367 | struct pci_dev *pdev = to_pci_dev(gdev); | |
2368 | int i, rc; | |
0d5ff566 | 2369 | |
6fdc99a2 AC |
2370 | /* No BAR4 allocation: No DMA */ |
2371 | if (pci_resource_start(pdev, 4) == 0) | |
2372 | return 0; | |
2373 | ||
0f834de3 TH |
2374 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
2375 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
2376 | if (rc) | |
2377 | return rc; | |
2378 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
2379 | if (rc) | |
2380 | return rc; | |
2381 | ||
2382 | /* request and iomap DMA region */ | |
35a10a80 | 2383 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); |
0f834de3 TH |
2384 | if (rc) { |
2385 | dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); | |
2386 | return -ENOMEM; | |
0d5ff566 | 2387 | } |
0f834de3 | 2388 | host->iomap = pcim_iomap_table(pdev); |
0d5ff566 | 2389 | |
1626aeb8 | 2390 | for (i = 0; i < 2; i++) { |
0f834de3 | 2391 | struct ata_port *ap = host->ports[i]; |
0f834de3 TH |
2392 | void __iomem *bmdma = host->iomap[4] + 8 * i; |
2393 | ||
2394 | if (ata_port_is_dummy(ap)) | |
2395 | continue; | |
2396 | ||
21b0ad4f | 2397 | ap->ioaddr.bmdma_addr = bmdma; |
0f834de3 TH |
2398 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && |
2399 | (ioread8(bmdma + 2) & 0x80)) | |
2400 | host->flags |= ATA_HOST_SIMPLEX; | |
cbcdd875 TH |
2401 | |
2402 | ata_port_desc(ap, "bmdma 0x%llx", | |
2403 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
0d5ff566 TH |
2404 | } |
2405 | ||
0f834de3 TH |
2406 | return 0; |
2407 | } | |
2ec7df04 | 2408 | |
272f7884 TH |
2409 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2410 | { | |
2411 | int i; | |
2412 | ||
2413 | /* Check the PCI resources for this channel are enabled */ | |
2414 | port = port * 2; | |
2415 | for (i = 0; i < 2; i ++) { | |
2416 | if (pci_resource_start(pdev, port + i) == 0 || | |
2417 | pci_resource_len(pdev, port + i) == 0) | |
2418 | return 0; | |
2419 | } | |
2420 | return 1; | |
2421 | } | |
2422 | ||
d491b27b | 2423 | /** |
9363c382 | 2424 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2425 | * @host: target ATA host |
d491b27b | 2426 | * |
1626aeb8 TH |
2427 | * Acquire native PCI ATA resources for @host and initialize the |
2428 | * first two ports of @host accordingly. Ports marked dummy are | |
2429 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2430 | * |
d583bc18 TH |
2431 | * Note that native PCI resources are valid even for legacy hosts |
2432 | * as we fix up pdev resources array early in boot, so this | |
2433 | * function can be used for both native and legacy SFF hosts. | |
2434 | * | |
d491b27b TH |
2435 | * LOCKING: |
2436 | * Inherited from calling layer (may sleep). | |
2437 | * | |
2438 | * RETURNS: | |
1626aeb8 TH |
2439 | * 0 if at least one port is initialized, -ENODEV if no port is |
2440 | * available. | |
d491b27b | 2441 | */ |
9363c382 | 2442 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2443 | { |
2444 | struct device *gdev = host->dev; | |
2445 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2446 | unsigned int mask = 0; |
d491b27b TH |
2447 | int i, rc; |
2448 | ||
d491b27b TH |
2449 | /* request, iomap BARs and init port addresses accordingly */ |
2450 | for (i = 0; i < 2; i++) { | |
2451 | struct ata_port *ap = host->ports[i]; | |
2452 | int base = i * 2; | |
2453 | void __iomem * const *iomap; | |
2454 | ||
1626aeb8 TH |
2455 | if (ata_port_is_dummy(ap)) |
2456 | continue; | |
2457 | ||
2458 | /* Discard disabled ports. Some controllers show | |
2459 | * their unused channels this way. Disabled ports are | |
2460 | * made dummy. | |
2461 | */ | |
2462 | if (!ata_resources_present(pdev, i)) { | |
2463 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2464 | continue; |
1626aeb8 | 2465 | } |
d491b27b | 2466 | |
35a10a80 TH |
2467 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2468 | dev_driver_string(gdev)); | |
d491b27b | 2469 | if (rc) { |
1626aeb8 TH |
2470 | dev_printk(KERN_WARNING, gdev, |
2471 | "failed to request/iomap BARs for port %d " | |
2472 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
2473 | if (rc == -EBUSY) |
2474 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2475 | ap->ops = &ata_dummy_port_ops; |
2476 | continue; | |
d491b27b TH |
2477 | } |
2478 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2479 | ||
2480 | ap->ioaddr.cmd_addr = iomap[base]; | |
2481 | ap->ioaddr.altstatus_addr = | |
2482 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2483 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2484 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2485 | |
cbcdd875 TH |
2486 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2487 | (unsigned long long)pci_resource_start(pdev, base), | |
2488 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2489 | ||
1626aeb8 TH |
2490 | mask |= 1 << i; |
2491 | } | |
2492 | ||
2493 | if (!mask) { | |
2494 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
2495 | return -ENODEV; | |
d491b27b TH |
2496 | } |
2497 | ||
2498 | return 0; | |
2499 | } | |
2500 | ||
21b0ad4f | 2501 | /** |
9363c382 | 2502 | * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host |
21b0ad4f | 2503 | * @pdev: target PCI device |
1626aeb8 | 2504 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2505 | * @r_host: out argument for the initialized ATA host |
2506 | * | |
2507 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
2508 | * resources and initialize it accordingly in one go. | |
2509 | * | |
2510 | * LOCKING: | |
2511 | * Inherited from calling layer (may sleep). | |
2512 | * | |
2513 | * RETURNS: | |
2514 | * 0 on success, -errno otherwise. | |
2515 | */ | |
9363c382 | 2516 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
d583bc18 TH |
2517 | const struct ata_port_info * const * ppi, |
2518 | struct ata_host **r_host) | |
21b0ad4f TH |
2519 | { |
2520 | struct ata_host *host; | |
21b0ad4f TH |
2521 | int rc; |
2522 | ||
2523 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2524 | return -ENOMEM; | |
2525 | ||
2526 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2527 | if (!host) { | |
2528 | dev_printk(KERN_ERR, &pdev->dev, | |
2529 | "failed to allocate ATA host\n"); | |
2530 | rc = -ENOMEM; | |
2531 | goto err_out; | |
2532 | } | |
2533 | ||
9363c382 | 2534 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2535 | if (rc) |
2536 | goto err_out; | |
2537 | ||
2538 | /* init DMA related stuff */ | |
9363c382 | 2539 | rc = ata_pci_bmdma_init(host); |
21b0ad4f TH |
2540 | if (rc) |
2541 | goto err_bmdma; | |
2542 | ||
2543 | devres_remove_group(&pdev->dev, NULL); | |
2544 | *r_host = host; | |
2545 | return 0; | |
2546 | ||
2547 | err_bmdma: | |
2548 | /* This is necessary because PCI and iomap resources are | |
2549 | * merged and releasing the top group won't release the | |
2550 | * acquired resources if some of those have been acquired | |
2551 | * before entering this function. | |
2552 | */ | |
2553 | pcim_iounmap_regions(pdev, 0xf); | |
2554 | err_out: | |
2555 | devres_release_group(&pdev->dev, NULL); | |
2556 | return rc; | |
2557 | } | |
2558 | ||
4e6b79fa | 2559 | /** |
9363c382 | 2560 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2561 | * @host: target SFF ATA host |
2562 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2563 | * @sht: scsi_host_template to use when registering the host | |
2564 | * | |
2565 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2566 | * hosts. This separate helper is necessary because SFF hosts | |
2567 | * use two separate interrupts in legacy mode. | |
2568 | * | |
2569 | * LOCKING: | |
2570 | * Inherited from calling layer (may sleep). | |
2571 | * | |
2572 | * RETURNS: | |
2573 | * 0 on success, -errno otherwise. | |
2574 | */ | |
9363c382 | 2575 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2576 | irq_handler_t irq_handler, |
2577 | struct scsi_host_template *sht) | |
2578 | { | |
2579 | struct device *dev = host->dev; | |
2580 | struct pci_dev *pdev = to_pci_dev(dev); | |
2581 | const char *drv_name = dev_driver_string(host->dev); | |
2582 | int legacy_mode = 0, rc; | |
2583 | ||
2584 | rc = ata_host_start(host); | |
2585 | if (rc) | |
2586 | return rc; | |
2587 | ||
2588 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
2589 | u8 tmp8, mask; | |
2590 | ||
2591 | /* TODO: What if one channel is in native mode ... */ | |
2592 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
2593 | mask = (1 << 2) | (1 << 0); | |
2594 | if ((tmp8 & mask) != mask) | |
2595 | legacy_mode = 1; | |
2596 | #if defined(CONFIG_NO_ATA_LEGACY) | |
2597 | /* Some platforms with PCI limits cannot address compat | |
2598 | port space. In that case we punt if their firmware has | |
2599 | left a device in compatibility mode */ | |
2600 | if (legacy_mode) { | |
2601 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
2602 | return -EOPNOTSUPP; | |
2603 | } | |
2604 | #endif | |
2605 | } | |
2606 | ||
2607 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2608 | return -ENOMEM; | |
2609 | ||
2610 | if (!legacy_mode && pdev->irq) { | |
2611 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
2612 | IRQF_SHARED, drv_name, host); | |
2613 | if (rc) | |
2614 | goto out; | |
2615 | ||
2616 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
2617 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
2618 | } else if (legacy_mode) { | |
2619 | if (!ata_port_is_dummy(host->ports[0])) { | |
2620 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2621 | irq_handler, IRQF_SHARED, | |
2622 | drv_name, host); | |
2623 | if (rc) | |
2624 | goto out; | |
2625 | ||
2626 | ata_port_desc(host->ports[0], "irq %d", | |
2627 | ATA_PRIMARY_IRQ(pdev)); | |
2628 | } | |
2629 | ||
2630 | if (!ata_port_is_dummy(host->ports[1])) { | |
2631 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2632 | irq_handler, IRQF_SHARED, | |
2633 | drv_name, host); | |
2634 | if (rc) | |
2635 | goto out; | |
2636 | ||
2637 | ata_port_desc(host->ports[1], "irq %d", | |
2638 | ATA_SECONDARY_IRQ(pdev)); | |
2639 | } | |
2640 | } | |
2641 | ||
2642 | rc = ata_host_register(host, sht); | |
2643 | out: | |
2644 | if (rc == 0) | |
2645 | devres_remove_group(dev, NULL); | |
2646 | else | |
2647 | devres_release_group(dev, NULL); | |
2648 | ||
2649 | return rc; | |
2650 | } | |
2651 | ||
1fdffbce | 2652 | /** |
9363c382 | 2653 | * ata_pci_sff_init_one - Initialize/register PCI IDE host controller |
1fdffbce | 2654 | * @pdev: Controller to be initialized |
1626aeb8 | 2655 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 2656 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 2657 | * @host_priv: host private_data |
1fdffbce JG |
2658 | * |
2659 | * This is a helper function which can be called from a driver's | |
2660 | * xxx_init_one() probe function if the hardware uses traditional | |
2661 | * IDE taskfile registers. | |
2662 | * | |
2663 | * This function calls pci_enable_device(), reserves its register | |
2664 | * regions, sets the dma mask, enables bus master mode, and calls | |
2665 | * ata_device_add() | |
2666 | * | |
2ec7df04 AC |
2667 | * ASSUMPTION: |
2668 | * Nobody makes a single channel controller that appears solely as | |
2669 | * the secondary legacy port on PCI. | |
2670 | * | |
1fdffbce JG |
2671 | * LOCKING: |
2672 | * Inherited from PCI layer (may sleep). | |
2673 | * | |
2674 | * RETURNS: | |
2675 | * Zero on success, negative on errno-based value on error. | |
2676 | */ | |
9363c382 TH |
2677 | int ata_pci_sff_init_one(struct pci_dev *pdev, |
2678 | const struct ata_port_info * const * ppi, | |
2679 | struct scsi_host_template *sht, void *host_priv) | |
1fdffbce | 2680 | { |
f0d36efd | 2681 | struct device *dev = &pdev->dev; |
1626aeb8 | 2682 | const struct ata_port_info *pi = NULL; |
0f834de3 | 2683 | struct ata_host *host = NULL; |
1626aeb8 | 2684 | int i, rc; |
1fdffbce JG |
2685 | |
2686 | DPRINTK("ENTER\n"); | |
2687 | ||
1626aeb8 TH |
2688 | /* look up the first valid port_info */ |
2689 | for (i = 0; i < 2 && ppi[i]; i++) { | |
2690 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
2691 | pi = ppi[i]; | |
2692 | break; | |
2693 | } | |
2694 | } | |
f0d36efd | 2695 | |
1626aeb8 TH |
2696 | if (!pi) { |
2697 | dev_printk(KERN_ERR, &pdev->dev, | |
2698 | "no valid port_info specified\n"); | |
2699 | return -EINVAL; | |
2700 | } | |
c791c306 | 2701 | |
1626aeb8 TH |
2702 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2703 | return -ENOMEM; | |
1fdffbce | 2704 | |
f0d36efd | 2705 | rc = pcim_enable_device(pdev); |
1fdffbce | 2706 | if (rc) |
4e6b79fa | 2707 | goto out; |
1fdffbce | 2708 | |
4e6b79fa | 2709 | /* prepare and activate SFF host */ |
9363c382 | 2710 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
d583bc18 | 2711 | if (rc) |
4e6b79fa | 2712 | goto out; |
887125e3 | 2713 | host->private_data = host_priv; |
d491b27b | 2714 | |
d491b27b | 2715 | pci_set_master(pdev); |
9363c382 | 2716 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
4e6b79fa TH |
2717 | out: |
2718 | if (rc == 0) | |
2719 | devres_remove_group(&pdev->dev, NULL); | |
2720 | else | |
2721 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2722 | |
1fdffbce JG |
2723 | return rc; |
2724 | } | |
2725 | ||
2726 | #endif /* CONFIG_PCI */ | |
2727 | ||
624d5c51 TH |
2728 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
2729 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); | |
9363c382 TH |
2730 | EXPORT_SYMBOL_GPL(ata_sff_qc_prep); |
2731 | EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep); | |
2732 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); | |
2733 | EXPORT_SYMBOL_GPL(ata_sff_check_status); | |
2734 | EXPORT_SYMBOL_GPL(ata_sff_altstatus); | |
2735 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); | |
2736 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); | |
2737 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); | |
2738 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); | |
2739 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); | |
2740 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); | |
2741 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); | |
2742 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); | |
2743 | EXPORT_SYMBOL_GPL(ata_sff_irq_clear); | |
2744 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); | |
2745 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); | |
22183bf5 | 2746 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
9363c382 TH |
2747 | EXPORT_SYMBOL_GPL(ata_sff_host_intr); |
2748 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); | |
2749 | EXPORT_SYMBOL_GPL(ata_sff_freeze); | |
2750 | EXPORT_SYMBOL_GPL(ata_sff_thaw); | |
2751 | EXPORT_SYMBOL_GPL(ata_sff_prereset); | |
2752 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); | |
2753 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); | |
2754 | EXPORT_SYMBOL_GPL(ata_sff_softreset); | |
2755 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); | |
2756 | EXPORT_SYMBOL_GPL(ata_sff_postreset); | |
2757 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); | |
2758 | EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd); | |
624d5c51 | 2759 | EXPORT_SYMBOL_GPL(ata_sff_port_start); |
9363c382 TH |
2760 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
2761 | EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter); | |
624d5c51 TH |
2762 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); |
2763 | EXPORT_SYMBOL_GPL(ata_bmdma_start); | |
2764 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); | |
2765 | EXPORT_SYMBOL_GPL(ata_bmdma_status); | |
2766 | EXPORT_SYMBOL_GPL(ata_bus_reset); | |
2767 | #ifdef CONFIG_PCI | |
9363c382 TH |
2768 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); |
2769 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); | |
2770 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); | |
2771 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); | |
2772 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); | |
2773 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); | |
624d5c51 | 2774 | #endif /* CONFIG_PCI */ |