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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce | 35 | #include <linux/kernel.h> |
5a0e3ad6 | 36 | #include <linux/gfp.h> |
1fdffbce JG |
37 | #include <linux/pci.h> |
38 | #include <linux/libata.h> | |
624d5c51 | 39 | #include <linux/highmem.h> |
1fdffbce JG |
40 | |
41 | #include "libata.h" | |
42 | ||
624d5c51 TH |
43 | const struct ata_port_operations ata_sff_port_ops = { |
44 | .inherits = &ata_base_port_ops, | |
45 | ||
9363c382 TH |
46 | .qc_prep = ata_sff_qc_prep, |
47 | .qc_issue = ata_sff_qc_issue, | |
4c9bf4e7 | 48 | .qc_fill_rtf = ata_sff_qc_fill_rtf, |
9363c382 TH |
49 | |
50 | .freeze = ata_sff_freeze, | |
51 | .thaw = ata_sff_thaw, | |
0aa1113d | 52 | .prereset = ata_sff_prereset, |
9363c382 | 53 | .softreset = ata_sff_softreset, |
57c9efdf | 54 | .hardreset = sata_sff_hardreset, |
203c75b8 | 55 | .postreset = ata_sff_postreset, |
9363c382 TH |
56 | .error_handler = ata_sff_error_handler, |
57 | .post_internal_cmd = ata_sff_post_internal_cmd, | |
58 | ||
5682ed33 TH |
59 | .sff_dev_select = ata_sff_dev_select, |
60 | .sff_check_status = ata_sff_check_status, | |
61 | .sff_tf_load = ata_sff_tf_load, | |
62 | .sff_tf_read = ata_sff_tf_read, | |
63 | .sff_exec_command = ata_sff_exec_command, | |
64 | .sff_data_xfer = ata_sff_data_xfer, | |
288623a0 | 65 | .sff_irq_clear = ata_sff_irq_clear, |
8244cd05 | 66 | .sff_drain_fifo = ata_sff_drain_fifo, |
624d5c51 | 67 | |
c96f1732 | 68 | .lost_interrupt = ata_sff_lost_interrupt, |
624d5c51 | 69 | }; |
0fe40ff8 | 70 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
624d5c51 | 71 | |
624d5c51 TH |
72 | /** |
73 | * ata_fill_sg - Fill PCI IDE PRD table | |
74 | * @qc: Metadata associated with taskfile to be transferred | |
75 | * | |
76 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
77 | * associated with the current disk command. | |
78 | * | |
79 | * LOCKING: | |
80 | * spin_lock_irqsave(host lock) | |
81 | * | |
82 | */ | |
83 | static void ata_fill_sg(struct ata_queued_cmd *qc) | |
84 | { | |
85 | struct ata_port *ap = qc->ap; | |
86 | struct scatterlist *sg; | |
87 | unsigned int si, pi; | |
88 | ||
89 | pi = 0; | |
90 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
91 | u32 addr, offset; | |
92 | u32 sg_len, len; | |
93 | ||
94 | /* determine if physical DMA addr spans 64K boundary. | |
95 | * Note h/w doesn't support 64-bit, so we unconditionally | |
96 | * truncate dma_addr_t to u32. | |
97 | */ | |
98 | addr = (u32) sg_dma_address(sg); | |
99 | sg_len = sg_dma_len(sg); | |
100 | ||
101 | while (sg_len) { | |
102 | offset = addr & 0xffff; | |
103 | len = sg_len; | |
104 | if ((offset + sg_len) > 0x10000) | |
105 | len = 0x10000 - offset; | |
106 | ||
107 | ap->prd[pi].addr = cpu_to_le32(addr); | |
108 | ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
109 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
110 | ||
111 | pi++; | |
112 | sg_len -= len; | |
113 | addr += len; | |
114 | } | |
115 | } | |
116 | ||
117 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
118 | } | |
119 | ||
120 | /** | |
121 | * ata_fill_sg_dumb - Fill PCI IDE PRD table | |
122 | * @qc: Metadata associated with taskfile to be transferred | |
123 | * | |
124 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
125 | * associated with the current disk command. Perform the fill | |
126 | * so that we avoid writing any length 64K records for | |
127 | * controllers that don't follow the spec. | |
128 | * | |
129 | * LOCKING: | |
130 | * spin_lock_irqsave(host lock) | |
131 | * | |
132 | */ | |
133 | static void ata_fill_sg_dumb(struct ata_queued_cmd *qc) | |
134 | { | |
135 | struct ata_port *ap = qc->ap; | |
136 | struct scatterlist *sg; | |
137 | unsigned int si, pi; | |
138 | ||
139 | pi = 0; | |
140 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
141 | u32 addr, offset; | |
142 | u32 sg_len, len, blen; | |
143 | ||
144 | /* determine if physical DMA addr spans 64K boundary. | |
145 | * Note h/w doesn't support 64-bit, so we unconditionally | |
146 | * truncate dma_addr_t to u32. | |
147 | */ | |
148 | addr = (u32) sg_dma_address(sg); | |
149 | sg_len = sg_dma_len(sg); | |
150 | ||
151 | while (sg_len) { | |
152 | offset = addr & 0xffff; | |
153 | len = sg_len; | |
154 | if ((offset + sg_len) > 0x10000) | |
155 | len = 0x10000 - offset; | |
156 | ||
157 | blen = len & 0xffff; | |
158 | ap->prd[pi].addr = cpu_to_le32(addr); | |
159 | if (blen == 0) { | |
0fe40ff8 AC |
160 | /* Some PATA chipsets like the CS5530 can't |
161 | cope with 0x0000 meaning 64K as the spec | |
162 | says */ | |
624d5c51 TH |
163 | ap->prd[pi].flags_len = cpu_to_le32(0x8000); |
164 | blen = 0x8000; | |
165 | ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000); | |
166 | } | |
167 | ap->prd[pi].flags_len = cpu_to_le32(blen); | |
168 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
169 | ||
170 | pi++; | |
171 | sg_len -= len; | |
172 | addr += len; | |
173 | } | |
174 | } | |
175 | ||
176 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
177 | } | |
178 | ||
179 | /** | |
9363c382 | 180 | * ata_sff_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
181 | * @qc: Metadata associated with taskfile to be prepared |
182 | * | |
183 | * Prepare ATA taskfile for submission. | |
184 | * | |
185 | * LOCKING: | |
186 | * spin_lock_irqsave(host lock) | |
187 | */ | |
9363c382 | 188 | void ata_sff_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
189 | { |
190 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
191 | return; | |
192 | ||
193 | ata_fill_sg(qc); | |
194 | } | |
0fe40ff8 | 195 | EXPORT_SYMBOL_GPL(ata_sff_qc_prep); |
624d5c51 TH |
196 | |
197 | /** | |
9363c382 | 198 | * ata_sff_dumb_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
199 | * @qc: Metadata associated with taskfile to be prepared |
200 | * | |
201 | * Prepare ATA taskfile for submission. | |
202 | * | |
203 | * LOCKING: | |
204 | * spin_lock_irqsave(host lock) | |
205 | */ | |
9363c382 | 206 | void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
207 | { |
208 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
209 | return; | |
210 | ||
211 | ata_fill_sg_dumb(qc); | |
212 | } | |
0fe40ff8 | 213 | EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep); |
624d5c51 | 214 | |
272f7884 | 215 | /** |
9363c382 | 216 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
217 | * @ap: port where the device is |
218 | * | |
219 | * Reads ATA taskfile status register for currently-selected device | |
220 | * and return its value. This also clears pending interrupts | |
221 | * from this device | |
222 | * | |
223 | * LOCKING: | |
224 | * Inherited from caller. | |
225 | */ | |
9363c382 | 226 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
227 | { |
228 | return ioread8(ap->ioaddr.status_addr); | |
229 | } | |
0fe40ff8 | 230 | EXPORT_SYMBOL_GPL(ata_sff_check_status); |
272f7884 TH |
231 | |
232 | /** | |
9363c382 | 233 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
234 | * @ap: port where the device is |
235 | * | |
236 | * Reads ATA taskfile alternate status register for | |
237 | * currently-selected device and return its value. | |
238 | * | |
239 | * Note: may NOT be used as the check_altstatus() entry in | |
240 | * ata_port_operations. | |
241 | * | |
242 | * LOCKING: | |
243 | * Inherited from caller. | |
244 | */ | |
a57c1bad | 245 | static u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 246 | { |
5682ed33 TH |
247 | if (ap->ops->sff_check_altstatus) |
248 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
249 | |
250 | return ioread8(ap->ioaddr.altstatus_addr); | |
251 | } | |
252 | ||
a57c1bad AC |
253 | /** |
254 | * ata_sff_irq_status - Check if the device is busy | |
255 | * @ap: port where the device is | |
256 | * | |
257 | * Determine if the port is currently busy. Uses altstatus | |
258 | * if available in order to avoid clearing shared IRQ status | |
259 | * when finding an IRQ source. Non ctl capable devices don't | |
260 | * share interrupt lines fortunately for us. | |
261 | * | |
262 | * LOCKING: | |
263 | * Inherited from caller. | |
264 | */ | |
265 | static u8 ata_sff_irq_status(struct ata_port *ap) | |
266 | { | |
267 | u8 status; | |
268 | ||
269 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
270 | status = ata_sff_altstatus(ap); | |
271 | /* Not us: We are busy */ | |
272 | if (status & ATA_BUSY) | |
0fe40ff8 | 273 | return status; |
a57c1bad AC |
274 | } |
275 | /* Clear INTRQ latch */ | |
6311c90a | 276 | status = ap->ops->sff_check_status(ap); |
a57c1bad AC |
277 | return status; |
278 | } | |
279 | ||
280 | /** | |
281 | * ata_sff_sync - Flush writes | |
282 | * @ap: Port to wait for. | |
283 | * | |
284 | * CAUTION: | |
285 | * If we have an mmio device with no ctl and no altstatus | |
286 | * method this will fail. No such devices are known to exist. | |
287 | * | |
288 | * LOCKING: | |
289 | * Inherited from caller. | |
290 | */ | |
291 | ||
292 | static void ata_sff_sync(struct ata_port *ap) | |
293 | { | |
294 | if (ap->ops->sff_check_altstatus) | |
295 | ap->ops->sff_check_altstatus(ap); | |
296 | else if (ap->ioaddr.altstatus_addr) | |
297 | ioread8(ap->ioaddr.altstatus_addr); | |
298 | } | |
299 | ||
300 | /** | |
301 | * ata_sff_pause - Flush writes and wait 400nS | |
302 | * @ap: Port to pause for. | |
303 | * | |
304 | * CAUTION: | |
305 | * If we have an mmio device with no ctl and no altstatus | |
306 | * method this will fail. No such devices are known to exist. | |
307 | * | |
308 | * LOCKING: | |
309 | * Inherited from caller. | |
310 | */ | |
311 | ||
312 | void ata_sff_pause(struct ata_port *ap) | |
313 | { | |
314 | ata_sff_sync(ap); | |
315 | ndelay(400); | |
316 | } | |
0fe40ff8 | 317 | EXPORT_SYMBOL_GPL(ata_sff_pause); |
a57c1bad AC |
318 | |
319 | /** | |
320 | * ata_sff_dma_pause - Pause before commencing DMA | |
321 | * @ap: Port to pause for. | |
322 | * | |
323 | * Perform I/O fencing and ensure sufficient cycle delays occur | |
324 | * for the HDMA1:0 transition | |
325 | */ | |
0fe40ff8 | 326 | |
a57c1bad AC |
327 | void ata_sff_dma_pause(struct ata_port *ap) |
328 | { | |
329 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
330 | /* An altstatus read will cause the needed delay without | |
331 | messing up the IRQ status */ | |
332 | ata_sff_altstatus(ap); | |
333 | return; | |
334 | } | |
335 | /* There are no DMA controllers without ctl. BUG here to ensure | |
336 | we never violate the HDMA1:0 transition timing and risk | |
337 | corruption. */ | |
338 | BUG(); | |
339 | } | |
0fe40ff8 | 340 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause); |
a57c1bad | 341 | |
624d5c51 | 342 | /** |
9363c382 | 343 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 | 344 | * @ap: port containing status register to be polled |
341c2c95 TH |
345 | * @tmout_pat: impatience timeout in msecs |
346 | * @tmout: overall timeout in msecs | |
624d5c51 TH |
347 | * |
348 | * Sleep until ATA Status register bit BSY clears, | |
349 | * or a timeout occurs. | |
350 | * | |
351 | * LOCKING: | |
352 | * Kernel thread context (may sleep). | |
353 | * | |
354 | * RETURNS: | |
355 | * 0 on success, -errno otherwise. | |
356 | */ | |
9363c382 TH |
357 | int ata_sff_busy_sleep(struct ata_port *ap, |
358 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
359 | { |
360 | unsigned long timer_start, timeout; | |
361 | u8 status; | |
362 | ||
9363c382 | 363 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 | 364 | timer_start = jiffies; |
341c2c95 | 365 | timeout = ata_deadline(timer_start, tmout_pat); |
624d5c51 TH |
366 | while (status != 0xff && (status & ATA_BUSY) && |
367 | time_before(jiffies, timeout)) { | |
368 | msleep(50); | |
9363c382 | 369 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
370 | } |
371 | ||
372 | if (status != 0xff && (status & ATA_BUSY)) | |
373 | ata_port_printk(ap, KERN_WARNING, | |
374 | "port is slow to respond, please be patient " | |
375 | "(Status 0x%x)\n", status); | |
376 | ||
341c2c95 | 377 | timeout = ata_deadline(timer_start, tmout); |
624d5c51 TH |
378 | while (status != 0xff && (status & ATA_BUSY) && |
379 | time_before(jiffies, timeout)) { | |
380 | msleep(50); | |
5682ed33 | 381 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
382 | } |
383 | ||
384 | if (status == 0xff) | |
385 | return -ENODEV; | |
386 | ||
387 | if (status & ATA_BUSY) { | |
388 | ata_port_printk(ap, KERN_ERR, "port failed to respond " | |
389 | "(%lu secs, Status 0x%x)\n", | |
341c2c95 | 390 | DIV_ROUND_UP(tmout, 1000), status); |
624d5c51 TH |
391 | return -EBUSY; |
392 | } | |
393 | ||
394 | return 0; | |
395 | } | |
0fe40ff8 | 396 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); |
624d5c51 | 397 | |
aa2731ad TH |
398 | static int ata_sff_check_ready(struct ata_link *link) |
399 | { | |
400 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
401 | ||
78ab88f0 | 402 | return ata_check_ready(status); |
aa2731ad TH |
403 | } |
404 | ||
624d5c51 | 405 | /** |
9363c382 | 406 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 407 | * @link: SFF link to wait ready status for |
624d5c51 TH |
408 | * @deadline: deadline jiffies for the operation |
409 | * | |
410 | * Sleep until ATA Status register bit BSY clears, or timeout | |
411 | * occurs. | |
412 | * | |
413 | * LOCKING: | |
414 | * Kernel thread context (may sleep). | |
415 | * | |
416 | * RETURNS: | |
417 | * 0 on success, -errno otherwise. | |
418 | */ | |
705e76be | 419 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 420 | { |
aa2731ad | 421 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 | 422 | } |
0fe40ff8 | 423 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); |
624d5c51 | 424 | |
41dec29b SS |
425 | /** |
426 | * ata_sff_set_devctl - Write device control reg | |
427 | * @ap: port where the device is | |
428 | * @ctl: value to write | |
429 | * | |
430 | * Writes ATA taskfile device control register. | |
431 | * | |
432 | * Note: may NOT be used as the sff_set_devctl() entry in | |
433 | * ata_port_operations. | |
434 | * | |
435 | * LOCKING: | |
436 | * Inherited from caller. | |
437 | */ | |
438 | static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl) | |
439 | { | |
440 | if (ap->ops->sff_set_devctl) | |
441 | ap->ops->sff_set_devctl(ap, ctl); | |
442 | else | |
443 | iowrite8(ctl, ap->ioaddr.ctl_addr); | |
444 | } | |
445 | ||
624d5c51 | 446 | /** |
9363c382 | 447 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
448 | * @ap: ATA channel to manipulate |
449 | * @device: ATA device (numbered from zero) to select | |
450 | * | |
451 | * Use the method defined in the ATA specification to | |
452 | * make either device 0, or device 1, active on the | |
453 | * ATA channel. Works with both PIO and MMIO. | |
454 | * | |
455 | * May be used as the dev_select() entry in ata_port_operations. | |
456 | * | |
457 | * LOCKING: | |
458 | * caller. | |
459 | */ | |
9363c382 | 460 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
461 | { |
462 | u8 tmp; | |
463 | ||
464 | if (device == 0) | |
465 | tmp = ATA_DEVICE_OBS; | |
466 | else | |
467 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
468 | ||
469 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 470 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 | 471 | } |
0fe40ff8 | 472 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); |
624d5c51 TH |
473 | |
474 | /** | |
475 | * ata_dev_select - Select device 0/1 on ATA bus | |
476 | * @ap: ATA channel to manipulate | |
477 | * @device: ATA device (numbered from zero) to select | |
478 | * @wait: non-zero to wait for Status register BSY bit to clear | |
479 | * @can_sleep: non-zero if context allows sleeping | |
480 | * | |
481 | * Use the method defined in the ATA specification to | |
482 | * make either device 0, or device 1, active on the | |
483 | * ATA channel. | |
484 | * | |
9363c382 TH |
485 | * This is a high-level version of ata_sff_dev_select(), which |
486 | * additionally provides the services of inserting the proper | |
487 | * pauses and status polling, where needed. | |
624d5c51 TH |
488 | * |
489 | * LOCKING: | |
490 | * caller. | |
491 | */ | |
c7a8209f | 492 | static void ata_dev_select(struct ata_port *ap, unsigned int device, |
624d5c51 TH |
493 | unsigned int wait, unsigned int can_sleep) |
494 | { | |
495 | if (ata_msg_probe(ap)) | |
496 | ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, " | |
497 | "device %u, wait %u\n", device, wait); | |
498 | ||
499 | if (wait) | |
500 | ata_wait_idle(ap); | |
501 | ||
5682ed33 | 502 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
503 | |
504 | if (wait) { | |
505 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
506 | msleep(150); | |
507 | ata_wait_idle(ap); | |
508 | } | |
509 | } | |
510 | ||
511 | /** | |
9363c382 | 512 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
513 | * @ap: Port on which interrupts are enabled. |
514 | * | |
515 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
516 | * wait for idle, clear any pending interrupts. | |
517 | * | |
e42a542b SS |
518 | * Note: may NOT be used as the sff_irq_on() entry in |
519 | * ata_port_operations. | |
520 | * | |
624d5c51 TH |
521 | * LOCKING: |
522 | * Inherited from caller. | |
523 | */ | |
e42a542b | 524 | void ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
525 | { |
526 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
e42a542b SS |
527 | |
528 | if (ap->ops->sff_irq_on) { | |
529 | ap->ops->sff_irq_on(ap); | |
530 | return; | |
531 | } | |
624d5c51 TH |
532 | |
533 | ap->ctl &= ~ATA_NIEN; | |
534 | ap->last_ctl = ap->ctl; | |
535 | ||
e42a542b SS |
536 | if (ap->ops->sff_set_devctl || ioaddr->ctl_addr) |
537 | ata_sff_set_devctl(ap, ap->ctl); | |
538 | ata_wait_idle(ap); | |
624d5c51 | 539 | |
5682ed33 | 540 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 541 | } |
0fe40ff8 | 542 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); |
624d5c51 TH |
543 | |
544 | /** | |
9363c382 | 545 | * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt. |
624d5c51 TH |
546 | * @ap: Port associated with this ATA transaction. |
547 | * | |
548 | * Clear interrupt and error flags in DMA status register. | |
549 | * | |
550 | * May be used as the irq_clear() entry in ata_port_operations. | |
551 | * | |
552 | * LOCKING: | |
553 | * spin_lock_irqsave(host lock) | |
554 | */ | |
9363c382 | 555 | void ata_sff_irq_clear(struct ata_port *ap) |
624d5c51 TH |
556 | { |
557 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
558 | ||
559 | if (!mmio) | |
560 | return; | |
561 | ||
562 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
563 | } | |
0fe40ff8 | 564 | EXPORT_SYMBOL_GPL(ata_sff_irq_clear); |
624d5c51 TH |
565 | |
566 | /** | |
9363c382 | 567 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
568 | * @ap: Port to which output is sent |
569 | * @tf: ATA taskfile register set | |
570 | * | |
571 | * Outputs ATA taskfile to standard ATA host controller. | |
572 | * | |
573 | * LOCKING: | |
574 | * Inherited from caller. | |
575 | */ | |
9363c382 | 576 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
577 | { |
578 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
579 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
580 | ||
581 | if (tf->ctl != ap->last_ctl) { | |
582 | if (ioaddr->ctl_addr) | |
583 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
584 | ap->last_ctl = tf->ctl; | |
624d5c51 TH |
585 | } |
586 | ||
587 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
efcb3cf7 | 588 | WARN_ON_ONCE(!ioaddr->ctl_addr); |
624d5c51 TH |
589 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
590 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
591 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
592 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
593 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
594 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
595 | tf->hob_feature, | |
596 | tf->hob_nsect, | |
597 | tf->hob_lbal, | |
598 | tf->hob_lbam, | |
599 | tf->hob_lbah); | |
600 | } | |
601 | ||
602 | if (is_addr) { | |
603 | iowrite8(tf->feature, ioaddr->feature_addr); | |
604 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
605 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
606 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
607 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
608 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
609 | tf->feature, | |
610 | tf->nsect, | |
611 | tf->lbal, | |
612 | tf->lbam, | |
613 | tf->lbah); | |
614 | } | |
615 | ||
616 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
617 | iowrite8(tf->device, ioaddr->device_addr); | |
618 | VPRINTK("device 0x%X\n", tf->device); | |
619 | } | |
624d5c51 | 620 | } |
0fe40ff8 | 621 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); |
624d5c51 TH |
622 | |
623 | /** | |
9363c382 | 624 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
625 | * @ap: Port from which input is read |
626 | * @tf: ATA taskfile register set for storing input | |
627 | * | |
628 | * Reads ATA taskfile registers for currently-selected device | |
629 | * into @tf. Assumes the device has a fully SFF compliant task file | |
630 | * layout and behaviour. If you device does not (eg has a different | |
631 | * status method) then you will need to provide a replacement tf_read | |
632 | * | |
633 | * LOCKING: | |
634 | * Inherited from caller. | |
635 | */ | |
9363c382 | 636 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
637 | { |
638 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
639 | ||
9363c382 | 640 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
641 | tf->feature = ioread8(ioaddr->error_addr); |
642 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
643 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
644 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
645 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
646 | tf->device = ioread8(ioaddr->device_addr); | |
647 | ||
648 | if (tf->flags & ATA_TFLAG_LBA48) { | |
649 | if (likely(ioaddr->ctl_addr)) { | |
650 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
651 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
652 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
653 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
654 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
655 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
656 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
657 | ap->last_ctl = tf->ctl; | |
658 | } else | |
efcb3cf7 | 659 | WARN_ON_ONCE(1); |
624d5c51 TH |
660 | } |
661 | } | |
0fe40ff8 | 662 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); |
624d5c51 TH |
663 | |
664 | /** | |
9363c382 | 665 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
666 | * @ap: port to which command is being issued |
667 | * @tf: ATA taskfile register set | |
668 | * | |
669 | * Issues ATA command, with proper synchronization with interrupt | |
670 | * handler / other threads. | |
671 | * | |
672 | * LOCKING: | |
673 | * spin_lock_irqsave(host lock) | |
674 | */ | |
9363c382 | 675 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
676 | { |
677 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
678 | ||
679 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 680 | ata_sff_pause(ap); |
624d5c51 | 681 | } |
0fe40ff8 | 682 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); |
624d5c51 TH |
683 | |
684 | /** | |
685 | * ata_tf_to_host - issue ATA taskfile to host controller | |
686 | * @ap: port to which command is being issued | |
687 | * @tf: ATA taskfile register set | |
688 | * | |
689 | * Issues ATA taskfile register set to ATA host controller, | |
690 | * with proper synchronization with interrupt handler and | |
691 | * other threads. | |
692 | * | |
693 | * LOCKING: | |
694 | * spin_lock_irqsave(host lock) | |
695 | */ | |
696 | static inline void ata_tf_to_host(struct ata_port *ap, | |
697 | const struct ata_taskfile *tf) | |
698 | { | |
5682ed33 TH |
699 | ap->ops->sff_tf_load(ap, tf); |
700 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
701 | } |
702 | ||
703 | /** | |
9363c382 | 704 | * ata_sff_data_xfer - Transfer data by PIO |
624d5c51 TH |
705 | * @dev: device to target |
706 | * @buf: data buffer | |
707 | * @buflen: buffer length | |
708 | * @rw: read/write | |
709 | * | |
710 | * Transfer data from/to the device data register by PIO. | |
711 | * | |
712 | * LOCKING: | |
713 | * Inherited from caller. | |
714 | * | |
715 | * RETURNS: | |
716 | * Bytes consumed. | |
717 | */ | |
9363c382 TH |
718 | unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, |
719 | unsigned int buflen, int rw) | |
624d5c51 TH |
720 | { |
721 | struct ata_port *ap = dev->link->ap; | |
722 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
723 | unsigned int words = buflen >> 1; | |
724 | ||
725 | /* Transfer multiple of 2 bytes */ | |
726 | if (rw == READ) | |
727 | ioread16_rep(data_addr, buf, words); | |
728 | else | |
729 | iowrite16_rep(data_addr, buf, words); | |
730 | ||
2102d749 | 731 | /* Transfer trailing byte, if any. */ |
624d5c51 | 732 | if (unlikely(buflen & 0x01)) { |
2102d749 | 733 | unsigned char pad[2]; |
624d5c51 | 734 | |
2102d749 SS |
735 | /* Point buf to the tail of buffer */ |
736 | buf += buflen - 1; | |
737 | ||
738 | /* | |
739 | * Use io*16_rep() accessors here as well to avoid pointlessly | |
972b94ff | 740 | * swapping bytes to and from on the big endian machines... |
2102d749 | 741 | */ |
624d5c51 | 742 | if (rw == READ) { |
2102d749 SS |
743 | ioread16_rep(data_addr, pad, 1); |
744 | *buf = pad[0]; | |
624d5c51 | 745 | } else { |
2102d749 SS |
746 | pad[0] = *buf; |
747 | iowrite16_rep(data_addr, pad, 1); | |
624d5c51 TH |
748 | } |
749 | words++; | |
750 | } | |
751 | ||
752 | return words << 1; | |
753 | } | |
0fe40ff8 | 754 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); |
624d5c51 | 755 | |
871af121 AC |
756 | /** |
757 | * ata_sff_data_xfer32 - Transfer data by PIO | |
758 | * @dev: device to target | |
759 | * @buf: data buffer | |
760 | * @buflen: buffer length | |
761 | * @rw: read/write | |
762 | * | |
763 | * Transfer data from/to the device data register by PIO using 32bit | |
764 | * I/O operations. | |
765 | * | |
766 | * LOCKING: | |
767 | * Inherited from caller. | |
768 | * | |
769 | * RETURNS: | |
770 | * Bytes consumed. | |
771 | */ | |
772 | ||
773 | unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf, | |
774 | unsigned int buflen, int rw) | |
775 | { | |
776 | struct ata_port *ap = dev->link->ap; | |
777 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
778 | unsigned int words = buflen >> 2; | |
779 | int slop = buflen & 3; | |
972b94ff | 780 | |
e3cf95dd AC |
781 | if (!(ap->pflags & ATA_PFLAG_PIO32)) |
782 | return ata_sff_data_xfer(dev, buf, buflen, rw); | |
871af121 AC |
783 | |
784 | /* Transfer multiple of 4 bytes */ | |
785 | if (rw == READ) | |
786 | ioread32_rep(data_addr, buf, words); | |
787 | else | |
788 | iowrite32_rep(data_addr, buf, words); | |
789 | ||
d1b3525b | 790 | /* Transfer trailing bytes, if any */ |
871af121 | 791 | if (unlikely(slop)) { |
d1b3525b SS |
792 | unsigned char pad[4]; |
793 | ||
794 | /* Point buf to the tail of buffer */ | |
795 | buf += buflen - slop; | |
796 | ||
797 | /* | |
798 | * Use io*_rep() accessors here as well to avoid pointlessly | |
972b94ff | 799 | * swapping bytes to and from on the big endian machines... |
d1b3525b | 800 | */ |
871af121 | 801 | if (rw == READ) { |
d1b3525b SS |
802 | if (slop < 3) |
803 | ioread16_rep(data_addr, pad, 1); | |
804 | else | |
805 | ioread32_rep(data_addr, pad, 1); | |
806 | memcpy(buf, pad, slop); | |
871af121 | 807 | } else { |
d1b3525b SS |
808 | memcpy(pad, buf, slop); |
809 | if (slop < 3) | |
810 | iowrite16_rep(data_addr, pad, 1); | |
811 | else | |
812 | iowrite32_rep(data_addr, pad, 1); | |
871af121 | 813 | } |
871af121 | 814 | } |
d1b3525b | 815 | return (buflen + 1) & ~1; |
871af121 AC |
816 | } |
817 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); | |
818 | ||
624d5c51 | 819 | /** |
9363c382 | 820 | * ata_sff_data_xfer_noirq - Transfer data by PIO |
624d5c51 TH |
821 | * @dev: device to target |
822 | * @buf: data buffer | |
823 | * @buflen: buffer length | |
824 | * @rw: read/write | |
825 | * | |
826 | * Transfer data from/to the device data register by PIO. Do the | |
827 | * transfer with interrupts disabled. | |
828 | * | |
829 | * LOCKING: | |
830 | * Inherited from caller. | |
831 | * | |
832 | * RETURNS: | |
833 | * Bytes consumed. | |
834 | */ | |
9363c382 TH |
835 | unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, |
836 | unsigned int buflen, int rw) | |
624d5c51 TH |
837 | { |
838 | unsigned long flags; | |
839 | unsigned int consumed; | |
840 | ||
841 | local_irq_save(flags); | |
9363c382 | 842 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); |
624d5c51 TH |
843 | local_irq_restore(flags); |
844 | ||
845 | return consumed; | |
846 | } | |
0fe40ff8 | 847 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); |
624d5c51 TH |
848 | |
849 | /** | |
850 | * ata_pio_sector - Transfer a sector of data. | |
851 | * @qc: Command on going | |
852 | * | |
853 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
854 | * | |
855 | * LOCKING: | |
856 | * Inherited from caller. | |
857 | */ | |
858 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
859 | { | |
860 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
861 | struct ata_port *ap = qc->ap; | |
862 | struct page *page; | |
863 | unsigned int offset; | |
864 | unsigned char *buf; | |
865 | ||
866 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
867 | ap->hsm_task_state = HSM_ST_LAST; | |
868 | ||
869 | page = sg_page(qc->cursg); | |
870 | offset = qc->cursg->offset + qc->cursg_ofs; | |
871 | ||
872 | /* get the current page and offset */ | |
873 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
874 | offset %= PAGE_SIZE; | |
875 | ||
876 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
877 | ||
878 | if (PageHighMem(page)) { | |
879 | unsigned long flags; | |
880 | ||
881 | /* FIXME: use a bounce buffer */ | |
882 | local_irq_save(flags); | |
883 | buf = kmap_atomic(page, KM_IRQ0); | |
884 | ||
885 | /* do the actual data transfer */ | |
5682ed33 TH |
886 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
887 | do_write); | |
624d5c51 TH |
888 | |
889 | kunmap_atomic(buf, KM_IRQ0); | |
890 | local_irq_restore(flags); | |
891 | } else { | |
892 | buf = page_address(page); | |
5682ed33 TH |
893 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
894 | do_write); | |
624d5c51 TH |
895 | } |
896 | ||
3842e835 | 897 | if (!do_write && !PageSlab(page)) |
2d68b7fe CM |
898 | flush_dcache_page(page); |
899 | ||
624d5c51 TH |
900 | qc->curbytes += qc->sect_size; |
901 | qc->cursg_ofs += qc->sect_size; | |
902 | ||
903 | if (qc->cursg_ofs == qc->cursg->length) { | |
904 | qc->cursg = sg_next(qc->cursg); | |
905 | qc->cursg_ofs = 0; | |
906 | } | |
907 | } | |
908 | ||
909 | /** | |
910 | * ata_pio_sectors - Transfer one or many sectors. | |
911 | * @qc: Command on going | |
912 | * | |
913 | * Transfer one or many sectors of data from/to the | |
914 | * ATA device for the DRQ request. | |
915 | * | |
916 | * LOCKING: | |
917 | * Inherited from caller. | |
918 | */ | |
919 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
920 | { | |
921 | if (is_multi_taskfile(&qc->tf)) { | |
922 | /* READ/WRITE MULTIPLE */ | |
923 | unsigned int nsect; | |
924 | ||
efcb3cf7 | 925 | WARN_ON_ONCE(qc->dev->multi_count == 0); |
624d5c51 TH |
926 | |
927 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
928 | qc->dev->multi_count); | |
929 | while (nsect--) | |
930 | ata_pio_sector(qc); | |
931 | } else | |
932 | ata_pio_sector(qc); | |
933 | ||
a57c1bad | 934 | ata_sff_sync(qc->ap); /* flush */ |
624d5c51 TH |
935 | } |
936 | ||
937 | /** | |
938 | * atapi_send_cdb - Write CDB bytes to hardware | |
939 | * @ap: Port to which ATAPI device is attached. | |
940 | * @qc: Taskfile currently active | |
941 | * | |
942 | * When device has indicated its readiness to accept | |
943 | * a CDB, this function is called. Send the CDB. | |
944 | * | |
945 | * LOCKING: | |
946 | * caller. | |
947 | */ | |
948 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
949 | { | |
950 | /* send SCSI cdb */ | |
951 | DPRINTK("send cdb\n"); | |
efcb3cf7 | 952 | WARN_ON_ONCE(qc->dev->cdb_len < 12); |
624d5c51 | 953 | |
5682ed33 | 954 | ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); |
a57c1bad AC |
955 | ata_sff_sync(ap); |
956 | /* FIXME: If the CDB is for DMA do we need to do the transition delay | |
957 | or is bmdma_start guaranteed to do it ? */ | |
624d5c51 TH |
958 | switch (qc->tf.protocol) { |
959 | case ATAPI_PROT_PIO: | |
960 | ap->hsm_task_state = HSM_ST; | |
961 | break; | |
962 | case ATAPI_PROT_NODATA: | |
963 | ap->hsm_task_state = HSM_ST_LAST; | |
964 | break; | |
965 | case ATAPI_PROT_DMA: | |
966 | ap->hsm_task_state = HSM_ST_LAST; | |
967 | /* initiate bmdma */ | |
968 | ap->ops->bmdma_start(qc); | |
969 | break; | |
970 | } | |
971 | } | |
972 | ||
973 | /** | |
974 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
975 | * @qc: Command on going | |
976 | * @bytes: number of bytes | |
977 | * | |
978 | * Transfer Transfer data from/to the ATAPI device. | |
979 | * | |
980 | * LOCKING: | |
981 | * Inherited from caller. | |
982 | * | |
983 | */ | |
984 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
985 | { | |
986 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
987 | struct ata_port *ap = qc->ap; | |
988 | struct ata_device *dev = qc->dev; | |
989 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
990 | struct scatterlist *sg; | |
991 | struct page *page; | |
992 | unsigned char *buf; | |
993 | unsigned int offset, count, consumed; | |
994 | ||
995 | next_sg: | |
996 | sg = qc->cursg; | |
997 | if (unlikely(!sg)) { | |
998 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
999 | "buf=%u cur=%u bytes=%u", | |
1000 | qc->nbytes, qc->curbytes, bytes); | |
1001 | return -1; | |
1002 | } | |
1003 | ||
1004 | page = sg_page(sg); | |
1005 | offset = sg->offset + qc->cursg_ofs; | |
1006 | ||
1007 | /* get the current page and offset */ | |
1008 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
1009 | offset %= PAGE_SIZE; | |
1010 | ||
1011 | /* don't overrun current sg */ | |
1012 | count = min(sg->length - qc->cursg_ofs, bytes); | |
1013 | ||
1014 | /* don't cross page boundaries */ | |
1015 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
1016 | ||
1017 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
1018 | ||
1019 | if (PageHighMem(page)) { | |
1020 | unsigned long flags; | |
1021 | ||
1022 | /* FIXME: use bounce buffer */ | |
1023 | local_irq_save(flags); | |
1024 | buf = kmap_atomic(page, KM_IRQ0); | |
1025 | ||
1026 | /* do the actual data transfer */ | |
0fe40ff8 AC |
1027 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
1028 | count, rw); | |
624d5c51 TH |
1029 | |
1030 | kunmap_atomic(buf, KM_IRQ0); | |
1031 | local_irq_restore(flags); | |
1032 | } else { | |
1033 | buf = page_address(page); | |
0fe40ff8 AC |
1034 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
1035 | count, rw); | |
624d5c51 TH |
1036 | } |
1037 | ||
1038 | bytes -= min(bytes, consumed); | |
1039 | qc->curbytes += count; | |
1040 | qc->cursg_ofs += count; | |
1041 | ||
1042 | if (qc->cursg_ofs == sg->length) { | |
1043 | qc->cursg = sg_next(qc->cursg); | |
1044 | qc->cursg_ofs = 0; | |
1045 | } | |
1046 | ||
a0f79f7a CB |
1047 | /* |
1048 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); | |
1049 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN | |
1050 | * check correctly as it doesn't know if it is the last request being | |
1051 | * made. Somebody should implement a proper sanity check. | |
1052 | */ | |
624d5c51 TH |
1053 | if (bytes) |
1054 | goto next_sg; | |
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | /** | |
1059 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
1060 | * @qc: Command on going | |
1061 | * | |
1062 | * Transfer Transfer data from/to the ATAPI device. | |
1063 | * | |
1064 | * LOCKING: | |
1065 | * Inherited from caller. | |
1066 | */ | |
1067 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
1068 | { | |
1069 | struct ata_port *ap = qc->ap; | |
1070 | struct ata_device *dev = qc->dev; | |
1071 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
1072 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
1073 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
1074 | ||
1075 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
1076 | * here to save some kernel stack usage. | |
1077 | * For normal completion, qc->result_tf is not relevant. For | |
1078 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
1079 | * So, the correctness of qc->result_tf is not affected. | |
1080 | */ | |
5682ed33 | 1081 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
1082 | ireason = qc->result_tf.nsect; |
1083 | bc_lo = qc->result_tf.lbam; | |
1084 | bc_hi = qc->result_tf.lbah; | |
1085 | bytes = (bc_hi << 8) | bc_lo; | |
1086 | ||
1087 | /* shall be cleared to zero, indicating xfer of data */ | |
1088 | if (unlikely(ireason & (1 << 0))) | |
1089 | goto atapi_check; | |
1090 | ||
1091 | /* make sure transfer direction matches expected */ | |
1092 | i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; | |
1093 | if (unlikely(do_write != i_write)) | |
1094 | goto atapi_check; | |
1095 | ||
1096 | if (unlikely(!bytes)) | |
1097 | goto atapi_check; | |
1098 | ||
1099 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
1100 | ||
1101 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
1102 | goto err_out; | |
a57c1bad | 1103 | ata_sff_sync(ap); /* flush */ |
624d5c51 TH |
1104 | |
1105 | return; | |
1106 | ||
1107 | atapi_check: | |
1108 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
1109 | ireason, bytes); | |
1110 | err_out: | |
1111 | qc->err_mask |= AC_ERR_HSM; | |
1112 | ap->hsm_task_state = HSM_ST_ERR; | |
1113 | } | |
1114 | ||
1115 | /** | |
1116 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
1117 | * @ap: the target ata_port | |
1118 | * @qc: qc on going | |
1119 | * | |
1120 | * RETURNS: | |
1121 | * 1 if ok in workqueue, 0 otherwise. | |
1122 | */ | |
0fe40ff8 AC |
1123 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, |
1124 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
1125 | { |
1126 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1127 | return 1; | |
1128 | ||
1129 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
1130 | if (qc->tf.protocol == ATA_PROT_PIO && | |
0fe40ff8 | 1131 | (qc->tf.flags & ATA_TFLAG_WRITE)) |
624d5c51 TH |
1132 | return 1; |
1133 | ||
1134 | if (ata_is_atapi(qc->tf.protocol) && | |
0fe40ff8 | 1135 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
624d5c51 TH |
1136 | return 1; |
1137 | } | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | /** | |
1143 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
1144 | * @qc: Command to complete | |
1145 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1146 | * | |
1147 | * Finish @qc which is running on standard HSM. | |
1148 | * | |
1149 | * LOCKING: | |
1150 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
1151 | * Otherwise, none on entry and grabs host lock. | |
1152 | */ | |
1153 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
1154 | { | |
1155 | struct ata_port *ap = qc->ap; | |
1156 | unsigned long flags; | |
1157 | ||
1158 | if (ap->ops->error_handler) { | |
1159 | if (in_wq) { | |
1160 | spin_lock_irqsave(ap->lock, flags); | |
1161 | ||
1162 | /* EH might have kicked in while host lock is | |
1163 | * released. | |
1164 | */ | |
1165 | qc = ata_qc_from_tag(ap, qc->tag); | |
1166 | if (qc) { | |
1167 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
e42a542b | 1168 | ata_sff_irq_on(ap); |
624d5c51 TH |
1169 | ata_qc_complete(qc); |
1170 | } else | |
1171 | ata_port_freeze(ap); | |
1172 | } | |
1173 | ||
1174 | spin_unlock_irqrestore(ap->lock, flags); | |
1175 | } else { | |
1176 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
1177 | ata_qc_complete(qc); | |
1178 | else | |
1179 | ata_port_freeze(ap); | |
1180 | } | |
1181 | } else { | |
1182 | if (in_wq) { | |
1183 | spin_lock_irqsave(ap->lock, flags); | |
e42a542b | 1184 | ata_sff_irq_on(ap); |
624d5c51 TH |
1185 | ata_qc_complete(qc); |
1186 | spin_unlock_irqrestore(ap->lock, flags); | |
1187 | } else | |
1188 | ata_qc_complete(qc); | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | /** | |
9363c382 | 1193 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
1194 | * @ap: the target ata_port |
1195 | * @qc: qc on going | |
1196 | * @status: current device status | |
1197 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1198 | * | |
1199 | * RETURNS: | |
1200 | * 1 when poll next status needed, 0 otherwise. | |
1201 | */ | |
9363c382 TH |
1202 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
1203 | u8 status, int in_wq) | |
624d5c51 | 1204 | { |
a836d3e8 | 1205 | struct ata_eh_info *ehi = &ap->link.eh_info; |
624d5c51 TH |
1206 | unsigned long flags = 0; |
1207 | int poll_next; | |
1208 | ||
efcb3cf7 | 1209 | WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0); |
624d5c51 | 1210 | |
9363c382 | 1211 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
1212 | * like DMA polling into the workqueue. Notice that |
1213 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
1214 | */ | |
efcb3cf7 | 1215 | WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc)); |
624d5c51 TH |
1216 | |
1217 | fsm_start: | |
1218 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
1219 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
1220 | ||
1221 | switch (ap->hsm_task_state) { | |
1222 | case HSM_ST_FIRST: | |
1223 | /* Send first data block or PACKET CDB */ | |
1224 | ||
1225 | /* If polling, we will stay in the work queue after | |
1226 | * sending the data. Otherwise, interrupt handler | |
1227 | * takes over after sending the data. | |
1228 | */ | |
1229 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
1230 | ||
1231 | /* check device status */ | |
1232 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1233 | /* handle BSY=0, DRQ=0 as error */ | |
1234 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1235 | /* device stops HSM for abort/error */ | |
1236 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 1237 | else { |
624d5c51 | 1238 | /* HSM violation. Let EH handle this */ |
a836d3e8 TH |
1239 | ata_ehi_push_desc(ehi, |
1240 | "ST_FIRST: !(DRQ|ERR|DF)"); | |
624d5c51 | 1241 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1242 | } |
624d5c51 TH |
1243 | |
1244 | ap->hsm_task_state = HSM_ST_ERR; | |
1245 | goto fsm_start; | |
1246 | } | |
1247 | ||
1248 | /* Device should not ask for data transfer (DRQ=1) | |
1249 | * when it finds something wrong. | |
1250 | * We ignore DRQ here and stop the HSM by | |
1251 | * changing hsm_task_state to HSM_ST_ERR and | |
1252 | * let the EH abort the command or reset the device. | |
1253 | */ | |
1254 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1255 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1256 | * when doing the next command (mostly request sense). | |
1257 | * We ignore ERR here to workaround and proceed sending | |
1258 | * the CDB. | |
1259 | */ | |
1260 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
a836d3e8 TH |
1261 | ata_ehi_push_desc(ehi, "ST_FIRST: " |
1262 | "DRQ=1 with device error, " | |
1263 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1264 | qc->err_mask |= AC_ERR_HSM; |
1265 | ap->hsm_task_state = HSM_ST_ERR; | |
1266 | goto fsm_start; | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | /* Send the CDB (atapi) or the first data block (ata pio out). | |
1271 | * During the state transition, interrupt handler shouldn't | |
1272 | * be invoked before the data transfer is complete and | |
1273 | * hsm_task_state is changed. Hence, the following locking. | |
1274 | */ | |
1275 | if (in_wq) | |
1276 | spin_lock_irqsave(ap->lock, flags); | |
1277 | ||
1278 | if (qc->tf.protocol == ATA_PROT_PIO) { | |
1279 | /* PIO data out protocol. | |
1280 | * send first data block. | |
1281 | */ | |
1282 | ||
1283 | /* ata_pio_sectors() might change the state | |
1284 | * to HSM_ST_LAST. so, the state is changed here | |
1285 | * before ata_pio_sectors(). | |
1286 | */ | |
1287 | ap->hsm_task_state = HSM_ST; | |
1288 | ata_pio_sectors(qc); | |
1289 | } else | |
1290 | /* send CDB */ | |
1291 | atapi_send_cdb(ap, qc); | |
1292 | ||
1293 | if (in_wq) | |
1294 | spin_unlock_irqrestore(ap->lock, flags); | |
1295 | ||
1296 | /* if polling, ata_pio_task() handles the rest. | |
1297 | * otherwise, interrupt handler takes over from here. | |
1298 | */ | |
1299 | break; | |
1300 | ||
1301 | case HSM_ST: | |
1302 | /* complete command or read/write the data register */ | |
1303 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1304 | /* ATAPI PIO protocol */ | |
1305 | if ((status & ATA_DRQ) == 0) { | |
1306 | /* No more data to transfer or device error. | |
1307 | * Device error will be tagged in HSM_ST_LAST. | |
1308 | */ | |
1309 | ap->hsm_task_state = HSM_ST_LAST; | |
1310 | goto fsm_start; | |
1311 | } | |
1312 | ||
1313 | /* Device should not ask for data transfer (DRQ=1) | |
1314 | * when it finds something wrong. | |
1315 | * We ignore DRQ here and stop the HSM by | |
1316 | * changing hsm_task_state to HSM_ST_ERR and | |
1317 | * let the EH abort the command or reset the device. | |
1318 | */ | |
1319 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
a836d3e8 TH |
1320 | ata_ehi_push_desc(ehi, "ST-ATAPI: " |
1321 | "DRQ=1 with device error, " | |
1322 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1323 | qc->err_mask |= AC_ERR_HSM; |
1324 | ap->hsm_task_state = HSM_ST_ERR; | |
1325 | goto fsm_start; | |
1326 | } | |
1327 | ||
1328 | atapi_pio_bytes(qc); | |
1329 | ||
1330 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1331 | /* bad ireason reported by device */ | |
1332 | goto fsm_start; | |
1333 | ||
1334 | } else { | |
1335 | /* ATA PIO protocol */ | |
1336 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1337 | /* handle BSY=0, DRQ=0 as error */ | |
6a6b97d3 | 1338 | if (likely(status & (ATA_ERR | ATA_DF))) { |
624d5c51 TH |
1339 | /* device stops HSM for abort/error */ |
1340 | qc->err_mask |= AC_ERR_DEV; | |
6a6b97d3 TH |
1341 | |
1342 | /* If diagnostic failed and this is | |
1343 | * IDENTIFY, it's likely a phantom | |
1344 | * device. Mark hint. | |
1345 | */ | |
1346 | if (qc->dev->horkage & | |
1347 | ATA_HORKAGE_DIAGNOSTIC) | |
1348 | qc->err_mask |= | |
1349 | AC_ERR_NODEV_HINT; | |
1350 | } else { | |
624d5c51 TH |
1351 | /* HSM violation. Let EH handle this. |
1352 | * Phantom devices also trigger this | |
1353 | * condition. Mark hint. | |
1354 | */ | |
a836d3e8 | 1355 | ata_ehi_push_desc(ehi, "ST-ATA: " |
80ee6f54 | 1356 | "DRQ=0 without device error, " |
a836d3e8 | 1357 | "dev_stat 0x%X", status); |
624d5c51 TH |
1358 | qc->err_mask |= AC_ERR_HSM | |
1359 | AC_ERR_NODEV_HINT; | |
a836d3e8 | 1360 | } |
624d5c51 TH |
1361 | |
1362 | ap->hsm_task_state = HSM_ST_ERR; | |
1363 | goto fsm_start; | |
1364 | } | |
1365 | ||
1366 | /* For PIO reads, some devices may ask for | |
1367 | * data transfer (DRQ=1) alone with ERR=1. | |
1368 | * We respect DRQ here and transfer one | |
1369 | * block of junk data before changing the | |
1370 | * hsm_task_state to HSM_ST_ERR. | |
1371 | * | |
1372 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1373 | * sense since the data block has been | |
1374 | * transferred to the device. | |
1375 | */ | |
1376 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1377 | /* data might be corrputed */ | |
1378 | qc->err_mask |= AC_ERR_DEV; | |
1379 | ||
1380 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1381 | ata_pio_sectors(qc); | |
1382 | status = ata_wait_idle(ap); | |
1383 | } | |
1384 | ||
a836d3e8 TH |
1385 | if (status & (ATA_BUSY | ATA_DRQ)) { |
1386 | ata_ehi_push_desc(ehi, "ST-ATA: " | |
1387 | "BUSY|DRQ persists on ERR|DF, " | |
1388 | "dev_stat 0x%X", status); | |
624d5c51 | 1389 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1390 | } |
624d5c51 | 1391 | |
b919930c TH |
1392 | /* There are oddball controllers with |
1393 | * status register stuck at 0x7f and | |
1394 | * lbal/m/h at zero which makes it | |
1395 | * pass all other presence detection | |
1396 | * mechanisms we have. Set NODEV_HINT | |
1397 | * for it. Kernel bz#7241. | |
1398 | */ | |
1399 | if (status == 0x7f) | |
1400 | qc->err_mask |= AC_ERR_NODEV_HINT; | |
1401 | ||
624d5c51 TH |
1402 | /* ata_pio_sectors() might change the |
1403 | * state to HSM_ST_LAST. so, the state | |
1404 | * is changed after ata_pio_sectors(). | |
1405 | */ | |
1406 | ap->hsm_task_state = HSM_ST_ERR; | |
1407 | goto fsm_start; | |
1408 | } | |
1409 | ||
1410 | ata_pio_sectors(qc); | |
1411 | ||
1412 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1413 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1414 | /* all data read */ | |
1415 | status = ata_wait_idle(ap); | |
1416 | goto fsm_start; | |
1417 | } | |
1418 | } | |
1419 | ||
1420 | poll_next = 1; | |
1421 | break; | |
1422 | ||
1423 | case HSM_ST_LAST: | |
1424 | if (unlikely(!ata_ok(status))) { | |
1425 | qc->err_mask |= __ac_err_mask(status); | |
1426 | ap->hsm_task_state = HSM_ST_ERR; | |
1427 | goto fsm_start; | |
1428 | } | |
1429 | ||
1430 | /* no more data to transfer */ | |
1431 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1432 | ap->print_id, qc->dev->devno, status); | |
1433 | ||
efcb3cf7 | 1434 | WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); |
624d5c51 TH |
1435 | |
1436 | ap->hsm_task_state = HSM_ST_IDLE; | |
1437 | ||
1438 | /* complete taskfile transaction */ | |
1439 | ata_hsm_qc_complete(qc, in_wq); | |
1440 | ||
1441 | poll_next = 0; | |
1442 | break; | |
1443 | ||
1444 | case HSM_ST_ERR: | |
624d5c51 TH |
1445 | ap->hsm_task_state = HSM_ST_IDLE; |
1446 | ||
1447 | /* complete taskfile transaction */ | |
1448 | ata_hsm_qc_complete(qc, in_wq); | |
1449 | ||
1450 | poll_next = 0; | |
1451 | break; | |
1452 | default: | |
1453 | poll_next = 0; | |
1454 | BUG(); | |
1455 | } | |
1456 | ||
1457 | return poll_next; | |
1458 | } | |
0fe40ff8 | 1459 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); |
624d5c51 TH |
1460 | |
1461 | void ata_pio_task(struct work_struct *work) | |
1462 | { | |
1463 | struct ata_port *ap = | |
1464 | container_of(work, struct ata_port, port_task.work); | |
1465 | struct ata_queued_cmd *qc = ap->port_task_data; | |
1466 | u8 status; | |
1467 | int poll_next; | |
1468 | ||
1469 | fsm_start: | |
efcb3cf7 | 1470 | WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE); |
624d5c51 TH |
1471 | |
1472 | /* | |
1473 | * This is purely heuristic. This is a fast path. | |
1474 | * Sometimes when we enter, BSY will be cleared in | |
1475 | * a chk-status or two. If not, the drive is probably seeking | |
1476 | * or something. Snooze for a couple msecs, then | |
1477 | * chk-status again. If still busy, queue delayed work. | |
1478 | */ | |
9363c382 | 1479 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 TH |
1480 | if (status & ATA_BUSY) { |
1481 | msleep(2); | |
9363c382 | 1482 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 TH |
1483 | if (status & ATA_BUSY) { |
1484 | ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE); | |
1485 | return; | |
1486 | } | |
1487 | } | |
1488 | ||
1489 | /* move the HSM */ | |
9363c382 | 1490 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1491 | |
1492 | /* another command or interrupt handler | |
1493 | * may be running at this point. | |
1494 | */ | |
1495 | if (poll_next) | |
1496 | goto fsm_start; | |
1497 | } | |
1498 | ||
1499 | /** | |
9363c382 | 1500 | * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner |
624d5c51 TH |
1501 | * @qc: command to issue to device |
1502 | * | |
1503 | * Using various libata functions and hooks, this function | |
1504 | * starts an ATA command. ATA commands are grouped into | |
1505 | * classes called "protocols", and issuing each type of protocol | |
1506 | * is slightly different. | |
1507 | * | |
1508 | * May be used as the qc_issue() entry in ata_port_operations. | |
1509 | * | |
1510 | * LOCKING: | |
1511 | * spin_lock_irqsave(host lock) | |
1512 | * | |
1513 | * RETURNS: | |
1514 | * Zero on success, AC_ERR_* mask on failure | |
1515 | */ | |
9363c382 | 1516 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1517 | { |
1518 | struct ata_port *ap = qc->ap; | |
1519 | ||
1520 | /* Use polling pio if the LLD doesn't handle | |
1521 | * interrupt driven pio and atapi CDB interrupt. | |
1522 | */ | |
1523 | if (ap->flags & ATA_FLAG_PIO_POLLING) { | |
1524 | switch (qc->tf.protocol) { | |
1525 | case ATA_PROT_PIO: | |
1526 | case ATA_PROT_NODATA: | |
1527 | case ATAPI_PROT_PIO: | |
1528 | case ATAPI_PROT_NODATA: | |
1529 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
1530 | break; | |
1531 | case ATAPI_PROT_DMA: | |
1532 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
1533 | /* see ata_dma_blacklisted() */ | |
1534 | BUG(); | |
1535 | break; | |
1536 | default: | |
1537 | break; | |
1538 | } | |
1539 | } | |
1540 | ||
1541 | /* select the device */ | |
1542 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1543 | ||
1544 | /* start the command */ | |
1545 | switch (qc->tf.protocol) { | |
1546 | case ATA_PROT_NODATA: | |
1547 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1548 | ata_qc_set_polling(qc); | |
1549 | ||
1550 | ata_tf_to_host(ap, &qc->tf); | |
1551 | ap->hsm_task_state = HSM_ST_LAST; | |
1552 | ||
1553 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1554 | ata_pio_queue_task(ap, qc, 0); | |
1555 | ||
1556 | break; | |
1557 | ||
1558 | case ATA_PROT_DMA: | |
efcb3cf7 | 1559 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); |
624d5c51 | 1560 | |
5682ed33 | 1561 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1562 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1563 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
1564 | ap->hsm_task_state = HSM_ST_LAST; | |
1565 | break; | |
1566 | ||
1567 | case ATA_PROT_PIO: | |
1568 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1569 | ata_qc_set_polling(qc); | |
1570 | ||
1571 | ata_tf_to_host(ap, &qc->tf); | |
1572 | ||
1573 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1574 | /* PIO data out protocol */ | |
1575 | ap->hsm_task_state = HSM_ST_FIRST; | |
1576 | ata_pio_queue_task(ap, qc, 0); | |
1577 | ||
1578 | /* always send first data block using | |
1579 | * the ata_pio_task() codepath. | |
1580 | */ | |
1581 | } else { | |
1582 | /* PIO data in protocol */ | |
1583 | ap->hsm_task_state = HSM_ST; | |
1584 | ||
1585 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1586 | ata_pio_queue_task(ap, qc, 0); | |
1587 | ||
1588 | /* if polling, ata_pio_task() handles the rest. | |
1589 | * otherwise, interrupt handler takes over from here. | |
1590 | */ | |
1591 | } | |
1592 | ||
1593 | break; | |
1594 | ||
1595 | case ATAPI_PROT_PIO: | |
1596 | case ATAPI_PROT_NODATA: | |
1597 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1598 | ata_qc_set_polling(qc); | |
1599 | ||
1600 | ata_tf_to_host(ap, &qc->tf); | |
1601 | ||
1602 | ap->hsm_task_state = HSM_ST_FIRST; | |
1603 | ||
1604 | /* send cdb by polling if no cdb interrupt */ | |
1605 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1606 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
1607 | ata_pio_queue_task(ap, qc, 0); | |
1608 | break; | |
1609 | ||
1610 | case ATAPI_PROT_DMA: | |
efcb3cf7 | 1611 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); |
624d5c51 | 1612 | |
5682ed33 | 1613 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1614 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1615 | ap->hsm_task_state = HSM_ST_FIRST; | |
1616 | ||
1617 | /* send cdb by polling if no cdb interrupt */ | |
1618 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1619 | ata_pio_queue_task(ap, qc, 0); | |
1620 | break; | |
1621 | ||
1622 | default: | |
efcb3cf7 | 1623 | WARN_ON_ONCE(1); |
624d5c51 TH |
1624 | return AC_ERR_SYSTEM; |
1625 | } | |
1626 | ||
1627 | return 0; | |
1628 | } | |
0fe40ff8 | 1629 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); |
624d5c51 | 1630 | |
22183bf5 TH |
1631 | /** |
1632 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1633 | * @qc: qc to fill result TF for | |
1634 | * | |
1635 | * @qc is finished and result TF needs to be filled. Fill it | |
1636 | * using ->sff_tf_read. | |
1637 | * | |
1638 | * LOCKING: | |
1639 | * spin_lock_irqsave(host lock) | |
1640 | * | |
1641 | * RETURNS: | |
1642 | * true indicating that result TF is successfully filled. | |
1643 | */ | |
1644 | bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) | |
1645 | { | |
1646 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
1647 | return true; | |
1648 | } | |
0fe40ff8 | 1649 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
22183bf5 | 1650 | |
624d5c51 | 1651 | /** |
9363c382 | 1652 | * ata_sff_host_intr - Handle host interrupt for given (port, task) |
624d5c51 TH |
1653 | * @ap: Port on which interrupt arrived (possibly...) |
1654 | * @qc: Taskfile currently active in engine | |
1655 | * | |
1656 | * Handle host interrupt for given queued command. Currently, | |
1657 | * only DMA interrupts are handled. All other commands are | |
1658 | * handled via polling with interrupts disabled (nIEN bit). | |
1659 | * | |
1660 | * LOCKING: | |
1661 | * spin_lock_irqsave(host lock) | |
1662 | * | |
1663 | * RETURNS: | |
1664 | * One if interrupt was handled, zero if not (shared irq). | |
1665 | */ | |
c96f1732 | 1666 | unsigned int ata_sff_host_intr(struct ata_port *ap, |
9363c382 | 1667 | struct ata_queued_cmd *qc) |
624d5c51 TH |
1668 | { |
1669 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
1670 | u8 status, host_stat = 0; | |
332ac7ff | 1671 | bool bmdma_stopped = false; |
624d5c51 TH |
1672 | |
1673 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1674 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1675 | ||
1676 | /* Check whether we are expecting interrupt in this state */ | |
1677 | switch (ap->hsm_task_state) { | |
1678 | case HSM_ST_FIRST: | |
1679 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1680 | * at this state when ready to receive CDB. | |
1681 | */ | |
1682 | ||
1683 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1684 | * The flag was turned on only for atapi devices. No | |
1685 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1686 | */ | |
1687 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1688 | goto idle_irq; | |
1689 | break; | |
1690 | case HSM_ST_LAST: | |
1691 | if (qc->tf.protocol == ATA_PROT_DMA || | |
1692 | qc->tf.protocol == ATAPI_PROT_DMA) { | |
1693 | /* check status of DMA engine */ | |
1694 | host_stat = ap->ops->bmdma_status(ap); | |
1695 | VPRINTK("ata%u: host_stat 0x%X\n", | |
1696 | ap->print_id, host_stat); | |
1697 | ||
1698 | /* if it's not our irq... */ | |
1699 | if (!(host_stat & ATA_DMA_INTR)) | |
1700 | goto idle_irq; | |
1701 | ||
1702 | /* before we do anything else, clear DMA-Start bit */ | |
1703 | ap->ops->bmdma_stop(qc); | |
332ac7ff | 1704 | bmdma_stopped = true; |
624d5c51 TH |
1705 | |
1706 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
1707 | /* error when transfering data to/from memory */ | |
1708 | qc->err_mask |= AC_ERR_HOST_BUS; | |
1709 | ap->hsm_task_state = HSM_ST_ERR; | |
1710 | } | |
1711 | } | |
1712 | break; | |
1713 | case HSM_ST: | |
1714 | break; | |
1715 | default: | |
1716 | goto idle_irq; | |
1717 | } | |
1718 | ||
624d5c51 | 1719 | |
a57c1bad AC |
1720 | /* check main status, clearing INTRQ if needed */ |
1721 | status = ata_sff_irq_status(ap); | |
332ac7ff TH |
1722 | if (status & ATA_BUSY) { |
1723 | if (bmdma_stopped) { | |
1724 | /* BMDMA engine is already stopped, we're screwed */ | |
1725 | qc->err_mask |= AC_ERR_HSM; | |
1726 | ap->hsm_task_state = HSM_ST_ERR; | |
1727 | } else | |
1728 | goto idle_irq; | |
1729 | } | |
624d5c51 | 1730 | |
9f2f7210 | 1731 | /* clear irq events */ |
5682ed33 | 1732 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1733 | |
9363c382 | 1734 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 TH |
1735 | |
1736 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || | |
1737 | qc->tf.protocol == ATAPI_PROT_DMA)) | |
1738 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
1739 | ||
1740 | return 1; /* irq handled */ | |
1741 | ||
1742 | idle_irq: | |
1743 | ap->stats.idle_irq++; | |
1744 | ||
1745 | #ifdef ATA_IRQ_TRAP | |
1746 | if ((ap->stats.idle_irq % 1000) == 0) { | |
5682ed33 TH |
1747 | ap->ops->sff_check_status(ap); |
1748 | ap->ops->sff_irq_clear(ap); | |
624d5c51 TH |
1749 | ata_port_printk(ap, KERN_WARNING, "irq trap\n"); |
1750 | return 1; | |
1751 | } | |
1752 | #endif | |
1753 | return 0; /* irq not handled */ | |
1754 | } | |
0fe40ff8 | 1755 | EXPORT_SYMBOL_GPL(ata_sff_host_intr); |
624d5c51 TH |
1756 | |
1757 | /** | |
9363c382 | 1758 | * ata_sff_interrupt - Default ATA host interrupt handler |
624d5c51 TH |
1759 | * @irq: irq line (unused) |
1760 | * @dev_instance: pointer to our ata_host information structure | |
1761 | * | |
1762 | * Default interrupt handler for PCI IDE devices. Calls | |
9363c382 | 1763 | * ata_sff_host_intr() for each port that is not disabled. |
624d5c51 TH |
1764 | * |
1765 | * LOCKING: | |
1766 | * Obtains host lock during operation. | |
1767 | * | |
1768 | * RETURNS: | |
1769 | * IRQ_NONE or IRQ_HANDLED. | |
1770 | */ | |
9363c382 | 1771 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) |
624d5c51 TH |
1772 | { |
1773 | struct ata_host *host = dev_instance; | |
332ac7ff | 1774 | bool retried = false; |
624d5c51 | 1775 | unsigned int i; |
332ac7ff | 1776 | unsigned int handled, idle, polling; |
624d5c51 TH |
1777 | unsigned long flags; |
1778 | ||
1779 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1780 | spin_lock_irqsave(&host->lock, flags); | |
1781 | ||
332ac7ff TH |
1782 | retry: |
1783 | handled = idle = polling = 0; | |
624d5c51 | 1784 | for (i = 0; i < host->n_ports; i++) { |
d88ec2e5 TH |
1785 | struct ata_port *ap = host->ports[i]; |
1786 | struct ata_queued_cmd *qc; | |
624d5c51 | 1787 | |
d88ec2e5 | 1788 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
27943620 TH |
1789 | if (qc) { |
1790 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) | |
1791 | handled |= ata_sff_host_intr(ap, qc); | |
1792 | else | |
1793 | polling |= 1 << i; | |
332ac7ff TH |
1794 | } else |
1795 | idle |= 1 << i; | |
27943620 TH |
1796 | } |
1797 | ||
1798 | /* | |
1799 | * If no port was expecting IRQ but the controller is actually | |
1800 | * asserting IRQ line, nobody cared will ensue. Check IRQ | |
1801 | * pending status if available and clear spurious IRQ. | |
1802 | */ | |
332ac7ff TH |
1803 | if (!handled && !retried) { |
1804 | bool retry = false; | |
1805 | ||
27943620 TH |
1806 | for (i = 0; i < host->n_ports; i++) { |
1807 | struct ata_port *ap = host->ports[i]; | |
1808 | ||
1809 | if (polling & (1 << i)) | |
1810 | continue; | |
1811 | ||
1812 | if (!ap->ops->sff_irq_check || | |
1813 | !ap->ops->sff_irq_check(ap)) | |
1814 | continue; | |
1815 | ||
332ac7ff TH |
1816 | if (idle & (1 << i)) { |
1817 | ap->ops->sff_check_status(ap); | |
1818 | ap->ops->sff_irq_clear(ap); | |
1819 | } else { | |
1820 | /* clear INTRQ and check if BUSY cleared */ | |
1821 | if (!(ap->ops->sff_check_status(ap) & ATA_BUSY)) | |
1822 | retry |= true; | |
1823 | /* | |
1824 | * With command in flight, we can't do | |
1825 | * sff_irq_clear() w/o racing with completion. | |
1826 | */ | |
1827 | } | |
1828 | } | |
1829 | ||
1830 | if (retry) { | |
1831 | retried = true; | |
1832 | goto retry; | |
27943620 | 1833 | } |
624d5c51 TH |
1834 | } |
1835 | ||
1836 | spin_unlock_irqrestore(&host->lock, flags); | |
1837 | ||
1838 | return IRQ_RETVAL(handled); | |
1839 | } | |
0fe40ff8 | 1840 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); |
624d5c51 | 1841 | |
c96f1732 AC |
1842 | /** |
1843 | * ata_sff_lost_interrupt - Check for an apparent lost interrupt | |
1844 | * @ap: port that appears to have timed out | |
1845 | * | |
1846 | * Called from the libata error handlers when the core code suspects | |
1847 | * an interrupt has been lost. If it has complete anything we can and | |
1848 | * then return. Interface must support altstatus for this faster | |
1849 | * recovery to occur. | |
1850 | * | |
1851 | * Locking: | |
1852 | * Caller holds host lock | |
1853 | */ | |
1854 | ||
1855 | void ata_sff_lost_interrupt(struct ata_port *ap) | |
1856 | { | |
1857 | u8 status; | |
1858 | struct ata_queued_cmd *qc; | |
1859 | ||
1860 | /* Only one outstanding command per SFF channel */ | |
1861 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
3e4ec344 TH |
1862 | /* We cannot lose an interrupt on a non-existent or polled command */ |
1863 | if (!qc || qc->tf.flags & ATA_TFLAG_POLLING) | |
c96f1732 AC |
1864 | return; |
1865 | /* See if the controller thinks it is still busy - if so the command | |
1866 | isn't a lost IRQ but is still in progress */ | |
1867 | status = ata_sff_altstatus(ap); | |
1868 | if (status & ATA_BUSY) | |
1869 | return; | |
1870 | ||
1871 | /* There was a command running, we are no longer busy and we have | |
1872 | no interrupt. */ | |
1873 | ata_port_printk(ap, KERN_WARNING, "lost interrupt (Status 0x%x)\n", | |
1874 | status); | |
1875 | /* Run the host interrupt logic as if the interrupt had not been | |
1876 | lost */ | |
1877 | ata_sff_host_intr(ap, qc); | |
1878 | } | |
1879 | EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt); | |
1880 | ||
624d5c51 | 1881 | /** |
9363c382 | 1882 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1883 | * @ap: port to freeze |
1884 | * | |
9f2f7210 | 1885 | * Freeze SFF controller port. |
624d5c51 TH |
1886 | * |
1887 | * LOCKING: | |
1888 | * Inherited from caller. | |
1889 | */ | |
9363c382 | 1890 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 | 1891 | { |
624d5c51 TH |
1892 | ap->ctl |= ATA_NIEN; |
1893 | ap->last_ctl = ap->ctl; | |
1894 | ||
41dec29b SS |
1895 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) |
1896 | ata_sff_set_devctl(ap, ap->ctl); | |
624d5c51 TH |
1897 | |
1898 | /* Under certain circumstances, some controllers raise IRQ on | |
1899 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1900 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1901 | */ | |
5682ed33 | 1902 | ap->ops->sff_check_status(ap); |
624d5c51 | 1903 | |
5682ed33 | 1904 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1905 | } |
0fe40ff8 | 1906 | EXPORT_SYMBOL_GPL(ata_sff_freeze); |
624d5c51 TH |
1907 | |
1908 | /** | |
9363c382 | 1909 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1910 | * @ap: port to thaw |
1911 | * | |
9363c382 | 1912 | * Thaw SFF controller port. |
624d5c51 TH |
1913 | * |
1914 | * LOCKING: | |
1915 | * Inherited from caller. | |
1916 | */ | |
9363c382 | 1917 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1918 | { |
624d5c51 | 1919 | /* clear & re-enable interrupts */ |
5682ed33 TH |
1920 | ap->ops->sff_check_status(ap); |
1921 | ap->ops->sff_irq_clear(ap); | |
e42a542b | 1922 | ata_sff_irq_on(ap); |
272f7884 | 1923 | } |
0fe40ff8 | 1924 | EXPORT_SYMBOL_GPL(ata_sff_thaw); |
272f7884 | 1925 | |
0aa1113d TH |
1926 | /** |
1927 | * ata_sff_prereset - prepare SFF link for reset | |
1928 | * @link: SFF link to be reset | |
1929 | * @deadline: deadline jiffies for the operation | |
1930 | * | |
1931 | * SFF link @link is about to be reset. Initialize it. It first | |
1932 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1933 | * being softreset. | |
1934 | * | |
1935 | * LOCKING: | |
1936 | * Kernel thread context (may sleep) | |
1937 | * | |
1938 | * RETURNS: | |
1939 | * 0 on success, -errno otherwise. | |
1940 | */ | |
1941 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1942 | { | |
0aa1113d TH |
1943 | struct ata_eh_context *ehc = &link->eh_context; |
1944 | int rc; | |
1945 | ||
1946 | rc = ata_std_prereset(link, deadline); | |
1947 | if (rc) | |
1948 | return rc; | |
1949 | ||
1950 | /* if we're about to do hardreset, nothing more to do */ | |
1951 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1952 | return 0; | |
1953 | ||
1954 | /* wait for !BSY if we don't know that no device is attached */ | |
1955 | if (!ata_link_offline(link)) { | |
705e76be | 1956 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d TH |
1957 | if (rc && rc != -ENODEV) { |
1958 | ata_link_printk(link, KERN_WARNING, "device not ready " | |
1959 | "(errno=%d), forcing hardreset\n", rc); | |
1960 | ehc->i.action |= ATA_EH_HARDRESET; | |
1961 | } | |
1962 | } | |
1963 | ||
1964 | return 0; | |
1965 | } | |
0fe40ff8 | 1966 | EXPORT_SYMBOL_GPL(ata_sff_prereset); |
0aa1113d | 1967 | |
90088bb4 | 1968 | /** |
624d5c51 TH |
1969 | * ata_devchk - PATA device presence detection |
1970 | * @ap: ATA channel to examine | |
1971 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1972 | * |
624d5c51 TH |
1973 | * This technique was originally described in |
1974 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1975 | * later found its way into the ATA/ATAPI spec. | |
1976 | * | |
1977 | * Write a pattern to the ATA shadow registers, | |
1978 | * and if a device is present, it will respond by | |
1979 | * correctly storing and echoing back the | |
1980 | * ATA shadow register contents. | |
90088bb4 TH |
1981 | * |
1982 | * LOCKING: | |
624d5c51 | 1983 | * caller. |
90088bb4 | 1984 | */ |
624d5c51 | 1985 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1986 | { |
1987 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1988 | u8 nsect, lbal; |
90088bb4 | 1989 | |
5682ed33 | 1990 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1991 | |
624d5c51 TH |
1992 | iowrite8(0x55, ioaddr->nsect_addr); |
1993 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1994 | |
624d5c51 TH |
1995 | iowrite8(0xaa, ioaddr->nsect_addr); |
1996 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1997 | |
624d5c51 TH |
1998 | iowrite8(0x55, ioaddr->nsect_addr); |
1999 | iowrite8(0xaa, ioaddr->lbal_addr); | |
2000 | ||
2001 | nsect = ioread8(ioaddr->nsect_addr); | |
2002 | lbal = ioread8(ioaddr->lbal_addr); | |
2003 | ||
2004 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
2005 | return 1; /* we found a device */ | |
2006 | ||
2007 | return 0; /* nothing found */ | |
90088bb4 TH |
2008 | } |
2009 | ||
272f7884 | 2010 | /** |
9363c382 | 2011 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
2012 | * @dev: ATA device to classify (starting at zero) |
2013 | * @present: device seems present | |
2014 | * @r_err: Value of error register on completion | |
272f7884 | 2015 | * |
624d5c51 TH |
2016 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
2017 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
2018 | * shadow registers, indicating the results of device detection | |
2019 | * and diagnostics. | |
272f7884 | 2020 | * |
624d5c51 TH |
2021 | * Select the ATA device, and read the values from the ATA shadow |
2022 | * registers. Then parse according to the Error register value, | |
2023 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
2024 | * |
2025 | * LOCKING: | |
624d5c51 TH |
2026 | * caller. |
2027 | * | |
2028 | * RETURNS: | |
2029 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 2030 | */ |
9363c382 | 2031 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 2032 | u8 *r_err) |
272f7884 | 2033 | { |
624d5c51 TH |
2034 | struct ata_port *ap = dev->link->ap; |
2035 | struct ata_taskfile tf; | |
2036 | unsigned int class; | |
2037 | u8 err; | |
2038 | ||
5682ed33 | 2039 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
2040 | |
2041 | memset(&tf, 0, sizeof(tf)); | |
2042 | ||
5682ed33 | 2043 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
2044 | err = tf.feature; |
2045 | if (r_err) | |
2046 | *r_err = err; | |
2047 | ||
2048 | /* see if device passed diags: continue and warn later */ | |
2049 | if (err == 0) | |
2050 | /* diagnostic fail : do nothing _YET_ */ | |
2051 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
2052 | else if (err == 1) | |
2053 | /* do nothing */ ; | |
2054 | else if ((dev->devno == 0) && (err == 0x81)) | |
2055 | /* do nothing */ ; | |
2056 | else | |
2057 | return ATA_DEV_NONE; | |
272f7884 | 2058 | |
624d5c51 TH |
2059 | /* determine if device is ATA or ATAPI */ |
2060 | class = ata_dev_classify(&tf); | |
272f7884 | 2061 | |
624d5c51 TH |
2062 | if (class == ATA_DEV_UNKNOWN) { |
2063 | /* If the device failed diagnostic, it's likely to | |
2064 | * have reported incorrect device signature too. | |
2065 | * Assume ATA device if the device seems present but | |
2066 | * device signature is invalid with diagnostic | |
2067 | * failure. | |
2068 | */ | |
2069 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
2070 | class = ATA_DEV_ATA; | |
2071 | else | |
2072 | class = ATA_DEV_NONE; | |
5682ed33 TH |
2073 | } else if ((class == ATA_DEV_ATA) && |
2074 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
2075 | class = ATA_DEV_NONE; |
2076 | ||
2077 | return class; | |
272f7884 | 2078 | } |
0fe40ff8 | 2079 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); |
272f7884 | 2080 | |
705e76be TH |
2081 | /** |
2082 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
2083 | * @link: SFF link which is just reset | |
2084 | * @devmask: mask of present devices | |
2085 | * @deadline: deadline jiffies for the operation | |
2086 | * | |
2087 | * Wait devices attached to SFF @link to become ready after | |
2088 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
2089 | * status register too early. | |
2090 | * | |
2091 | * LOCKING: | |
2092 | * Kernel thread context (may sleep). | |
2093 | * | |
2094 | * RETURNS: | |
2095 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
2096 | * don't seem to exist. -errno on other errors. | |
2097 | */ | |
2098 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
2099 | unsigned long deadline) | |
1fdffbce | 2100 | { |
705e76be | 2101 | struct ata_port *ap = link->ap; |
1fdffbce | 2102 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
2103 | unsigned int dev0 = devmask & (1 << 0); |
2104 | unsigned int dev1 = devmask & (1 << 1); | |
2105 | int rc, ret = 0; | |
1fdffbce | 2106 | |
341c2c95 | 2107 | msleep(ATA_WAIT_AFTER_RESET); |
705e76be TH |
2108 | |
2109 | /* always check readiness of the master device */ | |
2110 | rc = ata_sff_wait_ready(link, deadline); | |
2111 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
2112 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 2113 | */ |
705e76be TH |
2114 | if (rc) |
2115 | return rc; | |
1fdffbce | 2116 | |
624d5c51 TH |
2117 | /* if device 1 was found in ata_devchk, wait for register |
2118 | * access briefly, then wait for BSY to clear. | |
2119 | */ | |
2120 | if (dev1) { | |
2121 | int i; | |
1fdffbce | 2122 | |
5682ed33 | 2123 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 2124 | |
624d5c51 TH |
2125 | /* Wait for register access. Some ATAPI devices fail |
2126 | * to set nsect/lbal after reset, so don't waste too | |
2127 | * much time on it. We're gonna wait for !BSY anyway. | |
2128 | */ | |
2129 | for (i = 0; i < 2; i++) { | |
2130 | u8 nsect, lbal; | |
2131 | ||
2132 | nsect = ioread8(ioaddr->nsect_addr); | |
2133 | lbal = ioread8(ioaddr->lbal_addr); | |
2134 | if ((nsect == 1) && (lbal == 1)) | |
2135 | break; | |
2136 | msleep(50); /* give drive a breather */ | |
2137 | } | |
2138 | ||
705e76be | 2139 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
2140 | if (rc) { |
2141 | if (rc != -ENODEV) | |
2142 | return rc; | |
2143 | ret = rc; | |
2144 | } | |
1fdffbce JG |
2145 | } |
2146 | ||
624d5c51 | 2147 | /* is all this really necessary? */ |
5682ed33 | 2148 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 2149 | if (dev1) |
5682ed33 | 2150 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 2151 | if (dev0) |
5682ed33 | 2152 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2153 | |
2154 | return ret; | |
1fdffbce | 2155 | } |
0fe40ff8 | 2156 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); |
1fdffbce | 2157 | |
624d5c51 TH |
2158 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
2159 | unsigned long deadline) | |
2cc432ee | 2160 | { |
624d5c51 | 2161 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 2162 | |
624d5c51 TH |
2163 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
2164 | ||
2165 | /* software reset. causes dev0 to be selected */ | |
2166 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
2167 | udelay(20); /* FIXME: flush */ | |
2168 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
2169 | udelay(20); /* FIXME: flush */ | |
2170 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
e3e4385f | 2171 | ap->last_ctl = ap->ctl; |
624d5c51 | 2172 | |
705e76be TH |
2173 | /* wait the port to become ready */ |
2174 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
2175 | } |
2176 | ||
6d97dbd7 | 2177 | /** |
9363c382 | 2178 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
2179 | * @link: ATA link to reset |
2180 | * @classes: resulting classes of attached devices | |
2181 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2182 | * |
624d5c51 | 2183 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
2184 | * |
2185 | * LOCKING: | |
624d5c51 TH |
2186 | * Kernel thread context (may sleep) |
2187 | * | |
2188 | * RETURNS: | |
2189 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2190 | */ |
9363c382 | 2191 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 2192 | unsigned long deadline) |
6d97dbd7 | 2193 | { |
624d5c51 TH |
2194 | struct ata_port *ap = link->ap; |
2195 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
2196 | unsigned int devmask = 0; | |
2197 | int rc; | |
2198 | u8 err; | |
6d97dbd7 | 2199 | |
624d5c51 | 2200 | DPRINTK("ENTER\n"); |
6d97dbd7 | 2201 | |
624d5c51 TH |
2202 | /* determine if device 0/1 are present */ |
2203 | if (ata_devchk(ap, 0)) | |
2204 | devmask |= (1 << 0); | |
2205 | if (slave_possible && ata_devchk(ap, 1)) | |
2206 | devmask |= (1 << 1); | |
2207 | ||
2208 | /* select device 0 again */ | |
5682ed33 | 2209 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2210 | |
2211 | /* issue bus reset */ | |
2212 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
2213 | rc = ata_bus_softreset(ap, devmask, deadline); | |
2214 | /* if link is occupied, -ENODEV too is an error */ | |
2215 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
2216 | ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); | |
2217 | return rc; | |
2218 | } | |
0f0a3ad3 | 2219 | |
624d5c51 | 2220 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 2221 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
2222 | devmask & (1 << 0), &err); |
2223 | if (slave_possible && err != 0x81) | |
9363c382 | 2224 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
2225 | devmask & (1 << 1), &err); |
2226 | ||
624d5c51 TH |
2227 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
2228 | return 0; | |
6d97dbd7 | 2229 | } |
0fe40ff8 | 2230 | EXPORT_SYMBOL_GPL(ata_sff_softreset); |
6d97dbd7 TH |
2231 | |
2232 | /** | |
9363c382 | 2233 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
2234 | * @link: link to reset |
2235 | * @class: resulting class of attached device | |
2236 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2237 | * |
624d5c51 TH |
2238 | * SATA phy-reset host port using DET bits of SControl register, |
2239 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
2240 | * |
2241 | * LOCKING: | |
624d5c51 TH |
2242 | * Kernel thread context (may sleep) |
2243 | * | |
2244 | * RETURNS: | |
2245 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2246 | */ |
9363c382 | 2247 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 2248 | unsigned long deadline) |
6d97dbd7 | 2249 | { |
9dadd45b TH |
2250 | struct ata_eh_context *ehc = &link->eh_context; |
2251 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
2252 | bool online; | |
624d5c51 TH |
2253 | int rc; |
2254 | ||
9dadd45b TH |
2255 | rc = sata_link_hardreset(link, timing, deadline, &online, |
2256 | ata_sff_check_ready); | |
9dadd45b TH |
2257 | if (online) |
2258 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 TH |
2259 | |
2260 | DPRINTK("EXIT, class=%u\n", *class); | |
9dadd45b | 2261 | return rc; |
6d97dbd7 | 2262 | } |
0fe40ff8 | 2263 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); |
6d97dbd7 | 2264 | |
203c75b8 TH |
2265 | /** |
2266 | * ata_sff_postreset - SFF postreset callback | |
2267 | * @link: the target SFF ata_link | |
2268 | * @classes: classes of attached devices | |
2269 | * | |
2270 | * This function is invoked after a successful reset. It first | |
2271 | * calls ata_std_postreset() and performs SFF specific postreset | |
2272 | * processing. | |
2273 | * | |
2274 | * LOCKING: | |
2275 | * Kernel thread context (may sleep) | |
2276 | */ | |
2277 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
2278 | { | |
2279 | struct ata_port *ap = link->ap; | |
2280 | ||
2281 | ata_std_postreset(link, classes); | |
2282 | ||
2283 | /* is double-select really necessary? */ | |
2284 | if (classes[0] != ATA_DEV_NONE) | |
2285 | ap->ops->sff_dev_select(ap, 1); | |
2286 | if (classes[1] != ATA_DEV_NONE) | |
2287 | ap->ops->sff_dev_select(ap, 0); | |
2288 | ||
2289 | /* bail out if no device is present */ | |
2290 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
2291 | DPRINTK("EXIT, no device\n"); | |
2292 | return; | |
2293 | } | |
2294 | ||
2295 | /* set up device control */ | |
41dec29b SS |
2296 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) { |
2297 | ata_sff_set_devctl(ap, ap->ctl); | |
e3e4385f SM |
2298 | ap->last_ctl = ap->ctl; |
2299 | } | |
203c75b8 | 2300 | } |
0fe40ff8 | 2301 | EXPORT_SYMBOL_GPL(ata_sff_postreset); |
203c75b8 | 2302 | |
3d47aa8e AC |
2303 | /** |
2304 | * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers | |
2305 | * @qc: command | |
2306 | * | |
2307 | * Drain the FIFO and device of any stuck data following a command | |
3ad2f3fb | 2308 | * failing to complete. In some cases this is necessary before a |
3d47aa8e AC |
2309 | * reset will recover the device. |
2310 | * | |
2311 | */ | |
2312 | ||
2313 | void ata_sff_drain_fifo(struct ata_queued_cmd *qc) | |
2314 | { | |
2315 | int count; | |
2316 | struct ata_port *ap; | |
2317 | ||
2318 | /* We only need to flush incoming data when a command was running */ | |
2319 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) | |
2320 | return; | |
2321 | ||
2322 | ap = qc->ap; | |
2323 | /* Drain up to 64K of data before we give up this recovery method */ | |
2324 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) | |
9a8fd68b | 2325 | && count < 65536; count += 2) |
3d47aa8e AC |
2326 | ioread16(ap->ioaddr.data_addr); |
2327 | ||
2328 | /* Can become DEBUG later */ | |
2329 | if (count) | |
2330 | ata_port_printk(ap, KERN_DEBUG, | |
2331 | "drained %d bytes to clear DRQ.\n", count); | |
2332 | ||
2333 | } | |
2334 | EXPORT_SYMBOL_GPL(ata_sff_drain_fifo); | |
2335 | ||
6d97dbd7 | 2336 | /** |
9363c382 | 2337 | * ata_sff_error_handler - Stock error handler for BMDMA controller |
6d97dbd7 | 2338 | * @ap: port to handle error for |
6d97dbd7 | 2339 | * |
9363c382 | 2340 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2341 | * PATA and SATA controllers. Many controllers should be able to |
2342 | * use this EH as-is or with some added handling before and | |
2343 | * after. | |
2344 | * | |
6d97dbd7 TH |
2345 | * LOCKING: |
2346 | * Kernel thread context (may sleep) | |
2347 | */ | |
9363c382 | 2348 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2349 | { |
a1efdaba TH |
2350 | ata_reset_fn_t softreset = ap->ops->softreset; |
2351 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2352 | struct ata_queued_cmd *qc; |
2353 | unsigned long flags; | |
2a7adff0 | 2354 | bool thaw = false; |
6d97dbd7 | 2355 | |
9af5c9c9 | 2356 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2357 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2358 | qc = NULL; | |
2359 | ||
2360 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 2361 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2362 | |
6d97dbd7 TH |
2363 | ap->hsm_task_state = HSM_ST_IDLE; |
2364 | ||
ed82f964 TH |
2365 | if (ap->ioaddr.bmdma_addr && |
2366 | qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 2367 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
2368 | u8 host_stat; |
2369 | ||
fbbb262d | 2370 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 2371 | |
6d97dbd7 TH |
2372 | /* BMDMA controllers indicate host bus error by |
2373 | * setting DMA_ERR bit and timing out. As it wasn't | |
2374 | * really a timeout event, adjust error mask and | |
2375 | * cancel frozen state. | |
2376 | */ | |
3d47aa8e AC |
2377 | if (qc->err_mask == AC_ERR_TIMEOUT |
2378 | && (host_stat & ATA_DMA_ERR)) { | |
6d97dbd7 | 2379 | qc->err_mask = AC_ERR_HOST_BUS; |
2a7adff0 | 2380 | thaw = true; |
6d97dbd7 TH |
2381 | } |
2382 | ||
2383 | ap->ops->bmdma_stop(qc); | |
2a7adff0 TH |
2384 | |
2385 | /* if we're gonna thaw, make sure IRQ is clear */ | |
2386 | if (thaw) { | |
2387 | ap->ops->sff_check_status(ap); | |
2388 | ap->ops->sff_irq_clear(ap); | |
2389 | ||
2390 | spin_unlock_irqrestore(ap->lock, flags); | |
2391 | ata_eh_thaw_port(ap); | |
2392 | spin_lock_irqsave(ap->lock, flags); | |
2393 | } | |
6d97dbd7 TH |
2394 | } |
2395 | ||
3d47aa8e AC |
2396 | /* We *MUST* do FIFO draining before we issue a reset as several |
2397 | * devices helpfully clear their internal state and will lock solid | |
2398 | * if we touch the data port post reset. Pass qc in case anyone wants | |
2399 | * to do different PIO/DMA recovery or has per command fixups | |
2400 | */ | |
8244cd05 TH |
2401 | if (ap->ops->sff_drain_fifo) |
2402 | ap->ops->sff_drain_fifo(qc); | |
6d97dbd7 | 2403 | |
ba6a1308 | 2404 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 | 2405 | |
6d97dbd7 | 2406 | /* PIO and DMA engines have been stopped, perform recovery */ |
6d97dbd7 | 2407 | |
57c9efdf TH |
2408 | /* Ignore ata_sff_softreset if ctl isn't accessible and |
2409 | * built-in hardresets if SCR access isn't available. | |
a1efdaba | 2410 | */ |
9363c382 | 2411 | if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) |
a1efdaba | 2412 | softreset = NULL; |
57c9efdf | 2413 | if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link)) |
a1efdaba | 2414 | hardreset = NULL; |
6d97dbd7 | 2415 | |
a1efdaba TH |
2416 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2417 | ap->ops->postreset); | |
6d97dbd7 | 2418 | } |
0fe40ff8 | 2419 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); |
6d97dbd7 TH |
2420 | |
2421 | /** | |
9363c382 | 2422 | * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller |
6d97dbd7 TH |
2423 | * @qc: internal command to clean up |
2424 | * | |
2425 | * LOCKING: | |
2426 | * Kernel thread context (may sleep) | |
2427 | */ | |
9363c382 | 2428 | void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc) |
6d97dbd7 | 2429 | { |
570106df TH |
2430 | struct ata_port *ap = qc->ap; |
2431 | unsigned long flags; | |
2432 | ||
2433 | spin_lock_irqsave(ap->lock, flags); | |
2434 | ||
2435 | ap->hsm_task_state = HSM_ST_IDLE; | |
2436 | ||
2437 | if (ap->ioaddr.bmdma_addr) | |
294264a9 | 2438 | ap->ops->bmdma_stop(qc); |
570106df TH |
2439 | |
2440 | spin_unlock_irqrestore(ap->lock, flags); | |
6d97dbd7 | 2441 | } |
0fe40ff8 | 2442 | EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd); |
6d97dbd7 | 2443 | |
624d5c51 | 2444 | /** |
9363c382 | 2445 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2446 | * @ioaddr: IO address structure to be initialized |
2447 | * | |
2448 | * Utility function which initializes data_addr, error_addr, | |
2449 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2450 | * device_addr, status_addr, and command_addr to standard offsets | |
2451 | * relative to cmd_addr. | |
2452 | * | |
2453 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2454 | */ | |
9363c382 | 2455 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2456 | { |
2457 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2458 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2459 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2460 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2461 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2462 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2463 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2464 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2465 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2466 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2467 | } | |
0fe40ff8 | 2468 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
624d5c51 | 2469 | |
1fdffbce | 2470 | #ifdef CONFIG_PCI |
4112e16a | 2471 | |
272f7884 TH |
2472 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2473 | { | |
2474 | int i; | |
2475 | ||
2476 | /* Check the PCI resources for this channel are enabled */ | |
2477 | port = port * 2; | |
0fe40ff8 | 2478 | for (i = 0; i < 2; i++) { |
272f7884 TH |
2479 | if (pci_resource_start(pdev, port + i) == 0 || |
2480 | pci_resource_len(pdev, port + i) == 0) | |
2481 | return 0; | |
2482 | } | |
2483 | return 1; | |
2484 | } | |
2485 | ||
d491b27b | 2486 | /** |
9363c382 | 2487 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2488 | * @host: target ATA host |
d491b27b | 2489 | * |
1626aeb8 TH |
2490 | * Acquire native PCI ATA resources for @host and initialize the |
2491 | * first two ports of @host accordingly. Ports marked dummy are | |
2492 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2493 | * |
d583bc18 TH |
2494 | * Note that native PCI resources are valid even for legacy hosts |
2495 | * as we fix up pdev resources array early in boot, so this | |
2496 | * function can be used for both native and legacy SFF hosts. | |
2497 | * | |
d491b27b TH |
2498 | * LOCKING: |
2499 | * Inherited from calling layer (may sleep). | |
2500 | * | |
2501 | * RETURNS: | |
1626aeb8 TH |
2502 | * 0 if at least one port is initialized, -ENODEV if no port is |
2503 | * available. | |
d491b27b | 2504 | */ |
9363c382 | 2505 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2506 | { |
2507 | struct device *gdev = host->dev; | |
2508 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2509 | unsigned int mask = 0; |
d491b27b TH |
2510 | int i, rc; |
2511 | ||
d491b27b TH |
2512 | /* request, iomap BARs and init port addresses accordingly */ |
2513 | for (i = 0; i < 2; i++) { | |
2514 | struct ata_port *ap = host->ports[i]; | |
2515 | int base = i * 2; | |
2516 | void __iomem * const *iomap; | |
2517 | ||
1626aeb8 TH |
2518 | if (ata_port_is_dummy(ap)) |
2519 | continue; | |
2520 | ||
2521 | /* Discard disabled ports. Some controllers show | |
2522 | * their unused channels this way. Disabled ports are | |
2523 | * made dummy. | |
2524 | */ | |
2525 | if (!ata_resources_present(pdev, i)) { | |
2526 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2527 | continue; |
1626aeb8 | 2528 | } |
d491b27b | 2529 | |
35a10a80 TH |
2530 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2531 | dev_driver_string(gdev)); | |
d491b27b | 2532 | if (rc) { |
1626aeb8 TH |
2533 | dev_printk(KERN_WARNING, gdev, |
2534 | "failed to request/iomap BARs for port %d " | |
2535 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
2536 | if (rc == -EBUSY) |
2537 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2538 | ap->ops = &ata_dummy_port_ops; |
2539 | continue; | |
d491b27b TH |
2540 | } |
2541 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2542 | ||
2543 | ap->ioaddr.cmd_addr = iomap[base]; | |
2544 | ap->ioaddr.altstatus_addr = | |
2545 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2546 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2547 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2548 | |
cbcdd875 TH |
2549 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2550 | (unsigned long long)pci_resource_start(pdev, base), | |
2551 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2552 | ||
1626aeb8 TH |
2553 | mask |= 1 << i; |
2554 | } | |
2555 | ||
2556 | if (!mask) { | |
2557 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
2558 | return -ENODEV; | |
d491b27b TH |
2559 | } |
2560 | ||
2561 | return 0; | |
2562 | } | |
0fe40ff8 | 2563 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); |
d491b27b | 2564 | |
21b0ad4f | 2565 | /** |
9363c382 | 2566 | * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host |
21b0ad4f | 2567 | * @pdev: target PCI device |
1626aeb8 | 2568 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2569 | * @r_host: out argument for the initialized ATA host |
2570 | * | |
2571 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
2572 | * resources and initialize it accordingly in one go. | |
2573 | * | |
2574 | * LOCKING: | |
2575 | * Inherited from calling layer (may sleep). | |
2576 | * | |
2577 | * RETURNS: | |
2578 | * 0 on success, -errno otherwise. | |
2579 | */ | |
9363c382 | 2580 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
0fe40ff8 | 2581 | const struct ata_port_info * const *ppi, |
d583bc18 | 2582 | struct ata_host **r_host) |
21b0ad4f TH |
2583 | { |
2584 | struct ata_host *host; | |
21b0ad4f TH |
2585 | int rc; |
2586 | ||
2587 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2588 | return -ENOMEM; | |
2589 | ||
2590 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2591 | if (!host) { | |
2592 | dev_printk(KERN_ERR, &pdev->dev, | |
2593 | "failed to allocate ATA host\n"); | |
2594 | rc = -ENOMEM; | |
2595 | goto err_out; | |
2596 | } | |
2597 | ||
9363c382 | 2598 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2599 | if (rc) |
2600 | goto err_out; | |
2601 | ||
2602 | /* init DMA related stuff */ | |
c7087652 | 2603 | ata_pci_bmdma_init(host); |
21b0ad4f TH |
2604 | |
2605 | devres_remove_group(&pdev->dev, NULL); | |
2606 | *r_host = host; | |
2607 | return 0; | |
2608 | ||
0fe40ff8 | 2609 | err_out: |
21b0ad4f TH |
2610 | devres_release_group(&pdev->dev, NULL); |
2611 | return rc; | |
2612 | } | |
0fe40ff8 | 2613 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); |
21b0ad4f | 2614 | |
4e6b79fa | 2615 | /** |
9363c382 | 2616 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2617 | * @host: target SFF ATA host |
2618 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2619 | * @sht: scsi_host_template to use when registering the host | |
2620 | * | |
2621 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2622 | * hosts. This separate helper is necessary because SFF hosts | |
2623 | * use two separate interrupts in legacy mode. | |
2624 | * | |
2625 | * LOCKING: | |
2626 | * Inherited from calling layer (may sleep). | |
2627 | * | |
2628 | * RETURNS: | |
2629 | * 0 on success, -errno otherwise. | |
2630 | */ | |
9363c382 | 2631 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2632 | irq_handler_t irq_handler, |
2633 | struct scsi_host_template *sht) | |
2634 | { | |
2635 | struct device *dev = host->dev; | |
2636 | struct pci_dev *pdev = to_pci_dev(dev); | |
2637 | const char *drv_name = dev_driver_string(host->dev); | |
2638 | int legacy_mode = 0, rc; | |
2639 | ||
2640 | rc = ata_host_start(host); | |
2641 | if (rc) | |
2642 | return rc; | |
2643 | ||
2644 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
2645 | u8 tmp8, mask; | |
2646 | ||
2647 | /* TODO: What if one channel is in native mode ... */ | |
2648 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
2649 | mask = (1 << 2) | (1 << 0); | |
2650 | if ((tmp8 & mask) != mask) | |
2651 | legacy_mode = 1; | |
2652 | #if defined(CONFIG_NO_ATA_LEGACY) | |
2653 | /* Some platforms with PCI limits cannot address compat | |
2654 | port space. In that case we punt if their firmware has | |
2655 | left a device in compatibility mode */ | |
2656 | if (legacy_mode) { | |
2657 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
2658 | return -EOPNOTSUPP; | |
2659 | } | |
2660 | #endif | |
2661 | } | |
2662 | ||
2663 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2664 | return -ENOMEM; | |
2665 | ||
2666 | if (!legacy_mode && pdev->irq) { | |
2667 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
2668 | IRQF_SHARED, drv_name, host); | |
2669 | if (rc) | |
2670 | goto out; | |
2671 | ||
2672 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
2673 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
2674 | } else if (legacy_mode) { | |
2675 | if (!ata_port_is_dummy(host->ports[0])) { | |
2676 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2677 | irq_handler, IRQF_SHARED, | |
2678 | drv_name, host); | |
2679 | if (rc) | |
2680 | goto out; | |
2681 | ||
2682 | ata_port_desc(host->ports[0], "irq %d", | |
2683 | ATA_PRIMARY_IRQ(pdev)); | |
2684 | } | |
2685 | ||
2686 | if (!ata_port_is_dummy(host->ports[1])) { | |
2687 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2688 | irq_handler, IRQF_SHARED, | |
2689 | drv_name, host); | |
2690 | if (rc) | |
2691 | goto out; | |
2692 | ||
2693 | ata_port_desc(host->ports[1], "irq %d", | |
2694 | ATA_SECONDARY_IRQ(pdev)); | |
2695 | } | |
2696 | } | |
2697 | ||
2698 | rc = ata_host_register(host, sht); | |
0fe40ff8 | 2699 | out: |
4e6b79fa TH |
2700 | if (rc == 0) |
2701 | devres_remove_group(dev, NULL); | |
2702 | else | |
2703 | devres_release_group(dev, NULL); | |
2704 | ||
2705 | return rc; | |
2706 | } | |
0fe40ff8 | 2707 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); |
4e6b79fa | 2708 | |
1fdffbce | 2709 | /** |
9363c382 | 2710 | * ata_pci_sff_init_one - Initialize/register PCI IDE host controller |
1fdffbce | 2711 | * @pdev: Controller to be initialized |
1626aeb8 | 2712 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 2713 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 2714 | * @host_priv: host private_data |
16ea0fc9 | 2715 | * @hflag: host flags |
1fdffbce JG |
2716 | * |
2717 | * This is a helper function which can be called from a driver's | |
2718 | * xxx_init_one() probe function if the hardware uses traditional | |
2719 | * IDE taskfile registers. | |
2720 | * | |
2721 | * This function calls pci_enable_device(), reserves its register | |
2722 | * regions, sets the dma mask, enables bus master mode, and calls | |
2723 | * ata_device_add() | |
2724 | * | |
2ec7df04 AC |
2725 | * ASSUMPTION: |
2726 | * Nobody makes a single channel controller that appears solely as | |
2727 | * the secondary legacy port on PCI. | |
2728 | * | |
1fdffbce JG |
2729 | * LOCKING: |
2730 | * Inherited from PCI layer (may sleep). | |
2731 | * | |
2732 | * RETURNS: | |
2733 | * Zero on success, negative on errno-based value on error. | |
2734 | */ | |
9363c382 | 2735 | int ata_pci_sff_init_one(struct pci_dev *pdev, |
16ea0fc9 AC |
2736 | const struct ata_port_info * const *ppi, |
2737 | struct scsi_host_template *sht, void *host_priv, int hflag) | |
1fdffbce | 2738 | { |
f0d36efd | 2739 | struct device *dev = &pdev->dev; |
1626aeb8 | 2740 | const struct ata_port_info *pi = NULL; |
0f834de3 | 2741 | struct ata_host *host = NULL; |
1626aeb8 | 2742 | int i, rc; |
1fdffbce JG |
2743 | |
2744 | DPRINTK("ENTER\n"); | |
2745 | ||
1626aeb8 TH |
2746 | /* look up the first valid port_info */ |
2747 | for (i = 0; i < 2 && ppi[i]; i++) { | |
2748 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
2749 | pi = ppi[i]; | |
2750 | break; | |
2751 | } | |
2752 | } | |
f0d36efd | 2753 | |
1626aeb8 TH |
2754 | if (!pi) { |
2755 | dev_printk(KERN_ERR, &pdev->dev, | |
2756 | "no valid port_info specified\n"); | |
2757 | return -EINVAL; | |
2758 | } | |
c791c306 | 2759 | |
1626aeb8 TH |
2760 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2761 | return -ENOMEM; | |
1fdffbce | 2762 | |
f0d36efd | 2763 | rc = pcim_enable_device(pdev); |
1fdffbce | 2764 | if (rc) |
4e6b79fa | 2765 | goto out; |
1fdffbce | 2766 | |
4e6b79fa | 2767 | /* prepare and activate SFF host */ |
9363c382 | 2768 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
d583bc18 | 2769 | if (rc) |
4e6b79fa | 2770 | goto out; |
887125e3 | 2771 | host->private_data = host_priv; |
16ea0fc9 | 2772 | host->flags |= hflag; |
d491b27b | 2773 | |
d491b27b | 2774 | pci_set_master(pdev); |
9363c382 | 2775 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
0fe40ff8 | 2776 | out: |
4e6b79fa TH |
2777 | if (rc == 0) |
2778 | devres_remove_group(&pdev->dev, NULL); | |
2779 | else | |
2780 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2781 | |
1fdffbce JG |
2782 | return rc; |
2783 | } | |
0fe40ff8 | 2784 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); |
1fdffbce JG |
2785 | |
2786 | #endif /* CONFIG_PCI */ | |
9f2f7210 TH |
2787 | |
2788 | const struct ata_port_operations ata_bmdma_port_ops = { | |
2789 | .inherits = &ata_sff_port_ops, | |
2790 | ||
9f2f7210 TH |
2791 | .bmdma_setup = ata_bmdma_setup, |
2792 | .bmdma_start = ata_bmdma_start, | |
2793 | .bmdma_stop = ata_bmdma_stop, | |
2794 | .bmdma_status = ata_bmdma_status, | |
c7087652 TH |
2795 | |
2796 | .port_start = ata_bmdma_port_start, | |
9f2f7210 TH |
2797 | }; |
2798 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); | |
2799 | ||
2800 | const struct ata_port_operations ata_bmdma32_port_ops = { | |
2801 | .inherits = &ata_bmdma_port_ops, | |
2802 | ||
2803 | .sff_data_xfer = ata_sff_data_xfer32, | |
c7087652 | 2804 | .port_start = ata_bmdma_port_start32, |
9f2f7210 TH |
2805 | }; |
2806 | EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops); | |
2807 | ||
9f2f7210 TH |
2808 | /** |
2809 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2810 | * @qc: Info associated with this ATA transaction. | |
2811 | * | |
2812 | * LOCKING: | |
2813 | * spin_lock_irqsave(host lock) | |
2814 | */ | |
2815 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2816 | { | |
2817 | struct ata_port *ap = qc->ap; | |
2818 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2819 | u8 dmactl; | |
2820 | ||
2821 | /* load PRD table addr. */ | |
2822 | mb(); /* make sure PRD table writes are visible to controller */ | |
2823 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | |
2824 | ||
2825 | /* specify data direction, triple-check start bit is clear */ | |
2826 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2827 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2828 | if (!rw) | |
2829 | dmactl |= ATA_DMA_WR; | |
2830 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2831 | ||
2832 | /* issue r/w command */ | |
2833 | ap->ops->sff_exec_command(ap, &qc->tf); | |
2834 | } | |
2835 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); | |
2836 | ||
2837 | /** | |
2838 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2839 | * @qc: Info associated with this ATA transaction. | |
2840 | * | |
2841 | * LOCKING: | |
2842 | * spin_lock_irqsave(host lock) | |
2843 | */ | |
2844 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2845 | { | |
2846 | struct ata_port *ap = qc->ap; | |
2847 | u8 dmactl; | |
2848 | ||
2849 | /* start host DMA transaction */ | |
2850 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2851 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2852 | ||
2853 | /* Strictly, one may wish to issue an ioread8() here, to | |
2854 | * flush the mmio write. However, control also passes | |
2855 | * to the hardware at this point, and it will interrupt | |
2856 | * us when we are to resume control. So, in effect, | |
2857 | * we don't care when the mmio write flushes. | |
2858 | * Further, a read of the DMA status register _immediately_ | |
2859 | * following the write may not be what certain flaky hardware | |
2860 | * is expected, so I think it is best to not add a readb() | |
2861 | * without first all the MMIO ATA cards/mobos. | |
2862 | * Or maybe I'm just being paranoid. | |
2863 | * | |
2864 | * FIXME: The posting of this write means I/O starts are | |
2865 | * unneccessarily delayed for MMIO | |
2866 | */ | |
2867 | } | |
2868 | EXPORT_SYMBOL_GPL(ata_bmdma_start); | |
2869 | ||
2870 | /** | |
2871 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
2872 | * @qc: Command we are ending DMA for | |
2873 | * | |
2874 | * Clears the ATA_DMA_START flag in the dma control register | |
2875 | * | |
2876 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
2877 | * | |
2878 | * LOCKING: | |
2879 | * spin_lock_irqsave(host lock) | |
2880 | */ | |
2881 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
2882 | { | |
2883 | struct ata_port *ap = qc->ap; | |
2884 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2885 | ||
2886 | /* clear start/stop bit */ | |
2887 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
2888 | mmio + ATA_DMA_CMD); | |
2889 | ||
2890 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
2891 | ata_sff_dma_pause(ap); | |
2892 | } | |
2893 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); | |
2894 | ||
2895 | /** | |
2896 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
2897 | * @ap: Port associated with this ATA transaction. | |
2898 | * | |
2899 | * Read and return BMDMA status register. | |
2900 | * | |
2901 | * May be used as the bmdma_status() entry in ata_port_operations. | |
2902 | * | |
2903 | * LOCKING: | |
2904 | * spin_lock_irqsave(host lock) | |
2905 | */ | |
2906 | u8 ata_bmdma_status(struct ata_port *ap) | |
2907 | { | |
2908 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
2909 | } | |
2910 | EXPORT_SYMBOL_GPL(ata_bmdma_status); | |
2911 | ||
c7087652 TH |
2912 | |
2913 | /** | |
2914 | * ata_bmdma_port_start - Set port up for bmdma. | |
2915 | * @ap: Port to initialize | |
2916 | * | |
2917 | * Called just after data structures for each port are | |
2918 | * initialized. Allocates space for PRD table. | |
2919 | * | |
2920 | * May be used as the port_start() entry in ata_port_operations. | |
2921 | * | |
2922 | * LOCKING: | |
2923 | * Inherited from caller. | |
2924 | */ | |
2925 | int ata_bmdma_port_start(struct ata_port *ap) | |
2926 | { | |
2927 | if (ap->mwdma_mask || ap->udma_mask) { | |
2928 | ap->prd = dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ, | |
2929 | &ap->prd_dma, GFP_KERNEL); | |
2930 | if (!ap->prd) | |
2931 | return -ENOMEM; | |
2932 | } | |
2933 | ||
2934 | return 0; | |
2935 | } | |
2936 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start); | |
2937 | ||
2938 | /** | |
2939 | * ata_bmdma_port_start32 - Set port up for dma. | |
2940 | * @ap: Port to initialize | |
2941 | * | |
2942 | * Called just after data structures for each port are | |
2943 | * initialized. Enables 32bit PIO and allocates space for PRD | |
2944 | * table. | |
2945 | * | |
2946 | * May be used as the port_start() entry in ata_port_operations for | |
2947 | * devices that are capable of 32bit PIO. | |
2948 | * | |
2949 | * LOCKING: | |
2950 | * Inherited from caller. | |
2951 | */ | |
2952 | int ata_bmdma_port_start32(struct ata_port *ap) | |
2953 | { | |
2954 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; | |
2955 | return ata_bmdma_port_start(ap); | |
2956 | } | |
2957 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start32); | |
2958 | ||
9f2f7210 TH |
2959 | #ifdef CONFIG_PCI |
2960 | ||
2961 | /** | |
2962 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex | |
2963 | * @pdev: PCI device | |
2964 | * | |
2965 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2966 | * enter non simplex mode. This implements the necessary logic to | |
2967 | * perform the task on such devices. Calling it on other devices will | |
2968 | * have -undefined- behaviour. | |
2969 | */ | |
2970 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) | |
2971 | { | |
2972 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
2973 | u8 simplex; | |
2974 | ||
2975 | if (bmdma == 0) | |
2976 | return -ENOENT; | |
2977 | ||
2978 | simplex = inb(bmdma + 0x02); | |
2979 | outb(simplex & 0x60, bmdma + 0x02); | |
2980 | simplex = inb(bmdma + 0x02); | |
2981 | if (simplex & 0x80) | |
2982 | return -EOPNOTSUPP; | |
2983 | return 0; | |
2984 | } | |
2985 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); | |
2986 | ||
c7087652 TH |
2987 | static void ata_bmdma_nodma(struct ata_host *host, const char *reason) |
2988 | { | |
2989 | int i; | |
2990 | ||
2991 | dev_printk(KERN_ERR, host->dev, "BMDMA: %s, falling back to PIO\n", | |
2992 | reason); | |
2993 | ||
2994 | for (i = 0; i < 2; i++) { | |
2995 | host->ports[i]->mwdma_mask = 0; | |
2996 | host->ports[i]->udma_mask = 0; | |
2997 | } | |
2998 | } | |
2999 | ||
9f2f7210 TH |
3000 | /** |
3001 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host | |
3002 | * @host: target ATA host | |
3003 | * | |
3004 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
3005 | * | |
3006 | * LOCKING: | |
3007 | * Inherited from calling layer (may sleep). | |
9f2f7210 | 3008 | */ |
c7087652 | 3009 | void ata_pci_bmdma_init(struct ata_host *host) |
9f2f7210 TH |
3010 | { |
3011 | struct device *gdev = host->dev; | |
3012 | struct pci_dev *pdev = to_pci_dev(gdev); | |
3013 | int i, rc; | |
3014 | ||
3015 | /* No BAR4 allocation: No DMA */ | |
c7087652 TH |
3016 | if (pci_resource_start(pdev, 4) == 0) { |
3017 | ata_bmdma_nodma(host, "BAR4 is zero"); | |
3018 | return; | |
3019 | } | |
9f2f7210 | 3020 | |
c7087652 TH |
3021 | /* |
3022 | * Some controllers require BMDMA region to be initialized | |
3023 | * even if DMA is not in use to clear IRQ status via | |
3024 | * ->sff_irq_clear method. Try to initialize bmdma_addr | |
3025 | * regardless of dma masks. | |
3026 | */ | |
9f2f7210 TH |
3027 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
3028 | if (rc) | |
c7087652 TH |
3029 | ata_bmdma_nodma(host, "failed to set dma mask"); |
3030 | if (!rc) { | |
3031 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
3032 | if (rc) | |
3033 | ata_bmdma_nodma(host, | |
3034 | "failed to set consistent dma mask"); | |
3035 | } | |
9f2f7210 TH |
3036 | |
3037 | /* request and iomap DMA region */ | |
3038 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); | |
3039 | if (rc) { | |
c7087652 TH |
3040 | ata_bmdma_nodma(host, "failed to request/iomap BAR4"); |
3041 | return; | |
9f2f7210 TH |
3042 | } |
3043 | host->iomap = pcim_iomap_table(pdev); | |
3044 | ||
3045 | for (i = 0; i < 2; i++) { | |
3046 | struct ata_port *ap = host->ports[i]; | |
3047 | void __iomem *bmdma = host->iomap[4] + 8 * i; | |
3048 | ||
3049 | if (ata_port_is_dummy(ap)) | |
3050 | continue; | |
3051 | ||
3052 | ap->ioaddr.bmdma_addr = bmdma; | |
3053 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && | |
3054 | (ioread8(bmdma + 2) & 0x80)) | |
3055 | host->flags |= ATA_HOST_SIMPLEX; | |
3056 | ||
3057 | ata_port_desc(ap, "bmdma 0x%llx", | |
3058 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
3059 | } | |
9f2f7210 TH |
3060 | } |
3061 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); | |
3062 | ||
3063 | #endif /* CONFIG_PCI */ | |
270390e1 TH |
3064 | |
3065 | /** | |
3066 | * ata_sff_port_init - Initialize SFF/BMDMA ATA port | |
3067 | * @ap: Port to initialize | |
3068 | * | |
3069 | * Called on port allocation to initialize SFF/BMDMA specific | |
3070 | * fields. | |
3071 | * | |
3072 | * LOCKING: | |
3073 | * None. | |
3074 | */ | |
3075 | void ata_sff_port_init(struct ata_port *ap) | |
3076 | { | |
3077 | } | |
3078 | ||
3079 | int __init ata_sff_init(void) | |
3080 | { | |
3081 | return 0; | |
3082 | } | |
3083 | ||
3084 | void __exit ata_sff_exit(void) | |
3085 | { | |
3086 | } |