]>
Commit | Line | Data |
---|---|---|
1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce | 35 | #include <linux/kernel.h> |
5a0e3ad6 | 36 | #include <linux/gfp.h> |
1fdffbce JG |
37 | #include <linux/pci.h> |
38 | #include <linux/libata.h> | |
624d5c51 | 39 | #include <linux/highmem.h> |
1fdffbce JG |
40 | |
41 | #include "libata.h" | |
42 | ||
624d5c51 TH |
43 | const struct ata_port_operations ata_sff_port_ops = { |
44 | .inherits = &ata_base_port_ops, | |
45 | ||
9363c382 TH |
46 | .qc_prep = ata_sff_qc_prep, |
47 | .qc_issue = ata_sff_qc_issue, | |
4c9bf4e7 | 48 | .qc_fill_rtf = ata_sff_qc_fill_rtf, |
9363c382 TH |
49 | |
50 | .freeze = ata_sff_freeze, | |
51 | .thaw = ata_sff_thaw, | |
0aa1113d | 52 | .prereset = ata_sff_prereset, |
9363c382 | 53 | .softreset = ata_sff_softreset, |
57c9efdf | 54 | .hardreset = sata_sff_hardreset, |
203c75b8 | 55 | .postreset = ata_sff_postreset, |
3d47aa8e | 56 | .drain_fifo = ata_sff_drain_fifo, |
9363c382 TH |
57 | .error_handler = ata_sff_error_handler, |
58 | .post_internal_cmd = ata_sff_post_internal_cmd, | |
59 | ||
5682ed33 TH |
60 | .sff_dev_select = ata_sff_dev_select, |
61 | .sff_check_status = ata_sff_check_status, | |
62 | .sff_tf_load = ata_sff_tf_load, | |
63 | .sff_tf_read = ata_sff_tf_read, | |
64 | .sff_exec_command = ata_sff_exec_command, | |
65 | .sff_data_xfer = ata_sff_data_xfer, | |
288623a0 | 66 | .sff_irq_clear = ata_sff_irq_clear, |
624d5c51 | 67 | |
c96f1732 AC |
68 | .lost_interrupt = ata_sff_lost_interrupt, |
69 | ||
624d5c51 TH |
70 | .port_start = ata_sff_port_start, |
71 | }; | |
0fe40ff8 | 72 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
624d5c51 | 73 | |
624d5c51 TH |
74 | /** |
75 | * ata_fill_sg - Fill PCI IDE PRD table | |
76 | * @qc: Metadata associated with taskfile to be transferred | |
77 | * | |
78 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
79 | * associated with the current disk command. | |
80 | * | |
81 | * LOCKING: | |
82 | * spin_lock_irqsave(host lock) | |
83 | * | |
84 | */ | |
85 | static void ata_fill_sg(struct ata_queued_cmd *qc) | |
86 | { | |
87 | struct ata_port *ap = qc->ap; | |
88 | struct scatterlist *sg; | |
89 | unsigned int si, pi; | |
90 | ||
91 | pi = 0; | |
92 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
93 | u32 addr, offset; | |
94 | u32 sg_len, len; | |
95 | ||
96 | /* determine if physical DMA addr spans 64K boundary. | |
97 | * Note h/w doesn't support 64-bit, so we unconditionally | |
98 | * truncate dma_addr_t to u32. | |
99 | */ | |
100 | addr = (u32) sg_dma_address(sg); | |
101 | sg_len = sg_dma_len(sg); | |
102 | ||
103 | while (sg_len) { | |
104 | offset = addr & 0xffff; | |
105 | len = sg_len; | |
106 | if ((offset + sg_len) > 0x10000) | |
107 | len = 0x10000 - offset; | |
108 | ||
109 | ap->prd[pi].addr = cpu_to_le32(addr); | |
110 | ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
111 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
112 | ||
113 | pi++; | |
114 | sg_len -= len; | |
115 | addr += len; | |
116 | } | |
117 | } | |
118 | ||
119 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
120 | } | |
121 | ||
122 | /** | |
123 | * ata_fill_sg_dumb - Fill PCI IDE PRD table | |
124 | * @qc: Metadata associated with taskfile to be transferred | |
125 | * | |
126 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
127 | * associated with the current disk command. Perform the fill | |
128 | * so that we avoid writing any length 64K records for | |
129 | * controllers that don't follow the spec. | |
130 | * | |
131 | * LOCKING: | |
132 | * spin_lock_irqsave(host lock) | |
133 | * | |
134 | */ | |
135 | static void ata_fill_sg_dumb(struct ata_queued_cmd *qc) | |
136 | { | |
137 | struct ata_port *ap = qc->ap; | |
138 | struct scatterlist *sg; | |
139 | unsigned int si, pi; | |
140 | ||
141 | pi = 0; | |
142 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
143 | u32 addr, offset; | |
144 | u32 sg_len, len, blen; | |
145 | ||
146 | /* determine if physical DMA addr spans 64K boundary. | |
147 | * Note h/w doesn't support 64-bit, so we unconditionally | |
148 | * truncate dma_addr_t to u32. | |
149 | */ | |
150 | addr = (u32) sg_dma_address(sg); | |
151 | sg_len = sg_dma_len(sg); | |
152 | ||
153 | while (sg_len) { | |
154 | offset = addr & 0xffff; | |
155 | len = sg_len; | |
156 | if ((offset + sg_len) > 0x10000) | |
157 | len = 0x10000 - offset; | |
158 | ||
159 | blen = len & 0xffff; | |
160 | ap->prd[pi].addr = cpu_to_le32(addr); | |
161 | if (blen == 0) { | |
0fe40ff8 AC |
162 | /* Some PATA chipsets like the CS5530 can't |
163 | cope with 0x0000 meaning 64K as the spec | |
164 | says */ | |
624d5c51 TH |
165 | ap->prd[pi].flags_len = cpu_to_le32(0x8000); |
166 | blen = 0x8000; | |
167 | ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000); | |
168 | } | |
169 | ap->prd[pi].flags_len = cpu_to_le32(blen); | |
170 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
171 | ||
172 | pi++; | |
173 | sg_len -= len; | |
174 | addr += len; | |
175 | } | |
176 | } | |
177 | ||
178 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
179 | } | |
180 | ||
181 | /** | |
9363c382 | 182 | * ata_sff_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
183 | * @qc: Metadata associated with taskfile to be prepared |
184 | * | |
185 | * Prepare ATA taskfile for submission. | |
186 | * | |
187 | * LOCKING: | |
188 | * spin_lock_irqsave(host lock) | |
189 | */ | |
9363c382 | 190 | void ata_sff_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
191 | { |
192 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
193 | return; | |
194 | ||
195 | ata_fill_sg(qc); | |
196 | } | |
0fe40ff8 | 197 | EXPORT_SYMBOL_GPL(ata_sff_qc_prep); |
624d5c51 TH |
198 | |
199 | /** | |
9363c382 | 200 | * ata_sff_dumb_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
201 | * @qc: Metadata associated with taskfile to be prepared |
202 | * | |
203 | * Prepare ATA taskfile for submission. | |
204 | * | |
205 | * LOCKING: | |
206 | * spin_lock_irqsave(host lock) | |
207 | */ | |
9363c382 | 208 | void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
209 | { |
210 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
211 | return; | |
212 | ||
213 | ata_fill_sg_dumb(qc); | |
214 | } | |
0fe40ff8 | 215 | EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep); |
624d5c51 | 216 | |
272f7884 | 217 | /** |
9363c382 | 218 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
219 | * @ap: port where the device is |
220 | * | |
221 | * Reads ATA taskfile status register for currently-selected device | |
222 | * and return its value. This also clears pending interrupts | |
223 | * from this device | |
224 | * | |
225 | * LOCKING: | |
226 | * Inherited from caller. | |
227 | */ | |
9363c382 | 228 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
229 | { |
230 | return ioread8(ap->ioaddr.status_addr); | |
231 | } | |
0fe40ff8 | 232 | EXPORT_SYMBOL_GPL(ata_sff_check_status); |
272f7884 TH |
233 | |
234 | /** | |
9363c382 | 235 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
236 | * @ap: port where the device is |
237 | * | |
238 | * Reads ATA taskfile alternate status register for | |
239 | * currently-selected device and return its value. | |
240 | * | |
241 | * Note: may NOT be used as the check_altstatus() entry in | |
242 | * ata_port_operations. | |
243 | * | |
244 | * LOCKING: | |
245 | * Inherited from caller. | |
246 | */ | |
a57c1bad | 247 | static u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 248 | { |
5682ed33 TH |
249 | if (ap->ops->sff_check_altstatus) |
250 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
251 | |
252 | return ioread8(ap->ioaddr.altstatus_addr); | |
253 | } | |
254 | ||
a57c1bad AC |
255 | /** |
256 | * ata_sff_irq_status - Check if the device is busy | |
257 | * @ap: port where the device is | |
258 | * | |
259 | * Determine if the port is currently busy. Uses altstatus | |
260 | * if available in order to avoid clearing shared IRQ status | |
261 | * when finding an IRQ source. Non ctl capable devices don't | |
262 | * share interrupt lines fortunately for us. | |
263 | * | |
264 | * LOCKING: | |
265 | * Inherited from caller. | |
266 | */ | |
267 | static u8 ata_sff_irq_status(struct ata_port *ap) | |
268 | { | |
269 | u8 status; | |
270 | ||
271 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
272 | status = ata_sff_altstatus(ap); | |
273 | /* Not us: We are busy */ | |
274 | if (status & ATA_BUSY) | |
0fe40ff8 | 275 | return status; |
a57c1bad AC |
276 | } |
277 | /* Clear INTRQ latch */ | |
6311c90a | 278 | status = ap->ops->sff_check_status(ap); |
a57c1bad AC |
279 | return status; |
280 | } | |
281 | ||
282 | /** | |
283 | * ata_sff_sync - Flush writes | |
284 | * @ap: Port to wait for. | |
285 | * | |
286 | * CAUTION: | |
287 | * If we have an mmio device with no ctl and no altstatus | |
288 | * method this will fail. No such devices are known to exist. | |
289 | * | |
290 | * LOCKING: | |
291 | * Inherited from caller. | |
292 | */ | |
293 | ||
294 | static void ata_sff_sync(struct ata_port *ap) | |
295 | { | |
296 | if (ap->ops->sff_check_altstatus) | |
297 | ap->ops->sff_check_altstatus(ap); | |
298 | else if (ap->ioaddr.altstatus_addr) | |
299 | ioread8(ap->ioaddr.altstatus_addr); | |
300 | } | |
301 | ||
302 | /** | |
303 | * ata_sff_pause - Flush writes and wait 400nS | |
304 | * @ap: Port to pause for. | |
305 | * | |
306 | * CAUTION: | |
307 | * If we have an mmio device with no ctl and no altstatus | |
308 | * method this will fail. No such devices are known to exist. | |
309 | * | |
310 | * LOCKING: | |
311 | * Inherited from caller. | |
312 | */ | |
313 | ||
314 | void ata_sff_pause(struct ata_port *ap) | |
315 | { | |
316 | ata_sff_sync(ap); | |
317 | ndelay(400); | |
318 | } | |
0fe40ff8 | 319 | EXPORT_SYMBOL_GPL(ata_sff_pause); |
a57c1bad AC |
320 | |
321 | /** | |
322 | * ata_sff_dma_pause - Pause before commencing DMA | |
323 | * @ap: Port to pause for. | |
324 | * | |
325 | * Perform I/O fencing and ensure sufficient cycle delays occur | |
326 | * for the HDMA1:0 transition | |
327 | */ | |
0fe40ff8 | 328 | |
a57c1bad AC |
329 | void ata_sff_dma_pause(struct ata_port *ap) |
330 | { | |
331 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
332 | /* An altstatus read will cause the needed delay without | |
333 | messing up the IRQ status */ | |
334 | ata_sff_altstatus(ap); | |
335 | return; | |
336 | } | |
337 | /* There are no DMA controllers without ctl. BUG here to ensure | |
338 | we never violate the HDMA1:0 transition timing and risk | |
339 | corruption. */ | |
340 | BUG(); | |
341 | } | |
0fe40ff8 | 342 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause); |
a57c1bad | 343 | |
624d5c51 | 344 | /** |
9363c382 | 345 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 | 346 | * @ap: port containing status register to be polled |
341c2c95 TH |
347 | * @tmout_pat: impatience timeout in msecs |
348 | * @tmout: overall timeout in msecs | |
624d5c51 TH |
349 | * |
350 | * Sleep until ATA Status register bit BSY clears, | |
351 | * or a timeout occurs. | |
352 | * | |
353 | * LOCKING: | |
354 | * Kernel thread context (may sleep). | |
355 | * | |
356 | * RETURNS: | |
357 | * 0 on success, -errno otherwise. | |
358 | */ | |
9363c382 TH |
359 | int ata_sff_busy_sleep(struct ata_port *ap, |
360 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
361 | { |
362 | unsigned long timer_start, timeout; | |
363 | u8 status; | |
364 | ||
9363c382 | 365 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 | 366 | timer_start = jiffies; |
341c2c95 | 367 | timeout = ata_deadline(timer_start, tmout_pat); |
624d5c51 TH |
368 | while (status != 0xff && (status & ATA_BUSY) && |
369 | time_before(jiffies, timeout)) { | |
370 | msleep(50); | |
9363c382 | 371 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
372 | } |
373 | ||
374 | if (status != 0xff && (status & ATA_BUSY)) | |
375 | ata_port_printk(ap, KERN_WARNING, | |
376 | "port is slow to respond, please be patient " | |
377 | "(Status 0x%x)\n", status); | |
378 | ||
341c2c95 | 379 | timeout = ata_deadline(timer_start, tmout); |
624d5c51 TH |
380 | while (status != 0xff && (status & ATA_BUSY) && |
381 | time_before(jiffies, timeout)) { | |
382 | msleep(50); | |
5682ed33 | 383 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
384 | } |
385 | ||
386 | if (status == 0xff) | |
387 | return -ENODEV; | |
388 | ||
389 | if (status & ATA_BUSY) { | |
390 | ata_port_printk(ap, KERN_ERR, "port failed to respond " | |
391 | "(%lu secs, Status 0x%x)\n", | |
341c2c95 | 392 | DIV_ROUND_UP(tmout, 1000), status); |
624d5c51 TH |
393 | return -EBUSY; |
394 | } | |
395 | ||
396 | return 0; | |
397 | } | |
0fe40ff8 | 398 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); |
624d5c51 | 399 | |
aa2731ad TH |
400 | static int ata_sff_check_ready(struct ata_link *link) |
401 | { | |
402 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
403 | ||
78ab88f0 | 404 | return ata_check_ready(status); |
aa2731ad TH |
405 | } |
406 | ||
624d5c51 | 407 | /** |
9363c382 | 408 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 409 | * @link: SFF link to wait ready status for |
624d5c51 TH |
410 | * @deadline: deadline jiffies for the operation |
411 | * | |
412 | * Sleep until ATA Status register bit BSY clears, or timeout | |
413 | * occurs. | |
414 | * | |
415 | * LOCKING: | |
416 | * Kernel thread context (may sleep). | |
417 | * | |
418 | * RETURNS: | |
419 | * 0 on success, -errno otherwise. | |
420 | */ | |
705e76be | 421 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 422 | { |
aa2731ad | 423 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 | 424 | } |
0fe40ff8 | 425 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); |
624d5c51 | 426 | |
41dec29b SS |
427 | /** |
428 | * ata_sff_set_devctl - Write device control reg | |
429 | * @ap: port where the device is | |
430 | * @ctl: value to write | |
431 | * | |
432 | * Writes ATA taskfile device control register. | |
433 | * | |
434 | * Note: may NOT be used as the sff_set_devctl() entry in | |
435 | * ata_port_operations. | |
436 | * | |
437 | * LOCKING: | |
438 | * Inherited from caller. | |
439 | */ | |
440 | static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl) | |
441 | { | |
442 | if (ap->ops->sff_set_devctl) | |
443 | ap->ops->sff_set_devctl(ap, ctl); | |
444 | else | |
445 | iowrite8(ctl, ap->ioaddr.ctl_addr); | |
446 | } | |
447 | ||
624d5c51 | 448 | /** |
9363c382 | 449 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
450 | * @ap: ATA channel to manipulate |
451 | * @device: ATA device (numbered from zero) to select | |
452 | * | |
453 | * Use the method defined in the ATA specification to | |
454 | * make either device 0, or device 1, active on the | |
455 | * ATA channel. Works with both PIO and MMIO. | |
456 | * | |
457 | * May be used as the dev_select() entry in ata_port_operations. | |
458 | * | |
459 | * LOCKING: | |
460 | * caller. | |
461 | */ | |
9363c382 | 462 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
463 | { |
464 | u8 tmp; | |
465 | ||
466 | if (device == 0) | |
467 | tmp = ATA_DEVICE_OBS; | |
468 | else | |
469 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
470 | ||
471 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 472 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 | 473 | } |
0fe40ff8 | 474 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); |
624d5c51 TH |
475 | |
476 | /** | |
477 | * ata_dev_select - Select device 0/1 on ATA bus | |
478 | * @ap: ATA channel to manipulate | |
479 | * @device: ATA device (numbered from zero) to select | |
480 | * @wait: non-zero to wait for Status register BSY bit to clear | |
481 | * @can_sleep: non-zero if context allows sleeping | |
482 | * | |
483 | * Use the method defined in the ATA specification to | |
484 | * make either device 0, or device 1, active on the | |
485 | * ATA channel. | |
486 | * | |
9363c382 TH |
487 | * This is a high-level version of ata_sff_dev_select(), which |
488 | * additionally provides the services of inserting the proper | |
489 | * pauses and status polling, where needed. | |
624d5c51 TH |
490 | * |
491 | * LOCKING: | |
492 | * caller. | |
493 | */ | |
c7a8209f | 494 | static void ata_dev_select(struct ata_port *ap, unsigned int device, |
624d5c51 TH |
495 | unsigned int wait, unsigned int can_sleep) |
496 | { | |
497 | if (ata_msg_probe(ap)) | |
498 | ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, " | |
499 | "device %u, wait %u\n", device, wait); | |
500 | ||
501 | if (wait) | |
502 | ata_wait_idle(ap); | |
503 | ||
5682ed33 | 504 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
505 | |
506 | if (wait) { | |
507 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
508 | msleep(150); | |
509 | ata_wait_idle(ap); | |
510 | } | |
511 | } | |
512 | ||
513 | /** | |
9363c382 | 514 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
515 | * @ap: Port on which interrupts are enabled. |
516 | * | |
517 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
518 | * wait for idle, clear any pending interrupts. | |
519 | * | |
e42a542b SS |
520 | * Note: may NOT be used as the sff_irq_on() entry in |
521 | * ata_port_operations. | |
522 | * | |
624d5c51 TH |
523 | * LOCKING: |
524 | * Inherited from caller. | |
525 | */ | |
e42a542b | 526 | void ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
527 | { |
528 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
e42a542b SS |
529 | |
530 | if (ap->ops->sff_irq_on) { | |
531 | ap->ops->sff_irq_on(ap); | |
532 | return; | |
533 | } | |
624d5c51 TH |
534 | |
535 | ap->ctl &= ~ATA_NIEN; | |
536 | ap->last_ctl = ap->ctl; | |
537 | ||
e42a542b SS |
538 | if (ap->ops->sff_set_devctl || ioaddr->ctl_addr) |
539 | ata_sff_set_devctl(ap, ap->ctl); | |
540 | ata_wait_idle(ap); | |
624d5c51 | 541 | |
5682ed33 | 542 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 543 | } |
0fe40ff8 | 544 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); |
624d5c51 TH |
545 | |
546 | /** | |
9363c382 | 547 | * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt. |
624d5c51 TH |
548 | * @ap: Port associated with this ATA transaction. |
549 | * | |
550 | * Clear interrupt and error flags in DMA status register. | |
551 | * | |
552 | * May be used as the irq_clear() entry in ata_port_operations. | |
553 | * | |
554 | * LOCKING: | |
555 | * spin_lock_irqsave(host lock) | |
556 | */ | |
9363c382 | 557 | void ata_sff_irq_clear(struct ata_port *ap) |
624d5c51 TH |
558 | { |
559 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
560 | ||
561 | if (!mmio) | |
562 | return; | |
563 | ||
564 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
565 | } | |
0fe40ff8 | 566 | EXPORT_SYMBOL_GPL(ata_sff_irq_clear); |
624d5c51 TH |
567 | |
568 | /** | |
9363c382 | 569 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
570 | * @ap: Port to which output is sent |
571 | * @tf: ATA taskfile register set | |
572 | * | |
573 | * Outputs ATA taskfile to standard ATA host controller. | |
574 | * | |
575 | * LOCKING: | |
576 | * Inherited from caller. | |
577 | */ | |
9363c382 | 578 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
579 | { |
580 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
581 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
582 | ||
583 | if (tf->ctl != ap->last_ctl) { | |
584 | if (ioaddr->ctl_addr) | |
585 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
586 | ap->last_ctl = tf->ctl; | |
624d5c51 TH |
587 | } |
588 | ||
589 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
efcb3cf7 | 590 | WARN_ON_ONCE(!ioaddr->ctl_addr); |
624d5c51 TH |
591 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
592 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
593 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
594 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
595 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
596 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
597 | tf->hob_feature, | |
598 | tf->hob_nsect, | |
599 | tf->hob_lbal, | |
600 | tf->hob_lbam, | |
601 | tf->hob_lbah); | |
602 | } | |
603 | ||
604 | if (is_addr) { | |
605 | iowrite8(tf->feature, ioaddr->feature_addr); | |
606 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
607 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
608 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
609 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
610 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
611 | tf->feature, | |
612 | tf->nsect, | |
613 | tf->lbal, | |
614 | tf->lbam, | |
615 | tf->lbah); | |
616 | } | |
617 | ||
618 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
619 | iowrite8(tf->device, ioaddr->device_addr); | |
620 | VPRINTK("device 0x%X\n", tf->device); | |
621 | } | |
624d5c51 | 622 | } |
0fe40ff8 | 623 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); |
624d5c51 TH |
624 | |
625 | /** | |
9363c382 | 626 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
627 | * @ap: Port from which input is read |
628 | * @tf: ATA taskfile register set for storing input | |
629 | * | |
630 | * Reads ATA taskfile registers for currently-selected device | |
631 | * into @tf. Assumes the device has a fully SFF compliant task file | |
632 | * layout and behaviour. If you device does not (eg has a different | |
633 | * status method) then you will need to provide a replacement tf_read | |
634 | * | |
635 | * LOCKING: | |
636 | * Inherited from caller. | |
637 | */ | |
9363c382 | 638 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
639 | { |
640 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
641 | ||
9363c382 | 642 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
643 | tf->feature = ioread8(ioaddr->error_addr); |
644 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
645 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
646 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
647 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
648 | tf->device = ioread8(ioaddr->device_addr); | |
649 | ||
650 | if (tf->flags & ATA_TFLAG_LBA48) { | |
651 | if (likely(ioaddr->ctl_addr)) { | |
652 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
653 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
654 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
655 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
656 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
657 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
658 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
659 | ap->last_ctl = tf->ctl; | |
660 | } else | |
efcb3cf7 | 661 | WARN_ON_ONCE(1); |
624d5c51 TH |
662 | } |
663 | } | |
0fe40ff8 | 664 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); |
624d5c51 TH |
665 | |
666 | /** | |
9363c382 | 667 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
668 | * @ap: port to which command is being issued |
669 | * @tf: ATA taskfile register set | |
670 | * | |
671 | * Issues ATA command, with proper synchronization with interrupt | |
672 | * handler / other threads. | |
673 | * | |
674 | * LOCKING: | |
675 | * spin_lock_irqsave(host lock) | |
676 | */ | |
9363c382 | 677 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
678 | { |
679 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
680 | ||
681 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 682 | ata_sff_pause(ap); |
624d5c51 | 683 | } |
0fe40ff8 | 684 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); |
624d5c51 TH |
685 | |
686 | /** | |
687 | * ata_tf_to_host - issue ATA taskfile to host controller | |
688 | * @ap: port to which command is being issued | |
689 | * @tf: ATA taskfile register set | |
690 | * | |
691 | * Issues ATA taskfile register set to ATA host controller, | |
692 | * with proper synchronization with interrupt handler and | |
693 | * other threads. | |
694 | * | |
695 | * LOCKING: | |
696 | * spin_lock_irqsave(host lock) | |
697 | */ | |
698 | static inline void ata_tf_to_host(struct ata_port *ap, | |
699 | const struct ata_taskfile *tf) | |
700 | { | |
5682ed33 TH |
701 | ap->ops->sff_tf_load(ap, tf); |
702 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
703 | } |
704 | ||
705 | /** | |
9363c382 | 706 | * ata_sff_data_xfer - Transfer data by PIO |
624d5c51 TH |
707 | * @dev: device to target |
708 | * @buf: data buffer | |
709 | * @buflen: buffer length | |
710 | * @rw: read/write | |
711 | * | |
712 | * Transfer data from/to the device data register by PIO. | |
713 | * | |
714 | * LOCKING: | |
715 | * Inherited from caller. | |
716 | * | |
717 | * RETURNS: | |
718 | * Bytes consumed. | |
719 | */ | |
9363c382 TH |
720 | unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, |
721 | unsigned int buflen, int rw) | |
624d5c51 TH |
722 | { |
723 | struct ata_port *ap = dev->link->ap; | |
724 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
725 | unsigned int words = buflen >> 1; | |
726 | ||
727 | /* Transfer multiple of 2 bytes */ | |
728 | if (rw == READ) | |
729 | ioread16_rep(data_addr, buf, words); | |
730 | else | |
731 | iowrite16_rep(data_addr, buf, words); | |
732 | ||
2102d749 | 733 | /* Transfer trailing byte, if any. */ |
624d5c51 | 734 | if (unlikely(buflen & 0x01)) { |
2102d749 | 735 | unsigned char pad[2]; |
624d5c51 | 736 | |
2102d749 SS |
737 | /* Point buf to the tail of buffer */ |
738 | buf += buflen - 1; | |
739 | ||
740 | /* | |
741 | * Use io*16_rep() accessors here as well to avoid pointlessly | |
972b94ff | 742 | * swapping bytes to and from on the big endian machines... |
2102d749 | 743 | */ |
624d5c51 | 744 | if (rw == READ) { |
2102d749 SS |
745 | ioread16_rep(data_addr, pad, 1); |
746 | *buf = pad[0]; | |
624d5c51 | 747 | } else { |
2102d749 SS |
748 | pad[0] = *buf; |
749 | iowrite16_rep(data_addr, pad, 1); | |
624d5c51 TH |
750 | } |
751 | words++; | |
752 | } | |
753 | ||
754 | return words << 1; | |
755 | } | |
0fe40ff8 | 756 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); |
624d5c51 | 757 | |
871af121 AC |
758 | /** |
759 | * ata_sff_data_xfer32 - Transfer data by PIO | |
760 | * @dev: device to target | |
761 | * @buf: data buffer | |
762 | * @buflen: buffer length | |
763 | * @rw: read/write | |
764 | * | |
765 | * Transfer data from/to the device data register by PIO using 32bit | |
766 | * I/O operations. | |
767 | * | |
768 | * LOCKING: | |
769 | * Inherited from caller. | |
770 | * | |
771 | * RETURNS: | |
772 | * Bytes consumed. | |
773 | */ | |
774 | ||
775 | unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf, | |
776 | unsigned int buflen, int rw) | |
777 | { | |
778 | struct ata_port *ap = dev->link->ap; | |
779 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
780 | unsigned int words = buflen >> 2; | |
781 | int slop = buflen & 3; | |
972b94ff | 782 | |
e3cf95dd AC |
783 | if (!(ap->pflags & ATA_PFLAG_PIO32)) |
784 | return ata_sff_data_xfer(dev, buf, buflen, rw); | |
871af121 AC |
785 | |
786 | /* Transfer multiple of 4 bytes */ | |
787 | if (rw == READ) | |
788 | ioread32_rep(data_addr, buf, words); | |
789 | else | |
790 | iowrite32_rep(data_addr, buf, words); | |
791 | ||
d1b3525b | 792 | /* Transfer trailing bytes, if any */ |
871af121 | 793 | if (unlikely(slop)) { |
d1b3525b SS |
794 | unsigned char pad[4]; |
795 | ||
796 | /* Point buf to the tail of buffer */ | |
797 | buf += buflen - slop; | |
798 | ||
799 | /* | |
800 | * Use io*_rep() accessors here as well to avoid pointlessly | |
972b94ff | 801 | * swapping bytes to and from on the big endian machines... |
d1b3525b | 802 | */ |
871af121 | 803 | if (rw == READ) { |
d1b3525b SS |
804 | if (slop < 3) |
805 | ioread16_rep(data_addr, pad, 1); | |
806 | else | |
807 | ioread32_rep(data_addr, pad, 1); | |
808 | memcpy(buf, pad, slop); | |
871af121 | 809 | } else { |
d1b3525b SS |
810 | memcpy(pad, buf, slop); |
811 | if (slop < 3) | |
812 | iowrite16_rep(data_addr, pad, 1); | |
813 | else | |
814 | iowrite32_rep(data_addr, pad, 1); | |
871af121 | 815 | } |
871af121 | 816 | } |
d1b3525b | 817 | return (buflen + 1) & ~1; |
871af121 AC |
818 | } |
819 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); | |
820 | ||
624d5c51 | 821 | /** |
9363c382 | 822 | * ata_sff_data_xfer_noirq - Transfer data by PIO |
624d5c51 TH |
823 | * @dev: device to target |
824 | * @buf: data buffer | |
825 | * @buflen: buffer length | |
826 | * @rw: read/write | |
827 | * | |
828 | * Transfer data from/to the device data register by PIO. Do the | |
829 | * transfer with interrupts disabled. | |
830 | * | |
831 | * LOCKING: | |
832 | * Inherited from caller. | |
833 | * | |
834 | * RETURNS: | |
835 | * Bytes consumed. | |
836 | */ | |
9363c382 TH |
837 | unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, |
838 | unsigned int buflen, int rw) | |
624d5c51 TH |
839 | { |
840 | unsigned long flags; | |
841 | unsigned int consumed; | |
842 | ||
843 | local_irq_save(flags); | |
9363c382 | 844 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); |
624d5c51 TH |
845 | local_irq_restore(flags); |
846 | ||
847 | return consumed; | |
848 | } | |
0fe40ff8 | 849 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); |
624d5c51 TH |
850 | |
851 | /** | |
852 | * ata_pio_sector - Transfer a sector of data. | |
853 | * @qc: Command on going | |
854 | * | |
855 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
856 | * | |
857 | * LOCKING: | |
858 | * Inherited from caller. | |
859 | */ | |
860 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
861 | { | |
862 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
863 | struct ata_port *ap = qc->ap; | |
864 | struct page *page; | |
865 | unsigned int offset; | |
866 | unsigned char *buf; | |
867 | ||
868 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
869 | ap->hsm_task_state = HSM_ST_LAST; | |
870 | ||
871 | page = sg_page(qc->cursg); | |
872 | offset = qc->cursg->offset + qc->cursg_ofs; | |
873 | ||
874 | /* get the current page and offset */ | |
875 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
876 | offset %= PAGE_SIZE; | |
877 | ||
878 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
879 | ||
880 | if (PageHighMem(page)) { | |
881 | unsigned long flags; | |
882 | ||
883 | /* FIXME: use a bounce buffer */ | |
884 | local_irq_save(flags); | |
885 | buf = kmap_atomic(page, KM_IRQ0); | |
886 | ||
887 | /* do the actual data transfer */ | |
5682ed33 TH |
888 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
889 | do_write); | |
624d5c51 TH |
890 | |
891 | kunmap_atomic(buf, KM_IRQ0); | |
892 | local_irq_restore(flags); | |
893 | } else { | |
894 | buf = page_address(page); | |
5682ed33 TH |
895 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
896 | do_write); | |
624d5c51 TH |
897 | } |
898 | ||
3842e835 | 899 | if (!do_write && !PageSlab(page)) |
2d68b7fe CM |
900 | flush_dcache_page(page); |
901 | ||
624d5c51 TH |
902 | qc->curbytes += qc->sect_size; |
903 | qc->cursg_ofs += qc->sect_size; | |
904 | ||
905 | if (qc->cursg_ofs == qc->cursg->length) { | |
906 | qc->cursg = sg_next(qc->cursg); | |
907 | qc->cursg_ofs = 0; | |
908 | } | |
909 | } | |
910 | ||
911 | /** | |
912 | * ata_pio_sectors - Transfer one or many sectors. | |
913 | * @qc: Command on going | |
914 | * | |
915 | * Transfer one or many sectors of data from/to the | |
916 | * ATA device for the DRQ request. | |
917 | * | |
918 | * LOCKING: | |
919 | * Inherited from caller. | |
920 | */ | |
921 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
922 | { | |
923 | if (is_multi_taskfile(&qc->tf)) { | |
924 | /* READ/WRITE MULTIPLE */ | |
925 | unsigned int nsect; | |
926 | ||
efcb3cf7 | 927 | WARN_ON_ONCE(qc->dev->multi_count == 0); |
624d5c51 TH |
928 | |
929 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
930 | qc->dev->multi_count); | |
931 | while (nsect--) | |
932 | ata_pio_sector(qc); | |
933 | } else | |
934 | ata_pio_sector(qc); | |
935 | ||
a57c1bad | 936 | ata_sff_sync(qc->ap); /* flush */ |
624d5c51 TH |
937 | } |
938 | ||
939 | /** | |
940 | * atapi_send_cdb - Write CDB bytes to hardware | |
941 | * @ap: Port to which ATAPI device is attached. | |
942 | * @qc: Taskfile currently active | |
943 | * | |
944 | * When device has indicated its readiness to accept | |
945 | * a CDB, this function is called. Send the CDB. | |
946 | * | |
947 | * LOCKING: | |
948 | * caller. | |
949 | */ | |
950 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
951 | { | |
952 | /* send SCSI cdb */ | |
953 | DPRINTK("send cdb\n"); | |
efcb3cf7 | 954 | WARN_ON_ONCE(qc->dev->cdb_len < 12); |
624d5c51 | 955 | |
5682ed33 | 956 | ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); |
a57c1bad AC |
957 | ata_sff_sync(ap); |
958 | /* FIXME: If the CDB is for DMA do we need to do the transition delay | |
959 | or is bmdma_start guaranteed to do it ? */ | |
624d5c51 TH |
960 | switch (qc->tf.protocol) { |
961 | case ATAPI_PROT_PIO: | |
962 | ap->hsm_task_state = HSM_ST; | |
963 | break; | |
964 | case ATAPI_PROT_NODATA: | |
965 | ap->hsm_task_state = HSM_ST_LAST; | |
966 | break; | |
967 | case ATAPI_PROT_DMA: | |
968 | ap->hsm_task_state = HSM_ST_LAST; | |
969 | /* initiate bmdma */ | |
970 | ap->ops->bmdma_start(qc); | |
971 | break; | |
972 | } | |
973 | } | |
974 | ||
975 | /** | |
976 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
977 | * @qc: Command on going | |
978 | * @bytes: number of bytes | |
979 | * | |
980 | * Transfer Transfer data from/to the ATAPI device. | |
981 | * | |
982 | * LOCKING: | |
983 | * Inherited from caller. | |
984 | * | |
985 | */ | |
986 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
987 | { | |
988 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
989 | struct ata_port *ap = qc->ap; | |
990 | struct ata_device *dev = qc->dev; | |
991 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
992 | struct scatterlist *sg; | |
993 | struct page *page; | |
994 | unsigned char *buf; | |
995 | unsigned int offset, count, consumed; | |
996 | ||
997 | next_sg: | |
998 | sg = qc->cursg; | |
999 | if (unlikely(!sg)) { | |
1000 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
1001 | "buf=%u cur=%u bytes=%u", | |
1002 | qc->nbytes, qc->curbytes, bytes); | |
1003 | return -1; | |
1004 | } | |
1005 | ||
1006 | page = sg_page(sg); | |
1007 | offset = sg->offset + qc->cursg_ofs; | |
1008 | ||
1009 | /* get the current page and offset */ | |
1010 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
1011 | offset %= PAGE_SIZE; | |
1012 | ||
1013 | /* don't overrun current sg */ | |
1014 | count = min(sg->length - qc->cursg_ofs, bytes); | |
1015 | ||
1016 | /* don't cross page boundaries */ | |
1017 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
1018 | ||
1019 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
1020 | ||
1021 | if (PageHighMem(page)) { | |
1022 | unsigned long flags; | |
1023 | ||
1024 | /* FIXME: use bounce buffer */ | |
1025 | local_irq_save(flags); | |
1026 | buf = kmap_atomic(page, KM_IRQ0); | |
1027 | ||
1028 | /* do the actual data transfer */ | |
0fe40ff8 AC |
1029 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
1030 | count, rw); | |
624d5c51 TH |
1031 | |
1032 | kunmap_atomic(buf, KM_IRQ0); | |
1033 | local_irq_restore(flags); | |
1034 | } else { | |
1035 | buf = page_address(page); | |
0fe40ff8 AC |
1036 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
1037 | count, rw); | |
624d5c51 TH |
1038 | } |
1039 | ||
1040 | bytes -= min(bytes, consumed); | |
1041 | qc->curbytes += count; | |
1042 | qc->cursg_ofs += count; | |
1043 | ||
1044 | if (qc->cursg_ofs == sg->length) { | |
1045 | qc->cursg = sg_next(qc->cursg); | |
1046 | qc->cursg_ofs = 0; | |
1047 | } | |
1048 | ||
a0f79f7a CB |
1049 | /* |
1050 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); | |
1051 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN | |
1052 | * check correctly as it doesn't know if it is the last request being | |
1053 | * made. Somebody should implement a proper sanity check. | |
1054 | */ | |
624d5c51 TH |
1055 | if (bytes) |
1056 | goto next_sg; | |
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | /** | |
1061 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
1062 | * @qc: Command on going | |
1063 | * | |
1064 | * Transfer Transfer data from/to the ATAPI device. | |
1065 | * | |
1066 | * LOCKING: | |
1067 | * Inherited from caller. | |
1068 | */ | |
1069 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
1070 | { | |
1071 | struct ata_port *ap = qc->ap; | |
1072 | struct ata_device *dev = qc->dev; | |
1073 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
1074 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
1075 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
1076 | ||
1077 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
1078 | * here to save some kernel stack usage. | |
1079 | * For normal completion, qc->result_tf is not relevant. For | |
1080 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
1081 | * So, the correctness of qc->result_tf is not affected. | |
1082 | */ | |
5682ed33 | 1083 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
1084 | ireason = qc->result_tf.nsect; |
1085 | bc_lo = qc->result_tf.lbam; | |
1086 | bc_hi = qc->result_tf.lbah; | |
1087 | bytes = (bc_hi << 8) | bc_lo; | |
1088 | ||
1089 | /* shall be cleared to zero, indicating xfer of data */ | |
1090 | if (unlikely(ireason & (1 << 0))) | |
1091 | goto atapi_check; | |
1092 | ||
1093 | /* make sure transfer direction matches expected */ | |
1094 | i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; | |
1095 | if (unlikely(do_write != i_write)) | |
1096 | goto atapi_check; | |
1097 | ||
1098 | if (unlikely(!bytes)) | |
1099 | goto atapi_check; | |
1100 | ||
1101 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
1102 | ||
1103 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
1104 | goto err_out; | |
a57c1bad | 1105 | ata_sff_sync(ap); /* flush */ |
624d5c51 TH |
1106 | |
1107 | return; | |
1108 | ||
1109 | atapi_check: | |
1110 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
1111 | ireason, bytes); | |
1112 | err_out: | |
1113 | qc->err_mask |= AC_ERR_HSM; | |
1114 | ap->hsm_task_state = HSM_ST_ERR; | |
1115 | } | |
1116 | ||
1117 | /** | |
1118 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
1119 | * @ap: the target ata_port | |
1120 | * @qc: qc on going | |
1121 | * | |
1122 | * RETURNS: | |
1123 | * 1 if ok in workqueue, 0 otherwise. | |
1124 | */ | |
0fe40ff8 AC |
1125 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, |
1126 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
1127 | { |
1128 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1129 | return 1; | |
1130 | ||
1131 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
1132 | if (qc->tf.protocol == ATA_PROT_PIO && | |
0fe40ff8 | 1133 | (qc->tf.flags & ATA_TFLAG_WRITE)) |
624d5c51 TH |
1134 | return 1; |
1135 | ||
1136 | if (ata_is_atapi(qc->tf.protocol) && | |
0fe40ff8 | 1137 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
624d5c51 TH |
1138 | return 1; |
1139 | } | |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | /** | |
1145 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
1146 | * @qc: Command to complete | |
1147 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1148 | * | |
1149 | * Finish @qc which is running on standard HSM. | |
1150 | * | |
1151 | * LOCKING: | |
1152 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
1153 | * Otherwise, none on entry and grabs host lock. | |
1154 | */ | |
1155 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
1156 | { | |
1157 | struct ata_port *ap = qc->ap; | |
1158 | unsigned long flags; | |
1159 | ||
1160 | if (ap->ops->error_handler) { | |
1161 | if (in_wq) { | |
1162 | spin_lock_irqsave(ap->lock, flags); | |
1163 | ||
1164 | /* EH might have kicked in while host lock is | |
1165 | * released. | |
1166 | */ | |
1167 | qc = ata_qc_from_tag(ap, qc->tag); | |
1168 | if (qc) { | |
1169 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
e42a542b | 1170 | ata_sff_irq_on(ap); |
624d5c51 TH |
1171 | ata_qc_complete(qc); |
1172 | } else | |
1173 | ata_port_freeze(ap); | |
1174 | } | |
1175 | ||
1176 | spin_unlock_irqrestore(ap->lock, flags); | |
1177 | } else { | |
1178 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
1179 | ata_qc_complete(qc); | |
1180 | else | |
1181 | ata_port_freeze(ap); | |
1182 | } | |
1183 | } else { | |
1184 | if (in_wq) { | |
1185 | spin_lock_irqsave(ap->lock, flags); | |
e42a542b | 1186 | ata_sff_irq_on(ap); |
624d5c51 TH |
1187 | ata_qc_complete(qc); |
1188 | spin_unlock_irqrestore(ap->lock, flags); | |
1189 | } else | |
1190 | ata_qc_complete(qc); | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | /** | |
9363c382 | 1195 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
1196 | * @ap: the target ata_port |
1197 | * @qc: qc on going | |
1198 | * @status: current device status | |
1199 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1200 | * | |
1201 | * RETURNS: | |
1202 | * 1 when poll next status needed, 0 otherwise. | |
1203 | */ | |
9363c382 TH |
1204 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
1205 | u8 status, int in_wq) | |
624d5c51 | 1206 | { |
a836d3e8 | 1207 | struct ata_eh_info *ehi = &ap->link.eh_info; |
624d5c51 TH |
1208 | unsigned long flags = 0; |
1209 | int poll_next; | |
1210 | ||
efcb3cf7 | 1211 | WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0); |
624d5c51 | 1212 | |
9363c382 | 1213 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
1214 | * like DMA polling into the workqueue. Notice that |
1215 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
1216 | */ | |
efcb3cf7 | 1217 | WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc)); |
624d5c51 TH |
1218 | |
1219 | fsm_start: | |
1220 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
1221 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
1222 | ||
1223 | switch (ap->hsm_task_state) { | |
1224 | case HSM_ST_FIRST: | |
1225 | /* Send first data block or PACKET CDB */ | |
1226 | ||
1227 | /* If polling, we will stay in the work queue after | |
1228 | * sending the data. Otherwise, interrupt handler | |
1229 | * takes over after sending the data. | |
1230 | */ | |
1231 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
1232 | ||
1233 | /* check device status */ | |
1234 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1235 | /* handle BSY=0, DRQ=0 as error */ | |
1236 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1237 | /* device stops HSM for abort/error */ | |
1238 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 1239 | else { |
624d5c51 | 1240 | /* HSM violation. Let EH handle this */ |
a836d3e8 TH |
1241 | ata_ehi_push_desc(ehi, |
1242 | "ST_FIRST: !(DRQ|ERR|DF)"); | |
624d5c51 | 1243 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1244 | } |
624d5c51 TH |
1245 | |
1246 | ap->hsm_task_state = HSM_ST_ERR; | |
1247 | goto fsm_start; | |
1248 | } | |
1249 | ||
1250 | /* Device should not ask for data transfer (DRQ=1) | |
1251 | * when it finds something wrong. | |
1252 | * We ignore DRQ here and stop the HSM by | |
1253 | * changing hsm_task_state to HSM_ST_ERR and | |
1254 | * let the EH abort the command or reset the device. | |
1255 | */ | |
1256 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1257 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1258 | * when doing the next command (mostly request sense). | |
1259 | * We ignore ERR here to workaround and proceed sending | |
1260 | * the CDB. | |
1261 | */ | |
1262 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
a836d3e8 TH |
1263 | ata_ehi_push_desc(ehi, "ST_FIRST: " |
1264 | "DRQ=1 with device error, " | |
1265 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1266 | qc->err_mask |= AC_ERR_HSM; |
1267 | ap->hsm_task_state = HSM_ST_ERR; | |
1268 | goto fsm_start; | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | /* Send the CDB (atapi) or the first data block (ata pio out). | |
1273 | * During the state transition, interrupt handler shouldn't | |
1274 | * be invoked before the data transfer is complete and | |
1275 | * hsm_task_state is changed. Hence, the following locking. | |
1276 | */ | |
1277 | if (in_wq) | |
1278 | spin_lock_irqsave(ap->lock, flags); | |
1279 | ||
1280 | if (qc->tf.protocol == ATA_PROT_PIO) { | |
1281 | /* PIO data out protocol. | |
1282 | * send first data block. | |
1283 | */ | |
1284 | ||
1285 | /* ata_pio_sectors() might change the state | |
1286 | * to HSM_ST_LAST. so, the state is changed here | |
1287 | * before ata_pio_sectors(). | |
1288 | */ | |
1289 | ap->hsm_task_state = HSM_ST; | |
1290 | ata_pio_sectors(qc); | |
1291 | } else | |
1292 | /* send CDB */ | |
1293 | atapi_send_cdb(ap, qc); | |
1294 | ||
1295 | if (in_wq) | |
1296 | spin_unlock_irqrestore(ap->lock, flags); | |
1297 | ||
1298 | /* if polling, ata_pio_task() handles the rest. | |
1299 | * otherwise, interrupt handler takes over from here. | |
1300 | */ | |
1301 | break; | |
1302 | ||
1303 | case HSM_ST: | |
1304 | /* complete command or read/write the data register */ | |
1305 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1306 | /* ATAPI PIO protocol */ | |
1307 | if ((status & ATA_DRQ) == 0) { | |
1308 | /* No more data to transfer or device error. | |
1309 | * Device error will be tagged in HSM_ST_LAST. | |
1310 | */ | |
1311 | ap->hsm_task_state = HSM_ST_LAST; | |
1312 | goto fsm_start; | |
1313 | } | |
1314 | ||
1315 | /* Device should not ask for data transfer (DRQ=1) | |
1316 | * when it finds something wrong. | |
1317 | * We ignore DRQ here and stop the HSM by | |
1318 | * changing hsm_task_state to HSM_ST_ERR and | |
1319 | * let the EH abort the command or reset the device. | |
1320 | */ | |
1321 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
a836d3e8 TH |
1322 | ata_ehi_push_desc(ehi, "ST-ATAPI: " |
1323 | "DRQ=1 with device error, " | |
1324 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1325 | qc->err_mask |= AC_ERR_HSM; |
1326 | ap->hsm_task_state = HSM_ST_ERR; | |
1327 | goto fsm_start; | |
1328 | } | |
1329 | ||
1330 | atapi_pio_bytes(qc); | |
1331 | ||
1332 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1333 | /* bad ireason reported by device */ | |
1334 | goto fsm_start; | |
1335 | ||
1336 | } else { | |
1337 | /* ATA PIO protocol */ | |
1338 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1339 | /* handle BSY=0, DRQ=0 as error */ | |
6a6b97d3 | 1340 | if (likely(status & (ATA_ERR | ATA_DF))) { |
624d5c51 TH |
1341 | /* device stops HSM for abort/error */ |
1342 | qc->err_mask |= AC_ERR_DEV; | |
6a6b97d3 TH |
1343 | |
1344 | /* If diagnostic failed and this is | |
1345 | * IDENTIFY, it's likely a phantom | |
1346 | * device. Mark hint. | |
1347 | */ | |
1348 | if (qc->dev->horkage & | |
1349 | ATA_HORKAGE_DIAGNOSTIC) | |
1350 | qc->err_mask |= | |
1351 | AC_ERR_NODEV_HINT; | |
1352 | } else { | |
624d5c51 TH |
1353 | /* HSM violation. Let EH handle this. |
1354 | * Phantom devices also trigger this | |
1355 | * condition. Mark hint. | |
1356 | */ | |
a836d3e8 | 1357 | ata_ehi_push_desc(ehi, "ST-ATA: " |
80ee6f54 | 1358 | "DRQ=0 without device error, " |
a836d3e8 | 1359 | "dev_stat 0x%X", status); |
624d5c51 TH |
1360 | qc->err_mask |= AC_ERR_HSM | |
1361 | AC_ERR_NODEV_HINT; | |
a836d3e8 | 1362 | } |
624d5c51 TH |
1363 | |
1364 | ap->hsm_task_state = HSM_ST_ERR; | |
1365 | goto fsm_start; | |
1366 | } | |
1367 | ||
1368 | /* For PIO reads, some devices may ask for | |
1369 | * data transfer (DRQ=1) alone with ERR=1. | |
1370 | * We respect DRQ here and transfer one | |
1371 | * block of junk data before changing the | |
1372 | * hsm_task_state to HSM_ST_ERR. | |
1373 | * | |
1374 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1375 | * sense since the data block has been | |
1376 | * transferred to the device. | |
1377 | */ | |
1378 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1379 | /* data might be corrputed */ | |
1380 | qc->err_mask |= AC_ERR_DEV; | |
1381 | ||
1382 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1383 | ata_pio_sectors(qc); | |
1384 | status = ata_wait_idle(ap); | |
1385 | } | |
1386 | ||
a836d3e8 TH |
1387 | if (status & (ATA_BUSY | ATA_DRQ)) { |
1388 | ata_ehi_push_desc(ehi, "ST-ATA: " | |
1389 | "BUSY|DRQ persists on ERR|DF, " | |
1390 | "dev_stat 0x%X", status); | |
624d5c51 | 1391 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1392 | } |
624d5c51 | 1393 | |
b919930c TH |
1394 | /* There are oddball controllers with |
1395 | * status register stuck at 0x7f and | |
1396 | * lbal/m/h at zero which makes it | |
1397 | * pass all other presence detection | |
1398 | * mechanisms we have. Set NODEV_HINT | |
1399 | * for it. Kernel bz#7241. | |
1400 | */ | |
1401 | if (status == 0x7f) | |
1402 | qc->err_mask |= AC_ERR_NODEV_HINT; | |
1403 | ||
624d5c51 TH |
1404 | /* ata_pio_sectors() might change the |
1405 | * state to HSM_ST_LAST. so, the state | |
1406 | * is changed after ata_pio_sectors(). | |
1407 | */ | |
1408 | ap->hsm_task_state = HSM_ST_ERR; | |
1409 | goto fsm_start; | |
1410 | } | |
1411 | ||
1412 | ata_pio_sectors(qc); | |
1413 | ||
1414 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1415 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1416 | /* all data read */ | |
1417 | status = ata_wait_idle(ap); | |
1418 | goto fsm_start; | |
1419 | } | |
1420 | } | |
1421 | ||
1422 | poll_next = 1; | |
1423 | break; | |
1424 | ||
1425 | case HSM_ST_LAST: | |
1426 | if (unlikely(!ata_ok(status))) { | |
1427 | qc->err_mask |= __ac_err_mask(status); | |
1428 | ap->hsm_task_state = HSM_ST_ERR; | |
1429 | goto fsm_start; | |
1430 | } | |
1431 | ||
1432 | /* no more data to transfer */ | |
1433 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1434 | ap->print_id, qc->dev->devno, status); | |
1435 | ||
efcb3cf7 | 1436 | WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); |
624d5c51 TH |
1437 | |
1438 | ap->hsm_task_state = HSM_ST_IDLE; | |
1439 | ||
1440 | /* complete taskfile transaction */ | |
1441 | ata_hsm_qc_complete(qc, in_wq); | |
1442 | ||
1443 | poll_next = 0; | |
1444 | break; | |
1445 | ||
1446 | case HSM_ST_ERR: | |
624d5c51 TH |
1447 | ap->hsm_task_state = HSM_ST_IDLE; |
1448 | ||
1449 | /* complete taskfile transaction */ | |
1450 | ata_hsm_qc_complete(qc, in_wq); | |
1451 | ||
1452 | poll_next = 0; | |
1453 | break; | |
1454 | default: | |
1455 | poll_next = 0; | |
1456 | BUG(); | |
1457 | } | |
1458 | ||
1459 | return poll_next; | |
1460 | } | |
0fe40ff8 | 1461 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); |
624d5c51 TH |
1462 | |
1463 | void ata_pio_task(struct work_struct *work) | |
1464 | { | |
1465 | struct ata_port *ap = | |
1466 | container_of(work, struct ata_port, port_task.work); | |
1467 | struct ata_queued_cmd *qc = ap->port_task_data; | |
1468 | u8 status; | |
1469 | int poll_next; | |
1470 | ||
1471 | fsm_start: | |
efcb3cf7 | 1472 | WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE); |
624d5c51 TH |
1473 | |
1474 | /* | |
1475 | * This is purely heuristic. This is a fast path. | |
1476 | * Sometimes when we enter, BSY will be cleared in | |
1477 | * a chk-status or two. If not, the drive is probably seeking | |
1478 | * or something. Snooze for a couple msecs, then | |
1479 | * chk-status again. If still busy, queue delayed work. | |
1480 | */ | |
9363c382 | 1481 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 TH |
1482 | if (status & ATA_BUSY) { |
1483 | msleep(2); | |
9363c382 | 1484 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 TH |
1485 | if (status & ATA_BUSY) { |
1486 | ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE); | |
1487 | return; | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | /* move the HSM */ | |
9363c382 | 1492 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1493 | |
1494 | /* another command or interrupt handler | |
1495 | * may be running at this point. | |
1496 | */ | |
1497 | if (poll_next) | |
1498 | goto fsm_start; | |
1499 | } | |
1500 | ||
1501 | /** | |
9363c382 | 1502 | * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner |
624d5c51 TH |
1503 | * @qc: command to issue to device |
1504 | * | |
1505 | * Using various libata functions and hooks, this function | |
1506 | * starts an ATA command. ATA commands are grouped into | |
1507 | * classes called "protocols", and issuing each type of protocol | |
1508 | * is slightly different. | |
1509 | * | |
1510 | * May be used as the qc_issue() entry in ata_port_operations. | |
1511 | * | |
1512 | * LOCKING: | |
1513 | * spin_lock_irqsave(host lock) | |
1514 | * | |
1515 | * RETURNS: | |
1516 | * Zero on success, AC_ERR_* mask on failure | |
1517 | */ | |
9363c382 | 1518 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1519 | { |
1520 | struct ata_port *ap = qc->ap; | |
1521 | ||
1522 | /* Use polling pio if the LLD doesn't handle | |
1523 | * interrupt driven pio and atapi CDB interrupt. | |
1524 | */ | |
1525 | if (ap->flags & ATA_FLAG_PIO_POLLING) { | |
1526 | switch (qc->tf.protocol) { | |
1527 | case ATA_PROT_PIO: | |
1528 | case ATA_PROT_NODATA: | |
1529 | case ATAPI_PROT_PIO: | |
1530 | case ATAPI_PROT_NODATA: | |
1531 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
1532 | break; | |
1533 | case ATAPI_PROT_DMA: | |
1534 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
1535 | /* see ata_dma_blacklisted() */ | |
1536 | BUG(); | |
1537 | break; | |
1538 | default: | |
1539 | break; | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | /* select the device */ | |
1544 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1545 | ||
1546 | /* start the command */ | |
1547 | switch (qc->tf.protocol) { | |
1548 | case ATA_PROT_NODATA: | |
1549 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1550 | ata_qc_set_polling(qc); | |
1551 | ||
1552 | ata_tf_to_host(ap, &qc->tf); | |
1553 | ap->hsm_task_state = HSM_ST_LAST; | |
1554 | ||
1555 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1556 | ata_pio_queue_task(ap, qc, 0); | |
1557 | ||
1558 | break; | |
1559 | ||
1560 | case ATA_PROT_DMA: | |
efcb3cf7 | 1561 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); |
624d5c51 | 1562 | |
5682ed33 | 1563 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1564 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1565 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
1566 | ap->hsm_task_state = HSM_ST_LAST; | |
1567 | break; | |
1568 | ||
1569 | case ATA_PROT_PIO: | |
1570 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1571 | ata_qc_set_polling(qc); | |
1572 | ||
1573 | ata_tf_to_host(ap, &qc->tf); | |
1574 | ||
1575 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1576 | /* PIO data out protocol */ | |
1577 | ap->hsm_task_state = HSM_ST_FIRST; | |
1578 | ata_pio_queue_task(ap, qc, 0); | |
1579 | ||
1580 | /* always send first data block using | |
1581 | * the ata_pio_task() codepath. | |
1582 | */ | |
1583 | } else { | |
1584 | /* PIO data in protocol */ | |
1585 | ap->hsm_task_state = HSM_ST; | |
1586 | ||
1587 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1588 | ata_pio_queue_task(ap, qc, 0); | |
1589 | ||
1590 | /* if polling, ata_pio_task() handles the rest. | |
1591 | * otherwise, interrupt handler takes over from here. | |
1592 | */ | |
1593 | } | |
1594 | ||
1595 | break; | |
1596 | ||
1597 | case ATAPI_PROT_PIO: | |
1598 | case ATAPI_PROT_NODATA: | |
1599 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1600 | ata_qc_set_polling(qc); | |
1601 | ||
1602 | ata_tf_to_host(ap, &qc->tf); | |
1603 | ||
1604 | ap->hsm_task_state = HSM_ST_FIRST; | |
1605 | ||
1606 | /* send cdb by polling if no cdb interrupt */ | |
1607 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1608 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
1609 | ata_pio_queue_task(ap, qc, 0); | |
1610 | break; | |
1611 | ||
1612 | case ATAPI_PROT_DMA: | |
efcb3cf7 | 1613 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); |
624d5c51 | 1614 | |
5682ed33 | 1615 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1616 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1617 | ap->hsm_task_state = HSM_ST_FIRST; | |
1618 | ||
1619 | /* send cdb by polling if no cdb interrupt */ | |
1620 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1621 | ata_pio_queue_task(ap, qc, 0); | |
1622 | break; | |
1623 | ||
1624 | default: | |
efcb3cf7 | 1625 | WARN_ON_ONCE(1); |
624d5c51 TH |
1626 | return AC_ERR_SYSTEM; |
1627 | } | |
1628 | ||
1629 | return 0; | |
1630 | } | |
0fe40ff8 | 1631 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); |
624d5c51 | 1632 | |
22183bf5 TH |
1633 | /** |
1634 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1635 | * @qc: qc to fill result TF for | |
1636 | * | |
1637 | * @qc is finished and result TF needs to be filled. Fill it | |
1638 | * using ->sff_tf_read. | |
1639 | * | |
1640 | * LOCKING: | |
1641 | * spin_lock_irqsave(host lock) | |
1642 | * | |
1643 | * RETURNS: | |
1644 | * true indicating that result TF is successfully filled. | |
1645 | */ | |
1646 | bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) | |
1647 | { | |
1648 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
1649 | return true; | |
1650 | } | |
0fe40ff8 | 1651 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
22183bf5 | 1652 | |
624d5c51 | 1653 | /** |
9363c382 | 1654 | * ata_sff_host_intr - Handle host interrupt for given (port, task) |
624d5c51 TH |
1655 | * @ap: Port on which interrupt arrived (possibly...) |
1656 | * @qc: Taskfile currently active in engine | |
1657 | * | |
1658 | * Handle host interrupt for given queued command. Currently, | |
1659 | * only DMA interrupts are handled. All other commands are | |
1660 | * handled via polling with interrupts disabled (nIEN bit). | |
1661 | * | |
1662 | * LOCKING: | |
1663 | * spin_lock_irqsave(host lock) | |
1664 | * | |
1665 | * RETURNS: | |
1666 | * One if interrupt was handled, zero if not (shared irq). | |
1667 | */ | |
c96f1732 | 1668 | unsigned int ata_sff_host_intr(struct ata_port *ap, |
9363c382 | 1669 | struct ata_queued_cmd *qc) |
624d5c51 TH |
1670 | { |
1671 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
1672 | u8 status, host_stat = 0; | |
332ac7ff | 1673 | bool bmdma_stopped = false; |
624d5c51 TH |
1674 | |
1675 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1676 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1677 | ||
1678 | /* Check whether we are expecting interrupt in this state */ | |
1679 | switch (ap->hsm_task_state) { | |
1680 | case HSM_ST_FIRST: | |
1681 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1682 | * at this state when ready to receive CDB. | |
1683 | */ | |
1684 | ||
1685 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1686 | * The flag was turned on only for atapi devices. No | |
1687 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1688 | */ | |
1689 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1690 | goto idle_irq; | |
1691 | break; | |
1692 | case HSM_ST_LAST: | |
1693 | if (qc->tf.protocol == ATA_PROT_DMA || | |
1694 | qc->tf.protocol == ATAPI_PROT_DMA) { | |
1695 | /* check status of DMA engine */ | |
1696 | host_stat = ap->ops->bmdma_status(ap); | |
1697 | VPRINTK("ata%u: host_stat 0x%X\n", | |
1698 | ap->print_id, host_stat); | |
1699 | ||
1700 | /* if it's not our irq... */ | |
1701 | if (!(host_stat & ATA_DMA_INTR)) | |
1702 | goto idle_irq; | |
1703 | ||
1704 | /* before we do anything else, clear DMA-Start bit */ | |
1705 | ap->ops->bmdma_stop(qc); | |
332ac7ff | 1706 | bmdma_stopped = true; |
624d5c51 TH |
1707 | |
1708 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
1709 | /* error when transfering data to/from memory */ | |
1710 | qc->err_mask |= AC_ERR_HOST_BUS; | |
1711 | ap->hsm_task_state = HSM_ST_ERR; | |
1712 | } | |
1713 | } | |
1714 | break; | |
1715 | case HSM_ST: | |
1716 | break; | |
1717 | default: | |
1718 | goto idle_irq; | |
1719 | } | |
1720 | ||
624d5c51 | 1721 | |
a57c1bad AC |
1722 | /* check main status, clearing INTRQ if needed */ |
1723 | status = ata_sff_irq_status(ap); | |
332ac7ff TH |
1724 | if (status & ATA_BUSY) { |
1725 | if (bmdma_stopped) { | |
1726 | /* BMDMA engine is already stopped, we're screwed */ | |
1727 | qc->err_mask |= AC_ERR_HSM; | |
1728 | ap->hsm_task_state = HSM_ST_ERR; | |
1729 | } else | |
1730 | goto idle_irq; | |
1731 | } | |
624d5c51 | 1732 | |
9f2f7210 | 1733 | /* clear irq events */ |
5682ed33 | 1734 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1735 | |
9363c382 | 1736 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 TH |
1737 | |
1738 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || | |
1739 | qc->tf.protocol == ATAPI_PROT_DMA)) | |
1740 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
1741 | ||
1742 | return 1; /* irq handled */ | |
1743 | ||
1744 | idle_irq: | |
1745 | ap->stats.idle_irq++; | |
1746 | ||
1747 | #ifdef ATA_IRQ_TRAP | |
1748 | if ((ap->stats.idle_irq % 1000) == 0) { | |
5682ed33 TH |
1749 | ap->ops->sff_check_status(ap); |
1750 | ap->ops->sff_irq_clear(ap); | |
624d5c51 TH |
1751 | ata_port_printk(ap, KERN_WARNING, "irq trap\n"); |
1752 | return 1; | |
1753 | } | |
1754 | #endif | |
1755 | return 0; /* irq not handled */ | |
1756 | } | |
0fe40ff8 | 1757 | EXPORT_SYMBOL_GPL(ata_sff_host_intr); |
624d5c51 TH |
1758 | |
1759 | /** | |
9363c382 | 1760 | * ata_sff_interrupt - Default ATA host interrupt handler |
624d5c51 TH |
1761 | * @irq: irq line (unused) |
1762 | * @dev_instance: pointer to our ata_host information structure | |
1763 | * | |
1764 | * Default interrupt handler for PCI IDE devices. Calls | |
9363c382 | 1765 | * ata_sff_host_intr() for each port that is not disabled. |
624d5c51 TH |
1766 | * |
1767 | * LOCKING: | |
1768 | * Obtains host lock during operation. | |
1769 | * | |
1770 | * RETURNS: | |
1771 | * IRQ_NONE or IRQ_HANDLED. | |
1772 | */ | |
9363c382 | 1773 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) |
624d5c51 TH |
1774 | { |
1775 | struct ata_host *host = dev_instance; | |
332ac7ff | 1776 | bool retried = false; |
624d5c51 | 1777 | unsigned int i; |
332ac7ff | 1778 | unsigned int handled, idle, polling; |
624d5c51 TH |
1779 | unsigned long flags; |
1780 | ||
1781 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1782 | spin_lock_irqsave(&host->lock, flags); | |
1783 | ||
332ac7ff TH |
1784 | retry: |
1785 | handled = idle = polling = 0; | |
624d5c51 | 1786 | for (i = 0; i < host->n_ports; i++) { |
d88ec2e5 TH |
1787 | struct ata_port *ap = host->ports[i]; |
1788 | struct ata_queued_cmd *qc; | |
624d5c51 | 1789 | |
d88ec2e5 | 1790 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
27943620 TH |
1791 | if (qc) { |
1792 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) | |
1793 | handled |= ata_sff_host_intr(ap, qc); | |
1794 | else | |
1795 | polling |= 1 << i; | |
332ac7ff TH |
1796 | } else |
1797 | idle |= 1 << i; | |
27943620 TH |
1798 | } |
1799 | ||
1800 | /* | |
1801 | * If no port was expecting IRQ but the controller is actually | |
1802 | * asserting IRQ line, nobody cared will ensue. Check IRQ | |
1803 | * pending status if available and clear spurious IRQ. | |
1804 | */ | |
332ac7ff TH |
1805 | if (!handled && !retried) { |
1806 | bool retry = false; | |
1807 | ||
27943620 TH |
1808 | for (i = 0; i < host->n_ports; i++) { |
1809 | struct ata_port *ap = host->ports[i]; | |
1810 | ||
1811 | if (polling & (1 << i)) | |
1812 | continue; | |
1813 | ||
1814 | if (!ap->ops->sff_irq_check || | |
1815 | !ap->ops->sff_irq_check(ap)) | |
1816 | continue; | |
1817 | ||
332ac7ff TH |
1818 | if (idle & (1 << i)) { |
1819 | ap->ops->sff_check_status(ap); | |
1820 | ap->ops->sff_irq_clear(ap); | |
1821 | } else { | |
1822 | /* clear INTRQ and check if BUSY cleared */ | |
1823 | if (!(ap->ops->sff_check_status(ap) & ATA_BUSY)) | |
1824 | retry |= true; | |
1825 | /* | |
1826 | * With command in flight, we can't do | |
1827 | * sff_irq_clear() w/o racing with completion. | |
1828 | */ | |
1829 | } | |
1830 | } | |
1831 | ||
1832 | if (retry) { | |
1833 | retried = true; | |
1834 | goto retry; | |
27943620 | 1835 | } |
624d5c51 TH |
1836 | } |
1837 | ||
1838 | spin_unlock_irqrestore(&host->lock, flags); | |
1839 | ||
1840 | return IRQ_RETVAL(handled); | |
1841 | } | |
0fe40ff8 | 1842 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); |
624d5c51 | 1843 | |
c96f1732 AC |
1844 | /** |
1845 | * ata_sff_lost_interrupt - Check for an apparent lost interrupt | |
1846 | * @ap: port that appears to have timed out | |
1847 | * | |
1848 | * Called from the libata error handlers when the core code suspects | |
1849 | * an interrupt has been lost. If it has complete anything we can and | |
1850 | * then return. Interface must support altstatus for this faster | |
1851 | * recovery to occur. | |
1852 | * | |
1853 | * Locking: | |
1854 | * Caller holds host lock | |
1855 | */ | |
1856 | ||
1857 | void ata_sff_lost_interrupt(struct ata_port *ap) | |
1858 | { | |
1859 | u8 status; | |
1860 | struct ata_queued_cmd *qc; | |
1861 | ||
1862 | /* Only one outstanding command per SFF channel */ | |
1863 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
3e4ec344 TH |
1864 | /* We cannot lose an interrupt on a non-existent or polled command */ |
1865 | if (!qc || qc->tf.flags & ATA_TFLAG_POLLING) | |
c96f1732 AC |
1866 | return; |
1867 | /* See if the controller thinks it is still busy - if so the command | |
1868 | isn't a lost IRQ but is still in progress */ | |
1869 | status = ata_sff_altstatus(ap); | |
1870 | if (status & ATA_BUSY) | |
1871 | return; | |
1872 | ||
1873 | /* There was a command running, we are no longer busy and we have | |
1874 | no interrupt. */ | |
1875 | ata_port_printk(ap, KERN_WARNING, "lost interrupt (Status 0x%x)\n", | |
1876 | status); | |
1877 | /* Run the host interrupt logic as if the interrupt had not been | |
1878 | lost */ | |
1879 | ata_sff_host_intr(ap, qc); | |
1880 | } | |
1881 | EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt); | |
1882 | ||
624d5c51 | 1883 | /** |
9363c382 | 1884 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1885 | * @ap: port to freeze |
1886 | * | |
9f2f7210 | 1887 | * Freeze SFF controller port. |
624d5c51 TH |
1888 | * |
1889 | * LOCKING: | |
1890 | * Inherited from caller. | |
1891 | */ | |
9363c382 | 1892 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 | 1893 | { |
624d5c51 TH |
1894 | ap->ctl |= ATA_NIEN; |
1895 | ap->last_ctl = ap->ctl; | |
1896 | ||
41dec29b SS |
1897 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) |
1898 | ata_sff_set_devctl(ap, ap->ctl); | |
624d5c51 TH |
1899 | |
1900 | /* Under certain circumstances, some controllers raise IRQ on | |
1901 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1902 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1903 | */ | |
5682ed33 | 1904 | ap->ops->sff_check_status(ap); |
624d5c51 | 1905 | |
5682ed33 | 1906 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1907 | } |
0fe40ff8 | 1908 | EXPORT_SYMBOL_GPL(ata_sff_freeze); |
624d5c51 TH |
1909 | |
1910 | /** | |
9363c382 | 1911 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1912 | * @ap: port to thaw |
1913 | * | |
9363c382 | 1914 | * Thaw SFF controller port. |
624d5c51 TH |
1915 | * |
1916 | * LOCKING: | |
1917 | * Inherited from caller. | |
1918 | */ | |
9363c382 | 1919 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1920 | { |
624d5c51 | 1921 | /* clear & re-enable interrupts */ |
5682ed33 TH |
1922 | ap->ops->sff_check_status(ap); |
1923 | ap->ops->sff_irq_clear(ap); | |
e42a542b | 1924 | ata_sff_irq_on(ap); |
272f7884 | 1925 | } |
0fe40ff8 | 1926 | EXPORT_SYMBOL_GPL(ata_sff_thaw); |
272f7884 | 1927 | |
0aa1113d TH |
1928 | /** |
1929 | * ata_sff_prereset - prepare SFF link for reset | |
1930 | * @link: SFF link to be reset | |
1931 | * @deadline: deadline jiffies for the operation | |
1932 | * | |
1933 | * SFF link @link is about to be reset. Initialize it. It first | |
1934 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1935 | * being softreset. | |
1936 | * | |
1937 | * LOCKING: | |
1938 | * Kernel thread context (may sleep) | |
1939 | * | |
1940 | * RETURNS: | |
1941 | * 0 on success, -errno otherwise. | |
1942 | */ | |
1943 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1944 | { | |
0aa1113d TH |
1945 | struct ata_eh_context *ehc = &link->eh_context; |
1946 | int rc; | |
1947 | ||
1948 | rc = ata_std_prereset(link, deadline); | |
1949 | if (rc) | |
1950 | return rc; | |
1951 | ||
1952 | /* if we're about to do hardreset, nothing more to do */ | |
1953 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1954 | return 0; | |
1955 | ||
1956 | /* wait for !BSY if we don't know that no device is attached */ | |
1957 | if (!ata_link_offline(link)) { | |
705e76be | 1958 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d TH |
1959 | if (rc && rc != -ENODEV) { |
1960 | ata_link_printk(link, KERN_WARNING, "device not ready " | |
1961 | "(errno=%d), forcing hardreset\n", rc); | |
1962 | ehc->i.action |= ATA_EH_HARDRESET; | |
1963 | } | |
1964 | } | |
1965 | ||
1966 | return 0; | |
1967 | } | |
0fe40ff8 | 1968 | EXPORT_SYMBOL_GPL(ata_sff_prereset); |
0aa1113d | 1969 | |
90088bb4 | 1970 | /** |
624d5c51 TH |
1971 | * ata_devchk - PATA device presence detection |
1972 | * @ap: ATA channel to examine | |
1973 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1974 | * |
624d5c51 TH |
1975 | * This technique was originally described in |
1976 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1977 | * later found its way into the ATA/ATAPI spec. | |
1978 | * | |
1979 | * Write a pattern to the ATA shadow registers, | |
1980 | * and if a device is present, it will respond by | |
1981 | * correctly storing and echoing back the | |
1982 | * ATA shadow register contents. | |
90088bb4 TH |
1983 | * |
1984 | * LOCKING: | |
624d5c51 | 1985 | * caller. |
90088bb4 | 1986 | */ |
624d5c51 | 1987 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1988 | { |
1989 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1990 | u8 nsect, lbal; |
90088bb4 | 1991 | |
5682ed33 | 1992 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1993 | |
624d5c51 TH |
1994 | iowrite8(0x55, ioaddr->nsect_addr); |
1995 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1996 | |
624d5c51 TH |
1997 | iowrite8(0xaa, ioaddr->nsect_addr); |
1998 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1999 | |
624d5c51 TH |
2000 | iowrite8(0x55, ioaddr->nsect_addr); |
2001 | iowrite8(0xaa, ioaddr->lbal_addr); | |
2002 | ||
2003 | nsect = ioread8(ioaddr->nsect_addr); | |
2004 | lbal = ioread8(ioaddr->lbal_addr); | |
2005 | ||
2006 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
2007 | return 1; /* we found a device */ | |
2008 | ||
2009 | return 0; /* nothing found */ | |
90088bb4 TH |
2010 | } |
2011 | ||
272f7884 | 2012 | /** |
9363c382 | 2013 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
2014 | * @dev: ATA device to classify (starting at zero) |
2015 | * @present: device seems present | |
2016 | * @r_err: Value of error register on completion | |
272f7884 | 2017 | * |
624d5c51 TH |
2018 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
2019 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
2020 | * shadow registers, indicating the results of device detection | |
2021 | * and diagnostics. | |
272f7884 | 2022 | * |
624d5c51 TH |
2023 | * Select the ATA device, and read the values from the ATA shadow |
2024 | * registers. Then parse according to the Error register value, | |
2025 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
2026 | * |
2027 | * LOCKING: | |
624d5c51 TH |
2028 | * caller. |
2029 | * | |
2030 | * RETURNS: | |
2031 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 2032 | */ |
9363c382 | 2033 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 2034 | u8 *r_err) |
272f7884 | 2035 | { |
624d5c51 TH |
2036 | struct ata_port *ap = dev->link->ap; |
2037 | struct ata_taskfile tf; | |
2038 | unsigned int class; | |
2039 | u8 err; | |
2040 | ||
5682ed33 | 2041 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
2042 | |
2043 | memset(&tf, 0, sizeof(tf)); | |
2044 | ||
5682ed33 | 2045 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
2046 | err = tf.feature; |
2047 | if (r_err) | |
2048 | *r_err = err; | |
2049 | ||
2050 | /* see if device passed diags: continue and warn later */ | |
2051 | if (err == 0) | |
2052 | /* diagnostic fail : do nothing _YET_ */ | |
2053 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
2054 | else if (err == 1) | |
2055 | /* do nothing */ ; | |
2056 | else if ((dev->devno == 0) && (err == 0x81)) | |
2057 | /* do nothing */ ; | |
2058 | else | |
2059 | return ATA_DEV_NONE; | |
272f7884 | 2060 | |
624d5c51 TH |
2061 | /* determine if device is ATA or ATAPI */ |
2062 | class = ata_dev_classify(&tf); | |
272f7884 | 2063 | |
624d5c51 TH |
2064 | if (class == ATA_DEV_UNKNOWN) { |
2065 | /* If the device failed diagnostic, it's likely to | |
2066 | * have reported incorrect device signature too. | |
2067 | * Assume ATA device if the device seems present but | |
2068 | * device signature is invalid with diagnostic | |
2069 | * failure. | |
2070 | */ | |
2071 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
2072 | class = ATA_DEV_ATA; | |
2073 | else | |
2074 | class = ATA_DEV_NONE; | |
5682ed33 TH |
2075 | } else if ((class == ATA_DEV_ATA) && |
2076 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
2077 | class = ATA_DEV_NONE; |
2078 | ||
2079 | return class; | |
272f7884 | 2080 | } |
0fe40ff8 | 2081 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); |
272f7884 | 2082 | |
705e76be TH |
2083 | /** |
2084 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
2085 | * @link: SFF link which is just reset | |
2086 | * @devmask: mask of present devices | |
2087 | * @deadline: deadline jiffies for the operation | |
2088 | * | |
2089 | * Wait devices attached to SFF @link to become ready after | |
2090 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
2091 | * status register too early. | |
2092 | * | |
2093 | * LOCKING: | |
2094 | * Kernel thread context (may sleep). | |
2095 | * | |
2096 | * RETURNS: | |
2097 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
2098 | * don't seem to exist. -errno on other errors. | |
2099 | */ | |
2100 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
2101 | unsigned long deadline) | |
1fdffbce | 2102 | { |
705e76be | 2103 | struct ata_port *ap = link->ap; |
1fdffbce | 2104 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
2105 | unsigned int dev0 = devmask & (1 << 0); |
2106 | unsigned int dev1 = devmask & (1 << 1); | |
2107 | int rc, ret = 0; | |
1fdffbce | 2108 | |
341c2c95 | 2109 | msleep(ATA_WAIT_AFTER_RESET); |
705e76be TH |
2110 | |
2111 | /* always check readiness of the master device */ | |
2112 | rc = ata_sff_wait_ready(link, deadline); | |
2113 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
2114 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 2115 | */ |
705e76be TH |
2116 | if (rc) |
2117 | return rc; | |
1fdffbce | 2118 | |
624d5c51 TH |
2119 | /* if device 1 was found in ata_devchk, wait for register |
2120 | * access briefly, then wait for BSY to clear. | |
2121 | */ | |
2122 | if (dev1) { | |
2123 | int i; | |
1fdffbce | 2124 | |
5682ed33 | 2125 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 2126 | |
624d5c51 TH |
2127 | /* Wait for register access. Some ATAPI devices fail |
2128 | * to set nsect/lbal after reset, so don't waste too | |
2129 | * much time on it. We're gonna wait for !BSY anyway. | |
2130 | */ | |
2131 | for (i = 0; i < 2; i++) { | |
2132 | u8 nsect, lbal; | |
2133 | ||
2134 | nsect = ioread8(ioaddr->nsect_addr); | |
2135 | lbal = ioread8(ioaddr->lbal_addr); | |
2136 | if ((nsect == 1) && (lbal == 1)) | |
2137 | break; | |
2138 | msleep(50); /* give drive a breather */ | |
2139 | } | |
2140 | ||
705e76be | 2141 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
2142 | if (rc) { |
2143 | if (rc != -ENODEV) | |
2144 | return rc; | |
2145 | ret = rc; | |
2146 | } | |
1fdffbce JG |
2147 | } |
2148 | ||
624d5c51 | 2149 | /* is all this really necessary? */ |
5682ed33 | 2150 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 2151 | if (dev1) |
5682ed33 | 2152 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 2153 | if (dev0) |
5682ed33 | 2154 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2155 | |
2156 | return ret; | |
1fdffbce | 2157 | } |
0fe40ff8 | 2158 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); |
1fdffbce | 2159 | |
624d5c51 TH |
2160 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
2161 | unsigned long deadline) | |
2cc432ee | 2162 | { |
624d5c51 | 2163 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 2164 | |
624d5c51 TH |
2165 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
2166 | ||
2167 | /* software reset. causes dev0 to be selected */ | |
2168 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
2169 | udelay(20); /* FIXME: flush */ | |
2170 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
2171 | udelay(20); /* FIXME: flush */ | |
2172 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
e3e4385f | 2173 | ap->last_ctl = ap->ctl; |
624d5c51 | 2174 | |
705e76be TH |
2175 | /* wait the port to become ready */ |
2176 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
2177 | } |
2178 | ||
6d97dbd7 | 2179 | /** |
9363c382 | 2180 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
2181 | * @link: ATA link to reset |
2182 | * @classes: resulting classes of attached devices | |
2183 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2184 | * |
624d5c51 | 2185 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
2186 | * |
2187 | * LOCKING: | |
624d5c51 TH |
2188 | * Kernel thread context (may sleep) |
2189 | * | |
2190 | * RETURNS: | |
2191 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2192 | */ |
9363c382 | 2193 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 2194 | unsigned long deadline) |
6d97dbd7 | 2195 | { |
624d5c51 TH |
2196 | struct ata_port *ap = link->ap; |
2197 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
2198 | unsigned int devmask = 0; | |
2199 | int rc; | |
2200 | u8 err; | |
6d97dbd7 | 2201 | |
624d5c51 | 2202 | DPRINTK("ENTER\n"); |
6d97dbd7 | 2203 | |
624d5c51 TH |
2204 | /* determine if device 0/1 are present */ |
2205 | if (ata_devchk(ap, 0)) | |
2206 | devmask |= (1 << 0); | |
2207 | if (slave_possible && ata_devchk(ap, 1)) | |
2208 | devmask |= (1 << 1); | |
2209 | ||
2210 | /* select device 0 again */ | |
5682ed33 | 2211 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2212 | |
2213 | /* issue bus reset */ | |
2214 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
2215 | rc = ata_bus_softreset(ap, devmask, deadline); | |
2216 | /* if link is occupied, -ENODEV too is an error */ | |
2217 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
2218 | ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); | |
2219 | return rc; | |
2220 | } | |
0f0a3ad3 | 2221 | |
624d5c51 | 2222 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 2223 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
2224 | devmask & (1 << 0), &err); |
2225 | if (slave_possible && err != 0x81) | |
9363c382 | 2226 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
2227 | devmask & (1 << 1), &err); |
2228 | ||
624d5c51 TH |
2229 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
2230 | return 0; | |
6d97dbd7 | 2231 | } |
0fe40ff8 | 2232 | EXPORT_SYMBOL_GPL(ata_sff_softreset); |
6d97dbd7 TH |
2233 | |
2234 | /** | |
9363c382 | 2235 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
2236 | * @link: link to reset |
2237 | * @class: resulting class of attached device | |
2238 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2239 | * |
624d5c51 TH |
2240 | * SATA phy-reset host port using DET bits of SControl register, |
2241 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
2242 | * |
2243 | * LOCKING: | |
624d5c51 TH |
2244 | * Kernel thread context (may sleep) |
2245 | * | |
2246 | * RETURNS: | |
2247 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2248 | */ |
9363c382 | 2249 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 2250 | unsigned long deadline) |
6d97dbd7 | 2251 | { |
9dadd45b TH |
2252 | struct ata_eh_context *ehc = &link->eh_context; |
2253 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
2254 | bool online; | |
624d5c51 TH |
2255 | int rc; |
2256 | ||
9dadd45b TH |
2257 | rc = sata_link_hardreset(link, timing, deadline, &online, |
2258 | ata_sff_check_ready); | |
9dadd45b TH |
2259 | if (online) |
2260 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 TH |
2261 | |
2262 | DPRINTK("EXIT, class=%u\n", *class); | |
9dadd45b | 2263 | return rc; |
6d97dbd7 | 2264 | } |
0fe40ff8 | 2265 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); |
6d97dbd7 | 2266 | |
203c75b8 TH |
2267 | /** |
2268 | * ata_sff_postreset - SFF postreset callback | |
2269 | * @link: the target SFF ata_link | |
2270 | * @classes: classes of attached devices | |
2271 | * | |
2272 | * This function is invoked after a successful reset. It first | |
2273 | * calls ata_std_postreset() and performs SFF specific postreset | |
2274 | * processing. | |
2275 | * | |
2276 | * LOCKING: | |
2277 | * Kernel thread context (may sleep) | |
2278 | */ | |
2279 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
2280 | { | |
2281 | struct ata_port *ap = link->ap; | |
2282 | ||
2283 | ata_std_postreset(link, classes); | |
2284 | ||
2285 | /* is double-select really necessary? */ | |
2286 | if (classes[0] != ATA_DEV_NONE) | |
2287 | ap->ops->sff_dev_select(ap, 1); | |
2288 | if (classes[1] != ATA_DEV_NONE) | |
2289 | ap->ops->sff_dev_select(ap, 0); | |
2290 | ||
2291 | /* bail out if no device is present */ | |
2292 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
2293 | DPRINTK("EXIT, no device\n"); | |
2294 | return; | |
2295 | } | |
2296 | ||
2297 | /* set up device control */ | |
41dec29b SS |
2298 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) { |
2299 | ata_sff_set_devctl(ap, ap->ctl); | |
e3e4385f SM |
2300 | ap->last_ctl = ap->ctl; |
2301 | } | |
203c75b8 | 2302 | } |
0fe40ff8 | 2303 | EXPORT_SYMBOL_GPL(ata_sff_postreset); |
203c75b8 | 2304 | |
3d47aa8e AC |
2305 | /** |
2306 | * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers | |
2307 | * @qc: command | |
2308 | * | |
2309 | * Drain the FIFO and device of any stuck data following a command | |
3ad2f3fb | 2310 | * failing to complete. In some cases this is necessary before a |
3d47aa8e AC |
2311 | * reset will recover the device. |
2312 | * | |
2313 | */ | |
2314 | ||
2315 | void ata_sff_drain_fifo(struct ata_queued_cmd *qc) | |
2316 | { | |
2317 | int count; | |
2318 | struct ata_port *ap; | |
2319 | ||
2320 | /* We only need to flush incoming data when a command was running */ | |
2321 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) | |
2322 | return; | |
2323 | ||
2324 | ap = qc->ap; | |
2325 | /* Drain up to 64K of data before we give up this recovery method */ | |
2326 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) | |
9a8fd68b | 2327 | && count < 65536; count += 2) |
3d47aa8e AC |
2328 | ioread16(ap->ioaddr.data_addr); |
2329 | ||
2330 | /* Can become DEBUG later */ | |
2331 | if (count) | |
2332 | ata_port_printk(ap, KERN_DEBUG, | |
2333 | "drained %d bytes to clear DRQ.\n", count); | |
2334 | ||
2335 | } | |
2336 | EXPORT_SYMBOL_GPL(ata_sff_drain_fifo); | |
2337 | ||
6d97dbd7 | 2338 | /** |
9363c382 | 2339 | * ata_sff_error_handler - Stock error handler for BMDMA controller |
6d97dbd7 | 2340 | * @ap: port to handle error for |
6d97dbd7 | 2341 | * |
9363c382 | 2342 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2343 | * PATA and SATA controllers. Many controllers should be able to |
2344 | * use this EH as-is or with some added handling before and | |
2345 | * after. | |
2346 | * | |
6d97dbd7 TH |
2347 | * LOCKING: |
2348 | * Kernel thread context (may sleep) | |
2349 | */ | |
9363c382 | 2350 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2351 | { |
a1efdaba TH |
2352 | ata_reset_fn_t softreset = ap->ops->softreset; |
2353 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2354 | struct ata_queued_cmd *qc; |
2355 | unsigned long flags; | |
2a7adff0 | 2356 | bool thaw = false; |
6d97dbd7 | 2357 | |
9af5c9c9 | 2358 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2359 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2360 | qc = NULL; | |
2361 | ||
2362 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 2363 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2364 | |
6d97dbd7 TH |
2365 | ap->hsm_task_state = HSM_ST_IDLE; |
2366 | ||
ed82f964 TH |
2367 | if (ap->ioaddr.bmdma_addr && |
2368 | qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 2369 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
2370 | u8 host_stat; |
2371 | ||
fbbb262d | 2372 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 2373 | |
6d97dbd7 TH |
2374 | /* BMDMA controllers indicate host bus error by |
2375 | * setting DMA_ERR bit and timing out. As it wasn't | |
2376 | * really a timeout event, adjust error mask and | |
2377 | * cancel frozen state. | |
2378 | */ | |
3d47aa8e AC |
2379 | if (qc->err_mask == AC_ERR_TIMEOUT |
2380 | && (host_stat & ATA_DMA_ERR)) { | |
6d97dbd7 | 2381 | qc->err_mask = AC_ERR_HOST_BUS; |
2a7adff0 | 2382 | thaw = true; |
6d97dbd7 TH |
2383 | } |
2384 | ||
2385 | ap->ops->bmdma_stop(qc); | |
2a7adff0 TH |
2386 | |
2387 | /* if we're gonna thaw, make sure IRQ is clear */ | |
2388 | if (thaw) { | |
2389 | ap->ops->sff_check_status(ap); | |
2390 | ap->ops->sff_irq_clear(ap); | |
2391 | ||
2392 | spin_unlock_irqrestore(ap->lock, flags); | |
2393 | ata_eh_thaw_port(ap); | |
2394 | spin_lock_irqsave(ap->lock, flags); | |
2395 | } | |
6d97dbd7 TH |
2396 | } |
2397 | ||
3d47aa8e AC |
2398 | /* We *MUST* do FIFO draining before we issue a reset as several |
2399 | * devices helpfully clear their internal state and will lock solid | |
2400 | * if we touch the data port post reset. Pass qc in case anyone wants | |
2401 | * to do different PIO/DMA recovery or has per command fixups | |
2402 | */ | |
2403 | if (ap->ops->drain_fifo) | |
2404 | ap->ops->drain_fifo(qc); | |
6d97dbd7 | 2405 | |
ba6a1308 | 2406 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 | 2407 | |
6d97dbd7 | 2408 | /* PIO and DMA engines have been stopped, perform recovery */ |
6d97dbd7 | 2409 | |
57c9efdf TH |
2410 | /* Ignore ata_sff_softreset if ctl isn't accessible and |
2411 | * built-in hardresets if SCR access isn't available. | |
a1efdaba | 2412 | */ |
9363c382 | 2413 | if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) |
a1efdaba | 2414 | softreset = NULL; |
57c9efdf | 2415 | if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link)) |
a1efdaba | 2416 | hardreset = NULL; |
6d97dbd7 | 2417 | |
a1efdaba TH |
2418 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2419 | ap->ops->postreset); | |
6d97dbd7 | 2420 | } |
0fe40ff8 | 2421 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); |
6d97dbd7 TH |
2422 | |
2423 | /** | |
9363c382 | 2424 | * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller |
6d97dbd7 TH |
2425 | * @qc: internal command to clean up |
2426 | * | |
2427 | * LOCKING: | |
2428 | * Kernel thread context (may sleep) | |
2429 | */ | |
9363c382 | 2430 | void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc) |
6d97dbd7 | 2431 | { |
570106df TH |
2432 | struct ata_port *ap = qc->ap; |
2433 | unsigned long flags; | |
2434 | ||
2435 | spin_lock_irqsave(ap->lock, flags); | |
2436 | ||
2437 | ap->hsm_task_state = HSM_ST_IDLE; | |
2438 | ||
2439 | if (ap->ioaddr.bmdma_addr) | |
294264a9 | 2440 | ap->ops->bmdma_stop(qc); |
570106df TH |
2441 | |
2442 | spin_unlock_irqrestore(ap->lock, flags); | |
6d97dbd7 | 2443 | } |
0fe40ff8 | 2444 | EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd); |
6d97dbd7 | 2445 | |
d92e74d3 AC |
2446 | /** |
2447 | * ata_sff_port_start - Set port up for dma. | |
2448 | * @ap: Port to initialize | |
2449 | * | |
2450 | * Called just after data structures for each port are | |
2451 | * initialized. Allocates space for PRD table if the device | |
2452 | * is DMA capable SFF. | |
2453 | * | |
2454 | * May be used as the port_start() entry in ata_port_operations. | |
2455 | * | |
2456 | * LOCKING: | |
2457 | * Inherited from caller. | |
2458 | */ | |
d92e74d3 AC |
2459 | int ata_sff_port_start(struct ata_port *ap) |
2460 | { | |
2461 | if (ap->ioaddr.bmdma_addr) | |
2462 | return ata_port_start(ap); | |
2463 | return 0; | |
2464 | } | |
0fe40ff8 | 2465 | EXPORT_SYMBOL_GPL(ata_sff_port_start); |
d92e74d3 | 2466 | |
e3cf95dd AC |
2467 | /** |
2468 | * ata_sff_port_start32 - Set port up for dma. | |
2469 | * @ap: Port to initialize | |
2470 | * | |
2471 | * Called just after data structures for each port are | |
2472 | * initialized. Allocates space for PRD table if the device | |
2473 | * is DMA capable SFF. | |
2474 | * | |
2475 | * May be used as the port_start() entry in ata_port_operations for | |
2476 | * devices that are capable of 32bit PIO. | |
2477 | * | |
2478 | * LOCKING: | |
2479 | * Inherited from caller. | |
2480 | */ | |
2481 | int ata_sff_port_start32(struct ata_port *ap) | |
2482 | { | |
2483 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; | |
2484 | if (ap->ioaddr.bmdma_addr) | |
2485 | return ata_port_start(ap); | |
2486 | return 0; | |
2487 | } | |
2488 | EXPORT_SYMBOL_GPL(ata_sff_port_start32); | |
2489 | ||
624d5c51 | 2490 | /** |
9363c382 | 2491 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2492 | * @ioaddr: IO address structure to be initialized |
2493 | * | |
2494 | * Utility function which initializes data_addr, error_addr, | |
2495 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2496 | * device_addr, status_addr, and command_addr to standard offsets | |
2497 | * relative to cmd_addr. | |
2498 | * | |
2499 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2500 | */ | |
9363c382 | 2501 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2502 | { |
2503 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2504 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2505 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2506 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2507 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2508 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2509 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2510 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2511 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2512 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2513 | } | |
0fe40ff8 | 2514 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
624d5c51 | 2515 | |
1fdffbce | 2516 | #ifdef CONFIG_PCI |
4112e16a | 2517 | |
272f7884 TH |
2518 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2519 | { | |
2520 | int i; | |
2521 | ||
2522 | /* Check the PCI resources for this channel are enabled */ | |
2523 | port = port * 2; | |
0fe40ff8 | 2524 | for (i = 0; i < 2; i++) { |
272f7884 TH |
2525 | if (pci_resource_start(pdev, port + i) == 0 || |
2526 | pci_resource_len(pdev, port + i) == 0) | |
2527 | return 0; | |
2528 | } | |
2529 | return 1; | |
2530 | } | |
2531 | ||
d491b27b | 2532 | /** |
9363c382 | 2533 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2534 | * @host: target ATA host |
d491b27b | 2535 | * |
1626aeb8 TH |
2536 | * Acquire native PCI ATA resources for @host and initialize the |
2537 | * first two ports of @host accordingly. Ports marked dummy are | |
2538 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2539 | * |
d583bc18 TH |
2540 | * Note that native PCI resources are valid even for legacy hosts |
2541 | * as we fix up pdev resources array early in boot, so this | |
2542 | * function can be used for both native and legacy SFF hosts. | |
2543 | * | |
d491b27b TH |
2544 | * LOCKING: |
2545 | * Inherited from calling layer (may sleep). | |
2546 | * | |
2547 | * RETURNS: | |
1626aeb8 TH |
2548 | * 0 if at least one port is initialized, -ENODEV if no port is |
2549 | * available. | |
d491b27b | 2550 | */ |
9363c382 | 2551 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2552 | { |
2553 | struct device *gdev = host->dev; | |
2554 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2555 | unsigned int mask = 0; |
d491b27b TH |
2556 | int i, rc; |
2557 | ||
d491b27b TH |
2558 | /* request, iomap BARs and init port addresses accordingly */ |
2559 | for (i = 0; i < 2; i++) { | |
2560 | struct ata_port *ap = host->ports[i]; | |
2561 | int base = i * 2; | |
2562 | void __iomem * const *iomap; | |
2563 | ||
1626aeb8 TH |
2564 | if (ata_port_is_dummy(ap)) |
2565 | continue; | |
2566 | ||
2567 | /* Discard disabled ports. Some controllers show | |
2568 | * their unused channels this way. Disabled ports are | |
2569 | * made dummy. | |
2570 | */ | |
2571 | if (!ata_resources_present(pdev, i)) { | |
2572 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2573 | continue; |
1626aeb8 | 2574 | } |
d491b27b | 2575 | |
35a10a80 TH |
2576 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2577 | dev_driver_string(gdev)); | |
d491b27b | 2578 | if (rc) { |
1626aeb8 TH |
2579 | dev_printk(KERN_WARNING, gdev, |
2580 | "failed to request/iomap BARs for port %d " | |
2581 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
2582 | if (rc == -EBUSY) |
2583 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2584 | ap->ops = &ata_dummy_port_ops; |
2585 | continue; | |
d491b27b TH |
2586 | } |
2587 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2588 | ||
2589 | ap->ioaddr.cmd_addr = iomap[base]; | |
2590 | ap->ioaddr.altstatus_addr = | |
2591 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2592 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2593 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2594 | |
cbcdd875 TH |
2595 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2596 | (unsigned long long)pci_resource_start(pdev, base), | |
2597 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2598 | ||
1626aeb8 TH |
2599 | mask |= 1 << i; |
2600 | } | |
2601 | ||
2602 | if (!mask) { | |
2603 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
2604 | return -ENODEV; | |
d491b27b TH |
2605 | } |
2606 | ||
2607 | return 0; | |
2608 | } | |
0fe40ff8 | 2609 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); |
d491b27b | 2610 | |
21b0ad4f | 2611 | /** |
9363c382 | 2612 | * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host |
21b0ad4f | 2613 | * @pdev: target PCI device |
1626aeb8 | 2614 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2615 | * @r_host: out argument for the initialized ATA host |
2616 | * | |
2617 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
2618 | * resources and initialize it accordingly in one go. | |
2619 | * | |
2620 | * LOCKING: | |
2621 | * Inherited from calling layer (may sleep). | |
2622 | * | |
2623 | * RETURNS: | |
2624 | * 0 on success, -errno otherwise. | |
2625 | */ | |
9363c382 | 2626 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
0fe40ff8 | 2627 | const struct ata_port_info * const *ppi, |
d583bc18 | 2628 | struct ata_host **r_host) |
21b0ad4f TH |
2629 | { |
2630 | struct ata_host *host; | |
21b0ad4f TH |
2631 | int rc; |
2632 | ||
2633 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2634 | return -ENOMEM; | |
2635 | ||
2636 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2637 | if (!host) { | |
2638 | dev_printk(KERN_ERR, &pdev->dev, | |
2639 | "failed to allocate ATA host\n"); | |
2640 | rc = -ENOMEM; | |
2641 | goto err_out; | |
2642 | } | |
2643 | ||
9363c382 | 2644 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2645 | if (rc) |
2646 | goto err_out; | |
2647 | ||
2648 | /* init DMA related stuff */ | |
9363c382 | 2649 | rc = ata_pci_bmdma_init(host); |
21b0ad4f TH |
2650 | if (rc) |
2651 | goto err_bmdma; | |
2652 | ||
2653 | devres_remove_group(&pdev->dev, NULL); | |
2654 | *r_host = host; | |
2655 | return 0; | |
2656 | ||
0fe40ff8 | 2657 | err_bmdma: |
21b0ad4f TH |
2658 | /* This is necessary because PCI and iomap resources are |
2659 | * merged and releasing the top group won't release the | |
2660 | * acquired resources if some of those have been acquired | |
2661 | * before entering this function. | |
2662 | */ | |
2663 | pcim_iounmap_regions(pdev, 0xf); | |
0fe40ff8 | 2664 | err_out: |
21b0ad4f TH |
2665 | devres_release_group(&pdev->dev, NULL); |
2666 | return rc; | |
2667 | } | |
0fe40ff8 | 2668 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); |
21b0ad4f | 2669 | |
4e6b79fa | 2670 | /** |
9363c382 | 2671 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2672 | * @host: target SFF ATA host |
2673 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2674 | * @sht: scsi_host_template to use when registering the host | |
2675 | * | |
2676 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2677 | * hosts. This separate helper is necessary because SFF hosts | |
2678 | * use two separate interrupts in legacy mode. | |
2679 | * | |
2680 | * LOCKING: | |
2681 | * Inherited from calling layer (may sleep). | |
2682 | * | |
2683 | * RETURNS: | |
2684 | * 0 on success, -errno otherwise. | |
2685 | */ | |
9363c382 | 2686 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2687 | irq_handler_t irq_handler, |
2688 | struct scsi_host_template *sht) | |
2689 | { | |
2690 | struct device *dev = host->dev; | |
2691 | struct pci_dev *pdev = to_pci_dev(dev); | |
2692 | const char *drv_name = dev_driver_string(host->dev); | |
2693 | int legacy_mode = 0, rc; | |
2694 | ||
2695 | rc = ata_host_start(host); | |
2696 | if (rc) | |
2697 | return rc; | |
2698 | ||
2699 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
2700 | u8 tmp8, mask; | |
2701 | ||
2702 | /* TODO: What if one channel is in native mode ... */ | |
2703 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
2704 | mask = (1 << 2) | (1 << 0); | |
2705 | if ((tmp8 & mask) != mask) | |
2706 | legacy_mode = 1; | |
2707 | #if defined(CONFIG_NO_ATA_LEGACY) | |
2708 | /* Some platforms with PCI limits cannot address compat | |
2709 | port space. In that case we punt if their firmware has | |
2710 | left a device in compatibility mode */ | |
2711 | if (legacy_mode) { | |
2712 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
2713 | return -EOPNOTSUPP; | |
2714 | } | |
2715 | #endif | |
2716 | } | |
2717 | ||
2718 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2719 | return -ENOMEM; | |
2720 | ||
2721 | if (!legacy_mode && pdev->irq) { | |
2722 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
2723 | IRQF_SHARED, drv_name, host); | |
2724 | if (rc) | |
2725 | goto out; | |
2726 | ||
2727 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
2728 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
2729 | } else if (legacy_mode) { | |
2730 | if (!ata_port_is_dummy(host->ports[0])) { | |
2731 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2732 | irq_handler, IRQF_SHARED, | |
2733 | drv_name, host); | |
2734 | if (rc) | |
2735 | goto out; | |
2736 | ||
2737 | ata_port_desc(host->ports[0], "irq %d", | |
2738 | ATA_PRIMARY_IRQ(pdev)); | |
2739 | } | |
2740 | ||
2741 | if (!ata_port_is_dummy(host->ports[1])) { | |
2742 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2743 | irq_handler, IRQF_SHARED, | |
2744 | drv_name, host); | |
2745 | if (rc) | |
2746 | goto out; | |
2747 | ||
2748 | ata_port_desc(host->ports[1], "irq %d", | |
2749 | ATA_SECONDARY_IRQ(pdev)); | |
2750 | } | |
2751 | } | |
2752 | ||
2753 | rc = ata_host_register(host, sht); | |
0fe40ff8 | 2754 | out: |
4e6b79fa TH |
2755 | if (rc == 0) |
2756 | devres_remove_group(dev, NULL); | |
2757 | else | |
2758 | devres_release_group(dev, NULL); | |
2759 | ||
2760 | return rc; | |
2761 | } | |
0fe40ff8 | 2762 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); |
4e6b79fa | 2763 | |
1fdffbce | 2764 | /** |
9363c382 | 2765 | * ata_pci_sff_init_one - Initialize/register PCI IDE host controller |
1fdffbce | 2766 | * @pdev: Controller to be initialized |
1626aeb8 | 2767 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 2768 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 2769 | * @host_priv: host private_data |
16ea0fc9 | 2770 | * @hflag: host flags |
1fdffbce JG |
2771 | * |
2772 | * This is a helper function which can be called from a driver's | |
2773 | * xxx_init_one() probe function if the hardware uses traditional | |
2774 | * IDE taskfile registers. | |
2775 | * | |
2776 | * This function calls pci_enable_device(), reserves its register | |
2777 | * regions, sets the dma mask, enables bus master mode, and calls | |
2778 | * ata_device_add() | |
2779 | * | |
2ec7df04 AC |
2780 | * ASSUMPTION: |
2781 | * Nobody makes a single channel controller that appears solely as | |
2782 | * the secondary legacy port on PCI. | |
2783 | * | |
1fdffbce JG |
2784 | * LOCKING: |
2785 | * Inherited from PCI layer (may sleep). | |
2786 | * | |
2787 | * RETURNS: | |
2788 | * Zero on success, negative on errno-based value on error. | |
2789 | */ | |
9363c382 | 2790 | int ata_pci_sff_init_one(struct pci_dev *pdev, |
16ea0fc9 AC |
2791 | const struct ata_port_info * const *ppi, |
2792 | struct scsi_host_template *sht, void *host_priv, int hflag) | |
1fdffbce | 2793 | { |
f0d36efd | 2794 | struct device *dev = &pdev->dev; |
1626aeb8 | 2795 | const struct ata_port_info *pi = NULL; |
0f834de3 | 2796 | struct ata_host *host = NULL; |
1626aeb8 | 2797 | int i, rc; |
1fdffbce JG |
2798 | |
2799 | DPRINTK("ENTER\n"); | |
2800 | ||
1626aeb8 TH |
2801 | /* look up the first valid port_info */ |
2802 | for (i = 0; i < 2 && ppi[i]; i++) { | |
2803 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
2804 | pi = ppi[i]; | |
2805 | break; | |
2806 | } | |
2807 | } | |
f0d36efd | 2808 | |
1626aeb8 TH |
2809 | if (!pi) { |
2810 | dev_printk(KERN_ERR, &pdev->dev, | |
2811 | "no valid port_info specified\n"); | |
2812 | return -EINVAL; | |
2813 | } | |
c791c306 | 2814 | |
1626aeb8 TH |
2815 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2816 | return -ENOMEM; | |
1fdffbce | 2817 | |
f0d36efd | 2818 | rc = pcim_enable_device(pdev); |
1fdffbce | 2819 | if (rc) |
4e6b79fa | 2820 | goto out; |
1fdffbce | 2821 | |
4e6b79fa | 2822 | /* prepare and activate SFF host */ |
9363c382 | 2823 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
d583bc18 | 2824 | if (rc) |
4e6b79fa | 2825 | goto out; |
887125e3 | 2826 | host->private_data = host_priv; |
16ea0fc9 | 2827 | host->flags |= hflag; |
d491b27b | 2828 | |
d491b27b | 2829 | pci_set_master(pdev); |
9363c382 | 2830 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
0fe40ff8 | 2831 | out: |
4e6b79fa TH |
2832 | if (rc == 0) |
2833 | devres_remove_group(&pdev->dev, NULL); | |
2834 | else | |
2835 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2836 | |
1fdffbce JG |
2837 | return rc; |
2838 | } | |
0fe40ff8 | 2839 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); |
1fdffbce JG |
2840 | |
2841 | #endif /* CONFIG_PCI */ | |
9f2f7210 TH |
2842 | |
2843 | const struct ata_port_operations ata_bmdma_port_ops = { | |
2844 | .inherits = &ata_sff_port_ops, | |
2845 | ||
2846 | .mode_filter = ata_bmdma_mode_filter, | |
2847 | ||
2848 | .bmdma_setup = ata_bmdma_setup, | |
2849 | .bmdma_start = ata_bmdma_start, | |
2850 | .bmdma_stop = ata_bmdma_stop, | |
2851 | .bmdma_status = ata_bmdma_status, | |
2852 | }; | |
2853 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); | |
2854 | ||
2855 | const struct ata_port_operations ata_bmdma32_port_ops = { | |
2856 | .inherits = &ata_bmdma_port_ops, | |
2857 | ||
2858 | .sff_data_xfer = ata_sff_data_xfer32, | |
2859 | .port_start = ata_sff_port_start32, | |
2860 | }; | |
2861 | EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops); | |
2862 | ||
2863 | unsigned long ata_bmdma_mode_filter(struct ata_device *adev, | |
2864 | unsigned long xfer_mask) | |
2865 | { | |
2866 | /* Filter out DMA modes if the device has been configured by | |
2867 | the BIOS as PIO only */ | |
2868 | ||
2869 | if (adev->link->ap->ioaddr.bmdma_addr == NULL) | |
2870 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
2871 | return xfer_mask; | |
2872 | } | |
2873 | EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter); | |
2874 | ||
2875 | /** | |
2876 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2877 | * @qc: Info associated with this ATA transaction. | |
2878 | * | |
2879 | * LOCKING: | |
2880 | * spin_lock_irqsave(host lock) | |
2881 | */ | |
2882 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2883 | { | |
2884 | struct ata_port *ap = qc->ap; | |
2885 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2886 | u8 dmactl; | |
2887 | ||
2888 | /* load PRD table addr. */ | |
2889 | mb(); /* make sure PRD table writes are visible to controller */ | |
2890 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | |
2891 | ||
2892 | /* specify data direction, triple-check start bit is clear */ | |
2893 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2894 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2895 | if (!rw) | |
2896 | dmactl |= ATA_DMA_WR; | |
2897 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2898 | ||
2899 | /* issue r/w command */ | |
2900 | ap->ops->sff_exec_command(ap, &qc->tf); | |
2901 | } | |
2902 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); | |
2903 | ||
2904 | /** | |
2905 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2906 | * @qc: Info associated with this ATA transaction. | |
2907 | * | |
2908 | * LOCKING: | |
2909 | * spin_lock_irqsave(host lock) | |
2910 | */ | |
2911 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2912 | { | |
2913 | struct ata_port *ap = qc->ap; | |
2914 | u8 dmactl; | |
2915 | ||
2916 | /* start host DMA transaction */ | |
2917 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2918 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2919 | ||
2920 | /* Strictly, one may wish to issue an ioread8() here, to | |
2921 | * flush the mmio write. However, control also passes | |
2922 | * to the hardware at this point, and it will interrupt | |
2923 | * us when we are to resume control. So, in effect, | |
2924 | * we don't care when the mmio write flushes. | |
2925 | * Further, a read of the DMA status register _immediately_ | |
2926 | * following the write may not be what certain flaky hardware | |
2927 | * is expected, so I think it is best to not add a readb() | |
2928 | * without first all the MMIO ATA cards/mobos. | |
2929 | * Or maybe I'm just being paranoid. | |
2930 | * | |
2931 | * FIXME: The posting of this write means I/O starts are | |
2932 | * unneccessarily delayed for MMIO | |
2933 | */ | |
2934 | } | |
2935 | EXPORT_SYMBOL_GPL(ata_bmdma_start); | |
2936 | ||
2937 | /** | |
2938 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
2939 | * @qc: Command we are ending DMA for | |
2940 | * | |
2941 | * Clears the ATA_DMA_START flag in the dma control register | |
2942 | * | |
2943 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
2944 | * | |
2945 | * LOCKING: | |
2946 | * spin_lock_irqsave(host lock) | |
2947 | */ | |
2948 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
2949 | { | |
2950 | struct ata_port *ap = qc->ap; | |
2951 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2952 | ||
2953 | /* clear start/stop bit */ | |
2954 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
2955 | mmio + ATA_DMA_CMD); | |
2956 | ||
2957 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
2958 | ata_sff_dma_pause(ap); | |
2959 | } | |
2960 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); | |
2961 | ||
2962 | /** | |
2963 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
2964 | * @ap: Port associated with this ATA transaction. | |
2965 | * | |
2966 | * Read and return BMDMA status register. | |
2967 | * | |
2968 | * May be used as the bmdma_status() entry in ata_port_operations. | |
2969 | * | |
2970 | * LOCKING: | |
2971 | * spin_lock_irqsave(host lock) | |
2972 | */ | |
2973 | u8 ata_bmdma_status(struct ata_port *ap) | |
2974 | { | |
2975 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
2976 | } | |
2977 | EXPORT_SYMBOL_GPL(ata_bmdma_status); | |
2978 | ||
2979 | #ifdef CONFIG_PCI | |
2980 | ||
2981 | /** | |
2982 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex | |
2983 | * @pdev: PCI device | |
2984 | * | |
2985 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2986 | * enter non simplex mode. This implements the necessary logic to | |
2987 | * perform the task on such devices. Calling it on other devices will | |
2988 | * have -undefined- behaviour. | |
2989 | */ | |
2990 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) | |
2991 | { | |
2992 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
2993 | u8 simplex; | |
2994 | ||
2995 | if (bmdma == 0) | |
2996 | return -ENOENT; | |
2997 | ||
2998 | simplex = inb(bmdma + 0x02); | |
2999 | outb(simplex & 0x60, bmdma + 0x02); | |
3000 | simplex = inb(bmdma + 0x02); | |
3001 | if (simplex & 0x80) | |
3002 | return -EOPNOTSUPP; | |
3003 | return 0; | |
3004 | } | |
3005 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); | |
3006 | ||
3007 | /** | |
3008 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host | |
3009 | * @host: target ATA host | |
3010 | * | |
3011 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
3012 | * | |
3013 | * LOCKING: | |
3014 | * Inherited from calling layer (may sleep). | |
3015 | * | |
3016 | * RETURNS: | |
3017 | * 0 on success, -errno otherwise. | |
3018 | */ | |
3019 | int ata_pci_bmdma_init(struct ata_host *host) | |
3020 | { | |
3021 | struct device *gdev = host->dev; | |
3022 | struct pci_dev *pdev = to_pci_dev(gdev); | |
3023 | int i, rc; | |
3024 | ||
3025 | /* No BAR4 allocation: No DMA */ | |
3026 | if (pci_resource_start(pdev, 4) == 0) | |
3027 | return 0; | |
3028 | ||
3029 | /* TODO: If we get no DMA mask we should fall back to PIO */ | |
3030 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
3031 | if (rc) | |
3032 | return rc; | |
3033 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
3034 | if (rc) | |
3035 | return rc; | |
3036 | ||
3037 | /* request and iomap DMA region */ | |
3038 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); | |
3039 | if (rc) { | |
3040 | dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); | |
3041 | return -ENOMEM; | |
3042 | } | |
3043 | host->iomap = pcim_iomap_table(pdev); | |
3044 | ||
3045 | for (i = 0; i < 2; i++) { | |
3046 | struct ata_port *ap = host->ports[i]; | |
3047 | void __iomem *bmdma = host->iomap[4] + 8 * i; | |
3048 | ||
3049 | if (ata_port_is_dummy(ap)) | |
3050 | continue; | |
3051 | ||
3052 | ap->ioaddr.bmdma_addr = bmdma; | |
3053 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && | |
3054 | (ioread8(bmdma + 2) & 0x80)) | |
3055 | host->flags |= ATA_HOST_SIMPLEX; | |
3056 | ||
3057 | ata_port_desc(ap, "bmdma 0x%llx", | |
3058 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
3059 | } | |
3060 | ||
3061 | return 0; | |
3062 | } | |
3063 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); | |
3064 | ||
3065 | #endif /* CONFIG_PCI */ |