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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
624d5c51 | 38 | #include <linux/highmem.h> |
1fdffbce JG |
39 | |
40 | #include "libata.h" | |
41 | ||
624d5c51 TH |
42 | const struct ata_port_operations ata_sff_port_ops = { |
43 | .inherits = &ata_base_port_ops, | |
44 | ||
9363c382 TH |
45 | .qc_prep = ata_sff_qc_prep, |
46 | .qc_issue = ata_sff_qc_issue, | |
47 | ||
48 | .freeze = ata_sff_freeze, | |
49 | .thaw = ata_sff_thaw, | |
0aa1113d | 50 | .prereset = ata_sff_prereset, |
9363c382 | 51 | .softreset = ata_sff_softreset, |
203c75b8 | 52 | .postreset = ata_sff_postreset, |
9363c382 TH |
53 | .error_handler = ata_sff_error_handler, |
54 | .post_internal_cmd = ata_sff_post_internal_cmd, | |
55 | ||
5682ed33 TH |
56 | .sff_dev_select = ata_sff_dev_select, |
57 | .sff_check_status = ata_sff_check_status, | |
58 | .sff_tf_load = ata_sff_tf_load, | |
59 | .sff_tf_read = ata_sff_tf_read, | |
60 | .sff_exec_command = ata_sff_exec_command, | |
61 | .sff_data_xfer = ata_sff_data_xfer, | |
62 | .sff_irq_on = ata_sff_irq_on, | |
288623a0 | 63 | .sff_irq_clear = ata_sff_irq_clear, |
624d5c51 TH |
64 | |
65 | .port_start = ata_sff_port_start, | |
66 | }; | |
67 | ||
68 | const struct ata_port_operations ata_bmdma_port_ops = { | |
69 | .inherits = &ata_sff_port_ops, | |
70 | ||
9363c382 | 71 | .mode_filter = ata_bmdma_mode_filter, |
624d5c51 TH |
72 | |
73 | .bmdma_setup = ata_bmdma_setup, | |
74 | .bmdma_start = ata_bmdma_start, | |
75 | .bmdma_stop = ata_bmdma_stop, | |
76 | .bmdma_status = ata_bmdma_status, | |
624d5c51 TH |
77 | }; |
78 | ||
79 | /** | |
80 | * ata_fill_sg - Fill PCI IDE PRD table | |
81 | * @qc: Metadata associated with taskfile to be transferred | |
82 | * | |
83 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
84 | * associated with the current disk command. | |
85 | * | |
86 | * LOCKING: | |
87 | * spin_lock_irqsave(host lock) | |
88 | * | |
89 | */ | |
90 | static void ata_fill_sg(struct ata_queued_cmd *qc) | |
91 | { | |
92 | struct ata_port *ap = qc->ap; | |
93 | struct scatterlist *sg; | |
94 | unsigned int si, pi; | |
95 | ||
96 | pi = 0; | |
97 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
98 | u32 addr, offset; | |
99 | u32 sg_len, len; | |
100 | ||
101 | /* determine if physical DMA addr spans 64K boundary. | |
102 | * Note h/w doesn't support 64-bit, so we unconditionally | |
103 | * truncate dma_addr_t to u32. | |
104 | */ | |
105 | addr = (u32) sg_dma_address(sg); | |
106 | sg_len = sg_dma_len(sg); | |
107 | ||
108 | while (sg_len) { | |
109 | offset = addr & 0xffff; | |
110 | len = sg_len; | |
111 | if ((offset + sg_len) > 0x10000) | |
112 | len = 0x10000 - offset; | |
113 | ||
114 | ap->prd[pi].addr = cpu_to_le32(addr); | |
115 | ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
116 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
117 | ||
118 | pi++; | |
119 | sg_len -= len; | |
120 | addr += len; | |
121 | } | |
122 | } | |
123 | ||
124 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
125 | } | |
126 | ||
127 | /** | |
128 | * ata_fill_sg_dumb - Fill PCI IDE PRD table | |
129 | * @qc: Metadata associated with taskfile to be transferred | |
130 | * | |
131 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
132 | * associated with the current disk command. Perform the fill | |
133 | * so that we avoid writing any length 64K records for | |
134 | * controllers that don't follow the spec. | |
135 | * | |
136 | * LOCKING: | |
137 | * spin_lock_irqsave(host lock) | |
138 | * | |
139 | */ | |
140 | static void ata_fill_sg_dumb(struct ata_queued_cmd *qc) | |
141 | { | |
142 | struct ata_port *ap = qc->ap; | |
143 | struct scatterlist *sg; | |
144 | unsigned int si, pi; | |
145 | ||
146 | pi = 0; | |
147 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
148 | u32 addr, offset; | |
149 | u32 sg_len, len, blen; | |
150 | ||
151 | /* determine if physical DMA addr spans 64K boundary. | |
152 | * Note h/w doesn't support 64-bit, so we unconditionally | |
153 | * truncate dma_addr_t to u32. | |
154 | */ | |
155 | addr = (u32) sg_dma_address(sg); | |
156 | sg_len = sg_dma_len(sg); | |
157 | ||
158 | while (sg_len) { | |
159 | offset = addr & 0xffff; | |
160 | len = sg_len; | |
161 | if ((offset + sg_len) > 0x10000) | |
162 | len = 0x10000 - offset; | |
163 | ||
164 | blen = len & 0xffff; | |
165 | ap->prd[pi].addr = cpu_to_le32(addr); | |
166 | if (blen == 0) { | |
167 | /* Some PATA chipsets like the CS5530 can't | |
168 | cope with 0x0000 meaning 64K as the spec says */ | |
169 | ap->prd[pi].flags_len = cpu_to_le32(0x8000); | |
170 | blen = 0x8000; | |
171 | ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000); | |
172 | } | |
173 | ap->prd[pi].flags_len = cpu_to_le32(blen); | |
174 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
175 | ||
176 | pi++; | |
177 | sg_len -= len; | |
178 | addr += len; | |
179 | } | |
180 | } | |
181 | ||
182 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
183 | } | |
184 | ||
185 | /** | |
9363c382 | 186 | * ata_sff_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
187 | * @qc: Metadata associated with taskfile to be prepared |
188 | * | |
189 | * Prepare ATA taskfile for submission. | |
190 | * | |
191 | * LOCKING: | |
192 | * spin_lock_irqsave(host lock) | |
193 | */ | |
9363c382 | 194 | void ata_sff_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
195 | { |
196 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
197 | return; | |
198 | ||
199 | ata_fill_sg(qc); | |
200 | } | |
201 | ||
202 | /** | |
9363c382 | 203 | * ata_sff_dumb_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
204 | * @qc: Metadata associated with taskfile to be prepared |
205 | * | |
206 | * Prepare ATA taskfile for submission. | |
207 | * | |
208 | * LOCKING: | |
209 | * spin_lock_irqsave(host lock) | |
210 | */ | |
9363c382 | 211 | void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
212 | { |
213 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
214 | return; | |
215 | ||
216 | ata_fill_sg_dumb(qc); | |
217 | } | |
218 | ||
272f7884 | 219 | /** |
9363c382 | 220 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
221 | * @ap: port where the device is |
222 | * | |
223 | * Reads ATA taskfile status register for currently-selected device | |
224 | * and return its value. This also clears pending interrupts | |
225 | * from this device | |
226 | * | |
227 | * LOCKING: | |
228 | * Inherited from caller. | |
229 | */ | |
9363c382 | 230 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
231 | { |
232 | return ioread8(ap->ioaddr.status_addr); | |
233 | } | |
234 | ||
235 | /** | |
9363c382 | 236 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
237 | * @ap: port where the device is |
238 | * | |
239 | * Reads ATA taskfile alternate status register for | |
240 | * currently-selected device and return its value. | |
241 | * | |
242 | * Note: may NOT be used as the check_altstatus() entry in | |
243 | * ata_port_operations. | |
244 | * | |
245 | * LOCKING: | |
246 | * Inherited from caller. | |
247 | */ | |
9363c382 | 248 | u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 249 | { |
5682ed33 TH |
250 | if (ap->ops->sff_check_altstatus) |
251 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
252 | |
253 | return ioread8(ap->ioaddr.altstatus_addr); | |
254 | } | |
255 | ||
256 | /** | |
9363c382 | 257 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 TH |
258 | * @ap: port containing status register to be polled |
259 | * @tmout_pat: impatience timeout | |
260 | * @tmout: overall timeout | |
261 | * | |
262 | * Sleep until ATA Status register bit BSY clears, | |
263 | * or a timeout occurs. | |
264 | * | |
265 | * LOCKING: | |
266 | * Kernel thread context (may sleep). | |
267 | * | |
268 | * RETURNS: | |
269 | * 0 on success, -errno otherwise. | |
270 | */ | |
9363c382 TH |
271 | int ata_sff_busy_sleep(struct ata_port *ap, |
272 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
273 | { |
274 | unsigned long timer_start, timeout; | |
275 | u8 status; | |
276 | ||
9363c382 | 277 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 TH |
278 | timer_start = jiffies; |
279 | timeout = timer_start + tmout_pat; | |
280 | while (status != 0xff && (status & ATA_BUSY) && | |
281 | time_before(jiffies, timeout)) { | |
282 | msleep(50); | |
9363c382 | 283 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
284 | } |
285 | ||
286 | if (status != 0xff && (status & ATA_BUSY)) | |
287 | ata_port_printk(ap, KERN_WARNING, | |
288 | "port is slow to respond, please be patient " | |
289 | "(Status 0x%x)\n", status); | |
290 | ||
291 | timeout = timer_start + tmout; | |
292 | while (status != 0xff && (status & ATA_BUSY) && | |
293 | time_before(jiffies, timeout)) { | |
294 | msleep(50); | |
5682ed33 | 295 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
296 | } |
297 | ||
298 | if (status == 0xff) | |
299 | return -ENODEV; | |
300 | ||
301 | if (status & ATA_BUSY) { | |
302 | ata_port_printk(ap, KERN_ERR, "port failed to respond " | |
303 | "(%lu secs, Status 0x%x)\n", | |
304 | tmout / HZ, status); | |
305 | return -EBUSY; | |
306 | } | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
aa2731ad TH |
311 | static int ata_sff_check_ready(struct ata_link *link) |
312 | { | |
313 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
314 | ||
315 | if (!(status & ATA_BUSY)) | |
316 | return 1; | |
317 | if (status == 0xff) | |
318 | return -ENODEV; | |
319 | return 0; | |
320 | } | |
321 | ||
624d5c51 | 322 | /** |
9363c382 | 323 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 324 | * @link: SFF link to wait ready status for |
624d5c51 TH |
325 | * @deadline: deadline jiffies for the operation |
326 | * | |
327 | * Sleep until ATA Status register bit BSY clears, or timeout | |
328 | * occurs. | |
329 | * | |
330 | * LOCKING: | |
331 | * Kernel thread context (may sleep). | |
332 | * | |
333 | * RETURNS: | |
334 | * 0 on success, -errno otherwise. | |
335 | */ | |
705e76be | 336 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 337 | { |
aa2731ad | 338 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 TH |
339 | } |
340 | ||
341 | /** | |
9363c382 | 342 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
343 | * @ap: ATA channel to manipulate |
344 | * @device: ATA device (numbered from zero) to select | |
345 | * | |
346 | * Use the method defined in the ATA specification to | |
347 | * make either device 0, or device 1, active on the | |
348 | * ATA channel. Works with both PIO and MMIO. | |
349 | * | |
350 | * May be used as the dev_select() entry in ata_port_operations. | |
351 | * | |
352 | * LOCKING: | |
353 | * caller. | |
354 | */ | |
9363c382 | 355 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
356 | { |
357 | u8 tmp; | |
358 | ||
359 | if (device == 0) | |
360 | tmp = ATA_DEVICE_OBS; | |
361 | else | |
362 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
363 | ||
364 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 365 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 TH |
366 | } |
367 | ||
368 | /** | |
369 | * ata_dev_select - Select device 0/1 on ATA bus | |
370 | * @ap: ATA channel to manipulate | |
371 | * @device: ATA device (numbered from zero) to select | |
372 | * @wait: non-zero to wait for Status register BSY bit to clear | |
373 | * @can_sleep: non-zero if context allows sleeping | |
374 | * | |
375 | * Use the method defined in the ATA specification to | |
376 | * make either device 0, or device 1, active on the | |
377 | * ATA channel. | |
378 | * | |
9363c382 TH |
379 | * This is a high-level version of ata_sff_dev_select(), which |
380 | * additionally provides the services of inserting the proper | |
381 | * pauses and status polling, where needed. | |
624d5c51 TH |
382 | * |
383 | * LOCKING: | |
384 | * caller. | |
385 | */ | |
386 | void ata_dev_select(struct ata_port *ap, unsigned int device, | |
387 | unsigned int wait, unsigned int can_sleep) | |
388 | { | |
389 | if (ata_msg_probe(ap)) | |
390 | ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, " | |
391 | "device %u, wait %u\n", device, wait); | |
392 | ||
393 | if (wait) | |
394 | ata_wait_idle(ap); | |
395 | ||
5682ed33 | 396 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
397 | |
398 | if (wait) { | |
399 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
400 | msleep(150); | |
401 | ata_wait_idle(ap); | |
402 | } | |
403 | } | |
404 | ||
405 | /** | |
9363c382 | 406 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
407 | * @ap: Port on which interrupts are enabled. |
408 | * | |
409 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
410 | * wait for idle, clear any pending interrupts. | |
411 | * | |
412 | * LOCKING: | |
413 | * Inherited from caller. | |
414 | */ | |
9363c382 | 415 | u8 ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
416 | { |
417 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
418 | u8 tmp; | |
419 | ||
420 | ap->ctl &= ~ATA_NIEN; | |
421 | ap->last_ctl = ap->ctl; | |
422 | ||
423 | if (ioaddr->ctl_addr) | |
424 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
425 | tmp = ata_wait_idle(ap); | |
426 | ||
5682ed33 | 427 | ap->ops->sff_irq_clear(ap); |
624d5c51 TH |
428 | |
429 | return tmp; | |
430 | } | |
431 | ||
432 | /** | |
9363c382 | 433 | * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt. |
624d5c51 TH |
434 | * @ap: Port associated with this ATA transaction. |
435 | * | |
436 | * Clear interrupt and error flags in DMA status register. | |
437 | * | |
438 | * May be used as the irq_clear() entry in ata_port_operations. | |
439 | * | |
440 | * LOCKING: | |
441 | * spin_lock_irqsave(host lock) | |
442 | */ | |
9363c382 | 443 | void ata_sff_irq_clear(struct ata_port *ap) |
624d5c51 TH |
444 | { |
445 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
446 | ||
447 | if (!mmio) | |
448 | return; | |
449 | ||
450 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
451 | } | |
452 | ||
453 | /** | |
9363c382 | 454 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
455 | * @ap: Port to which output is sent |
456 | * @tf: ATA taskfile register set | |
457 | * | |
458 | * Outputs ATA taskfile to standard ATA host controller. | |
459 | * | |
460 | * LOCKING: | |
461 | * Inherited from caller. | |
462 | */ | |
9363c382 | 463 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
464 | { |
465 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
466 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
467 | ||
468 | if (tf->ctl != ap->last_ctl) { | |
469 | if (ioaddr->ctl_addr) | |
470 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
471 | ap->last_ctl = tf->ctl; | |
472 | ata_wait_idle(ap); | |
473 | } | |
474 | ||
475 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
476 | WARN_ON(!ioaddr->ctl_addr); | |
477 | iowrite8(tf->hob_feature, ioaddr->feature_addr); | |
478 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
479 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
480 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
481 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
482 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
483 | tf->hob_feature, | |
484 | tf->hob_nsect, | |
485 | tf->hob_lbal, | |
486 | tf->hob_lbam, | |
487 | tf->hob_lbah); | |
488 | } | |
489 | ||
490 | if (is_addr) { | |
491 | iowrite8(tf->feature, ioaddr->feature_addr); | |
492 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
493 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
494 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
495 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
496 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
497 | tf->feature, | |
498 | tf->nsect, | |
499 | tf->lbal, | |
500 | tf->lbam, | |
501 | tf->lbah); | |
502 | } | |
503 | ||
504 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
505 | iowrite8(tf->device, ioaddr->device_addr); | |
506 | VPRINTK("device 0x%X\n", tf->device); | |
507 | } | |
508 | ||
509 | ata_wait_idle(ap); | |
510 | } | |
511 | ||
512 | /** | |
9363c382 | 513 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
514 | * @ap: Port from which input is read |
515 | * @tf: ATA taskfile register set for storing input | |
516 | * | |
517 | * Reads ATA taskfile registers for currently-selected device | |
518 | * into @tf. Assumes the device has a fully SFF compliant task file | |
519 | * layout and behaviour. If you device does not (eg has a different | |
520 | * status method) then you will need to provide a replacement tf_read | |
521 | * | |
522 | * LOCKING: | |
523 | * Inherited from caller. | |
524 | */ | |
9363c382 | 525 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
526 | { |
527 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
528 | ||
9363c382 | 529 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
530 | tf->feature = ioread8(ioaddr->error_addr); |
531 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
532 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
533 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
534 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
535 | tf->device = ioread8(ioaddr->device_addr); | |
536 | ||
537 | if (tf->flags & ATA_TFLAG_LBA48) { | |
538 | if (likely(ioaddr->ctl_addr)) { | |
539 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
540 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
541 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
542 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
543 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
544 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
545 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
546 | ap->last_ctl = tf->ctl; | |
547 | } else | |
548 | WARN_ON(1); | |
549 | } | |
550 | } | |
551 | ||
552 | /** | |
9363c382 | 553 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
554 | * @ap: port to which command is being issued |
555 | * @tf: ATA taskfile register set | |
556 | * | |
557 | * Issues ATA command, with proper synchronization with interrupt | |
558 | * handler / other threads. | |
559 | * | |
560 | * LOCKING: | |
561 | * spin_lock_irqsave(host lock) | |
562 | */ | |
9363c382 | 563 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
564 | { |
565 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
566 | ||
567 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 568 | ata_sff_pause(ap); |
624d5c51 TH |
569 | } |
570 | ||
571 | /** | |
572 | * ata_tf_to_host - issue ATA taskfile to host controller | |
573 | * @ap: port to which command is being issued | |
574 | * @tf: ATA taskfile register set | |
575 | * | |
576 | * Issues ATA taskfile register set to ATA host controller, | |
577 | * with proper synchronization with interrupt handler and | |
578 | * other threads. | |
579 | * | |
580 | * LOCKING: | |
581 | * spin_lock_irqsave(host lock) | |
582 | */ | |
583 | static inline void ata_tf_to_host(struct ata_port *ap, | |
584 | const struct ata_taskfile *tf) | |
585 | { | |
5682ed33 TH |
586 | ap->ops->sff_tf_load(ap, tf); |
587 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
588 | } |
589 | ||
590 | /** | |
9363c382 | 591 | * ata_sff_data_xfer - Transfer data by PIO |
624d5c51 TH |
592 | * @dev: device to target |
593 | * @buf: data buffer | |
594 | * @buflen: buffer length | |
595 | * @rw: read/write | |
596 | * | |
597 | * Transfer data from/to the device data register by PIO. | |
598 | * | |
599 | * LOCKING: | |
600 | * Inherited from caller. | |
601 | * | |
602 | * RETURNS: | |
603 | * Bytes consumed. | |
604 | */ | |
9363c382 TH |
605 | unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, |
606 | unsigned int buflen, int rw) | |
624d5c51 TH |
607 | { |
608 | struct ata_port *ap = dev->link->ap; | |
609 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
610 | unsigned int words = buflen >> 1; | |
611 | ||
612 | /* Transfer multiple of 2 bytes */ | |
613 | if (rw == READ) | |
614 | ioread16_rep(data_addr, buf, words); | |
615 | else | |
616 | iowrite16_rep(data_addr, buf, words); | |
617 | ||
618 | /* Transfer trailing 1 byte, if any. */ | |
619 | if (unlikely(buflen & 0x01)) { | |
620 | __le16 align_buf[1] = { 0 }; | |
621 | unsigned char *trailing_buf = buf + buflen - 1; | |
622 | ||
623 | if (rw == READ) { | |
624 | align_buf[0] = cpu_to_le16(ioread16(data_addr)); | |
625 | memcpy(trailing_buf, align_buf, 1); | |
626 | } else { | |
627 | memcpy(align_buf, trailing_buf, 1); | |
628 | iowrite16(le16_to_cpu(align_buf[0]), data_addr); | |
629 | } | |
630 | words++; | |
631 | } | |
632 | ||
633 | return words << 1; | |
634 | } | |
635 | ||
636 | /** | |
9363c382 | 637 | * ata_sff_data_xfer_noirq - Transfer data by PIO |
624d5c51 TH |
638 | * @dev: device to target |
639 | * @buf: data buffer | |
640 | * @buflen: buffer length | |
641 | * @rw: read/write | |
642 | * | |
643 | * Transfer data from/to the device data register by PIO. Do the | |
644 | * transfer with interrupts disabled. | |
645 | * | |
646 | * LOCKING: | |
647 | * Inherited from caller. | |
648 | * | |
649 | * RETURNS: | |
650 | * Bytes consumed. | |
651 | */ | |
9363c382 TH |
652 | unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, |
653 | unsigned int buflen, int rw) | |
624d5c51 TH |
654 | { |
655 | unsigned long flags; | |
656 | unsigned int consumed; | |
657 | ||
658 | local_irq_save(flags); | |
9363c382 | 659 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); |
624d5c51 TH |
660 | local_irq_restore(flags); |
661 | ||
662 | return consumed; | |
663 | } | |
664 | ||
665 | /** | |
666 | * ata_pio_sector - Transfer a sector of data. | |
667 | * @qc: Command on going | |
668 | * | |
669 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
670 | * | |
671 | * LOCKING: | |
672 | * Inherited from caller. | |
673 | */ | |
674 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
675 | { | |
676 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
677 | struct ata_port *ap = qc->ap; | |
678 | struct page *page; | |
679 | unsigned int offset; | |
680 | unsigned char *buf; | |
681 | ||
682 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
683 | ap->hsm_task_state = HSM_ST_LAST; | |
684 | ||
685 | page = sg_page(qc->cursg); | |
686 | offset = qc->cursg->offset + qc->cursg_ofs; | |
687 | ||
688 | /* get the current page and offset */ | |
689 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
690 | offset %= PAGE_SIZE; | |
691 | ||
692 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
693 | ||
694 | if (PageHighMem(page)) { | |
695 | unsigned long flags; | |
696 | ||
697 | /* FIXME: use a bounce buffer */ | |
698 | local_irq_save(flags); | |
699 | buf = kmap_atomic(page, KM_IRQ0); | |
700 | ||
701 | /* do the actual data transfer */ | |
5682ed33 TH |
702 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
703 | do_write); | |
624d5c51 TH |
704 | |
705 | kunmap_atomic(buf, KM_IRQ0); | |
706 | local_irq_restore(flags); | |
707 | } else { | |
708 | buf = page_address(page); | |
5682ed33 TH |
709 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
710 | do_write); | |
624d5c51 TH |
711 | } |
712 | ||
713 | qc->curbytes += qc->sect_size; | |
714 | qc->cursg_ofs += qc->sect_size; | |
715 | ||
716 | if (qc->cursg_ofs == qc->cursg->length) { | |
717 | qc->cursg = sg_next(qc->cursg); | |
718 | qc->cursg_ofs = 0; | |
719 | } | |
720 | } | |
721 | ||
722 | /** | |
723 | * ata_pio_sectors - Transfer one or many sectors. | |
724 | * @qc: Command on going | |
725 | * | |
726 | * Transfer one or many sectors of data from/to the | |
727 | * ATA device for the DRQ request. | |
728 | * | |
729 | * LOCKING: | |
730 | * Inherited from caller. | |
731 | */ | |
732 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
733 | { | |
734 | if (is_multi_taskfile(&qc->tf)) { | |
735 | /* READ/WRITE MULTIPLE */ | |
736 | unsigned int nsect; | |
737 | ||
738 | WARN_ON(qc->dev->multi_count == 0); | |
739 | ||
740 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
741 | qc->dev->multi_count); | |
742 | while (nsect--) | |
743 | ata_pio_sector(qc); | |
744 | } else | |
745 | ata_pio_sector(qc); | |
746 | ||
9363c382 | 747 | ata_sff_altstatus(qc->ap); /* flush */ |
624d5c51 TH |
748 | } |
749 | ||
750 | /** | |
751 | * atapi_send_cdb - Write CDB bytes to hardware | |
752 | * @ap: Port to which ATAPI device is attached. | |
753 | * @qc: Taskfile currently active | |
754 | * | |
755 | * When device has indicated its readiness to accept | |
756 | * a CDB, this function is called. Send the CDB. | |
757 | * | |
758 | * LOCKING: | |
759 | * caller. | |
760 | */ | |
761 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
762 | { | |
763 | /* send SCSI cdb */ | |
764 | DPRINTK("send cdb\n"); | |
765 | WARN_ON(qc->dev->cdb_len < 12); | |
766 | ||
5682ed33 | 767 | ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); |
9363c382 | 768 | ata_sff_altstatus(ap); /* flush */ |
624d5c51 TH |
769 | |
770 | switch (qc->tf.protocol) { | |
771 | case ATAPI_PROT_PIO: | |
772 | ap->hsm_task_state = HSM_ST; | |
773 | break; | |
774 | case ATAPI_PROT_NODATA: | |
775 | ap->hsm_task_state = HSM_ST_LAST; | |
776 | break; | |
777 | case ATAPI_PROT_DMA: | |
778 | ap->hsm_task_state = HSM_ST_LAST; | |
779 | /* initiate bmdma */ | |
780 | ap->ops->bmdma_start(qc); | |
781 | break; | |
782 | } | |
783 | } | |
784 | ||
785 | /** | |
786 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
787 | * @qc: Command on going | |
788 | * @bytes: number of bytes | |
789 | * | |
790 | * Transfer Transfer data from/to the ATAPI device. | |
791 | * | |
792 | * LOCKING: | |
793 | * Inherited from caller. | |
794 | * | |
795 | */ | |
796 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
797 | { | |
798 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
799 | struct ata_port *ap = qc->ap; | |
800 | struct ata_device *dev = qc->dev; | |
801 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
802 | struct scatterlist *sg; | |
803 | struct page *page; | |
804 | unsigned char *buf; | |
805 | unsigned int offset, count, consumed; | |
806 | ||
807 | next_sg: | |
808 | sg = qc->cursg; | |
809 | if (unlikely(!sg)) { | |
810 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
811 | "buf=%u cur=%u bytes=%u", | |
812 | qc->nbytes, qc->curbytes, bytes); | |
813 | return -1; | |
814 | } | |
815 | ||
816 | page = sg_page(sg); | |
817 | offset = sg->offset + qc->cursg_ofs; | |
818 | ||
819 | /* get the current page and offset */ | |
820 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
821 | offset %= PAGE_SIZE; | |
822 | ||
823 | /* don't overrun current sg */ | |
824 | count = min(sg->length - qc->cursg_ofs, bytes); | |
825 | ||
826 | /* don't cross page boundaries */ | |
827 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
828 | ||
829 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
830 | ||
831 | if (PageHighMem(page)) { | |
832 | unsigned long flags; | |
833 | ||
834 | /* FIXME: use bounce buffer */ | |
835 | local_irq_save(flags); | |
836 | buf = kmap_atomic(page, KM_IRQ0); | |
837 | ||
838 | /* do the actual data transfer */ | |
5682ed33 | 839 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); |
624d5c51 TH |
840 | |
841 | kunmap_atomic(buf, KM_IRQ0); | |
842 | local_irq_restore(flags); | |
843 | } else { | |
844 | buf = page_address(page); | |
5682ed33 | 845 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); |
624d5c51 TH |
846 | } |
847 | ||
848 | bytes -= min(bytes, consumed); | |
849 | qc->curbytes += count; | |
850 | qc->cursg_ofs += count; | |
851 | ||
852 | if (qc->cursg_ofs == sg->length) { | |
853 | qc->cursg = sg_next(qc->cursg); | |
854 | qc->cursg_ofs = 0; | |
855 | } | |
856 | ||
857 | /* consumed can be larger than count only for the last transfer */ | |
858 | WARN_ON(qc->cursg && count != consumed); | |
859 | ||
860 | if (bytes) | |
861 | goto next_sg; | |
862 | return 0; | |
863 | } | |
864 | ||
865 | /** | |
866 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
867 | * @qc: Command on going | |
868 | * | |
869 | * Transfer Transfer data from/to the ATAPI device. | |
870 | * | |
871 | * LOCKING: | |
872 | * Inherited from caller. | |
873 | */ | |
874 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
875 | { | |
876 | struct ata_port *ap = qc->ap; | |
877 | struct ata_device *dev = qc->dev; | |
878 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
879 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
880 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
881 | ||
882 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
883 | * here to save some kernel stack usage. | |
884 | * For normal completion, qc->result_tf is not relevant. For | |
885 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
886 | * So, the correctness of qc->result_tf is not affected. | |
887 | */ | |
5682ed33 | 888 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
889 | ireason = qc->result_tf.nsect; |
890 | bc_lo = qc->result_tf.lbam; | |
891 | bc_hi = qc->result_tf.lbah; | |
892 | bytes = (bc_hi << 8) | bc_lo; | |
893 | ||
894 | /* shall be cleared to zero, indicating xfer of data */ | |
895 | if (unlikely(ireason & (1 << 0))) | |
896 | goto atapi_check; | |
897 | ||
898 | /* make sure transfer direction matches expected */ | |
899 | i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; | |
900 | if (unlikely(do_write != i_write)) | |
901 | goto atapi_check; | |
902 | ||
903 | if (unlikely(!bytes)) | |
904 | goto atapi_check; | |
905 | ||
906 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
907 | ||
908 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
909 | goto err_out; | |
9363c382 | 910 | ata_sff_altstatus(ap); /* flush */ |
624d5c51 TH |
911 | |
912 | return; | |
913 | ||
914 | atapi_check: | |
915 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
916 | ireason, bytes); | |
917 | err_out: | |
918 | qc->err_mask |= AC_ERR_HSM; | |
919 | ap->hsm_task_state = HSM_ST_ERR; | |
920 | } | |
921 | ||
922 | /** | |
923 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
924 | * @ap: the target ata_port | |
925 | * @qc: qc on going | |
926 | * | |
927 | * RETURNS: | |
928 | * 1 if ok in workqueue, 0 otherwise. | |
929 | */ | |
930 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc) | |
931 | { | |
932 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
933 | return 1; | |
934 | ||
935 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
936 | if (qc->tf.protocol == ATA_PROT_PIO && | |
937 | (qc->tf.flags & ATA_TFLAG_WRITE)) | |
938 | return 1; | |
939 | ||
940 | if (ata_is_atapi(qc->tf.protocol) && | |
941 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
942 | return 1; | |
943 | } | |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
948 | /** | |
949 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
950 | * @qc: Command to complete | |
951 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
952 | * | |
953 | * Finish @qc which is running on standard HSM. | |
954 | * | |
955 | * LOCKING: | |
956 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
957 | * Otherwise, none on entry and grabs host lock. | |
958 | */ | |
959 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
960 | { | |
961 | struct ata_port *ap = qc->ap; | |
962 | unsigned long flags; | |
963 | ||
964 | if (ap->ops->error_handler) { | |
965 | if (in_wq) { | |
966 | spin_lock_irqsave(ap->lock, flags); | |
967 | ||
968 | /* EH might have kicked in while host lock is | |
969 | * released. | |
970 | */ | |
971 | qc = ata_qc_from_tag(ap, qc->tag); | |
972 | if (qc) { | |
973 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
5682ed33 | 974 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
975 | ata_qc_complete(qc); |
976 | } else | |
977 | ata_port_freeze(ap); | |
978 | } | |
979 | ||
980 | spin_unlock_irqrestore(ap->lock, flags); | |
981 | } else { | |
982 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
983 | ata_qc_complete(qc); | |
984 | else | |
985 | ata_port_freeze(ap); | |
986 | } | |
987 | } else { | |
988 | if (in_wq) { | |
989 | spin_lock_irqsave(ap->lock, flags); | |
5682ed33 | 990 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
991 | ata_qc_complete(qc); |
992 | spin_unlock_irqrestore(ap->lock, flags); | |
993 | } else | |
994 | ata_qc_complete(qc); | |
995 | } | |
996 | } | |
997 | ||
998 | /** | |
9363c382 | 999 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
1000 | * @ap: the target ata_port |
1001 | * @qc: qc on going | |
1002 | * @status: current device status | |
1003 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1004 | * | |
1005 | * RETURNS: | |
1006 | * 1 when poll next status needed, 0 otherwise. | |
1007 | */ | |
9363c382 TH |
1008 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
1009 | u8 status, int in_wq) | |
624d5c51 TH |
1010 | { |
1011 | unsigned long flags = 0; | |
1012 | int poll_next; | |
1013 | ||
1014 | WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0); | |
1015 | ||
9363c382 | 1016 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
1017 | * like DMA polling into the workqueue. Notice that |
1018 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
1019 | */ | |
1020 | WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc)); | |
1021 | ||
1022 | fsm_start: | |
1023 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
1024 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
1025 | ||
1026 | switch (ap->hsm_task_state) { | |
1027 | case HSM_ST_FIRST: | |
1028 | /* Send first data block or PACKET CDB */ | |
1029 | ||
1030 | /* If polling, we will stay in the work queue after | |
1031 | * sending the data. Otherwise, interrupt handler | |
1032 | * takes over after sending the data. | |
1033 | */ | |
1034 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
1035 | ||
1036 | /* check device status */ | |
1037 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1038 | /* handle BSY=0, DRQ=0 as error */ | |
1039 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1040 | /* device stops HSM for abort/error */ | |
1041 | qc->err_mask |= AC_ERR_DEV; | |
1042 | else | |
1043 | /* HSM violation. Let EH handle this */ | |
1044 | qc->err_mask |= AC_ERR_HSM; | |
1045 | ||
1046 | ap->hsm_task_state = HSM_ST_ERR; | |
1047 | goto fsm_start; | |
1048 | } | |
1049 | ||
1050 | /* Device should not ask for data transfer (DRQ=1) | |
1051 | * when it finds something wrong. | |
1052 | * We ignore DRQ here and stop the HSM by | |
1053 | * changing hsm_task_state to HSM_ST_ERR and | |
1054 | * let the EH abort the command or reset the device. | |
1055 | */ | |
1056 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1057 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1058 | * when doing the next command (mostly request sense). | |
1059 | * We ignore ERR here to workaround and proceed sending | |
1060 | * the CDB. | |
1061 | */ | |
1062 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
1063 | ata_port_printk(ap, KERN_WARNING, | |
1064 | "DRQ=1 with device error, " | |
1065 | "dev_stat 0x%X\n", status); | |
1066 | qc->err_mask |= AC_ERR_HSM; | |
1067 | ap->hsm_task_state = HSM_ST_ERR; | |
1068 | goto fsm_start; | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | /* Send the CDB (atapi) or the first data block (ata pio out). | |
1073 | * During the state transition, interrupt handler shouldn't | |
1074 | * be invoked before the data transfer is complete and | |
1075 | * hsm_task_state is changed. Hence, the following locking. | |
1076 | */ | |
1077 | if (in_wq) | |
1078 | spin_lock_irqsave(ap->lock, flags); | |
1079 | ||
1080 | if (qc->tf.protocol == ATA_PROT_PIO) { | |
1081 | /* PIO data out protocol. | |
1082 | * send first data block. | |
1083 | */ | |
1084 | ||
1085 | /* ata_pio_sectors() might change the state | |
1086 | * to HSM_ST_LAST. so, the state is changed here | |
1087 | * before ata_pio_sectors(). | |
1088 | */ | |
1089 | ap->hsm_task_state = HSM_ST; | |
1090 | ata_pio_sectors(qc); | |
1091 | } else | |
1092 | /* send CDB */ | |
1093 | atapi_send_cdb(ap, qc); | |
1094 | ||
1095 | if (in_wq) | |
1096 | spin_unlock_irqrestore(ap->lock, flags); | |
1097 | ||
1098 | /* if polling, ata_pio_task() handles the rest. | |
1099 | * otherwise, interrupt handler takes over from here. | |
1100 | */ | |
1101 | break; | |
1102 | ||
1103 | case HSM_ST: | |
1104 | /* complete command or read/write the data register */ | |
1105 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1106 | /* ATAPI PIO protocol */ | |
1107 | if ((status & ATA_DRQ) == 0) { | |
1108 | /* No more data to transfer or device error. | |
1109 | * Device error will be tagged in HSM_ST_LAST. | |
1110 | */ | |
1111 | ap->hsm_task_state = HSM_ST_LAST; | |
1112 | goto fsm_start; | |
1113 | } | |
1114 | ||
1115 | /* Device should not ask for data transfer (DRQ=1) | |
1116 | * when it finds something wrong. | |
1117 | * We ignore DRQ here and stop the HSM by | |
1118 | * changing hsm_task_state to HSM_ST_ERR and | |
1119 | * let the EH abort the command or reset the device. | |
1120 | */ | |
1121 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1122 | ata_port_printk(ap, KERN_WARNING, "DRQ=1 with " | |
1123 | "device error, dev_stat 0x%X\n", | |
1124 | status); | |
1125 | qc->err_mask |= AC_ERR_HSM; | |
1126 | ap->hsm_task_state = HSM_ST_ERR; | |
1127 | goto fsm_start; | |
1128 | } | |
1129 | ||
1130 | atapi_pio_bytes(qc); | |
1131 | ||
1132 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1133 | /* bad ireason reported by device */ | |
1134 | goto fsm_start; | |
1135 | ||
1136 | } else { | |
1137 | /* ATA PIO protocol */ | |
1138 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1139 | /* handle BSY=0, DRQ=0 as error */ | |
1140 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1141 | /* device stops HSM for abort/error */ | |
1142 | qc->err_mask |= AC_ERR_DEV; | |
1143 | else | |
1144 | /* HSM violation. Let EH handle this. | |
1145 | * Phantom devices also trigger this | |
1146 | * condition. Mark hint. | |
1147 | */ | |
1148 | qc->err_mask |= AC_ERR_HSM | | |
1149 | AC_ERR_NODEV_HINT; | |
1150 | ||
1151 | ap->hsm_task_state = HSM_ST_ERR; | |
1152 | goto fsm_start; | |
1153 | } | |
1154 | ||
1155 | /* For PIO reads, some devices may ask for | |
1156 | * data transfer (DRQ=1) alone with ERR=1. | |
1157 | * We respect DRQ here and transfer one | |
1158 | * block of junk data before changing the | |
1159 | * hsm_task_state to HSM_ST_ERR. | |
1160 | * | |
1161 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1162 | * sense since the data block has been | |
1163 | * transferred to the device. | |
1164 | */ | |
1165 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1166 | /* data might be corrputed */ | |
1167 | qc->err_mask |= AC_ERR_DEV; | |
1168 | ||
1169 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1170 | ata_pio_sectors(qc); | |
1171 | status = ata_wait_idle(ap); | |
1172 | } | |
1173 | ||
1174 | if (status & (ATA_BUSY | ATA_DRQ)) | |
1175 | qc->err_mask |= AC_ERR_HSM; | |
1176 | ||
1177 | /* ata_pio_sectors() might change the | |
1178 | * state to HSM_ST_LAST. so, the state | |
1179 | * is changed after ata_pio_sectors(). | |
1180 | */ | |
1181 | ap->hsm_task_state = HSM_ST_ERR; | |
1182 | goto fsm_start; | |
1183 | } | |
1184 | ||
1185 | ata_pio_sectors(qc); | |
1186 | ||
1187 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1188 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1189 | /* all data read */ | |
1190 | status = ata_wait_idle(ap); | |
1191 | goto fsm_start; | |
1192 | } | |
1193 | } | |
1194 | ||
1195 | poll_next = 1; | |
1196 | break; | |
1197 | ||
1198 | case HSM_ST_LAST: | |
1199 | if (unlikely(!ata_ok(status))) { | |
1200 | qc->err_mask |= __ac_err_mask(status); | |
1201 | ap->hsm_task_state = HSM_ST_ERR; | |
1202 | goto fsm_start; | |
1203 | } | |
1204 | ||
1205 | /* no more data to transfer */ | |
1206 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1207 | ap->print_id, qc->dev->devno, status); | |
1208 | ||
1209 | WARN_ON(qc->err_mask); | |
1210 | ||
1211 | ap->hsm_task_state = HSM_ST_IDLE; | |
1212 | ||
1213 | /* complete taskfile transaction */ | |
1214 | ata_hsm_qc_complete(qc, in_wq); | |
1215 | ||
1216 | poll_next = 0; | |
1217 | break; | |
1218 | ||
1219 | case HSM_ST_ERR: | |
1220 | /* make sure qc->err_mask is available to | |
1221 | * know what's wrong and recover | |
1222 | */ | |
1223 | WARN_ON(qc->err_mask == 0); | |
1224 | ||
1225 | ap->hsm_task_state = HSM_ST_IDLE; | |
1226 | ||
1227 | /* complete taskfile transaction */ | |
1228 | ata_hsm_qc_complete(qc, in_wq); | |
1229 | ||
1230 | poll_next = 0; | |
1231 | break; | |
1232 | default: | |
1233 | poll_next = 0; | |
1234 | BUG(); | |
1235 | } | |
1236 | ||
1237 | return poll_next; | |
1238 | } | |
1239 | ||
1240 | void ata_pio_task(struct work_struct *work) | |
1241 | { | |
1242 | struct ata_port *ap = | |
1243 | container_of(work, struct ata_port, port_task.work); | |
1244 | struct ata_queued_cmd *qc = ap->port_task_data; | |
1245 | u8 status; | |
1246 | int poll_next; | |
1247 | ||
1248 | fsm_start: | |
1249 | WARN_ON(ap->hsm_task_state == HSM_ST_IDLE); | |
1250 | ||
1251 | /* | |
1252 | * This is purely heuristic. This is a fast path. | |
1253 | * Sometimes when we enter, BSY will be cleared in | |
1254 | * a chk-status or two. If not, the drive is probably seeking | |
1255 | * or something. Snooze for a couple msecs, then | |
1256 | * chk-status again. If still busy, queue delayed work. | |
1257 | */ | |
9363c382 | 1258 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 TH |
1259 | if (status & ATA_BUSY) { |
1260 | msleep(2); | |
9363c382 | 1261 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 TH |
1262 | if (status & ATA_BUSY) { |
1263 | ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE); | |
1264 | return; | |
1265 | } | |
1266 | } | |
1267 | ||
1268 | /* move the HSM */ | |
9363c382 | 1269 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1270 | |
1271 | /* another command or interrupt handler | |
1272 | * may be running at this point. | |
1273 | */ | |
1274 | if (poll_next) | |
1275 | goto fsm_start; | |
1276 | } | |
1277 | ||
1278 | /** | |
9363c382 | 1279 | * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner |
624d5c51 TH |
1280 | * @qc: command to issue to device |
1281 | * | |
1282 | * Using various libata functions and hooks, this function | |
1283 | * starts an ATA command. ATA commands are grouped into | |
1284 | * classes called "protocols", and issuing each type of protocol | |
1285 | * is slightly different. | |
1286 | * | |
1287 | * May be used as the qc_issue() entry in ata_port_operations. | |
1288 | * | |
1289 | * LOCKING: | |
1290 | * spin_lock_irqsave(host lock) | |
1291 | * | |
1292 | * RETURNS: | |
1293 | * Zero on success, AC_ERR_* mask on failure | |
1294 | */ | |
9363c382 | 1295 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1296 | { |
1297 | struct ata_port *ap = qc->ap; | |
1298 | ||
1299 | /* Use polling pio if the LLD doesn't handle | |
1300 | * interrupt driven pio and atapi CDB interrupt. | |
1301 | */ | |
1302 | if (ap->flags & ATA_FLAG_PIO_POLLING) { | |
1303 | switch (qc->tf.protocol) { | |
1304 | case ATA_PROT_PIO: | |
1305 | case ATA_PROT_NODATA: | |
1306 | case ATAPI_PROT_PIO: | |
1307 | case ATAPI_PROT_NODATA: | |
1308 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
1309 | break; | |
1310 | case ATAPI_PROT_DMA: | |
1311 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
1312 | /* see ata_dma_blacklisted() */ | |
1313 | BUG(); | |
1314 | break; | |
1315 | default: | |
1316 | break; | |
1317 | } | |
1318 | } | |
1319 | ||
1320 | /* select the device */ | |
1321 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1322 | ||
1323 | /* start the command */ | |
1324 | switch (qc->tf.protocol) { | |
1325 | case ATA_PROT_NODATA: | |
1326 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1327 | ata_qc_set_polling(qc); | |
1328 | ||
1329 | ata_tf_to_host(ap, &qc->tf); | |
1330 | ap->hsm_task_state = HSM_ST_LAST; | |
1331 | ||
1332 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1333 | ata_pio_queue_task(ap, qc, 0); | |
1334 | ||
1335 | break; | |
1336 | ||
1337 | case ATA_PROT_DMA: | |
1338 | WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); | |
1339 | ||
5682ed33 | 1340 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1341 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1342 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
1343 | ap->hsm_task_state = HSM_ST_LAST; | |
1344 | break; | |
1345 | ||
1346 | case ATA_PROT_PIO: | |
1347 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1348 | ata_qc_set_polling(qc); | |
1349 | ||
1350 | ata_tf_to_host(ap, &qc->tf); | |
1351 | ||
1352 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1353 | /* PIO data out protocol */ | |
1354 | ap->hsm_task_state = HSM_ST_FIRST; | |
1355 | ata_pio_queue_task(ap, qc, 0); | |
1356 | ||
1357 | /* always send first data block using | |
1358 | * the ata_pio_task() codepath. | |
1359 | */ | |
1360 | } else { | |
1361 | /* PIO data in protocol */ | |
1362 | ap->hsm_task_state = HSM_ST; | |
1363 | ||
1364 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1365 | ata_pio_queue_task(ap, qc, 0); | |
1366 | ||
1367 | /* if polling, ata_pio_task() handles the rest. | |
1368 | * otherwise, interrupt handler takes over from here. | |
1369 | */ | |
1370 | } | |
1371 | ||
1372 | break; | |
1373 | ||
1374 | case ATAPI_PROT_PIO: | |
1375 | case ATAPI_PROT_NODATA: | |
1376 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1377 | ata_qc_set_polling(qc); | |
1378 | ||
1379 | ata_tf_to_host(ap, &qc->tf); | |
1380 | ||
1381 | ap->hsm_task_state = HSM_ST_FIRST; | |
1382 | ||
1383 | /* send cdb by polling if no cdb interrupt */ | |
1384 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1385 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
1386 | ata_pio_queue_task(ap, qc, 0); | |
1387 | break; | |
1388 | ||
1389 | case ATAPI_PROT_DMA: | |
1390 | WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); | |
1391 | ||
5682ed33 | 1392 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1393 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1394 | ap->hsm_task_state = HSM_ST_FIRST; | |
1395 | ||
1396 | /* send cdb by polling if no cdb interrupt */ | |
1397 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1398 | ata_pio_queue_task(ap, qc, 0); | |
1399 | break; | |
1400 | ||
1401 | default: | |
1402 | WARN_ON(1); | |
1403 | return AC_ERR_SYSTEM; | |
1404 | } | |
1405 | ||
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | /** | |
9363c382 | 1410 | * ata_sff_host_intr - Handle host interrupt for given (port, task) |
624d5c51 TH |
1411 | * @ap: Port on which interrupt arrived (possibly...) |
1412 | * @qc: Taskfile currently active in engine | |
1413 | * | |
1414 | * Handle host interrupt for given queued command. Currently, | |
1415 | * only DMA interrupts are handled. All other commands are | |
1416 | * handled via polling with interrupts disabled (nIEN bit). | |
1417 | * | |
1418 | * LOCKING: | |
1419 | * spin_lock_irqsave(host lock) | |
1420 | * | |
1421 | * RETURNS: | |
1422 | * One if interrupt was handled, zero if not (shared irq). | |
1423 | */ | |
9363c382 TH |
1424 | inline unsigned int ata_sff_host_intr(struct ata_port *ap, |
1425 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
1426 | { |
1427 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
1428 | u8 status, host_stat = 0; | |
1429 | ||
1430 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1431 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1432 | ||
1433 | /* Check whether we are expecting interrupt in this state */ | |
1434 | switch (ap->hsm_task_state) { | |
1435 | case HSM_ST_FIRST: | |
1436 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1437 | * at this state when ready to receive CDB. | |
1438 | */ | |
1439 | ||
1440 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1441 | * The flag was turned on only for atapi devices. No | |
1442 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1443 | */ | |
1444 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1445 | goto idle_irq; | |
1446 | break; | |
1447 | case HSM_ST_LAST: | |
1448 | if (qc->tf.protocol == ATA_PROT_DMA || | |
1449 | qc->tf.protocol == ATAPI_PROT_DMA) { | |
1450 | /* check status of DMA engine */ | |
1451 | host_stat = ap->ops->bmdma_status(ap); | |
1452 | VPRINTK("ata%u: host_stat 0x%X\n", | |
1453 | ap->print_id, host_stat); | |
1454 | ||
1455 | /* if it's not our irq... */ | |
1456 | if (!(host_stat & ATA_DMA_INTR)) | |
1457 | goto idle_irq; | |
1458 | ||
1459 | /* before we do anything else, clear DMA-Start bit */ | |
1460 | ap->ops->bmdma_stop(qc); | |
1461 | ||
1462 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
1463 | /* error when transfering data to/from memory */ | |
1464 | qc->err_mask |= AC_ERR_HOST_BUS; | |
1465 | ap->hsm_task_state = HSM_ST_ERR; | |
1466 | } | |
1467 | } | |
1468 | break; | |
1469 | case HSM_ST: | |
1470 | break; | |
1471 | default: | |
1472 | goto idle_irq; | |
1473 | } | |
1474 | ||
1475 | /* check altstatus */ | |
9363c382 | 1476 | status = ata_sff_altstatus(ap); |
624d5c51 TH |
1477 | if (status & ATA_BUSY) |
1478 | goto idle_irq; | |
1479 | ||
1480 | /* check main status, clearing INTRQ */ | |
5682ed33 | 1481 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
1482 | if (unlikely(status & ATA_BUSY)) |
1483 | goto idle_irq; | |
1484 | ||
1485 | /* ack bmdma irq events */ | |
5682ed33 | 1486 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1487 | |
9363c382 | 1488 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 TH |
1489 | |
1490 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || | |
1491 | qc->tf.protocol == ATAPI_PROT_DMA)) | |
1492 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
1493 | ||
1494 | return 1; /* irq handled */ | |
1495 | ||
1496 | idle_irq: | |
1497 | ap->stats.idle_irq++; | |
1498 | ||
1499 | #ifdef ATA_IRQ_TRAP | |
1500 | if ((ap->stats.idle_irq % 1000) == 0) { | |
5682ed33 TH |
1501 | ap->ops->sff_check_status(ap); |
1502 | ap->ops->sff_irq_clear(ap); | |
624d5c51 TH |
1503 | ata_port_printk(ap, KERN_WARNING, "irq trap\n"); |
1504 | return 1; | |
1505 | } | |
1506 | #endif | |
1507 | return 0; /* irq not handled */ | |
1508 | } | |
1509 | ||
1510 | /** | |
9363c382 | 1511 | * ata_sff_interrupt - Default ATA host interrupt handler |
624d5c51 TH |
1512 | * @irq: irq line (unused) |
1513 | * @dev_instance: pointer to our ata_host information structure | |
1514 | * | |
1515 | * Default interrupt handler for PCI IDE devices. Calls | |
9363c382 | 1516 | * ata_sff_host_intr() for each port that is not disabled. |
624d5c51 TH |
1517 | * |
1518 | * LOCKING: | |
1519 | * Obtains host lock during operation. | |
1520 | * | |
1521 | * RETURNS: | |
1522 | * IRQ_NONE or IRQ_HANDLED. | |
1523 | */ | |
9363c382 | 1524 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) |
624d5c51 TH |
1525 | { |
1526 | struct ata_host *host = dev_instance; | |
1527 | unsigned int i; | |
1528 | unsigned int handled = 0; | |
1529 | unsigned long flags; | |
1530 | ||
1531 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1532 | spin_lock_irqsave(&host->lock, flags); | |
1533 | ||
1534 | for (i = 0; i < host->n_ports; i++) { | |
1535 | struct ata_port *ap; | |
1536 | ||
1537 | ap = host->ports[i]; | |
1538 | if (ap && | |
1539 | !(ap->flags & ATA_FLAG_DISABLED)) { | |
1540 | struct ata_queued_cmd *qc; | |
1541 | ||
1542 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
1543 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && | |
1544 | (qc->flags & ATA_QCFLAG_ACTIVE)) | |
9363c382 | 1545 | handled |= ata_sff_host_intr(ap, qc); |
624d5c51 TH |
1546 | } |
1547 | } | |
1548 | ||
1549 | spin_unlock_irqrestore(&host->lock, flags); | |
1550 | ||
1551 | return IRQ_RETVAL(handled); | |
1552 | } | |
1553 | ||
1554 | /** | |
9363c382 | 1555 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1556 | * @ap: port to freeze |
1557 | * | |
1558 | * Freeze BMDMA controller port. | |
1559 | * | |
1560 | * LOCKING: | |
1561 | * Inherited from caller. | |
1562 | */ | |
9363c382 | 1563 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 TH |
1564 | { |
1565 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
1566 | ||
1567 | ap->ctl |= ATA_NIEN; | |
1568 | ap->last_ctl = ap->ctl; | |
1569 | ||
1570 | if (ioaddr->ctl_addr) | |
1571 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1572 | ||
1573 | /* Under certain circumstances, some controllers raise IRQ on | |
1574 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1575 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1576 | */ | |
5682ed33 | 1577 | ap->ops->sff_check_status(ap); |
624d5c51 | 1578 | |
5682ed33 | 1579 | ap->ops->sff_irq_clear(ap); |
624d5c51 TH |
1580 | } |
1581 | ||
1582 | /** | |
9363c382 | 1583 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1584 | * @ap: port to thaw |
1585 | * | |
9363c382 | 1586 | * Thaw SFF controller port. |
624d5c51 TH |
1587 | * |
1588 | * LOCKING: | |
1589 | * Inherited from caller. | |
1590 | */ | |
9363c382 | 1591 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1592 | { |
624d5c51 | 1593 | /* clear & re-enable interrupts */ |
5682ed33 TH |
1594 | ap->ops->sff_check_status(ap); |
1595 | ap->ops->sff_irq_clear(ap); | |
1596 | ap->ops->sff_irq_on(ap); | |
272f7884 TH |
1597 | } |
1598 | ||
0aa1113d TH |
1599 | /** |
1600 | * ata_sff_prereset - prepare SFF link for reset | |
1601 | * @link: SFF link to be reset | |
1602 | * @deadline: deadline jiffies for the operation | |
1603 | * | |
1604 | * SFF link @link is about to be reset. Initialize it. It first | |
1605 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1606 | * being softreset. | |
1607 | * | |
1608 | * LOCKING: | |
1609 | * Kernel thread context (may sleep) | |
1610 | * | |
1611 | * RETURNS: | |
1612 | * 0 on success, -errno otherwise. | |
1613 | */ | |
1614 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1615 | { | |
0aa1113d TH |
1616 | struct ata_eh_context *ehc = &link->eh_context; |
1617 | int rc; | |
1618 | ||
1619 | rc = ata_std_prereset(link, deadline); | |
1620 | if (rc) | |
1621 | return rc; | |
1622 | ||
1623 | /* if we're about to do hardreset, nothing more to do */ | |
1624 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1625 | return 0; | |
1626 | ||
1627 | /* wait for !BSY if we don't know that no device is attached */ | |
1628 | if (!ata_link_offline(link)) { | |
705e76be | 1629 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d TH |
1630 | if (rc && rc != -ENODEV) { |
1631 | ata_link_printk(link, KERN_WARNING, "device not ready " | |
1632 | "(errno=%d), forcing hardreset\n", rc); | |
1633 | ehc->i.action |= ATA_EH_HARDRESET; | |
1634 | } | |
1635 | } | |
1636 | ||
1637 | return 0; | |
1638 | } | |
1639 | ||
90088bb4 | 1640 | /** |
624d5c51 TH |
1641 | * ata_devchk - PATA device presence detection |
1642 | * @ap: ATA channel to examine | |
1643 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1644 | * |
624d5c51 TH |
1645 | * This technique was originally described in |
1646 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1647 | * later found its way into the ATA/ATAPI spec. | |
1648 | * | |
1649 | * Write a pattern to the ATA shadow registers, | |
1650 | * and if a device is present, it will respond by | |
1651 | * correctly storing and echoing back the | |
1652 | * ATA shadow register contents. | |
90088bb4 TH |
1653 | * |
1654 | * LOCKING: | |
624d5c51 | 1655 | * caller. |
90088bb4 | 1656 | */ |
624d5c51 | 1657 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1658 | { |
1659 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1660 | u8 nsect, lbal; |
90088bb4 | 1661 | |
5682ed33 | 1662 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1663 | |
624d5c51 TH |
1664 | iowrite8(0x55, ioaddr->nsect_addr); |
1665 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1666 | |
624d5c51 TH |
1667 | iowrite8(0xaa, ioaddr->nsect_addr); |
1668 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1669 | |
624d5c51 TH |
1670 | iowrite8(0x55, ioaddr->nsect_addr); |
1671 | iowrite8(0xaa, ioaddr->lbal_addr); | |
1672 | ||
1673 | nsect = ioread8(ioaddr->nsect_addr); | |
1674 | lbal = ioread8(ioaddr->lbal_addr); | |
1675 | ||
1676 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
1677 | return 1; /* we found a device */ | |
1678 | ||
1679 | return 0; /* nothing found */ | |
90088bb4 TH |
1680 | } |
1681 | ||
272f7884 | 1682 | /** |
9363c382 | 1683 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
1684 | * @dev: ATA device to classify (starting at zero) |
1685 | * @present: device seems present | |
1686 | * @r_err: Value of error register on completion | |
272f7884 | 1687 | * |
624d5c51 TH |
1688 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
1689 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
1690 | * shadow registers, indicating the results of device detection | |
1691 | * and diagnostics. | |
272f7884 | 1692 | * |
624d5c51 TH |
1693 | * Select the ATA device, and read the values from the ATA shadow |
1694 | * registers. Then parse according to the Error register value, | |
1695 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
1696 | * |
1697 | * LOCKING: | |
624d5c51 TH |
1698 | * caller. |
1699 | * | |
1700 | * RETURNS: | |
1701 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 1702 | */ |
9363c382 | 1703 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 1704 | u8 *r_err) |
272f7884 | 1705 | { |
624d5c51 TH |
1706 | struct ata_port *ap = dev->link->ap; |
1707 | struct ata_taskfile tf; | |
1708 | unsigned int class; | |
1709 | u8 err; | |
1710 | ||
5682ed33 | 1711 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
1712 | |
1713 | memset(&tf, 0, sizeof(tf)); | |
1714 | ||
5682ed33 | 1715 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
1716 | err = tf.feature; |
1717 | if (r_err) | |
1718 | *r_err = err; | |
1719 | ||
1720 | /* see if device passed diags: continue and warn later */ | |
1721 | if (err == 0) | |
1722 | /* diagnostic fail : do nothing _YET_ */ | |
1723 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
1724 | else if (err == 1) | |
1725 | /* do nothing */ ; | |
1726 | else if ((dev->devno == 0) && (err == 0x81)) | |
1727 | /* do nothing */ ; | |
1728 | else | |
1729 | return ATA_DEV_NONE; | |
272f7884 | 1730 | |
624d5c51 TH |
1731 | /* determine if device is ATA or ATAPI */ |
1732 | class = ata_dev_classify(&tf); | |
272f7884 | 1733 | |
624d5c51 TH |
1734 | if (class == ATA_DEV_UNKNOWN) { |
1735 | /* If the device failed diagnostic, it's likely to | |
1736 | * have reported incorrect device signature too. | |
1737 | * Assume ATA device if the device seems present but | |
1738 | * device signature is invalid with diagnostic | |
1739 | * failure. | |
1740 | */ | |
1741 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
1742 | class = ATA_DEV_ATA; | |
1743 | else | |
1744 | class = ATA_DEV_NONE; | |
5682ed33 TH |
1745 | } else if ((class == ATA_DEV_ATA) && |
1746 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
1747 | class = ATA_DEV_NONE; |
1748 | ||
1749 | return class; | |
272f7884 TH |
1750 | } |
1751 | ||
705e76be TH |
1752 | /** |
1753 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
1754 | * @link: SFF link which is just reset | |
1755 | * @devmask: mask of present devices | |
1756 | * @deadline: deadline jiffies for the operation | |
1757 | * | |
1758 | * Wait devices attached to SFF @link to become ready after | |
1759 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
1760 | * status register too early. | |
1761 | * | |
1762 | * LOCKING: | |
1763 | * Kernel thread context (may sleep). | |
1764 | * | |
1765 | * RETURNS: | |
1766 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
1767 | * don't seem to exist. -errno on other errors. | |
1768 | */ | |
1769 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
1770 | unsigned long deadline) | |
1fdffbce | 1771 | { |
705e76be | 1772 | struct ata_port *ap = link->ap; |
1fdffbce | 1773 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
1774 | unsigned int dev0 = devmask & (1 << 0); |
1775 | unsigned int dev1 = devmask & (1 << 1); | |
1776 | int rc, ret = 0; | |
1fdffbce | 1777 | |
705e76be TH |
1778 | msleep(ATA_WAIT_AFTER_RESET_MSECS); |
1779 | ||
1780 | /* always check readiness of the master device */ | |
1781 | rc = ata_sff_wait_ready(link, deadline); | |
1782 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
1783 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 1784 | */ |
705e76be TH |
1785 | if (rc) |
1786 | return rc; | |
1fdffbce | 1787 | |
624d5c51 TH |
1788 | /* if device 1 was found in ata_devchk, wait for register |
1789 | * access briefly, then wait for BSY to clear. | |
1790 | */ | |
1791 | if (dev1) { | |
1792 | int i; | |
1fdffbce | 1793 | |
5682ed33 | 1794 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 1795 | |
624d5c51 TH |
1796 | /* Wait for register access. Some ATAPI devices fail |
1797 | * to set nsect/lbal after reset, so don't waste too | |
1798 | * much time on it. We're gonna wait for !BSY anyway. | |
1799 | */ | |
1800 | for (i = 0; i < 2; i++) { | |
1801 | u8 nsect, lbal; | |
1802 | ||
1803 | nsect = ioread8(ioaddr->nsect_addr); | |
1804 | lbal = ioread8(ioaddr->lbal_addr); | |
1805 | if ((nsect == 1) && (lbal == 1)) | |
1806 | break; | |
1807 | msleep(50); /* give drive a breather */ | |
1808 | } | |
1809 | ||
705e76be | 1810 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
1811 | if (rc) { |
1812 | if (rc != -ENODEV) | |
1813 | return rc; | |
1814 | ret = rc; | |
1815 | } | |
1fdffbce JG |
1816 | } |
1817 | ||
624d5c51 | 1818 | /* is all this really necessary? */ |
5682ed33 | 1819 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 1820 | if (dev1) |
5682ed33 | 1821 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 1822 | if (dev0) |
5682ed33 | 1823 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1824 | |
1825 | return ret; | |
1fdffbce JG |
1826 | } |
1827 | ||
624d5c51 TH |
1828 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
1829 | unsigned long deadline) | |
2cc432ee | 1830 | { |
624d5c51 | 1831 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 1832 | |
624d5c51 TH |
1833 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
1834 | ||
1835 | /* software reset. causes dev0 to be selected */ | |
1836 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1837 | udelay(20); /* FIXME: flush */ | |
1838 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
1839 | udelay(20); /* FIXME: flush */ | |
1840 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1841 | ||
705e76be TH |
1842 | /* wait the port to become ready */ |
1843 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
1844 | } |
1845 | ||
6d97dbd7 | 1846 | /** |
9363c382 | 1847 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
1848 | * @link: ATA link to reset |
1849 | * @classes: resulting classes of attached devices | |
1850 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1851 | * |
624d5c51 | 1852 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
1853 | * |
1854 | * LOCKING: | |
624d5c51 TH |
1855 | * Kernel thread context (may sleep) |
1856 | * | |
1857 | * RETURNS: | |
1858 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 1859 | */ |
9363c382 | 1860 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 1861 | unsigned long deadline) |
6d97dbd7 | 1862 | { |
624d5c51 TH |
1863 | struct ata_port *ap = link->ap; |
1864 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
1865 | unsigned int devmask = 0; | |
1866 | int rc; | |
1867 | u8 err; | |
6d97dbd7 | 1868 | |
624d5c51 | 1869 | DPRINTK("ENTER\n"); |
6d97dbd7 | 1870 | |
624d5c51 TH |
1871 | if (ata_link_offline(link)) { |
1872 | classes[0] = ATA_DEV_NONE; | |
1873 | goto out; | |
1874 | } | |
0f0a3ad3 | 1875 | |
624d5c51 TH |
1876 | /* determine if device 0/1 are present */ |
1877 | if (ata_devchk(ap, 0)) | |
1878 | devmask |= (1 << 0); | |
1879 | if (slave_possible && ata_devchk(ap, 1)) | |
1880 | devmask |= (1 << 1); | |
1881 | ||
1882 | /* select device 0 again */ | |
5682ed33 | 1883 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1884 | |
1885 | /* issue bus reset */ | |
1886 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
1887 | rc = ata_bus_softreset(ap, devmask, deadline); | |
1888 | /* if link is occupied, -ENODEV too is an error */ | |
1889 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
1890 | ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); | |
1891 | return rc; | |
1892 | } | |
0f0a3ad3 | 1893 | |
624d5c51 | 1894 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 1895 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
1896 | devmask & (1 << 0), &err); |
1897 | if (slave_possible && err != 0x81) | |
9363c382 | 1898 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
1899 | devmask & (1 << 1), &err); |
1900 | ||
1901 | out: | |
1902 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); | |
1903 | return 0; | |
6d97dbd7 TH |
1904 | } |
1905 | ||
1906 | /** | |
9363c382 | 1907 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
1908 | * @link: link to reset |
1909 | * @class: resulting class of attached device | |
1910 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1911 | * |
624d5c51 TH |
1912 | * SATA phy-reset host port using DET bits of SControl register, |
1913 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
1914 | * |
1915 | * LOCKING: | |
624d5c51 TH |
1916 | * Kernel thread context (may sleep) |
1917 | * | |
1918 | * RETURNS: | |
1919 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 1920 | */ |
9363c382 | 1921 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 1922 | unsigned long deadline) |
6d97dbd7 | 1923 | { |
624d5c51 TH |
1924 | struct ata_port *ap = link->ap; |
1925 | const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); | |
1926 | int rc; | |
1927 | ||
1928 | DPRINTK("ENTER\n"); | |
1929 | ||
1930 | /* do hardreset */ | |
1931 | rc = sata_link_hardreset(link, timing, deadline); | |
1932 | if (rc) { | |
1933 | ata_link_printk(link, KERN_ERR, | |
1934 | "COMRESET failed (errno=%d)\n", rc); | |
1935 | return rc; | |
1936 | } | |
1937 | ||
1938 | /* TODO: phy layer with polling, timeouts, etc. */ | |
1939 | if (ata_link_offline(link)) { | |
1940 | *class = ATA_DEV_NONE; | |
1941 | DPRINTK("EXIT, link offline\n"); | |
1942 | return 0; | |
1943 | } | |
1944 | ||
624d5c51 TH |
1945 | /* If PMP is supported, we have to do follow-up SRST. Note |
1946 | * that some PMPs don't send D2H Reg FIS after hardreset at | |
1947 | * all if the first port is empty. Wait for it just for a | |
1948 | * second and request follow-up SRST. | |
1949 | */ | |
1950 | if (ap->flags & ATA_FLAG_PMP) { | |
705e76be | 1951 | ata_sff_wait_after_reset(link, 1, jiffies + HZ); |
624d5c51 TH |
1952 | return -EAGAIN; |
1953 | } | |
1954 | ||
705e76be TH |
1955 | /* wait for the link to become online */ |
1956 | rc = ata_sff_wait_after_reset(link, 1, deadline); | |
624d5c51 TH |
1957 | /* link occupied, -ENODEV too is an error */ |
1958 | if (rc) { | |
1959 | ata_link_printk(link, KERN_ERR, | |
1960 | "COMRESET failed (errno=%d)\n", rc); | |
1961 | return rc; | |
1962 | } | |
1963 | ||
9363c382 | 1964 | *class = ata_sff_dev_classify(link->device, 1, NULL); |
624d5c51 TH |
1965 | |
1966 | DPRINTK("EXIT, class=%u\n", *class); | |
1967 | return 0; | |
6d97dbd7 TH |
1968 | } |
1969 | ||
203c75b8 TH |
1970 | /** |
1971 | * ata_sff_postreset - SFF postreset callback | |
1972 | * @link: the target SFF ata_link | |
1973 | * @classes: classes of attached devices | |
1974 | * | |
1975 | * This function is invoked after a successful reset. It first | |
1976 | * calls ata_std_postreset() and performs SFF specific postreset | |
1977 | * processing. | |
1978 | * | |
1979 | * LOCKING: | |
1980 | * Kernel thread context (may sleep) | |
1981 | */ | |
1982 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
1983 | { | |
1984 | struct ata_port *ap = link->ap; | |
1985 | ||
1986 | ata_std_postreset(link, classes); | |
1987 | ||
1988 | /* is double-select really necessary? */ | |
1989 | if (classes[0] != ATA_DEV_NONE) | |
1990 | ap->ops->sff_dev_select(ap, 1); | |
1991 | if (classes[1] != ATA_DEV_NONE) | |
1992 | ap->ops->sff_dev_select(ap, 0); | |
1993 | ||
1994 | /* bail out if no device is present */ | |
1995 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
1996 | DPRINTK("EXIT, no device\n"); | |
1997 | return; | |
1998 | } | |
1999 | ||
2000 | /* set up device control */ | |
2001 | if (ap->ioaddr.ctl_addr) | |
2002 | iowrite8(ap->ctl, ap->ioaddr.ctl_addr); | |
2003 | } | |
2004 | ||
6d97dbd7 | 2005 | /** |
9363c382 | 2006 | * ata_sff_error_handler - Stock error handler for BMDMA controller |
6d97dbd7 | 2007 | * @ap: port to handle error for |
6d97dbd7 | 2008 | * |
9363c382 | 2009 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2010 | * PATA and SATA controllers. Many controllers should be able to |
2011 | * use this EH as-is or with some added handling before and | |
2012 | * after. | |
2013 | * | |
6d97dbd7 TH |
2014 | * LOCKING: |
2015 | * Kernel thread context (may sleep) | |
2016 | */ | |
9363c382 | 2017 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2018 | { |
a1efdaba TH |
2019 | ata_reset_fn_t softreset = ap->ops->softreset; |
2020 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2021 | struct ata_queued_cmd *qc; |
2022 | unsigned long flags; | |
2023 | int thaw = 0; | |
2024 | ||
9af5c9c9 | 2025 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2026 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2027 | qc = NULL; | |
2028 | ||
2029 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 2030 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2031 | |
6d97dbd7 TH |
2032 | ap->hsm_task_state = HSM_ST_IDLE; |
2033 | ||
ed82f964 TH |
2034 | if (ap->ioaddr.bmdma_addr && |
2035 | qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 2036 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
2037 | u8 host_stat; |
2038 | ||
fbbb262d | 2039 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 2040 | |
6d97dbd7 TH |
2041 | /* BMDMA controllers indicate host bus error by |
2042 | * setting DMA_ERR bit and timing out. As it wasn't | |
2043 | * really a timeout event, adjust error mask and | |
2044 | * cancel frozen state. | |
2045 | */ | |
18d90deb | 2046 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { |
6d97dbd7 TH |
2047 | qc->err_mask = AC_ERR_HOST_BUS; |
2048 | thaw = 1; | |
2049 | } | |
2050 | ||
2051 | ap->ops->bmdma_stop(qc); | |
2052 | } | |
2053 | ||
9363c382 | 2054 | ata_sff_altstatus(ap); |
5682ed33 TH |
2055 | ap->ops->sff_check_status(ap); |
2056 | ap->ops->sff_irq_clear(ap); | |
6d97dbd7 | 2057 | |
ba6a1308 | 2058 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
2059 | |
2060 | if (thaw) | |
2061 | ata_eh_thaw_port(ap); | |
2062 | ||
2063 | /* PIO and DMA engines have been stopped, perform recovery */ | |
6d97dbd7 | 2064 | |
9363c382 | 2065 | /* ata_sff_softreset and sata_sff_hardreset are inherited to |
a1efdaba TH |
2066 | * all SFF drivers from ata_sff_port_ops. Ignore softreset if |
2067 | * ctl isn't accessible. Ignore hardreset if SCR access isn't | |
2068 | * available. | |
2069 | */ | |
9363c382 | 2070 | if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) |
a1efdaba | 2071 | softreset = NULL; |
9363c382 | 2072 | if (hardreset == sata_sff_hardreset && !sata_scr_valid(&ap->link)) |
a1efdaba | 2073 | hardreset = NULL; |
6d97dbd7 | 2074 | |
a1efdaba TH |
2075 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2076 | ap->ops->postreset); | |
6d97dbd7 TH |
2077 | } |
2078 | ||
2079 | /** | |
9363c382 | 2080 | * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller |
6d97dbd7 TH |
2081 | * @qc: internal command to clean up |
2082 | * | |
2083 | * LOCKING: | |
2084 | * Kernel thread context (may sleep) | |
2085 | */ | |
9363c382 | 2086 | void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc) |
6d97dbd7 | 2087 | { |
61dd08c6 AC |
2088 | if (qc->ap->ioaddr.bmdma_addr) |
2089 | ata_bmdma_stop(qc); | |
6d97dbd7 TH |
2090 | } |
2091 | ||
d92e74d3 AC |
2092 | /** |
2093 | * ata_sff_port_start - Set port up for dma. | |
2094 | * @ap: Port to initialize | |
2095 | * | |
2096 | * Called just after data structures for each port are | |
2097 | * initialized. Allocates space for PRD table if the device | |
2098 | * is DMA capable SFF. | |
2099 | * | |
2100 | * May be used as the port_start() entry in ata_port_operations. | |
2101 | * | |
2102 | * LOCKING: | |
2103 | * Inherited from caller. | |
2104 | */ | |
d92e74d3 AC |
2105 | int ata_sff_port_start(struct ata_port *ap) |
2106 | { | |
2107 | if (ap->ioaddr.bmdma_addr) | |
2108 | return ata_port_start(ap); | |
2109 | return 0; | |
2110 | } | |
2111 | ||
624d5c51 | 2112 | /** |
9363c382 | 2113 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2114 | * @ioaddr: IO address structure to be initialized |
2115 | * | |
2116 | * Utility function which initializes data_addr, error_addr, | |
2117 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2118 | * device_addr, status_addr, and command_addr to standard offsets | |
2119 | * relative to cmd_addr. | |
2120 | * | |
2121 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2122 | */ | |
9363c382 | 2123 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2124 | { |
2125 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2126 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2127 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2128 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2129 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2130 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2131 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2132 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2133 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2134 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2135 | } | |
2136 | ||
9363c382 TH |
2137 | unsigned long ata_bmdma_mode_filter(struct ata_device *adev, |
2138 | unsigned long xfer_mask) | |
071ce34d TH |
2139 | { |
2140 | /* Filter out DMA modes if the device has been configured by | |
2141 | the BIOS as PIO only */ | |
2142 | ||
2143 | if (adev->link->ap->ioaddr.bmdma_addr == NULL) | |
2144 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
2145 | return xfer_mask; | |
2146 | } | |
2147 | ||
272f7884 TH |
2148 | /** |
2149 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2150 | * @qc: Info associated with this ATA transaction. | |
2151 | * | |
2152 | * LOCKING: | |
2153 | * spin_lock_irqsave(host lock) | |
2154 | */ | |
2155 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2156 | { | |
2157 | struct ata_port *ap = qc->ap; | |
2158 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2159 | u8 dmactl; | |
2160 | ||
2161 | /* load PRD table addr. */ | |
2162 | mb(); /* make sure PRD table writes are visible to controller */ | |
2163 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | |
2164 | ||
2165 | /* specify data direction, triple-check start bit is clear */ | |
2166 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2167 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2168 | if (!rw) | |
2169 | dmactl |= ATA_DMA_WR; | |
2170 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2171 | ||
2172 | /* issue r/w command */ | |
5682ed33 | 2173 | ap->ops->sff_exec_command(ap, &qc->tf); |
272f7884 TH |
2174 | } |
2175 | ||
2176 | /** | |
2177 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2178 | * @qc: Info associated with this ATA transaction. | |
2179 | * | |
2180 | * LOCKING: | |
2181 | * spin_lock_irqsave(host lock) | |
2182 | */ | |
2183 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2184 | { | |
2185 | struct ata_port *ap = qc->ap; | |
2186 | u8 dmactl; | |
2187 | ||
2188 | /* start host DMA transaction */ | |
2189 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2190 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2191 | ||
2192 | /* Strictly, one may wish to issue an ioread8() here, to | |
2193 | * flush the mmio write. However, control also passes | |
2194 | * to the hardware at this point, and it will interrupt | |
2195 | * us when we are to resume control. So, in effect, | |
2196 | * we don't care when the mmio write flushes. | |
2197 | * Further, a read of the DMA status register _immediately_ | |
2198 | * following the write may not be what certain flaky hardware | |
2199 | * is expected, so I think it is best to not add a readb() | |
2200 | * without first all the MMIO ATA cards/mobos. | |
2201 | * Or maybe I'm just being paranoid. | |
2202 | * | |
2203 | * FIXME: The posting of this write means I/O starts are | |
2204 | * unneccessarily delayed for MMIO | |
2205 | */ | |
2206 | } | |
2207 | ||
2208 | /** | |
2209 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
2210 | * @qc: Command we are ending DMA for | |
2211 | * | |
2212 | * Clears the ATA_DMA_START flag in the dma control register | |
2213 | * | |
2214 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
2215 | * | |
2216 | * LOCKING: | |
2217 | * spin_lock_irqsave(host lock) | |
2218 | */ | |
2219 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
2220 | { | |
2221 | struct ata_port *ap = qc->ap; | |
2222 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2223 | ||
2224 | /* clear start/stop bit */ | |
2225 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
2226 | mmio + ATA_DMA_CMD); | |
2227 | ||
2228 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
9363c382 | 2229 | ata_sff_altstatus(ap); /* dummy read */ |
272f7884 TH |
2230 | } |
2231 | ||
2232 | /** | |
2233 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
2234 | * @ap: Port associated with this ATA transaction. | |
2235 | * | |
2236 | * Read and return BMDMA status register. | |
2237 | * | |
2238 | * May be used as the bmdma_status() entry in ata_port_operations. | |
2239 | * | |
2240 | * LOCKING: | |
2241 | * spin_lock_irqsave(host lock) | |
2242 | */ | |
2243 | u8 ata_bmdma_status(struct ata_port *ap) | |
2244 | { | |
2245 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
2246 | } | |
2247 | ||
2248 | /** | |
624d5c51 TH |
2249 | * ata_bus_reset - reset host port and associated ATA channel |
2250 | * @ap: port to reset | |
2251 | * | |
2252 | * This is typically the first time we actually start issuing | |
2253 | * commands to the ATA channel. We wait for BSY to clear, then | |
2254 | * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its | |
2255 | * result. Determine what devices, if any, are on the channel | |
2256 | * by looking at the device 0/1 error register. Look at the signature | |
2257 | * stored in each device's taskfile registers, to determine if | |
2258 | * the device is ATA or ATAPI. | |
2259 | * | |
2260 | * LOCKING: | |
2261 | * PCI/etc. bus probe sem. | |
2262 | * Obtains host lock. | |
2263 | * | |
2264 | * SIDE EFFECTS: | |
2265 | * Sets ATA_FLAG_DISABLED if bus reset fails. | |
2266 | * | |
2267 | * DEPRECATED: | |
2268 | * This function is only for drivers which still use old EH and | |
2269 | * will be removed soon. | |
272f7884 | 2270 | */ |
624d5c51 | 2271 | void ata_bus_reset(struct ata_port *ap) |
272f7884 | 2272 | { |
624d5c51 TH |
2273 | struct ata_device *device = ap->link.device; |
2274 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
2275 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
2276 | u8 err; | |
2277 | unsigned int dev0, dev1 = 0, devmask = 0; | |
2278 | int rc; | |
2279 | ||
2280 | DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no); | |
2281 | ||
2282 | /* determine if device 0/1 are present */ | |
2283 | if (ap->flags & ATA_FLAG_SATA_RESET) | |
2284 | dev0 = 1; | |
2285 | else { | |
2286 | dev0 = ata_devchk(ap, 0); | |
2287 | if (slave_possible) | |
2288 | dev1 = ata_devchk(ap, 1); | |
2289 | } | |
2290 | ||
2291 | if (dev0) | |
2292 | devmask |= (1 << 0); | |
2293 | if (dev1) | |
2294 | devmask |= (1 << 1); | |
2295 | ||
2296 | /* select device 0 again */ | |
5682ed33 | 2297 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2298 | |
2299 | /* issue bus reset */ | |
2300 | if (ap->flags & ATA_FLAG_SRST) { | |
2301 | rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ); | |
2302 | if (rc && rc != -ENODEV) | |
2303 | goto err_out; | |
2304 | } | |
2305 | ||
2306 | /* | |
2307 | * determine by signature whether we have ATA or ATAPI devices | |
2308 | */ | |
9363c382 | 2309 | device[0].class = ata_sff_dev_classify(&device[0], dev0, &err); |
624d5c51 | 2310 | if ((slave_possible) && (err != 0x81)) |
9363c382 | 2311 | device[1].class = ata_sff_dev_classify(&device[1], dev1, &err); |
624d5c51 TH |
2312 | |
2313 | /* is double-select really necessary? */ | |
2314 | if (device[1].class != ATA_DEV_NONE) | |
5682ed33 | 2315 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 2316 | if (device[0].class != ATA_DEV_NONE) |
5682ed33 | 2317 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2318 | |
2319 | /* if no devices were detected, disable this port */ | |
2320 | if ((device[0].class == ATA_DEV_NONE) && | |
2321 | (device[1].class == ATA_DEV_NONE)) | |
2322 | goto err_out; | |
2323 | ||
2324 | if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { | |
2325 | /* set up device control for ATA_FLAG_SATA_RESET */ | |
2326 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
2327 | } | |
2328 | ||
2329 | DPRINTK("EXIT\n"); | |
2330 | return; | |
2331 | ||
2332 | err_out: | |
2333 | ata_port_printk(ap, KERN_ERR, "disabling port\n"); | |
2334 | ata_port_disable(ap); | |
2335 | ||
2336 | DPRINTK("EXIT\n"); | |
272f7884 TH |
2337 | } |
2338 | ||
1fdffbce | 2339 | #ifdef CONFIG_PCI |
4112e16a | 2340 | |
272f7884 | 2341 | /** |
9363c382 | 2342 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex |
272f7884 TH |
2343 | * @pdev: PCI device |
2344 | * | |
2345 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2346 | * enter non simplex mode. This implements the necessary logic to | |
2347 | * perform the task on such devices. Calling it on other devices will | |
2348 | * have -undefined- behaviour. | |
2349 | */ | |
9363c382 | 2350 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) |
4112e16a | 2351 | { |
272f7884 TH |
2352 | unsigned long bmdma = pci_resource_start(pdev, 4); |
2353 | u8 simplex; | |
a84471fe | 2354 | |
272f7884 TH |
2355 | if (bmdma == 0) |
2356 | return -ENOENT; | |
2357 | ||
2358 | simplex = inb(bmdma + 0x02); | |
2359 | outb(simplex & 0x60, bmdma + 0x02); | |
2360 | simplex = inb(bmdma + 0x02); | |
2361 | if (simplex & 0x80) | |
2362 | return -EOPNOTSUPP; | |
2363 | return 0; | |
2364 | } | |
2365 | ||
0f834de3 | 2366 | /** |
9363c382 | 2367 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host |
0f834de3 TH |
2368 | * @host: target ATA host |
2369 | * | |
2370 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
2371 | * | |
2372 | * LOCKING: | |
2373 | * Inherited from calling layer (may sleep). | |
2374 | * | |
2375 | * RETURNS: | |
2376 | * 0 on success, -errno otherwise. | |
2377 | */ | |
9363c382 | 2378 | int ata_pci_bmdma_init(struct ata_host *host) |
1fdffbce | 2379 | { |
0f834de3 TH |
2380 | struct device *gdev = host->dev; |
2381 | struct pci_dev *pdev = to_pci_dev(gdev); | |
2382 | int i, rc; | |
0d5ff566 | 2383 | |
6fdc99a2 AC |
2384 | /* No BAR4 allocation: No DMA */ |
2385 | if (pci_resource_start(pdev, 4) == 0) | |
2386 | return 0; | |
2387 | ||
0f834de3 TH |
2388 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
2389 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
2390 | if (rc) | |
2391 | return rc; | |
2392 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
2393 | if (rc) | |
2394 | return rc; | |
2395 | ||
2396 | /* request and iomap DMA region */ | |
35a10a80 | 2397 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); |
0f834de3 TH |
2398 | if (rc) { |
2399 | dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); | |
2400 | return -ENOMEM; | |
0d5ff566 | 2401 | } |
0f834de3 | 2402 | host->iomap = pcim_iomap_table(pdev); |
0d5ff566 | 2403 | |
1626aeb8 | 2404 | for (i = 0; i < 2; i++) { |
0f834de3 | 2405 | struct ata_port *ap = host->ports[i]; |
0f834de3 TH |
2406 | void __iomem *bmdma = host->iomap[4] + 8 * i; |
2407 | ||
2408 | if (ata_port_is_dummy(ap)) | |
2409 | continue; | |
2410 | ||
21b0ad4f | 2411 | ap->ioaddr.bmdma_addr = bmdma; |
0f834de3 TH |
2412 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && |
2413 | (ioread8(bmdma + 2) & 0x80)) | |
2414 | host->flags |= ATA_HOST_SIMPLEX; | |
cbcdd875 TH |
2415 | |
2416 | ata_port_desc(ap, "bmdma 0x%llx", | |
2417 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
0d5ff566 TH |
2418 | } |
2419 | ||
0f834de3 TH |
2420 | return 0; |
2421 | } | |
2ec7df04 | 2422 | |
272f7884 TH |
2423 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2424 | { | |
2425 | int i; | |
2426 | ||
2427 | /* Check the PCI resources for this channel are enabled */ | |
2428 | port = port * 2; | |
2429 | for (i = 0; i < 2; i ++) { | |
2430 | if (pci_resource_start(pdev, port + i) == 0 || | |
2431 | pci_resource_len(pdev, port + i) == 0) | |
2432 | return 0; | |
2433 | } | |
2434 | return 1; | |
2435 | } | |
2436 | ||
d491b27b | 2437 | /** |
9363c382 | 2438 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2439 | * @host: target ATA host |
d491b27b | 2440 | * |
1626aeb8 TH |
2441 | * Acquire native PCI ATA resources for @host and initialize the |
2442 | * first two ports of @host accordingly. Ports marked dummy are | |
2443 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2444 | * |
d583bc18 TH |
2445 | * Note that native PCI resources are valid even for legacy hosts |
2446 | * as we fix up pdev resources array early in boot, so this | |
2447 | * function can be used for both native and legacy SFF hosts. | |
2448 | * | |
d491b27b TH |
2449 | * LOCKING: |
2450 | * Inherited from calling layer (may sleep). | |
2451 | * | |
2452 | * RETURNS: | |
1626aeb8 TH |
2453 | * 0 if at least one port is initialized, -ENODEV if no port is |
2454 | * available. | |
d491b27b | 2455 | */ |
9363c382 | 2456 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2457 | { |
2458 | struct device *gdev = host->dev; | |
2459 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2460 | unsigned int mask = 0; |
d491b27b TH |
2461 | int i, rc; |
2462 | ||
d491b27b TH |
2463 | /* request, iomap BARs and init port addresses accordingly */ |
2464 | for (i = 0; i < 2; i++) { | |
2465 | struct ata_port *ap = host->ports[i]; | |
2466 | int base = i * 2; | |
2467 | void __iomem * const *iomap; | |
2468 | ||
1626aeb8 TH |
2469 | if (ata_port_is_dummy(ap)) |
2470 | continue; | |
2471 | ||
2472 | /* Discard disabled ports. Some controllers show | |
2473 | * their unused channels this way. Disabled ports are | |
2474 | * made dummy. | |
2475 | */ | |
2476 | if (!ata_resources_present(pdev, i)) { | |
2477 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2478 | continue; |
1626aeb8 | 2479 | } |
d491b27b | 2480 | |
35a10a80 TH |
2481 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2482 | dev_driver_string(gdev)); | |
d491b27b | 2483 | if (rc) { |
1626aeb8 TH |
2484 | dev_printk(KERN_WARNING, gdev, |
2485 | "failed to request/iomap BARs for port %d " | |
2486 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
2487 | if (rc == -EBUSY) |
2488 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2489 | ap->ops = &ata_dummy_port_ops; |
2490 | continue; | |
d491b27b TH |
2491 | } |
2492 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2493 | ||
2494 | ap->ioaddr.cmd_addr = iomap[base]; | |
2495 | ap->ioaddr.altstatus_addr = | |
2496 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2497 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2498 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2499 | |
cbcdd875 TH |
2500 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2501 | (unsigned long long)pci_resource_start(pdev, base), | |
2502 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2503 | ||
1626aeb8 TH |
2504 | mask |= 1 << i; |
2505 | } | |
2506 | ||
2507 | if (!mask) { | |
2508 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
2509 | return -ENODEV; | |
d491b27b TH |
2510 | } |
2511 | ||
2512 | return 0; | |
2513 | } | |
2514 | ||
21b0ad4f | 2515 | /** |
9363c382 | 2516 | * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host |
21b0ad4f | 2517 | * @pdev: target PCI device |
1626aeb8 | 2518 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2519 | * @r_host: out argument for the initialized ATA host |
2520 | * | |
2521 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
2522 | * resources and initialize it accordingly in one go. | |
2523 | * | |
2524 | * LOCKING: | |
2525 | * Inherited from calling layer (may sleep). | |
2526 | * | |
2527 | * RETURNS: | |
2528 | * 0 on success, -errno otherwise. | |
2529 | */ | |
9363c382 | 2530 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
d583bc18 TH |
2531 | const struct ata_port_info * const * ppi, |
2532 | struct ata_host **r_host) | |
21b0ad4f TH |
2533 | { |
2534 | struct ata_host *host; | |
21b0ad4f TH |
2535 | int rc; |
2536 | ||
2537 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2538 | return -ENOMEM; | |
2539 | ||
2540 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2541 | if (!host) { | |
2542 | dev_printk(KERN_ERR, &pdev->dev, | |
2543 | "failed to allocate ATA host\n"); | |
2544 | rc = -ENOMEM; | |
2545 | goto err_out; | |
2546 | } | |
2547 | ||
9363c382 | 2548 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2549 | if (rc) |
2550 | goto err_out; | |
2551 | ||
2552 | /* init DMA related stuff */ | |
9363c382 | 2553 | rc = ata_pci_bmdma_init(host); |
21b0ad4f TH |
2554 | if (rc) |
2555 | goto err_bmdma; | |
2556 | ||
2557 | devres_remove_group(&pdev->dev, NULL); | |
2558 | *r_host = host; | |
2559 | return 0; | |
2560 | ||
2561 | err_bmdma: | |
2562 | /* This is necessary because PCI and iomap resources are | |
2563 | * merged and releasing the top group won't release the | |
2564 | * acquired resources if some of those have been acquired | |
2565 | * before entering this function. | |
2566 | */ | |
2567 | pcim_iounmap_regions(pdev, 0xf); | |
2568 | err_out: | |
2569 | devres_release_group(&pdev->dev, NULL); | |
2570 | return rc; | |
2571 | } | |
2572 | ||
4e6b79fa | 2573 | /** |
9363c382 | 2574 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2575 | * @host: target SFF ATA host |
2576 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2577 | * @sht: scsi_host_template to use when registering the host | |
2578 | * | |
2579 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2580 | * hosts. This separate helper is necessary because SFF hosts | |
2581 | * use two separate interrupts in legacy mode. | |
2582 | * | |
2583 | * LOCKING: | |
2584 | * Inherited from calling layer (may sleep). | |
2585 | * | |
2586 | * RETURNS: | |
2587 | * 0 on success, -errno otherwise. | |
2588 | */ | |
9363c382 | 2589 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2590 | irq_handler_t irq_handler, |
2591 | struct scsi_host_template *sht) | |
2592 | { | |
2593 | struct device *dev = host->dev; | |
2594 | struct pci_dev *pdev = to_pci_dev(dev); | |
2595 | const char *drv_name = dev_driver_string(host->dev); | |
2596 | int legacy_mode = 0, rc; | |
2597 | ||
2598 | rc = ata_host_start(host); | |
2599 | if (rc) | |
2600 | return rc; | |
2601 | ||
2602 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
2603 | u8 tmp8, mask; | |
2604 | ||
2605 | /* TODO: What if one channel is in native mode ... */ | |
2606 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
2607 | mask = (1 << 2) | (1 << 0); | |
2608 | if ((tmp8 & mask) != mask) | |
2609 | legacy_mode = 1; | |
2610 | #if defined(CONFIG_NO_ATA_LEGACY) | |
2611 | /* Some platforms with PCI limits cannot address compat | |
2612 | port space. In that case we punt if their firmware has | |
2613 | left a device in compatibility mode */ | |
2614 | if (legacy_mode) { | |
2615 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
2616 | return -EOPNOTSUPP; | |
2617 | } | |
2618 | #endif | |
2619 | } | |
2620 | ||
2621 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2622 | return -ENOMEM; | |
2623 | ||
2624 | if (!legacy_mode && pdev->irq) { | |
2625 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
2626 | IRQF_SHARED, drv_name, host); | |
2627 | if (rc) | |
2628 | goto out; | |
2629 | ||
2630 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
2631 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
2632 | } else if (legacy_mode) { | |
2633 | if (!ata_port_is_dummy(host->ports[0])) { | |
2634 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2635 | irq_handler, IRQF_SHARED, | |
2636 | drv_name, host); | |
2637 | if (rc) | |
2638 | goto out; | |
2639 | ||
2640 | ata_port_desc(host->ports[0], "irq %d", | |
2641 | ATA_PRIMARY_IRQ(pdev)); | |
2642 | } | |
2643 | ||
2644 | if (!ata_port_is_dummy(host->ports[1])) { | |
2645 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2646 | irq_handler, IRQF_SHARED, | |
2647 | drv_name, host); | |
2648 | if (rc) | |
2649 | goto out; | |
2650 | ||
2651 | ata_port_desc(host->ports[1], "irq %d", | |
2652 | ATA_SECONDARY_IRQ(pdev)); | |
2653 | } | |
2654 | } | |
2655 | ||
2656 | rc = ata_host_register(host, sht); | |
2657 | out: | |
2658 | if (rc == 0) | |
2659 | devres_remove_group(dev, NULL); | |
2660 | else | |
2661 | devres_release_group(dev, NULL); | |
2662 | ||
2663 | return rc; | |
2664 | } | |
2665 | ||
1fdffbce | 2666 | /** |
9363c382 | 2667 | * ata_pci_sff_init_one - Initialize/register PCI IDE host controller |
1fdffbce | 2668 | * @pdev: Controller to be initialized |
1626aeb8 | 2669 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 2670 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 2671 | * @host_priv: host private_data |
1fdffbce JG |
2672 | * |
2673 | * This is a helper function which can be called from a driver's | |
2674 | * xxx_init_one() probe function if the hardware uses traditional | |
2675 | * IDE taskfile registers. | |
2676 | * | |
2677 | * This function calls pci_enable_device(), reserves its register | |
2678 | * regions, sets the dma mask, enables bus master mode, and calls | |
2679 | * ata_device_add() | |
2680 | * | |
2ec7df04 AC |
2681 | * ASSUMPTION: |
2682 | * Nobody makes a single channel controller that appears solely as | |
2683 | * the secondary legacy port on PCI. | |
2684 | * | |
1fdffbce JG |
2685 | * LOCKING: |
2686 | * Inherited from PCI layer (may sleep). | |
2687 | * | |
2688 | * RETURNS: | |
2689 | * Zero on success, negative on errno-based value on error. | |
2690 | */ | |
9363c382 TH |
2691 | int ata_pci_sff_init_one(struct pci_dev *pdev, |
2692 | const struct ata_port_info * const * ppi, | |
2693 | struct scsi_host_template *sht, void *host_priv) | |
1fdffbce | 2694 | { |
f0d36efd | 2695 | struct device *dev = &pdev->dev; |
1626aeb8 | 2696 | const struct ata_port_info *pi = NULL; |
0f834de3 | 2697 | struct ata_host *host = NULL; |
1626aeb8 | 2698 | int i, rc; |
1fdffbce JG |
2699 | |
2700 | DPRINTK("ENTER\n"); | |
2701 | ||
1626aeb8 TH |
2702 | /* look up the first valid port_info */ |
2703 | for (i = 0; i < 2 && ppi[i]; i++) { | |
2704 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
2705 | pi = ppi[i]; | |
2706 | break; | |
2707 | } | |
2708 | } | |
f0d36efd | 2709 | |
1626aeb8 TH |
2710 | if (!pi) { |
2711 | dev_printk(KERN_ERR, &pdev->dev, | |
2712 | "no valid port_info specified\n"); | |
2713 | return -EINVAL; | |
2714 | } | |
c791c306 | 2715 | |
1626aeb8 TH |
2716 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2717 | return -ENOMEM; | |
1fdffbce | 2718 | |
f0d36efd | 2719 | rc = pcim_enable_device(pdev); |
1fdffbce | 2720 | if (rc) |
4e6b79fa | 2721 | goto out; |
1fdffbce | 2722 | |
4e6b79fa | 2723 | /* prepare and activate SFF host */ |
9363c382 | 2724 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
d583bc18 | 2725 | if (rc) |
4e6b79fa | 2726 | goto out; |
887125e3 | 2727 | host->private_data = host_priv; |
d491b27b | 2728 | |
d491b27b | 2729 | pci_set_master(pdev); |
9363c382 | 2730 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
4e6b79fa TH |
2731 | out: |
2732 | if (rc == 0) | |
2733 | devres_remove_group(&pdev->dev, NULL); | |
2734 | else | |
2735 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2736 | |
1fdffbce JG |
2737 | return rc; |
2738 | } | |
2739 | ||
2740 | #endif /* CONFIG_PCI */ | |
2741 | ||
624d5c51 TH |
2742 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
2743 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); | |
9363c382 TH |
2744 | EXPORT_SYMBOL_GPL(ata_sff_qc_prep); |
2745 | EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep); | |
2746 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); | |
2747 | EXPORT_SYMBOL_GPL(ata_sff_check_status); | |
2748 | EXPORT_SYMBOL_GPL(ata_sff_altstatus); | |
2749 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); | |
2750 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); | |
2751 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); | |
2752 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); | |
2753 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); | |
2754 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); | |
2755 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); | |
2756 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); | |
2757 | EXPORT_SYMBOL_GPL(ata_sff_irq_clear); | |
2758 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); | |
2759 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); | |
2760 | EXPORT_SYMBOL_GPL(ata_sff_host_intr); | |
2761 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); | |
2762 | EXPORT_SYMBOL_GPL(ata_sff_freeze); | |
2763 | EXPORT_SYMBOL_GPL(ata_sff_thaw); | |
2764 | EXPORT_SYMBOL_GPL(ata_sff_prereset); | |
2765 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); | |
2766 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); | |
2767 | EXPORT_SYMBOL_GPL(ata_sff_softreset); | |
2768 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); | |
2769 | EXPORT_SYMBOL_GPL(ata_sff_postreset); | |
2770 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); | |
2771 | EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd); | |
624d5c51 | 2772 | EXPORT_SYMBOL_GPL(ata_sff_port_start); |
9363c382 TH |
2773 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
2774 | EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter); | |
624d5c51 TH |
2775 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); |
2776 | EXPORT_SYMBOL_GPL(ata_bmdma_start); | |
2777 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); | |
2778 | EXPORT_SYMBOL_GPL(ata_bmdma_status); | |
2779 | EXPORT_SYMBOL_GPL(ata_bus_reset); | |
2780 | #ifdef CONFIG_PCI | |
9363c382 TH |
2781 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); |
2782 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); | |
2783 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); | |
2784 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); | |
2785 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); | |
2786 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); | |
624d5c51 | 2787 | #endif /* CONFIG_PCI */ |