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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce JG |
35 | #include <linux/kernel.h> |
36 | #include <linux/pci.h> | |
37 | #include <linux/libata.h> | |
624d5c51 | 38 | #include <linux/highmem.h> |
1fdffbce JG |
39 | |
40 | #include "libata.h" | |
41 | ||
624d5c51 TH |
42 | const struct ata_port_operations ata_sff_port_ops = { |
43 | .inherits = &ata_base_port_ops, | |
44 | ||
9363c382 TH |
45 | .qc_prep = ata_sff_qc_prep, |
46 | .qc_issue = ata_sff_qc_issue, | |
4c9bf4e7 | 47 | .qc_fill_rtf = ata_sff_qc_fill_rtf, |
9363c382 TH |
48 | |
49 | .freeze = ata_sff_freeze, | |
50 | .thaw = ata_sff_thaw, | |
0aa1113d | 51 | .prereset = ata_sff_prereset, |
9363c382 | 52 | .softreset = ata_sff_softreset, |
57c9efdf | 53 | .hardreset = sata_sff_hardreset, |
203c75b8 | 54 | .postreset = ata_sff_postreset, |
9363c382 TH |
55 | .error_handler = ata_sff_error_handler, |
56 | .post_internal_cmd = ata_sff_post_internal_cmd, | |
57 | ||
5682ed33 TH |
58 | .sff_dev_select = ata_sff_dev_select, |
59 | .sff_check_status = ata_sff_check_status, | |
60 | .sff_tf_load = ata_sff_tf_load, | |
61 | .sff_tf_read = ata_sff_tf_read, | |
62 | .sff_exec_command = ata_sff_exec_command, | |
63 | .sff_data_xfer = ata_sff_data_xfer, | |
64 | .sff_irq_on = ata_sff_irq_on, | |
288623a0 | 65 | .sff_irq_clear = ata_sff_irq_clear, |
624d5c51 TH |
66 | |
67 | .port_start = ata_sff_port_start, | |
68 | }; | |
69 | ||
70 | const struct ata_port_operations ata_bmdma_port_ops = { | |
71 | .inherits = &ata_sff_port_ops, | |
72 | ||
9363c382 | 73 | .mode_filter = ata_bmdma_mode_filter, |
624d5c51 TH |
74 | |
75 | .bmdma_setup = ata_bmdma_setup, | |
76 | .bmdma_start = ata_bmdma_start, | |
77 | .bmdma_stop = ata_bmdma_stop, | |
78 | .bmdma_status = ata_bmdma_status, | |
624d5c51 TH |
79 | }; |
80 | ||
81 | /** | |
82 | * ata_fill_sg - Fill PCI IDE PRD table | |
83 | * @qc: Metadata associated with taskfile to be transferred | |
84 | * | |
85 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
86 | * associated with the current disk command. | |
87 | * | |
88 | * LOCKING: | |
89 | * spin_lock_irqsave(host lock) | |
90 | * | |
91 | */ | |
92 | static void ata_fill_sg(struct ata_queued_cmd *qc) | |
93 | { | |
94 | struct ata_port *ap = qc->ap; | |
95 | struct scatterlist *sg; | |
96 | unsigned int si, pi; | |
97 | ||
98 | pi = 0; | |
99 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
100 | u32 addr, offset; | |
101 | u32 sg_len, len; | |
102 | ||
103 | /* determine if physical DMA addr spans 64K boundary. | |
104 | * Note h/w doesn't support 64-bit, so we unconditionally | |
105 | * truncate dma_addr_t to u32. | |
106 | */ | |
107 | addr = (u32) sg_dma_address(sg); | |
108 | sg_len = sg_dma_len(sg); | |
109 | ||
110 | while (sg_len) { | |
111 | offset = addr & 0xffff; | |
112 | len = sg_len; | |
113 | if ((offset + sg_len) > 0x10000) | |
114 | len = 0x10000 - offset; | |
115 | ||
116 | ap->prd[pi].addr = cpu_to_le32(addr); | |
117 | ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
118 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
119 | ||
120 | pi++; | |
121 | sg_len -= len; | |
122 | addr += len; | |
123 | } | |
124 | } | |
125 | ||
126 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
127 | } | |
128 | ||
129 | /** | |
130 | * ata_fill_sg_dumb - Fill PCI IDE PRD table | |
131 | * @qc: Metadata associated with taskfile to be transferred | |
132 | * | |
133 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
134 | * associated with the current disk command. Perform the fill | |
135 | * so that we avoid writing any length 64K records for | |
136 | * controllers that don't follow the spec. | |
137 | * | |
138 | * LOCKING: | |
139 | * spin_lock_irqsave(host lock) | |
140 | * | |
141 | */ | |
142 | static void ata_fill_sg_dumb(struct ata_queued_cmd *qc) | |
143 | { | |
144 | struct ata_port *ap = qc->ap; | |
145 | struct scatterlist *sg; | |
146 | unsigned int si, pi; | |
147 | ||
148 | pi = 0; | |
149 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
150 | u32 addr, offset; | |
151 | u32 sg_len, len, blen; | |
152 | ||
153 | /* determine if physical DMA addr spans 64K boundary. | |
154 | * Note h/w doesn't support 64-bit, so we unconditionally | |
155 | * truncate dma_addr_t to u32. | |
156 | */ | |
157 | addr = (u32) sg_dma_address(sg); | |
158 | sg_len = sg_dma_len(sg); | |
159 | ||
160 | while (sg_len) { | |
161 | offset = addr & 0xffff; | |
162 | len = sg_len; | |
163 | if ((offset + sg_len) > 0x10000) | |
164 | len = 0x10000 - offset; | |
165 | ||
166 | blen = len & 0xffff; | |
167 | ap->prd[pi].addr = cpu_to_le32(addr); | |
168 | if (blen == 0) { | |
169 | /* Some PATA chipsets like the CS5530 can't | |
170 | cope with 0x0000 meaning 64K as the spec says */ | |
171 | ap->prd[pi].flags_len = cpu_to_le32(0x8000); | |
172 | blen = 0x8000; | |
173 | ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000); | |
174 | } | |
175 | ap->prd[pi].flags_len = cpu_to_le32(blen); | |
176 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); | |
177 | ||
178 | pi++; | |
179 | sg_len -= len; | |
180 | addr += len; | |
181 | } | |
182 | } | |
183 | ||
184 | ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
185 | } | |
186 | ||
187 | /** | |
9363c382 | 188 | * ata_sff_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
189 | * @qc: Metadata associated with taskfile to be prepared |
190 | * | |
191 | * Prepare ATA taskfile for submission. | |
192 | * | |
193 | * LOCKING: | |
194 | * spin_lock_irqsave(host lock) | |
195 | */ | |
9363c382 | 196 | void ata_sff_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
197 | { |
198 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
199 | return; | |
200 | ||
201 | ata_fill_sg(qc); | |
202 | } | |
203 | ||
204 | /** | |
9363c382 | 205 | * ata_sff_dumb_qc_prep - Prepare taskfile for submission |
624d5c51 TH |
206 | * @qc: Metadata associated with taskfile to be prepared |
207 | * | |
208 | * Prepare ATA taskfile for submission. | |
209 | * | |
210 | * LOCKING: | |
211 | * spin_lock_irqsave(host lock) | |
212 | */ | |
9363c382 | 213 | void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc) |
624d5c51 TH |
214 | { |
215 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
216 | return; | |
217 | ||
218 | ata_fill_sg_dumb(qc); | |
219 | } | |
220 | ||
272f7884 | 221 | /** |
9363c382 | 222 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
223 | * @ap: port where the device is |
224 | * | |
225 | * Reads ATA taskfile status register for currently-selected device | |
226 | * and return its value. This also clears pending interrupts | |
227 | * from this device | |
228 | * | |
229 | * LOCKING: | |
230 | * Inherited from caller. | |
231 | */ | |
9363c382 | 232 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
233 | { |
234 | return ioread8(ap->ioaddr.status_addr); | |
235 | } | |
236 | ||
237 | /** | |
9363c382 | 238 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
239 | * @ap: port where the device is |
240 | * | |
241 | * Reads ATA taskfile alternate status register for | |
242 | * currently-selected device and return its value. | |
243 | * | |
244 | * Note: may NOT be used as the check_altstatus() entry in | |
245 | * ata_port_operations. | |
246 | * | |
247 | * LOCKING: | |
248 | * Inherited from caller. | |
249 | */ | |
a57c1bad | 250 | static u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 251 | { |
5682ed33 TH |
252 | if (ap->ops->sff_check_altstatus) |
253 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
254 | |
255 | return ioread8(ap->ioaddr.altstatus_addr); | |
256 | } | |
257 | ||
a57c1bad AC |
258 | /** |
259 | * ata_sff_irq_status - Check if the device is busy | |
260 | * @ap: port where the device is | |
261 | * | |
262 | * Determine if the port is currently busy. Uses altstatus | |
263 | * if available in order to avoid clearing shared IRQ status | |
264 | * when finding an IRQ source. Non ctl capable devices don't | |
265 | * share interrupt lines fortunately for us. | |
266 | * | |
267 | * LOCKING: | |
268 | * Inherited from caller. | |
269 | */ | |
270 | static u8 ata_sff_irq_status(struct ata_port *ap) | |
271 | { | |
272 | u8 status; | |
273 | ||
274 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
275 | status = ata_sff_altstatus(ap); | |
276 | /* Not us: We are busy */ | |
277 | if (status & ATA_BUSY) | |
278 | return status; | |
279 | } | |
280 | /* Clear INTRQ latch */ | |
6311c90a | 281 | status = ap->ops->sff_check_status(ap); |
a57c1bad AC |
282 | return status; |
283 | } | |
284 | ||
285 | /** | |
286 | * ata_sff_sync - Flush writes | |
287 | * @ap: Port to wait for. | |
288 | * | |
289 | * CAUTION: | |
290 | * If we have an mmio device with no ctl and no altstatus | |
291 | * method this will fail. No such devices are known to exist. | |
292 | * | |
293 | * LOCKING: | |
294 | * Inherited from caller. | |
295 | */ | |
296 | ||
297 | static void ata_sff_sync(struct ata_port *ap) | |
298 | { | |
299 | if (ap->ops->sff_check_altstatus) | |
300 | ap->ops->sff_check_altstatus(ap); | |
301 | else if (ap->ioaddr.altstatus_addr) | |
302 | ioread8(ap->ioaddr.altstatus_addr); | |
303 | } | |
304 | ||
305 | /** | |
306 | * ata_sff_pause - Flush writes and wait 400nS | |
307 | * @ap: Port to pause for. | |
308 | * | |
309 | * CAUTION: | |
310 | * If we have an mmio device with no ctl and no altstatus | |
311 | * method this will fail. No such devices are known to exist. | |
312 | * | |
313 | * LOCKING: | |
314 | * Inherited from caller. | |
315 | */ | |
316 | ||
317 | void ata_sff_pause(struct ata_port *ap) | |
318 | { | |
319 | ata_sff_sync(ap); | |
320 | ndelay(400); | |
321 | } | |
322 | ||
323 | /** | |
324 | * ata_sff_dma_pause - Pause before commencing DMA | |
325 | * @ap: Port to pause for. | |
326 | * | |
327 | * Perform I/O fencing and ensure sufficient cycle delays occur | |
328 | * for the HDMA1:0 transition | |
329 | */ | |
330 | ||
331 | void ata_sff_dma_pause(struct ata_port *ap) | |
332 | { | |
333 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
334 | /* An altstatus read will cause the needed delay without | |
335 | messing up the IRQ status */ | |
336 | ata_sff_altstatus(ap); | |
337 | return; | |
338 | } | |
339 | /* There are no DMA controllers without ctl. BUG here to ensure | |
340 | we never violate the HDMA1:0 transition timing and risk | |
341 | corruption. */ | |
342 | BUG(); | |
343 | } | |
344 | ||
624d5c51 | 345 | /** |
9363c382 | 346 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 TH |
347 | * @ap: port containing status register to be polled |
348 | * @tmout_pat: impatience timeout | |
349 | * @tmout: overall timeout | |
350 | * | |
351 | * Sleep until ATA Status register bit BSY clears, | |
352 | * or a timeout occurs. | |
353 | * | |
354 | * LOCKING: | |
355 | * Kernel thread context (may sleep). | |
356 | * | |
357 | * RETURNS: | |
358 | * 0 on success, -errno otherwise. | |
359 | */ | |
9363c382 TH |
360 | int ata_sff_busy_sleep(struct ata_port *ap, |
361 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
362 | { |
363 | unsigned long timer_start, timeout; | |
364 | u8 status; | |
365 | ||
9363c382 | 366 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 TH |
367 | timer_start = jiffies; |
368 | timeout = timer_start + tmout_pat; | |
369 | while (status != 0xff && (status & ATA_BUSY) && | |
370 | time_before(jiffies, timeout)) { | |
371 | msleep(50); | |
9363c382 | 372 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
373 | } |
374 | ||
375 | if (status != 0xff && (status & ATA_BUSY)) | |
376 | ata_port_printk(ap, KERN_WARNING, | |
377 | "port is slow to respond, please be patient " | |
378 | "(Status 0x%x)\n", status); | |
379 | ||
380 | timeout = timer_start + tmout; | |
381 | while (status != 0xff && (status & ATA_BUSY) && | |
382 | time_before(jiffies, timeout)) { | |
383 | msleep(50); | |
5682ed33 | 384 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
385 | } |
386 | ||
387 | if (status == 0xff) | |
388 | return -ENODEV; | |
389 | ||
390 | if (status & ATA_BUSY) { | |
391 | ata_port_printk(ap, KERN_ERR, "port failed to respond " | |
392 | "(%lu secs, Status 0x%x)\n", | |
393 | tmout / HZ, status); | |
394 | return -EBUSY; | |
395 | } | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
aa2731ad TH |
400 | static int ata_sff_check_ready(struct ata_link *link) |
401 | { | |
402 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
403 | ||
78ab88f0 | 404 | return ata_check_ready(status); |
aa2731ad TH |
405 | } |
406 | ||
624d5c51 | 407 | /** |
9363c382 | 408 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 409 | * @link: SFF link to wait ready status for |
624d5c51 TH |
410 | * @deadline: deadline jiffies for the operation |
411 | * | |
412 | * Sleep until ATA Status register bit BSY clears, or timeout | |
413 | * occurs. | |
414 | * | |
415 | * LOCKING: | |
416 | * Kernel thread context (may sleep). | |
417 | * | |
418 | * RETURNS: | |
419 | * 0 on success, -errno otherwise. | |
420 | */ | |
705e76be | 421 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 422 | { |
aa2731ad | 423 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 TH |
424 | } |
425 | ||
426 | /** | |
9363c382 | 427 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
428 | * @ap: ATA channel to manipulate |
429 | * @device: ATA device (numbered from zero) to select | |
430 | * | |
431 | * Use the method defined in the ATA specification to | |
432 | * make either device 0, or device 1, active on the | |
433 | * ATA channel. Works with both PIO and MMIO. | |
434 | * | |
435 | * May be used as the dev_select() entry in ata_port_operations. | |
436 | * | |
437 | * LOCKING: | |
438 | * caller. | |
439 | */ | |
9363c382 | 440 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
441 | { |
442 | u8 tmp; | |
443 | ||
444 | if (device == 0) | |
445 | tmp = ATA_DEVICE_OBS; | |
446 | else | |
447 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
448 | ||
449 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 450 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 TH |
451 | } |
452 | ||
453 | /** | |
454 | * ata_dev_select - Select device 0/1 on ATA bus | |
455 | * @ap: ATA channel to manipulate | |
456 | * @device: ATA device (numbered from zero) to select | |
457 | * @wait: non-zero to wait for Status register BSY bit to clear | |
458 | * @can_sleep: non-zero if context allows sleeping | |
459 | * | |
460 | * Use the method defined in the ATA specification to | |
461 | * make either device 0, or device 1, active on the | |
462 | * ATA channel. | |
463 | * | |
9363c382 TH |
464 | * This is a high-level version of ata_sff_dev_select(), which |
465 | * additionally provides the services of inserting the proper | |
466 | * pauses and status polling, where needed. | |
624d5c51 TH |
467 | * |
468 | * LOCKING: | |
469 | * caller. | |
470 | */ | |
471 | void ata_dev_select(struct ata_port *ap, unsigned int device, | |
472 | unsigned int wait, unsigned int can_sleep) | |
473 | { | |
474 | if (ata_msg_probe(ap)) | |
475 | ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, " | |
476 | "device %u, wait %u\n", device, wait); | |
477 | ||
478 | if (wait) | |
479 | ata_wait_idle(ap); | |
480 | ||
5682ed33 | 481 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
482 | |
483 | if (wait) { | |
484 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
485 | msleep(150); | |
486 | ata_wait_idle(ap); | |
487 | } | |
488 | } | |
489 | ||
490 | /** | |
9363c382 | 491 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
492 | * @ap: Port on which interrupts are enabled. |
493 | * | |
494 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
495 | * wait for idle, clear any pending interrupts. | |
496 | * | |
497 | * LOCKING: | |
498 | * Inherited from caller. | |
499 | */ | |
9363c382 | 500 | u8 ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
501 | { |
502 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
503 | u8 tmp; | |
504 | ||
505 | ap->ctl &= ~ATA_NIEN; | |
506 | ap->last_ctl = ap->ctl; | |
507 | ||
508 | if (ioaddr->ctl_addr) | |
509 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
510 | tmp = ata_wait_idle(ap); | |
511 | ||
5682ed33 | 512 | ap->ops->sff_irq_clear(ap); |
624d5c51 TH |
513 | |
514 | return tmp; | |
515 | } | |
516 | ||
517 | /** | |
9363c382 | 518 | * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt. |
624d5c51 TH |
519 | * @ap: Port associated with this ATA transaction. |
520 | * | |
521 | * Clear interrupt and error flags in DMA status register. | |
522 | * | |
523 | * May be used as the irq_clear() entry in ata_port_operations. | |
524 | * | |
525 | * LOCKING: | |
526 | * spin_lock_irqsave(host lock) | |
527 | */ | |
9363c382 | 528 | void ata_sff_irq_clear(struct ata_port *ap) |
624d5c51 TH |
529 | { |
530 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
531 | ||
532 | if (!mmio) | |
533 | return; | |
534 | ||
535 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
536 | } | |
537 | ||
538 | /** | |
9363c382 | 539 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
540 | * @ap: Port to which output is sent |
541 | * @tf: ATA taskfile register set | |
542 | * | |
543 | * Outputs ATA taskfile to standard ATA host controller. | |
544 | * | |
545 | * LOCKING: | |
546 | * Inherited from caller. | |
547 | */ | |
9363c382 | 548 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
549 | { |
550 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
551 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
552 | ||
553 | if (tf->ctl != ap->last_ctl) { | |
554 | if (ioaddr->ctl_addr) | |
555 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
556 | ap->last_ctl = tf->ctl; | |
557 | ata_wait_idle(ap); | |
558 | } | |
559 | ||
560 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
561 | WARN_ON(!ioaddr->ctl_addr); | |
562 | iowrite8(tf->hob_feature, ioaddr->feature_addr); | |
563 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
564 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
565 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
566 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
567 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
568 | tf->hob_feature, | |
569 | tf->hob_nsect, | |
570 | tf->hob_lbal, | |
571 | tf->hob_lbam, | |
572 | tf->hob_lbah); | |
573 | } | |
574 | ||
575 | if (is_addr) { | |
576 | iowrite8(tf->feature, ioaddr->feature_addr); | |
577 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
578 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
579 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
580 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
581 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
582 | tf->feature, | |
583 | tf->nsect, | |
584 | tf->lbal, | |
585 | tf->lbam, | |
586 | tf->lbah); | |
587 | } | |
588 | ||
589 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
590 | iowrite8(tf->device, ioaddr->device_addr); | |
591 | VPRINTK("device 0x%X\n", tf->device); | |
592 | } | |
593 | ||
594 | ata_wait_idle(ap); | |
595 | } | |
596 | ||
597 | /** | |
9363c382 | 598 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
599 | * @ap: Port from which input is read |
600 | * @tf: ATA taskfile register set for storing input | |
601 | * | |
602 | * Reads ATA taskfile registers for currently-selected device | |
603 | * into @tf. Assumes the device has a fully SFF compliant task file | |
604 | * layout and behaviour. If you device does not (eg has a different | |
605 | * status method) then you will need to provide a replacement tf_read | |
606 | * | |
607 | * LOCKING: | |
608 | * Inherited from caller. | |
609 | */ | |
9363c382 | 610 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
611 | { |
612 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
613 | ||
9363c382 | 614 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
615 | tf->feature = ioread8(ioaddr->error_addr); |
616 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
617 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
618 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
619 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
620 | tf->device = ioread8(ioaddr->device_addr); | |
621 | ||
622 | if (tf->flags & ATA_TFLAG_LBA48) { | |
623 | if (likely(ioaddr->ctl_addr)) { | |
624 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
625 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
626 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
627 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
628 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
629 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
630 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
631 | ap->last_ctl = tf->ctl; | |
632 | } else | |
633 | WARN_ON(1); | |
634 | } | |
635 | } | |
636 | ||
637 | /** | |
9363c382 | 638 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
639 | * @ap: port to which command is being issued |
640 | * @tf: ATA taskfile register set | |
641 | * | |
642 | * Issues ATA command, with proper synchronization with interrupt | |
643 | * handler / other threads. | |
644 | * | |
645 | * LOCKING: | |
646 | * spin_lock_irqsave(host lock) | |
647 | */ | |
9363c382 | 648 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
649 | { |
650 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
651 | ||
652 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 653 | ata_sff_pause(ap); |
624d5c51 TH |
654 | } |
655 | ||
656 | /** | |
657 | * ata_tf_to_host - issue ATA taskfile to host controller | |
658 | * @ap: port to which command is being issued | |
659 | * @tf: ATA taskfile register set | |
660 | * | |
661 | * Issues ATA taskfile register set to ATA host controller, | |
662 | * with proper synchronization with interrupt handler and | |
663 | * other threads. | |
664 | * | |
665 | * LOCKING: | |
666 | * spin_lock_irqsave(host lock) | |
667 | */ | |
668 | static inline void ata_tf_to_host(struct ata_port *ap, | |
669 | const struct ata_taskfile *tf) | |
670 | { | |
5682ed33 TH |
671 | ap->ops->sff_tf_load(ap, tf); |
672 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
673 | } |
674 | ||
675 | /** | |
9363c382 | 676 | * ata_sff_data_xfer - Transfer data by PIO |
624d5c51 TH |
677 | * @dev: device to target |
678 | * @buf: data buffer | |
679 | * @buflen: buffer length | |
680 | * @rw: read/write | |
681 | * | |
682 | * Transfer data from/to the device data register by PIO. | |
683 | * | |
684 | * LOCKING: | |
685 | * Inherited from caller. | |
686 | * | |
687 | * RETURNS: | |
688 | * Bytes consumed. | |
689 | */ | |
9363c382 TH |
690 | unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, |
691 | unsigned int buflen, int rw) | |
624d5c51 TH |
692 | { |
693 | struct ata_port *ap = dev->link->ap; | |
694 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
695 | unsigned int words = buflen >> 1; | |
696 | ||
697 | /* Transfer multiple of 2 bytes */ | |
698 | if (rw == READ) | |
699 | ioread16_rep(data_addr, buf, words); | |
700 | else | |
701 | iowrite16_rep(data_addr, buf, words); | |
702 | ||
703 | /* Transfer trailing 1 byte, if any. */ | |
704 | if (unlikely(buflen & 0x01)) { | |
705 | __le16 align_buf[1] = { 0 }; | |
706 | unsigned char *trailing_buf = buf + buflen - 1; | |
707 | ||
708 | if (rw == READ) { | |
709 | align_buf[0] = cpu_to_le16(ioread16(data_addr)); | |
710 | memcpy(trailing_buf, align_buf, 1); | |
711 | } else { | |
712 | memcpy(align_buf, trailing_buf, 1); | |
713 | iowrite16(le16_to_cpu(align_buf[0]), data_addr); | |
714 | } | |
715 | words++; | |
716 | } | |
717 | ||
718 | return words << 1; | |
719 | } | |
720 | ||
721 | /** | |
9363c382 | 722 | * ata_sff_data_xfer_noirq - Transfer data by PIO |
624d5c51 TH |
723 | * @dev: device to target |
724 | * @buf: data buffer | |
725 | * @buflen: buffer length | |
726 | * @rw: read/write | |
727 | * | |
728 | * Transfer data from/to the device data register by PIO. Do the | |
729 | * transfer with interrupts disabled. | |
730 | * | |
731 | * LOCKING: | |
732 | * Inherited from caller. | |
733 | * | |
734 | * RETURNS: | |
735 | * Bytes consumed. | |
736 | */ | |
9363c382 TH |
737 | unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, |
738 | unsigned int buflen, int rw) | |
624d5c51 TH |
739 | { |
740 | unsigned long flags; | |
741 | unsigned int consumed; | |
742 | ||
743 | local_irq_save(flags); | |
9363c382 | 744 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); |
624d5c51 TH |
745 | local_irq_restore(flags); |
746 | ||
747 | return consumed; | |
748 | } | |
749 | ||
750 | /** | |
751 | * ata_pio_sector - Transfer a sector of data. | |
752 | * @qc: Command on going | |
753 | * | |
754 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
755 | * | |
756 | * LOCKING: | |
757 | * Inherited from caller. | |
758 | */ | |
759 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
760 | { | |
761 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
762 | struct ata_port *ap = qc->ap; | |
763 | struct page *page; | |
764 | unsigned int offset; | |
765 | unsigned char *buf; | |
766 | ||
767 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
768 | ap->hsm_task_state = HSM_ST_LAST; | |
769 | ||
770 | page = sg_page(qc->cursg); | |
771 | offset = qc->cursg->offset + qc->cursg_ofs; | |
772 | ||
773 | /* get the current page and offset */ | |
774 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
775 | offset %= PAGE_SIZE; | |
776 | ||
777 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
778 | ||
779 | if (PageHighMem(page)) { | |
780 | unsigned long flags; | |
781 | ||
782 | /* FIXME: use a bounce buffer */ | |
783 | local_irq_save(flags); | |
784 | buf = kmap_atomic(page, KM_IRQ0); | |
785 | ||
786 | /* do the actual data transfer */ | |
5682ed33 TH |
787 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
788 | do_write); | |
624d5c51 TH |
789 | |
790 | kunmap_atomic(buf, KM_IRQ0); | |
791 | local_irq_restore(flags); | |
792 | } else { | |
793 | buf = page_address(page); | |
5682ed33 TH |
794 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
795 | do_write); | |
624d5c51 TH |
796 | } |
797 | ||
798 | qc->curbytes += qc->sect_size; | |
799 | qc->cursg_ofs += qc->sect_size; | |
800 | ||
801 | if (qc->cursg_ofs == qc->cursg->length) { | |
802 | qc->cursg = sg_next(qc->cursg); | |
803 | qc->cursg_ofs = 0; | |
804 | } | |
805 | } | |
806 | ||
807 | /** | |
808 | * ata_pio_sectors - Transfer one or many sectors. | |
809 | * @qc: Command on going | |
810 | * | |
811 | * Transfer one or many sectors of data from/to the | |
812 | * ATA device for the DRQ request. | |
813 | * | |
814 | * LOCKING: | |
815 | * Inherited from caller. | |
816 | */ | |
817 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
818 | { | |
819 | if (is_multi_taskfile(&qc->tf)) { | |
820 | /* READ/WRITE MULTIPLE */ | |
821 | unsigned int nsect; | |
822 | ||
823 | WARN_ON(qc->dev->multi_count == 0); | |
824 | ||
825 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
826 | qc->dev->multi_count); | |
827 | while (nsect--) | |
828 | ata_pio_sector(qc); | |
829 | } else | |
830 | ata_pio_sector(qc); | |
831 | ||
a57c1bad | 832 | ata_sff_sync(qc->ap); /* flush */ |
624d5c51 TH |
833 | } |
834 | ||
835 | /** | |
836 | * atapi_send_cdb - Write CDB bytes to hardware | |
837 | * @ap: Port to which ATAPI device is attached. | |
838 | * @qc: Taskfile currently active | |
839 | * | |
840 | * When device has indicated its readiness to accept | |
841 | * a CDB, this function is called. Send the CDB. | |
842 | * | |
843 | * LOCKING: | |
844 | * caller. | |
845 | */ | |
846 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
847 | { | |
848 | /* send SCSI cdb */ | |
849 | DPRINTK("send cdb\n"); | |
850 | WARN_ON(qc->dev->cdb_len < 12); | |
851 | ||
5682ed33 | 852 | ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); |
a57c1bad AC |
853 | ata_sff_sync(ap); |
854 | /* FIXME: If the CDB is for DMA do we need to do the transition delay | |
855 | or is bmdma_start guaranteed to do it ? */ | |
624d5c51 TH |
856 | switch (qc->tf.protocol) { |
857 | case ATAPI_PROT_PIO: | |
858 | ap->hsm_task_state = HSM_ST; | |
859 | break; | |
860 | case ATAPI_PROT_NODATA: | |
861 | ap->hsm_task_state = HSM_ST_LAST; | |
862 | break; | |
863 | case ATAPI_PROT_DMA: | |
864 | ap->hsm_task_state = HSM_ST_LAST; | |
865 | /* initiate bmdma */ | |
866 | ap->ops->bmdma_start(qc); | |
867 | break; | |
868 | } | |
869 | } | |
870 | ||
871 | /** | |
872 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
873 | * @qc: Command on going | |
874 | * @bytes: number of bytes | |
875 | * | |
876 | * Transfer Transfer data from/to the ATAPI device. | |
877 | * | |
878 | * LOCKING: | |
879 | * Inherited from caller. | |
880 | * | |
881 | */ | |
882 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
883 | { | |
884 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
885 | struct ata_port *ap = qc->ap; | |
886 | struct ata_device *dev = qc->dev; | |
887 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
888 | struct scatterlist *sg; | |
889 | struct page *page; | |
890 | unsigned char *buf; | |
891 | unsigned int offset, count, consumed; | |
892 | ||
893 | next_sg: | |
894 | sg = qc->cursg; | |
895 | if (unlikely(!sg)) { | |
896 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
897 | "buf=%u cur=%u bytes=%u", | |
898 | qc->nbytes, qc->curbytes, bytes); | |
899 | return -1; | |
900 | } | |
901 | ||
902 | page = sg_page(sg); | |
903 | offset = sg->offset + qc->cursg_ofs; | |
904 | ||
905 | /* get the current page and offset */ | |
906 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
907 | offset %= PAGE_SIZE; | |
908 | ||
909 | /* don't overrun current sg */ | |
910 | count = min(sg->length - qc->cursg_ofs, bytes); | |
911 | ||
912 | /* don't cross page boundaries */ | |
913 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
914 | ||
915 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
916 | ||
917 | if (PageHighMem(page)) { | |
918 | unsigned long flags; | |
919 | ||
920 | /* FIXME: use bounce buffer */ | |
921 | local_irq_save(flags); | |
922 | buf = kmap_atomic(page, KM_IRQ0); | |
923 | ||
924 | /* do the actual data transfer */ | |
5682ed33 | 925 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); |
624d5c51 TH |
926 | |
927 | kunmap_atomic(buf, KM_IRQ0); | |
928 | local_irq_restore(flags); | |
929 | } else { | |
930 | buf = page_address(page); | |
5682ed33 | 931 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, count, rw); |
624d5c51 TH |
932 | } |
933 | ||
934 | bytes -= min(bytes, consumed); | |
935 | qc->curbytes += count; | |
936 | qc->cursg_ofs += count; | |
937 | ||
938 | if (qc->cursg_ofs == sg->length) { | |
939 | qc->cursg = sg_next(qc->cursg); | |
940 | qc->cursg_ofs = 0; | |
941 | } | |
942 | ||
943 | /* consumed can be larger than count only for the last transfer */ | |
944 | WARN_ON(qc->cursg && count != consumed); | |
945 | ||
946 | if (bytes) | |
947 | goto next_sg; | |
948 | return 0; | |
949 | } | |
950 | ||
951 | /** | |
952 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
953 | * @qc: Command on going | |
954 | * | |
955 | * Transfer Transfer data from/to the ATAPI device. | |
956 | * | |
957 | * LOCKING: | |
958 | * Inherited from caller. | |
959 | */ | |
960 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
961 | { | |
962 | struct ata_port *ap = qc->ap; | |
963 | struct ata_device *dev = qc->dev; | |
964 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
965 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
966 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
967 | ||
968 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
969 | * here to save some kernel stack usage. | |
970 | * For normal completion, qc->result_tf is not relevant. For | |
971 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
972 | * So, the correctness of qc->result_tf is not affected. | |
973 | */ | |
5682ed33 | 974 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
975 | ireason = qc->result_tf.nsect; |
976 | bc_lo = qc->result_tf.lbam; | |
977 | bc_hi = qc->result_tf.lbah; | |
978 | bytes = (bc_hi << 8) | bc_lo; | |
979 | ||
980 | /* shall be cleared to zero, indicating xfer of data */ | |
981 | if (unlikely(ireason & (1 << 0))) | |
982 | goto atapi_check; | |
983 | ||
984 | /* make sure transfer direction matches expected */ | |
985 | i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; | |
986 | if (unlikely(do_write != i_write)) | |
987 | goto atapi_check; | |
988 | ||
989 | if (unlikely(!bytes)) | |
990 | goto atapi_check; | |
991 | ||
992 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
993 | ||
994 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
995 | goto err_out; | |
a57c1bad | 996 | ata_sff_sync(ap); /* flush */ |
624d5c51 TH |
997 | |
998 | return; | |
999 | ||
1000 | atapi_check: | |
1001 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
1002 | ireason, bytes); | |
1003 | err_out: | |
1004 | qc->err_mask |= AC_ERR_HSM; | |
1005 | ap->hsm_task_state = HSM_ST_ERR; | |
1006 | } | |
1007 | ||
1008 | /** | |
1009 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
1010 | * @ap: the target ata_port | |
1011 | * @qc: qc on going | |
1012 | * | |
1013 | * RETURNS: | |
1014 | * 1 if ok in workqueue, 0 otherwise. | |
1015 | */ | |
1016 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc) | |
1017 | { | |
1018 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1019 | return 1; | |
1020 | ||
1021 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
1022 | if (qc->tf.protocol == ATA_PROT_PIO && | |
1023 | (qc->tf.flags & ATA_TFLAG_WRITE)) | |
1024 | return 1; | |
1025 | ||
1026 | if (ata_is_atapi(qc->tf.protocol) && | |
1027 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1028 | return 1; | |
1029 | } | |
1030 | ||
1031 | return 0; | |
1032 | } | |
1033 | ||
1034 | /** | |
1035 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
1036 | * @qc: Command to complete | |
1037 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1038 | * | |
1039 | * Finish @qc which is running on standard HSM. | |
1040 | * | |
1041 | * LOCKING: | |
1042 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
1043 | * Otherwise, none on entry and grabs host lock. | |
1044 | */ | |
1045 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
1046 | { | |
1047 | struct ata_port *ap = qc->ap; | |
1048 | unsigned long flags; | |
1049 | ||
1050 | if (ap->ops->error_handler) { | |
1051 | if (in_wq) { | |
1052 | spin_lock_irqsave(ap->lock, flags); | |
1053 | ||
1054 | /* EH might have kicked in while host lock is | |
1055 | * released. | |
1056 | */ | |
1057 | qc = ata_qc_from_tag(ap, qc->tag); | |
1058 | if (qc) { | |
1059 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
5682ed33 | 1060 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
1061 | ata_qc_complete(qc); |
1062 | } else | |
1063 | ata_port_freeze(ap); | |
1064 | } | |
1065 | ||
1066 | spin_unlock_irqrestore(ap->lock, flags); | |
1067 | } else { | |
1068 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
1069 | ata_qc_complete(qc); | |
1070 | else | |
1071 | ata_port_freeze(ap); | |
1072 | } | |
1073 | } else { | |
1074 | if (in_wq) { | |
1075 | spin_lock_irqsave(ap->lock, flags); | |
5682ed33 | 1076 | ap->ops->sff_irq_on(ap); |
624d5c51 TH |
1077 | ata_qc_complete(qc); |
1078 | spin_unlock_irqrestore(ap->lock, flags); | |
1079 | } else | |
1080 | ata_qc_complete(qc); | |
1081 | } | |
1082 | } | |
1083 | ||
1084 | /** | |
9363c382 | 1085 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
1086 | * @ap: the target ata_port |
1087 | * @qc: qc on going | |
1088 | * @status: current device status | |
1089 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1090 | * | |
1091 | * RETURNS: | |
1092 | * 1 when poll next status needed, 0 otherwise. | |
1093 | */ | |
9363c382 TH |
1094 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
1095 | u8 status, int in_wq) | |
624d5c51 | 1096 | { |
a836d3e8 | 1097 | struct ata_eh_info *ehi = &ap->link.eh_info; |
624d5c51 TH |
1098 | unsigned long flags = 0; |
1099 | int poll_next; | |
1100 | ||
1101 | WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0); | |
1102 | ||
9363c382 | 1103 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
1104 | * like DMA polling into the workqueue. Notice that |
1105 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
1106 | */ | |
1107 | WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc)); | |
1108 | ||
1109 | fsm_start: | |
1110 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
1111 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
1112 | ||
1113 | switch (ap->hsm_task_state) { | |
1114 | case HSM_ST_FIRST: | |
1115 | /* Send first data block or PACKET CDB */ | |
1116 | ||
1117 | /* If polling, we will stay in the work queue after | |
1118 | * sending the data. Otherwise, interrupt handler | |
1119 | * takes over after sending the data. | |
1120 | */ | |
1121 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
1122 | ||
1123 | /* check device status */ | |
1124 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1125 | /* handle BSY=0, DRQ=0 as error */ | |
1126 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1127 | /* device stops HSM for abort/error */ | |
1128 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 1129 | else { |
624d5c51 | 1130 | /* HSM violation. Let EH handle this */ |
a836d3e8 TH |
1131 | ata_ehi_push_desc(ehi, |
1132 | "ST_FIRST: !(DRQ|ERR|DF)"); | |
624d5c51 | 1133 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1134 | } |
624d5c51 TH |
1135 | |
1136 | ap->hsm_task_state = HSM_ST_ERR; | |
1137 | goto fsm_start; | |
1138 | } | |
1139 | ||
1140 | /* Device should not ask for data transfer (DRQ=1) | |
1141 | * when it finds something wrong. | |
1142 | * We ignore DRQ here and stop the HSM by | |
1143 | * changing hsm_task_state to HSM_ST_ERR and | |
1144 | * let the EH abort the command or reset the device. | |
1145 | */ | |
1146 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1147 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1148 | * when doing the next command (mostly request sense). | |
1149 | * We ignore ERR here to workaround and proceed sending | |
1150 | * the CDB. | |
1151 | */ | |
1152 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
a836d3e8 TH |
1153 | ata_ehi_push_desc(ehi, "ST_FIRST: " |
1154 | "DRQ=1 with device error, " | |
1155 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1156 | qc->err_mask |= AC_ERR_HSM; |
1157 | ap->hsm_task_state = HSM_ST_ERR; | |
1158 | goto fsm_start; | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | /* Send the CDB (atapi) or the first data block (ata pio out). | |
1163 | * During the state transition, interrupt handler shouldn't | |
1164 | * be invoked before the data transfer is complete and | |
1165 | * hsm_task_state is changed. Hence, the following locking. | |
1166 | */ | |
1167 | if (in_wq) | |
1168 | spin_lock_irqsave(ap->lock, flags); | |
1169 | ||
1170 | if (qc->tf.protocol == ATA_PROT_PIO) { | |
1171 | /* PIO data out protocol. | |
1172 | * send first data block. | |
1173 | */ | |
1174 | ||
1175 | /* ata_pio_sectors() might change the state | |
1176 | * to HSM_ST_LAST. so, the state is changed here | |
1177 | * before ata_pio_sectors(). | |
1178 | */ | |
1179 | ap->hsm_task_state = HSM_ST; | |
1180 | ata_pio_sectors(qc); | |
1181 | } else | |
1182 | /* send CDB */ | |
1183 | atapi_send_cdb(ap, qc); | |
1184 | ||
1185 | if (in_wq) | |
1186 | spin_unlock_irqrestore(ap->lock, flags); | |
1187 | ||
1188 | /* if polling, ata_pio_task() handles the rest. | |
1189 | * otherwise, interrupt handler takes over from here. | |
1190 | */ | |
1191 | break; | |
1192 | ||
1193 | case HSM_ST: | |
1194 | /* complete command or read/write the data register */ | |
1195 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1196 | /* ATAPI PIO protocol */ | |
1197 | if ((status & ATA_DRQ) == 0) { | |
1198 | /* No more data to transfer or device error. | |
1199 | * Device error will be tagged in HSM_ST_LAST. | |
1200 | */ | |
1201 | ap->hsm_task_state = HSM_ST_LAST; | |
1202 | goto fsm_start; | |
1203 | } | |
1204 | ||
1205 | /* Device should not ask for data transfer (DRQ=1) | |
1206 | * when it finds something wrong. | |
1207 | * We ignore DRQ here and stop the HSM by | |
1208 | * changing hsm_task_state to HSM_ST_ERR and | |
1209 | * let the EH abort the command or reset the device. | |
1210 | */ | |
1211 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
a836d3e8 TH |
1212 | ata_ehi_push_desc(ehi, "ST-ATAPI: " |
1213 | "DRQ=1 with device error, " | |
1214 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1215 | qc->err_mask |= AC_ERR_HSM; |
1216 | ap->hsm_task_state = HSM_ST_ERR; | |
1217 | goto fsm_start; | |
1218 | } | |
1219 | ||
1220 | atapi_pio_bytes(qc); | |
1221 | ||
1222 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1223 | /* bad ireason reported by device */ | |
1224 | goto fsm_start; | |
1225 | ||
1226 | } else { | |
1227 | /* ATA PIO protocol */ | |
1228 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1229 | /* handle BSY=0, DRQ=0 as error */ | |
1230 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1231 | /* device stops HSM for abort/error */ | |
1232 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 1233 | else { |
624d5c51 TH |
1234 | /* HSM violation. Let EH handle this. |
1235 | * Phantom devices also trigger this | |
1236 | * condition. Mark hint. | |
1237 | */ | |
a836d3e8 TH |
1238 | ata_ehi_push_desc(ehi, "ST-ATA: " |
1239 | "DRQ=1 with device error, " | |
1240 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1241 | qc->err_mask |= AC_ERR_HSM | |
1242 | AC_ERR_NODEV_HINT; | |
a836d3e8 | 1243 | } |
624d5c51 TH |
1244 | |
1245 | ap->hsm_task_state = HSM_ST_ERR; | |
1246 | goto fsm_start; | |
1247 | } | |
1248 | ||
1249 | /* For PIO reads, some devices may ask for | |
1250 | * data transfer (DRQ=1) alone with ERR=1. | |
1251 | * We respect DRQ here and transfer one | |
1252 | * block of junk data before changing the | |
1253 | * hsm_task_state to HSM_ST_ERR. | |
1254 | * | |
1255 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1256 | * sense since the data block has been | |
1257 | * transferred to the device. | |
1258 | */ | |
1259 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1260 | /* data might be corrputed */ | |
1261 | qc->err_mask |= AC_ERR_DEV; | |
1262 | ||
1263 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1264 | ata_pio_sectors(qc); | |
1265 | status = ata_wait_idle(ap); | |
1266 | } | |
1267 | ||
a836d3e8 TH |
1268 | if (status & (ATA_BUSY | ATA_DRQ)) { |
1269 | ata_ehi_push_desc(ehi, "ST-ATA: " | |
1270 | "BUSY|DRQ persists on ERR|DF, " | |
1271 | "dev_stat 0x%X", status); | |
624d5c51 | 1272 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1273 | } |
624d5c51 TH |
1274 | |
1275 | /* ata_pio_sectors() might change the | |
1276 | * state to HSM_ST_LAST. so, the state | |
1277 | * is changed after ata_pio_sectors(). | |
1278 | */ | |
1279 | ap->hsm_task_state = HSM_ST_ERR; | |
1280 | goto fsm_start; | |
1281 | } | |
1282 | ||
1283 | ata_pio_sectors(qc); | |
1284 | ||
1285 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1286 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1287 | /* all data read */ | |
1288 | status = ata_wait_idle(ap); | |
1289 | goto fsm_start; | |
1290 | } | |
1291 | } | |
1292 | ||
1293 | poll_next = 1; | |
1294 | break; | |
1295 | ||
1296 | case HSM_ST_LAST: | |
1297 | if (unlikely(!ata_ok(status))) { | |
1298 | qc->err_mask |= __ac_err_mask(status); | |
1299 | ap->hsm_task_state = HSM_ST_ERR; | |
1300 | goto fsm_start; | |
1301 | } | |
1302 | ||
1303 | /* no more data to transfer */ | |
1304 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1305 | ap->print_id, qc->dev->devno, status); | |
1306 | ||
411cb386 | 1307 | WARN_ON(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); |
624d5c51 TH |
1308 | |
1309 | ap->hsm_task_state = HSM_ST_IDLE; | |
1310 | ||
1311 | /* complete taskfile transaction */ | |
1312 | ata_hsm_qc_complete(qc, in_wq); | |
1313 | ||
1314 | poll_next = 0; | |
1315 | break; | |
1316 | ||
1317 | case HSM_ST_ERR: | |
1318 | /* make sure qc->err_mask is available to | |
1319 | * know what's wrong and recover | |
1320 | */ | |
411cb386 | 1321 | WARN_ON(!(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM))); |
624d5c51 TH |
1322 | |
1323 | ap->hsm_task_state = HSM_ST_IDLE; | |
1324 | ||
1325 | /* complete taskfile transaction */ | |
1326 | ata_hsm_qc_complete(qc, in_wq); | |
1327 | ||
1328 | poll_next = 0; | |
1329 | break; | |
1330 | default: | |
1331 | poll_next = 0; | |
1332 | BUG(); | |
1333 | } | |
1334 | ||
1335 | return poll_next; | |
1336 | } | |
1337 | ||
1338 | void ata_pio_task(struct work_struct *work) | |
1339 | { | |
1340 | struct ata_port *ap = | |
1341 | container_of(work, struct ata_port, port_task.work); | |
1342 | struct ata_queued_cmd *qc = ap->port_task_data; | |
1343 | u8 status; | |
1344 | int poll_next; | |
1345 | ||
1346 | fsm_start: | |
1347 | WARN_ON(ap->hsm_task_state == HSM_ST_IDLE); | |
1348 | ||
1349 | /* | |
1350 | * This is purely heuristic. This is a fast path. | |
1351 | * Sometimes when we enter, BSY will be cleared in | |
1352 | * a chk-status or two. If not, the drive is probably seeking | |
1353 | * or something. Snooze for a couple msecs, then | |
1354 | * chk-status again. If still busy, queue delayed work. | |
1355 | */ | |
9363c382 | 1356 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 TH |
1357 | if (status & ATA_BUSY) { |
1358 | msleep(2); | |
9363c382 | 1359 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 TH |
1360 | if (status & ATA_BUSY) { |
1361 | ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE); | |
1362 | return; | |
1363 | } | |
1364 | } | |
1365 | ||
1366 | /* move the HSM */ | |
9363c382 | 1367 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1368 | |
1369 | /* another command or interrupt handler | |
1370 | * may be running at this point. | |
1371 | */ | |
1372 | if (poll_next) | |
1373 | goto fsm_start; | |
1374 | } | |
1375 | ||
1376 | /** | |
9363c382 | 1377 | * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner |
624d5c51 TH |
1378 | * @qc: command to issue to device |
1379 | * | |
1380 | * Using various libata functions and hooks, this function | |
1381 | * starts an ATA command. ATA commands are grouped into | |
1382 | * classes called "protocols", and issuing each type of protocol | |
1383 | * is slightly different. | |
1384 | * | |
1385 | * May be used as the qc_issue() entry in ata_port_operations. | |
1386 | * | |
1387 | * LOCKING: | |
1388 | * spin_lock_irqsave(host lock) | |
1389 | * | |
1390 | * RETURNS: | |
1391 | * Zero on success, AC_ERR_* mask on failure | |
1392 | */ | |
9363c382 | 1393 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1394 | { |
1395 | struct ata_port *ap = qc->ap; | |
1396 | ||
1397 | /* Use polling pio if the LLD doesn't handle | |
1398 | * interrupt driven pio and atapi CDB interrupt. | |
1399 | */ | |
1400 | if (ap->flags & ATA_FLAG_PIO_POLLING) { | |
1401 | switch (qc->tf.protocol) { | |
1402 | case ATA_PROT_PIO: | |
1403 | case ATA_PROT_NODATA: | |
1404 | case ATAPI_PROT_PIO: | |
1405 | case ATAPI_PROT_NODATA: | |
1406 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
1407 | break; | |
1408 | case ATAPI_PROT_DMA: | |
1409 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
1410 | /* see ata_dma_blacklisted() */ | |
1411 | BUG(); | |
1412 | break; | |
1413 | default: | |
1414 | break; | |
1415 | } | |
1416 | } | |
1417 | ||
1418 | /* select the device */ | |
1419 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1420 | ||
1421 | /* start the command */ | |
1422 | switch (qc->tf.protocol) { | |
1423 | case ATA_PROT_NODATA: | |
1424 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1425 | ata_qc_set_polling(qc); | |
1426 | ||
1427 | ata_tf_to_host(ap, &qc->tf); | |
1428 | ap->hsm_task_state = HSM_ST_LAST; | |
1429 | ||
1430 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1431 | ata_pio_queue_task(ap, qc, 0); | |
1432 | ||
1433 | break; | |
1434 | ||
1435 | case ATA_PROT_DMA: | |
1436 | WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); | |
1437 | ||
5682ed33 | 1438 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1439 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1440 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
1441 | ap->hsm_task_state = HSM_ST_LAST; | |
1442 | break; | |
1443 | ||
1444 | case ATA_PROT_PIO: | |
1445 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1446 | ata_qc_set_polling(qc); | |
1447 | ||
1448 | ata_tf_to_host(ap, &qc->tf); | |
1449 | ||
1450 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1451 | /* PIO data out protocol */ | |
1452 | ap->hsm_task_state = HSM_ST_FIRST; | |
1453 | ata_pio_queue_task(ap, qc, 0); | |
1454 | ||
1455 | /* always send first data block using | |
1456 | * the ata_pio_task() codepath. | |
1457 | */ | |
1458 | } else { | |
1459 | /* PIO data in protocol */ | |
1460 | ap->hsm_task_state = HSM_ST; | |
1461 | ||
1462 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1463 | ata_pio_queue_task(ap, qc, 0); | |
1464 | ||
1465 | /* if polling, ata_pio_task() handles the rest. | |
1466 | * otherwise, interrupt handler takes over from here. | |
1467 | */ | |
1468 | } | |
1469 | ||
1470 | break; | |
1471 | ||
1472 | case ATAPI_PROT_PIO: | |
1473 | case ATAPI_PROT_NODATA: | |
1474 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1475 | ata_qc_set_polling(qc); | |
1476 | ||
1477 | ata_tf_to_host(ap, &qc->tf); | |
1478 | ||
1479 | ap->hsm_task_state = HSM_ST_FIRST; | |
1480 | ||
1481 | /* send cdb by polling if no cdb interrupt */ | |
1482 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1483 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
1484 | ata_pio_queue_task(ap, qc, 0); | |
1485 | break; | |
1486 | ||
1487 | case ATAPI_PROT_DMA: | |
1488 | WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); | |
1489 | ||
5682ed33 | 1490 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
624d5c51 TH |
1491 | ap->ops->bmdma_setup(qc); /* set up bmdma */ |
1492 | ap->hsm_task_state = HSM_ST_FIRST; | |
1493 | ||
1494 | /* send cdb by polling if no cdb interrupt */ | |
1495 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1496 | ata_pio_queue_task(ap, qc, 0); | |
1497 | break; | |
1498 | ||
1499 | default: | |
1500 | WARN_ON(1); | |
1501 | return AC_ERR_SYSTEM; | |
1502 | } | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
22183bf5 TH |
1507 | /** |
1508 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1509 | * @qc: qc to fill result TF for | |
1510 | * | |
1511 | * @qc is finished and result TF needs to be filled. Fill it | |
1512 | * using ->sff_tf_read. | |
1513 | * | |
1514 | * LOCKING: | |
1515 | * spin_lock_irqsave(host lock) | |
1516 | * | |
1517 | * RETURNS: | |
1518 | * true indicating that result TF is successfully filled. | |
1519 | */ | |
1520 | bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) | |
1521 | { | |
1522 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
1523 | return true; | |
1524 | } | |
1525 | ||
624d5c51 | 1526 | /** |
9363c382 | 1527 | * ata_sff_host_intr - Handle host interrupt for given (port, task) |
624d5c51 TH |
1528 | * @ap: Port on which interrupt arrived (possibly...) |
1529 | * @qc: Taskfile currently active in engine | |
1530 | * | |
1531 | * Handle host interrupt for given queued command. Currently, | |
1532 | * only DMA interrupts are handled. All other commands are | |
1533 | * handled via polling with interrupts disabled (nIEN bit). | |
1534 | * | |
1535 | * LOCKING: | |
1536 | * spin_lock_irqsave(host lock) | |
1537 | * | |
1538 | * RETURNS: | |
1539 | * One if interrupt was handled, zero if not (shared irq). | |
1540 | */ | |
9363c382 TH |
1541 | inline unsigned int ata_sff_host_intr(struct ata_port *ap, |
1542 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
1543 | { |
1544 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
1545 | u8 status, host_stat = 0; | |
1546 | ||
1547 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1548 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1549 | ||
1550 | /* Check whether we are expecting interrupt in this state */ | |
1551 | switch (ap->hsm_task_state) { | |
1552 | case HSM_ST_FIRST: | |
1553 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1554 | * at this state when ready to receive CDB. | |
1555 | */ | |
1556 | ||
1557 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1558 | * The flag was turned on only for atapi devices. No | |
1559 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1560 | */ | |
1561 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
1562 | goto idle_irq; | |
1563 | break; | |
1564 | case HSM_ST_LAST: | |
1565 | if (qc->tf.protocol == ATA_PROT_DMA || | |
1566 | qc->tf.protocol == ATAPI_PROT_DMA) { | |
1567 | /* check status of DMA engine */ | |
1568 | host_stat = ap->ops->bmdma_status(ap); | |
1569 | VPRINTK("ata%u: host_stat 0x%X\n", | |
1570 | ap->print_id, host_stat); | |
1571 | ||
1572 | /* if it's not our irq... */ | |
1573 | if (!(host_stat & ATA_DMA_INTR)) | |
1574 | goto idle_irq; | |
1575 | ||
1576 | /* before we do anything else, clear DMA-Start bit */ | |
1577 | ap->ops->bmdma_stop(qc); | |
1578 | ||
1579 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
1580 | /* error when transfering data to/from memory */ | |
1581 | qc->err_mask |= AC_ERR_HOST_BUS; | |
1582 | ap->hsm_task_state = HSM_ST_ERR; | |
1583 | } | |
1584 | } | |
1585 | break; | |
1586 | case HSM_ST: | |
1587 | break; | |
1588 | default: | |
1589 | goto idle_irq; | |
1590 | } | |
1591 | ||
624d5c51 | 1592 | |
a57c1bad AC |
1593 | /* check main status, clearing INTRQ if needed */ |
1594 | status = ata_sff_irq_status(ap); | |
1595 | if (status & ATA_BUSY) | |
624d5c51 TH |
1596 | goto idle_irq; |
1597 | ||
1598 | /* ack bmdma irq events */ | |
5682ed33 | 1599 | ap->ops->sff_irq_clear(ap); |
624d5c51 | 1600 | |
9363c382 | 1601 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 TH |
1602 | |
1603 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || | |
1604 | qc->tf.protocol == ATAPI_PROT_DMA)) | |
1605 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
1606 | ||
1607 | return 1; /* irq handled */ | |
1608 | ||
1609 | idle_irq: | |
1610 | ap->stats.idle_irq++; | |
1611 | ||
1612 | #ifdef ATA_IRQ_TRAP | |
1613 | if ((ap->stats.idle_irq % 1000) == 0) { | |
5682ed33 TH |
1614 | ap->ops->sff_check_status(ap); |
1615 | ap->ops->sff_irq_clear(ap); | |
624d5c51 TH |
1616 | ata_port_printk(ap, KERN_WARNING, "irq trap\n"); |
1617 | return 1; | |
1618 | } | |
1619 | #endif | |
1620 | return 0; /* irq not handled */ | |
1621 | } | |
1622 | ||
1623 | /** | |
9363c382 | 1624 | * ata_sff_interrupt - Default ATA host interrupt handler |
624d5c51 TH |
1625 | * @irq: irq line (unused) |
1626 | * @dev_instance: pointer to our ata_host information structure | |
1627 | * | |
1628 | * Default interrupt handler for PCI IDE devices. Calls | |
9363c382 | 1629 | * ata_sff_host_intr() for each port that is not disabled. |
624d5c51 TH |
1630 | * |
1631 | * LOCKING: | |
1632 | * Obtains host lock during operation. | |
1633 | * | |
1634 | * RETURNS: | |
1635 | * IRQ_NONE or IRQ_HANDLED. | |
1636 | */ | |
9363c382 | 1637 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) |
624d5c51 TH |
1638 | { |
1639 | struct ata_host *host = dev_instance; | |
1640 | unsigned int i; | |
1641 | unsigned int handled = 0; | |
1642 | unsigned long flags; | |
1643 | ||
1644 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1645 | spin_lock_irqsave(&host->lock, flags); | |
1646 | ||
1647 | for (i = 0; i < host->n_ports; i++) { | |
1648 | struct ata_port *ap; | |
1649 | ||
1650 | ap = host->ports[i]; | |
1651 | if (ap && | |
1652 | !(ap->flags & ATA_FLAG_DISABLED)) { | |
1653 | struct ata_queued_cmd *qc; | |
1654 | ||
1655 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
1656 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && | |
1657 | (qc->flags & ATA_QCFLAG_ACTIVE)) | |
9363c382 | 1658 | handled |= ata_sff_host_intr(ap, qc); |
624d5c51 TH |
1659 | } |
1660 | } | |
1661 | ||
1662 | spin_unlock_irqrestore(&host->lock, flags); | |
1663 | ||
1664 | return IRQ_RETVAL(handled); | |
1665 | } | |
1666 | ||
1667 | /** | |
9363c382 | 1668 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1669 | * @ap: port to freeze |
1670 | * | |
1671 | * Freeze BMDMA controller port. | |
1672 | * | |
1673 | * LOCKING: | |
1674 | * Inherited from caller. | |
1675 | */ | |
9363c382 | 1676 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 TH |
1677 | { |
1678 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
1679 | ||
1680 | ap->ctl |= ATA_NIEN; | |
1681 | ap->last_ctl = ap->ctl; | |
1682 | ||
1683 | if (ioaddr->ctl_addr) | |
1684 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1685 | ||
1686 | /* Under certain circumstances, some controllers raise IRQ on | |
1687 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1688 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1689 | */ | |
5682ed33 | 1690 | ap->ops->sff_check_status(ap); |
624d5c51 | 1691 | |
5682ed33 | 1692 | ap->ops->sff_irq_clear(ap); |
624d5c51 TH |
1693 | } |
1694 | ||
1695 | /** | |
9363c382 | 1696 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1697 | * @ap: port to thaw |
1698 | * | |
9363c382 | 1699 | * Thaw SFF controller port. |
624d5c51 TH |
1700 | * |
1701 | * LOCKING: | |
1702 | * Inherited from caller. | |
1703 | */ | |
9363c382 | 1704 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1705 | { |
624d5c51 | 1706 | /* clear & re-enable interrupts */ |
5682ed33 TH |
1707 | ap->ops->sff_check_status(ap); |
1708 | ap->ops->sff_irq_clear(ap); | |
1709 | ap->ops->sff_irq_on(ap); | |
272f7884 TH |
1710 | } |
1711 | ||
0aa1113d TH |
1712 | /** |
1713 | * ata_sff_prereset - prepare SFF link for reset | |
1714 | * @link: SFF link to be reset | |
1715 | * @deadline: deadline jiffies for the operation | |
1716 | * | |
1717 | * SFF link @link is about to be reset. Initialize it. It first | |
1718 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1719 | * being softreset. | |
1720 | * | |
1721 | * LOCKING: | |
1722 | * Kernel thread context (may sleep) | |
1723 | * | |
1724 | * RETURNS: | |
1725 | * 0 on success, -errno otherwise. | |
1726 | */ | |
1727 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1728 | { | |
0aa1113d TH |
1729 | struct ata_eh_context *ehc = &link->eh_context; |
1730 | int rc; | |
1731 | ||
1732 | rc = ata_std_prereset(link, deadline); | |
1733 | if (rc) | |
1734 | return rc; | |
1735 | ||
1736 | /* if we're about to do hardreset, nothing more to do */ | |
1737 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1738 | return 0; | |
1739 | ||
1740 | /* wait for !BSY if we don't know that no device is attached */ | |
1741 | if (!ata_link_offline(link)) { | |
705e76be | 1742 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d TH |
1743 | if (rc && rc != -ENODEV) { |
1744 | ata_link_printk(link, KERN_WARNING, "device not ready " | |
1745 | "(errno=%d), forcing hardreset\n", rc); | |
1746 | ehc->i.action |= ATA_EH_HARDRESET; | |
1747 | } | |
1748 | } | |
1749 | ||
1750 | return 0; | |
1751 | } | |
1752 | ||
90088bb4 | 1753 | /** |
624d5c51 TH |
1754 | * ata_devchk - PATA device presence detection |
1755 | * @ap: ATA channel to examine | |
1756 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1757 | * |
624d5c51 TH |
1758 | * This technique was originally described in |
1759 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1760 | * later found its way into the ATA/ATAPI spec. | |
1761 | * | |
1762 | * Write a pattern to the ATA shadow registers, | |
1763 | * and if a device is present, it will respond by | |
1764 | * correctly storing and echoing back the | |
1765 | * ATA shadow register contents. | |
90088bb4 TH |
1766 | * |
1767 | * LOCKING: | |
624d5c51 | 1768 | * caller. |
90088bb4 | 1769 | */ |
624d5c51 | 1770 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1771 | { |
1772 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1773 | u8 nsect, lbal; |
90088bb4 | 1774 | |
5682ed33 | 1775 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1776 | |
624d5c51 TH |
1777 | iowrite8(0x55, ioaddr->nsect_addr); |
1778 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1779 | |
624d5c51 TH |
1780 | iowrite8(0xaa, ioaddr->nsect_addr); |
1781 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1782 | |
624d5c51 TH |
1783 | iowrite8(0x55, ioaddr->nsect_addr); |
1784 | iowrite8(0xaa, ioaddr->lbal_addr); | |
1785 | ||
1786 | nsect = ioread8(ioaddr->nsect_addr); | |
1787 | lbal = ioread8(ioaddr->lbal_addr); | |
1788 | ||
1789 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
1790 | return 1; /* we found a device */ | |
1791 | ||
1792 | return 0; /* nothing found */ | |
90088bb4 TH |
1793 | } |
1794 | ||
272f7884 | 1795 | /** |
9363c382 | 1796 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
1797 | * @dev: ATA device to classify (starting at zero) |
1798 | * @present: device seems present | |
1799 | * @r_err: Value of error register on completion | |
272f7884 | 1800 | * |
624d5c51 TH |
1801 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
1802 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
1803 | * shadow registers, indicating the results of device detection | |
1804 | * and diagnostics. | |
272f7884 | 1805 | * |
624d5c51 TH |
1806 | * Select the ATA device, and read the values from the ATA shadow |
1807 | * registers. Then parse according to the Error register value, | |
1808 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
1809 | * |
1810 | * LOCKING: | |
624d5c51 TH |
1811 | * caller. |
1812 | * | |
1813 | * RETURNS: | |
1814 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 1815 | */ |
9363c382 | 1816 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 1817 | u8 *r_err) |
272f7884 | 1818 | { |
624d5c51 TH |
1819 | struct ata_port *ap = dev->link->ap; |
1820 | struct ata_taskfile tf; | |
1821 | unsigned int class; | |
1822 | u8 err; | |
1823 | ||
5682ed33 | 1824 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
1825 | |
1826 | memset(&tf, 0, sizeof(tf)); | |
1827 | ||
5682ed33 | 1828 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
1829 | err = tf.feature; |
1830 | if (r_err) | |
1831 | *r_err = err; | |
1832 | ||
1833 | /* see if device passed diags: continue and warn later */ | |
1834 | if (err == 0) | |
1835 | /* diagnostic fail : do nothing _YET_ */ | |
1836 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
1837 | else if (err == 1) | |
1838 | /* do nothing */ ; | |
1839 | else if ((dev->devno == 0) && (err == 0x81)) | |
1840 | /* do nothing */ ; | |
1841 | else | |
1842 | return ATA_DEV_NONE; | |
272f7884 | 1843 | |
624d5c51 TH |
1844 | /* determine if device is ATA or ATAPI */ |
1845 | class = ata_dev_classify(&tf); | |
272f7884 | 1846 | |
624d5c51 TH |
1847 | if (class == ATA_DEV_UNKNOWN) { |
1848 | /* If the device failed diagnostic, it's likely to | |
1849 | * have reported incorrect device signature too. | |
1850 | * Assume ATA device if the device seems present but | |
1851 | * device signature is invalid with diagnostic | |
1852 | * failure. | |
1853 | */ | |
1854 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
1855 | class = ATA_DEV_ATA; | |
1856 | else | |
1857 | class = ATA_DEV_NONE; | |
5682ed33 TH |
1858 | } else if ((class == ATA_DEV_ATA) && |
1859 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
1860 | class = ATA_DEV_NONE; |
1861 | ||
1862 | return class; | |
272f7884 TH |
1863 | } |
1864 | ||
705e76be TH |
1865 | /** |
1866 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
1867 | * @link: SFF link which is just reset | |
1868 | * @devmask: mask of present devices | |
1869 | * @deadline: deadline jiffies for the operation | |
1870 | * | |
1871 | * Wait devices attached to SFF @link to become ready after | |
1872 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
1873 | * status register too early. | |
1874 | * | |
1875 | * LOCKING: | |
1876 | * Kernel thread context (may sleep). | |
1877 | * | |
1878 | * RETURNS: | |
1879 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
1880 | * don't seem to exist. -errno on other errors. | |
1881 | */ | |
1882 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
1883 | unsigned long deadline) | |
1fdffbce | 1884 | { |
705e76be | 1885 | struct ata_port *ap = link->ap; |
1fdffbce | 1886 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
1887 | unsigned int dev0 = devmask & (1 << 0); |
1888 | unsigned int dev1 = devmask & (1 << 1); | |
1889 | int rc, ret = 0; | |
1fdffbce | 1890 | |
705e76be TH |
1891 | msleep(ATA_WAIT_AFTER_RESET_MSECS); |
1892 | ||
1893 | /* always check readiness of the master device */ | |
1894 | rc = ata_sff_wait_ready(link, deadline); | |
1895 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
1896 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 1897 | */ |
705e76be TH |
1898 | if (rc) |
1899 | return rc; | |
1fdffbce | 1900 | |
624d5c51 TH |
1901 | /* if device 1 was found in ata_devchk, wait for register |
1902 | * access briefly, then wait for BSY to clear. | |
1903 | */ | |
1904 | if (dev1) { | |
1905 | int i; | |
1fdffbce | 1906 | |
5682ed33 | 1907 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 1908 | |
624d5c51 TH |
1909 | /* Wait for register access. Some ATAPI devices fail |
1910 | * to set nsect/lbal after reset, so don't waste too | |
1911 | * much time on it. We're gonna wait for !BSY anyway. | |
1912 | */ | |
1913 | for (i = 0; i < 2; i++) { | |
1914 | u8 nsect, lbal; | |
1915 | ||
1916 | nsect = ioread8(ioaddr->nsect_addr); | |
1917 | lbal = ioread8(ioaddr->lbal_addr); | |
1918 | if ((nsect == 1) && (lbal == 1)) | |
1919 | break; | |
1920 | msleep(50); /* give drive a breather */ | |
1921 | } | |
1922 | ||
705e76be | 1923 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
1924 | if (rc) { |
1925 | if (rc != -ENODEV) | |
1926 | return rc; | |
1927 | ret = rc; | |
1928 | } | |
1fdffbce JG |
1929 | } |
1930 | ||
624d5c51 | 1931 | /* is all this really necessary? */ |
5682ed33 | 1932 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 1933 | if (dev1) |
5682ed33 | 1934 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 1935 | if (dev0) |
5682ed33 | 1936 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1937 | |
1938 | return ret; | |
1fdffbce JG |
1939 | } |
1940 | ||
624d5c51 TH |
1941 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
1942 | unsigned long deadline) | |
2cc432ee | 1943 | { |
624d5c51 | 1944 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 1945 | |
624d5c51 TH |
1946 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
1947 | ||
1948 | /* software reset. causes dev0 to be selected */ | |
1949 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1950 | udelay(20); /* FIXME: flush */ | |
1951 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
1952 | udelay(20); /* FIXME: flush */ | |
1953 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1954 | ||
705e76be TH |
1955 | /* wait the port to become ready */ |
1956 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
1957 | } |
1958 | ||
6d97dbd7 | 1959 | /** |
9363c382 | 1960 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
1961 | * @link: ATA link to reset |
1962 | * @classes: resulting classes of attached devices | |
1963 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1964 | * |
624d5c51 | 1965 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
1966 | * |
1967 | * LOCKING: | |
624d5c51 TH |
1968 | * Kernel thread context (may sleep) |
1969 | * | |
1970 | * RETURNS: | |
1971 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 1972 | */ |
9363c382 | 1973 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 1974 | unsigned long deadline) |
6d97dbd7 | 1975 | { |
624d5c51 TH |
1976 | struct ata_port *ap = link->ap; |
1977 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
1978 | unsigned int devmask = 0; | |
1979 | int rc; | |
1980 | u8 err; | |
6d97dbd7 | 1981 | |
624d5c51 | 1982 | DPRINTK("ENTER\n"); |
6d97dbd7 | 1983 | |
624d5c51 TH |
1984 | /* determine if device 0/1 are present */ |
1985 | if (ata_devchk(ap, 0)) | |
1986 | devmask |= (1 << 0); | |
1987 | if (slave_possible && ata_devchk(ap, 1)) | |
1988 | devmask |= (1 << 1); | |
1989 | ||
1990 | /* select device 0 again */ | |
5682ed33 | 1991 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1992 | |
1993 | /* issue bus reset */ | |
1994 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
1995 | rc = ata_bus_softreset(ap, devmask, deadline); | |
1996 | /* if link is occupied, -ENODEV too is an error */ | |
1997 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
1998 | ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); | |
1999 | return rc; | |
2000 | } | |
0f0a3ad3 | 2001 | |
624d5c51 | 2002 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 2003 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
2004 | devmask & (1 << 0), &err); |
2005 | if (slave_possible && err != 0x81) | |
9363c382 | 2006 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
2007 | devmask & (1 << 1), &err); |
2008 | ||
624d5c51 TH |
2009 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
2010 | return 0; | |
6d97dbd7 TH |
2011 | } |
2012 | ||
2013 | /** | |
9363c382 | 2014 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
2015 | * @link: link to reset |
2016 | * @class: resulting class of attached device | |
2017 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2018 | * |
624d5c51 TH |
2019 | * SATA phy-reset host port using DET bits of SControl register, |
2020 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
2021 | * |
2022 | * LOCKING: | |
624d5c51 TH |
2023 | * Kernel thread context (may sleep) |
2024 | * | |
2025 | * RETURNS: | |
2026 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2027 | */ |
9363c382 | 2028 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 2029 | unsigned long deadline) |
6d97dbd7 | 2030 | { |
9dadd45b TH |
2031 | struct ata_eh_context *ehc = &link->eh_context; |
2032 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
2033 | bool online; | |
624d5c51 TH |
2034 | int rc; |
2035 | ||
9dadd45b TH |
2036 | rc = sata_link_hardreset(link, timing, deadline, &online, |
2037 | ata_sff_check_ready); | |
9dadd45b TH |
2038 | if (online) |
2039 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 TH |
2040 | |
2041 | DPRINTK("EXIT, class=%u\n", *class); | |
9dadd45b | 2042 | return rc; |
6d97dbd7 TH |
2043 | } |
2044 | ||
203c75b8 TH |
2045 | /** |
2046 | * ata_sff_postreset - SFF postreset callback | |
2047 | * @link: the target SFF ata_link | |
2048 | * @classes: classes of attached devices | |
2049 | * | |
2050 | * This function is invoked after a successful reset. It first | |
2051 | * calls ata_std_postreset() and performs SFF specific postreset | |
2052 | * processing. | |
2053 | * | |
2054 | * LOCKING: | |
2055 | * Kernel thread context (may sleep) | |
2056 | */ | |
2057 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
2058 | { | |
2059 | struct ata_port *ap = link->ap; | |
2060 | ||
2061 | ata_std_postreset(link, classes); | |
2062 | ||
2063 | /* is double-select really necessary? */ | |
2064 | if (classes[0] != ATA_DEV_NONE) | |
2065 | ap->ops->sff_dev_select(ap, 1); | |
2066 | if (classes[1] != ATA_DEV_NONE) | |
2067 | ap->ops->sff_dev_select(ap, 0); | |
2068 | ||
2069 | /* bail out if no device is present */ | |
2070 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
2071 | DPRINTK("EXIT, no device\n"); | |
2072 | return; | |
2073 | } | |
2074 | ||
2075 | /* set up device control */ | |
2076 | if (ap->ioaddr.ctl_addr) | |
2077 | iowrite8(ap->ctl, ap->ioaddr.ctl_addr); | |
2078 | } | |
2079 | ||
6d97dbd7 | 2080 | /** |
9363c382 | 2081 | * ata_sff_error_handler - Stock error handler for BMDMA controller |
6d97dbd7 | 2082 | * @ap: port to handle error for |
6d97dbd7 | 2083 | * |
9363c382 | 2084 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2085 | * PATA and SATA controllers. Many controllers should be able to |
2086 | * use this EH as-is or with some added handling before and | |
2087 | * after. | |
2088 | * | |
6d97dbd7 TH |
2089 | * LOCKING: |
2090 | * Kernel thread context (may sleep) | |
2091 | */ | |
9363c382 | 2092 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2093 | { |
a1efdaba TH |
2094 | ata_reset_fn_t softreset = ap->ops->softreset; |
2095 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2096 | struct ata_queued_cmd *qc; |
2097 | unsigned long flags; | |
2098 | int thaw = 0; | |
2099 | ||
9af5c9c9 | 2100 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2101 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2102 | qc = NULL; | |
2103 | ||
2104 | /* reset PIO HSM and stop DMA engine */ | |
ba6a1308 | 2105 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2106 | |
6d97dbd7 TH |
2107 | ap->hsm_task_state = HSM_ST_IDLE; |
2108 | ||
ed82f964 TH |
2109 | if (ap->ioaddr.bmdma_addr && |
2110 | qc && (qc->tf.protocol == ATA_PROT_DMA || | |
0dc36888 | 2111 | qc->tf.protocol == ATAPI_PROT_DMA)) { |
6d97dbd7 TH |
2112 | u8 host_stat; |
2113 | ||
fbbb262d | 2114 | host_stat = ap->ops->bmdma_status(ap); |
6d97dbd7 | 2115 | |
6d97dbd7 TH |
2116 | /* BMDMA controllers indicate host bus error by |
2117 | * setting DMA_ERR bit and timing out. As it wasn't | |
2118 | * really a timeout event, adjust error mask and | |
2119 | * cancel frozen state. | |
2120 | */ | |
18d90deb | 2121 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { |
6d97dbd7 TH |
2122 | qc->err_mask = AC_ERR_HOST_BUS; |
2123 | thaw = 1; | |
2124 | } | |
2125 | ||
2126 | ap->ops->bmdma_stop(qc); | |
2127 | } | |
2128 | ||
a57c1bad | 2129 | ata_sff_sync(ap); /* FIXME: We don't need this */ |
5682ed33 TH |
2130 | ap->ops->sff_check_status(ap); |
2131 | ap->ops->sff_irq_clear(ap); | |
6d97dbd7 | 2132 | |
ba6a1308 | 2133 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 TH |
2134 | |
2135 | if (thaw) | |
2136 | ata_eh_thaw_port(ap); | |
2137 | ||
2138 | /* PIO and DMA engines have been stopped, perform recovery */ | |
6d97dbd7 | 2139 | |
57c9efdf TH |
2140 | /* Ignore ata_sff_softreset if ctl isn't accessible and |
2141 | * built-in hardresets if SCR access isn't available. | |
a1efdaba | 2142 | */ |
9363c382 | 2143 | if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) |
a1efdaba | 2144 | softreset = NULL; |
57c9efdf | 2145 | if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link)) |
a1efdaba | 2146 | hardreset = NULL; |
6d97dbd7 | 2147 | |
a1efdaba TH |
2148 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2149 | ap->ops->postreset); | |
6d97dbd7 TH |
2150 | } |
2151 | ||
2152 | /** | |
9363c382 | 2153 | * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller |
6d97dbd7 TH |
2154 | * @qc: internal command to clean up |
2155 | * | |
2156 | * LOCKING: | |
2157 | * Kernel thread context (may sleep) | |
2158 | */ | |
9363c382 | 2159 | void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc) |
6d97dbd7 | 2160 | { |
61dd08c6 AC |
2161 | if (qc->ap->ioaddr.bmdma_addr) |
2162 | ata_bmdma_stop(qc); | |
6d97dbd7 TH |
2163 | } |
2164 | ||
d92e74d3 AC |
2165 | /** |
2166 | * ata_sff_port_start - Set port up for dma. | |
2167 | * @ap: Port to initialize | |
2168 | * | |
2169 | * Called just after data structures for each port are | |
2170 | * initialized. Allocates space for PRD table if the device | |
2171 | * is DMA capable SFF. | |
2172 | * | |
2173 | * May be used as the port_start() entry in ata_port_operations. | |
2174 | * | |
2175 | * LOCKING: | |
2176 | * Inherited from caller. | |
2177 | */ | |
d92e74d3 AC |
2178 | int ata_sff_port_start(struct ata_port *ap) |
2179 | { | |
2180 | if (ap->ioaddr.bmdma_addr) | |
2181 | return ata_port_start(ap); | |
2182 | return 0; | |
2183 | } | |
2184 | ||
624d5c51 | 2185 | /** |
9363c382 | 2186 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2187 | * @ioaddr: IO address structure to be initialized |
2188 | * | |
2189 | * Utility function which initializes data_addr, error_addr, | |
2190 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2191 | * device_addr, status_addr, and command_addr to standard offsets | |
2192 | * relative to cmd_addr. | |
2193 | * | |
2194 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2195 | */ | |
9363c382 | 2196 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2197 | { |
2198 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2199 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2200 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2201 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2202 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2203 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2204 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2205 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2206 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2207 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2208 | } | |
2209 | ||
9363c382 TH |
2210 | unsigned long ata_bmdma_mode_filter(struct ata_device *adev, |
2211 | unsigned long xfer_mask) | |
071ce34d TH |
2212 | { |
2213 | /* Filter out DMA modes if the device has been configured by | |
2214 | the BIOS as PIO only */ | |
2215 | ||
2216 | if (adev->link->ap->ioaddr.bmdma_addr == NULL) | |
2217 | xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); | |
2218 | return xfer_mask; | |
2219 | } | |
2220 | ||
272f7884 TH |
2221 | /** |
2222 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2223 | * @qc: Info associated with this ATA transaction. | |
2224 | * | |
2225 | * LOCKING: | |
2226 | * spin_lock_irqsave(host lock) | |
2227 | */ | |
2228 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2229 | { | |
2230 | struct ata_port *ap = qc->ap; | |
2231 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2232 | u8 dmactl; | |
2233 | ||
2234 | /* load PRD table addr. */ | |
2235 | mb(); /* make sure PRD table writes are visible to controller */ | |
2236 | iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); | |
2237 | ||
2238 | /* specify data direction, triple-check start bit is clear */ | |
2239 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2240 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2241 | if (!rw) | |
2242 | dmactl |= ATA_DMA_WR; | |
2243 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2244 | ||
2245 | /* issue r/w command */ | |
5682ed33 | 2246 | ap->ops->sff_exec_command(ap, &qc->tf); |
272f7884 TH |
2247 | } |
2248 | ||
2249 | /** | |
2250 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2251 | * @qc: Info associated with this ATA transaction. | |
2252 | * | |
2253 | * LOCKING: | |
2254 | * spin_lock_irqsave(host lock) | |
2255 | */ | |
2256 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2257 | { | |
2258 | struct ata_port *ap = qc->ap; | |
2259 | u8 dmactl; | |
2260 | ||
2261 | /* start host DMA transaction */ | |
2262 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2263 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2264 | ||
2265 | /* Strictly, one may wish to issue an ioread8() here, to | |
2266 | * flush the mmio write. However, control also passes | |
2267 | * to the hardware at this point, and it will interrupt | |
2268 | * us when we are to resume control. So, in effect, | |
2269 | * we don't care when the mmio write flushes. | |
2270 | * Further, a read of the DMA status register _immediately_ | |
2271 | * following the write may not be what certain flaky hardware | |
2272 | * is expected, so I think it is best to not add a readb() | |
2273 | * without first all the MMIO ATA cards/mobos. | |
2274 | * Or maybe I'm just being paranoid. | |
2275 | * | |
2276 | * FIXME: The posting of this write means I/O starts are | |
2277 | * unneccessarily delayed for MMIO | |
2278 | */ | |
2279 | } | |
2280 | ||
2281 | /** | |
2282 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
2283 | * @qc: Command we are ending DMA for | |
2284 | * | |
2285 | * Clears the ATA_DMA_START flag in the dma control register | |
2286 | * | |
2287 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
2288 | * | |
2289 | * LOCKING: | |
2290 | * spin_lock_irqsave(host lock) | |
2291 | */ | |
2292 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
2293 | { | |
2294 | struct ata_port *ap = qc->ap; | |
2295 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2296 | ||
2297 | /* clear start/stop bit */ | |
2298 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
2299 | mmio + ATA_DMA_CMD); | |
2300 | ||
2301 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
a57c1bad | 2302 | ata_sff_dma_pause(ap); |
272f7884 TH |
2303 | } |
2304 | ||
2305 | /** | |
2306 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
2307 | * @ap: Port associated with this ATA transaction. | |
2308 | * | |
2309 | * Read and return BMDMA status register. | |
2310 | * | |
2311 | * May be used as the bmdma_status() entry in ata_port_operations. | |
2312 | * | |
2313 | * LOCKING: | |
2314 | * spin_lock_irqsave(host lock) | |
2315 | */ | |
2316 | u8 ata_bmdma_status(struct ata_port *ap) | |
2317 | { | |
2318 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
2319 | } | |
2320 | ||
2321 | /** | |
624d5c51 TH |
2322 | * ata_bus_reset - reset host port and associated ATA channel |
2323 | * @ap: port to reset | |
2324 | * | |
2325 | * This is typically the first time we actually start issuing | |
2326 | * commands to the ATA channel. We wait for BSY to clear, then | |
2327 | * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its | |
2328 | * result. Determine what devices, if any, are on the channel | |
2329 | * by looking at the device 0/1 error register. Look at the signature | |
2330 | * stored in each device's taskfile registers, to determine if | |
2331 | * the device is ATA or ATAPI. | |
2332 | * | |
2333 | * LOCKING: | |
2334 | * PCI/etc. bus probe sem. | |
2335 | * Obtains host lock. | |
2336 | * | |
2337 | * SIDE EFFECTS: | |
2338 | * Sets ATA_FLAG_DISABLED if bus reset fails. | |
2339 | * | |
2340 | * DEPRECATED: | |
2341 | * This function is only for drivers which still use old EH and | |
2342 | * will be removed soon. | |
272f7884 | 2343 | */ |
624d5c51 | 2344 | void ata_bus_reset(struct ata_port *ap) |
272f7884 | 2345 | { |
624d5c51 TH |
2346 | struct ata_device *device = ap->link.device; |
2347 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
2348 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
2349 | u8 err; | |
2350 | unsigned int dev0, dev1 = 0, devmask = 0; | |
2351 | int rc; | |
2352 | ||
2353 | DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no); | |
2354 | ||
2355 | /* determine if device 0/1 are present */ | |
2356 | if (ap->flags & ATA_FLAG_SATA_RESET) | |
2357 | dev0 = 1; | |
2358 | else { | |
2359 | dev0 = ata_devchk(ap, 0); | |
2360 | if (slave_possible) | |
2361 | dev1 = ata_devchk(ap, 1); | |
2362 | } | |
2363 | ||
2364 | if (dev0) | |
2365 | devmask |= (1 << 0); | |
2366 | if (dev1) | |
2367 | devmask |= (1 << 1); | |
2368 | ||
2369 | /* select device 0 again */ | |
5682ed33 | 2370 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2371 | |
2372 | /* issue bus reset */ | |
2373 | if (ap->flags & ATA_FLAG_SRST) { | |
2374 | rc = ata_bus_softreset(ap, devmask, jiffies + 40 * HZ); | |
2375 | if (rc && rc != -ENODEV) | |
2376 | goto err_out; | |
2377 | } | |
2378 | ||
2379 | /* | |
2380 | * determine by signature whether we have ATA or ATAPI devices | |
2381 | */ | |
9363c382 | 2382 | device[0].class = ata_sff_dev_classify(&device[0], dev0, &err); |
624d5c51 | 2383 | if ((slave_possible) && (err != 0x81)) |
9363c382 | 2384 | device[1].class = ata_sff_dev_classify(&device[1], dev1, &err); |
624d5c51 TH |
2385 | |
2386 | /* is double-select really necessary? */ | |
2387 | if (device[1].class != ATA_DEV_NONE) | |
5682ed33 | 2388 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 2389 | if (device[0].class != ATA_DEV_NONE) |
5682ed33 | 2390 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2391 | |
2392 | /* if no devices were detected, disable this port */ | |
2393 | if ((device[0].class == ATA_DEV_NONE) && | |
2394 | (device[1].class == ATA_DEV_NONE)) | |
2395 | goto err_out; | |
2396 | ||
2397 | if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { | |
2398 | /* set up device control for ATA_FLAG_SATA_RESET */ | |
2399 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
2400 | } | |
2401 | ||
2402 | DPRINTK("EXIT\n"); | |
2403 | return; | |
2404 | ||
2405 | err_out: | |
2406 | ata_port_printk(ap, KERN_ERR, "disabling port\n"); | |
2407 | ata_port_disable(ap); | |
2408 | ||
2409 | DPRINTK("EXIT\n"); | |
272f7884 TH |
2410 | } |
2411 | ||
1fdffbce | 2412 | #ifdef CONFIG_PCI |
4112e16a | 2413 | |
272f7884 | 2414 | /** |
9363c382 | 2415 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex |
272f7884 TH |
2416 | * @pdev: PCI device |
2417 | * | |
2418 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
2419 | * enter non simplex mode. This implements the necessary logic to | |
2420 | * perform the task on such devices. Calling it on other devices will | |
2421 | * have -undefined- behaviour. | |
2422 | */ | |
9363c382 | 2423 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) |
4112e16a | 2424 | { |
272f7884 TH |
2425 | unsigned long bmdma = pci_resource_start(pdev, 4); |
2426 | u8 simplex; | |
a84471fe | 2427 | |
272f7884 TH |
2428 | if (bmdma == 0) |
2429 | return -ENOENT; | |
2430 | ||
2431 | simplex = inb(bmdma + 0x02); | |
2432 | outb(simplex & 0x60, bmdma + 0x02); | |
2433 | simplex = inb(bmdma + 0x02); | |
2434 | if (simplex & 0x80) | |
2435 | return -EOPNOTSUPP; | |
2436 | return 0; | |
2437 | } | |
2438 | ||
0f834de3 | 2439 | /** |
9363c382 | 2440 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host |
0f834de3 TH |
2441 | * @host: target ATA host |
2442 | * | |
2443 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
2444 | * | |
2445 | * LOCKING: | |
2446 | * Inherited from calling layer (may sleep). | |
2447 | * | |
2448 | * RETURNS: | |
2449 | * 0 on success, -errno otherwise. | |
2450 | */ | |
9363c382 | 2451 | int ata_pci_bmdma_init(struct ata_host *host) |
1fdffbce | 2452 | { |
0f834de3 TH |
2453 | struct device *gdev = host->dev; |
2454 | struct pci_dev *pdev = to_pci_dev(gdev); | |
2455 | int i, rc; | |
0d5ff566 | 2456 | |
6fdc99a2 AC |
2457 | /* No BAR4 allocation: No DMA */ |
2458 | if (pci_resource_start(pdev, 4) == 0) | |
2459 | return 0; | |
2460 | ||
0f834de3 TH |
2461 | /* TODO: If we get no DMA mask we should fall back to PIO */ |
2462 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
2463 | if (rc) | |
2464 | return rc; | |
2465 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
2466 | if (rc) | |
2467 | return rc; | |
2468 | ||
2469 | /* request and iomap DMA region */ | |
35a10a80 | 2470 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); |
0f834de3 TH |
2471 | if (rc) { |
2472 | dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n"); | |
2473 | return -ENOMEM; | |
0d5ff566 | 2474 | } |
0f834de3 | 2475 | host->iomap = pcim_iomap_table(pdev); |
0d5ff566 | 2476 | |
1626aeb8 | 2477 | for (i = 0; i < 2; i++) { |
0f834de3 | 2478 | struct ata_port *ap = host->ports[i]; |
0f834de3 TH |
2479 | void __iomem *bmdma = host->iomap[4] + 8 * i; |
2480 | ||
2481 | if (ata_port_is_dummy(ap)) | |
2482 | continue; | |
2483 | ||
21b0ad4f | 2484 | ap->ioaddr.bmdma_addr = bmdma; |
0f834de3 TH |
2485 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && |
2486 | (ioread8(bmdma + 2) & 0x80)) | |
2487 | host->flags |= ATA_HOST_SIMPLEX; | |
cbcdd875 TH |
2488 | |
2489 | ata_port_desc(ap, "bmdma 0x%llx", | |
2490 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
0d5ff566 TH |
2491 | } |
2492 | ||
0f834de3 TH |
2493 | return 0; |
2494 | } | |
2ec7df04 | 2495 | |
272f7884 TH |
2496 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2497 | { | |
2498 | int i; | |
2499 | ||
2500 | /* Check the PCI resources for this channel are enabled */ | |
2501 | port = port * 2; | |
2502 | for (i = 0; i < 2; i ++) { | |
2503 | if (pci_resource_start(pdev, port + i) == 0 || | |
2504 | pci_resource_len(pdev, port + i) == 0) | |
2505 | return 0; | |
2506 | } | |
2507 | return 1; | |
2508 | } | |
2509 | ||
d491b27b | 2510 | /** |
9363c382 | 2511 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2512 | * @host: target ATA host |
d491b27b | 2513 | * |
1626aeb8 TH |
2514 | * Acquire native PCI ATA resources for @host and initialize the |
2515 | * first two ports of @host accordingly. Ports marked dummy are | |
2516 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2517 | * |
d583bc18 TH |
2518 | * Note that native PCI resources are valid even for legacy hosts |
2519 | * as we fix up pdev resources array early in boot, so this | |
2520 | * function can be used for both native and legacy SFF hosts. | |
2521 | * | |
d491b27b TH |
2522 | * LOCKING: |
2523 | * Inherited from calling layer (may sleep). | |
2524 | * | |
2525 | * RETURNS: | |
1626aeb8 TH |
2526 | * 0 if at least one port is initialized, -ENODEV if no port is |
2527 | * available. | |
d491b27b | 2528 | */ |
9363c382 | 2529 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2530 | { |
2531 | struct device *gdev = host->dev; | |
2532 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2533 | unsigned int mask = 0; |
d491b27b TH |
2534 | int i, rc; |
2535 | ||
d491b27b TH |
2536 | /* request, iomap BARs and init port addresses accordingly */ |
2537 | for (i = 0; i < 2; i++) { | |
2538 | struct ata_port *ap = host->ports[i]; | |
2539 | int base = i * 2; | |
2540 | void __iomem * const *iomap; | |
2541 | ||
1626aeb8 TH |
2542 | if (ata_port_is_dummy(ap)) |
2543 | continue; | |
2544 | ||
2545 | /* Discard disabled ports. Some controllers show | |
2546 | * their unused channels this way. Disabled ports are | |
2547 | * made dummy. | |
2548 | */ | |
2549 | if (!ata_resources_present(pdev, i)) { | |
2550 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2551 | continue; |
1626aeb8 | 2552 | } |
d491b27b | 2553 | |
35a10a80 TH |
2554 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2555 | dev_driver_string(gdev)); | |
d491b27b | 2556 | if (rc) { |
1626aeb8 TH |
2557 | dev_printk(KERN_WARNING, gdev, |
2558 | "failed to request/iomap BARs for port %d " | |
2559 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
2560 | if (rc == -EBUSY) |
2561 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2562 | ap->ops = &ata_dummy_port_ops; |
2563 | continue; | |
d491b27b TH |
2564 | } |
2565 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2566 | ||
2567 | ap->ioaddr.cmd_addr = iomap[base]; | |
2568 | ap->ioaddr.altstatus_addr = | |
2569 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2570 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2571 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2572 | |
cbcdd875 TH |
2573 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2574 | (unsigned long long)pci_resource_start(pdev, base), | |
2575 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2576 | ||
1626aeb8 TH |
2577 | mask |= 1 << i; |
2578 | } | |
2579 | ||
2580 | if (!mask) { | |
2581 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
2582 | return -ENODEV; | |
d491b27b TH |
2583 | } |
2584 | ||
2585 | return 0; | |
2586 | } | |
2587 | ||
21b0ad4f | 2588 | /** |
9363c382 | 2589 | * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host |
21b0ad4f | 2590 | * @pdev: target PCI device |
1626aeb8 | 2591 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2592 | * @r_host: out argument for the initialized ATA host |
2593 | * | |
2594 | * Helper to allocate ATA host for @pdev, acquire all native PCI | |
2595 | * resources and initialize it accordingly in one go. | |
2596 | * | |
2597 | * LOCKING: | |
2598 | * Inherited from calling layer (may sleep). | |
2599 | * | |
2600 | * RETURNS: | |
2601 | * 0 on success, -errno otherwise. | |
2602 | */ | |
9363c382 | 2603 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
d583bc18 TH |
2604 | const struct ata_port_info * const * ppi, |
2605 | struct ata_host **r_host) | |
21b0ad4f TH |
2606 | { |
2607 | struct ata_host *host; | |
21b0ad4f TH |
2608 | int rc; |
2609 | ||
2610 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2611 | return -ENOMEM; | |
2612 | ||
2613 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2614 | if (!host) { | |
2615 | dev_printk(KERN_ERR, &pdev->dev, | |
2616 | "failed to allocate ATA host\n"); | |
2617 | rc = -ENOMEM; | |
2618 | goto err_out; | |
2619 | } | |
2620 | ||
9363c382 | 2621 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2622 | if (rc) |
2623 | goto err_out; | |
2624 | ||
2625 | /* init DMA related stuff */ | |
9363c382 | 2626 | rc = ata_pci_bmdma_init(host); |
21b0ad4f TH |
2627 | if (rc) |
2628 | goto err_bmdma; | |
2629 | ||
2630 | devres_remove_group(&pdev->dev, NULL); | |
2631 | *r_host = host; | |
2632 | return 0; | |
2633 | ||
2634 | err_bmdma: | |
2635 | /* This is necessary because PCI and iomap resources are | |
2636 | * merged and releasing the top group won't release the | |
2637 | * acquired resources if some of those have been acquired | |
2638 | * before entering this function. | |
2639 | */ | |
2640 | pcim_iounmap_regions(pdev, 0xf); | |
2641 | err_out: | |
2642 | devres_release_group(&pdev->dev, NULL); | |
2643 | return rc; | |
2644 | } | |
2645 | ||
4e6b79fa | 2646 | /** |
9363c382 | 2647 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2648 | * @host: target SFF ATA host |
2649 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2650 | * @sht: scsi_host_template to use when registering the host | |
2651 | * | |
2652 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2653 | * hosts. This separate helper is necessary because SFF hosts | |
2654 | * use two separate interrupts in legacy mode. | |
2655 | * | |
2656 | * LOCKING: | |
2657 | * Inherited from calling layer (may sleep). | |
2658 | * | |
2659 | * RETURNS: | |
2660 | * 0 on success, -errno otherwise. | |
2661 | */ | |
9363c382 | 2662 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2663 | irq_handler_t irq_handler, |
2664 | struct scsi_host_template *sht) | |
2665 | { | |
2666 | struct device *dev = host->dev; | |
2667 | struct pci_dev *pdev = to_pci_dev(dev); | |
2668 | const char *drv_name = dev_driver_string(host->dev); | |
2669 | int legacy_mode = 0, rc; | |
2670 | ||
2671 | rc = ata_host_start(host); | |
2672 | if (rc) | |
2673 | return rc; | |
2674 | ||
2675 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
2676 | u8 tmp8, mask; | |
2677 | ||
2678 | /* TODO: What if one channel is in native mode ... */ | |
2679 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
2680 | mask = (1 << 2) | (1 << 0); | |
2681 | if ((tmp8 & mask) != mask) | |
2682 | legacy_mode = 1; | |
2683 | #if defined(CONFIG_NO_ATA_LEGACY) | |
2684 | /* Some platforms with PCI limits cannot address compat | |
2685 | port space. In that case we punt if their firmware has | |
2686 | left a device in compatibility mode */ | |
2687 | if (legacy_mode) { | |
2688 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
2689 | return -EOPNOTSUPP; | |
2690 | } | |
2691 | #endif | |
2692 | } | |
2693 | ||
2694 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2695 | return -ENOMEM; | |
2696 | ||
2697 | if (!legacy_mode && pdev->irq) { | |
2698 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
2699 | IRQF_SHARED, drv_name, host); | |
2700 | if (rc) | |
2701 | goto out; | |
2702 | ||
2703 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
2704 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
2705 | } else if (legacy_mode) { | |
2706 | if (!ata_port_is_dummy(host->ports[0])) { | |
2707 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2708 | irq_handler, IRQF_SHARED, | |
2709 | drv_name, host); | |
2710 | if (rc) | |
2711 | goto out; | |
2712 | ||
2713 | ata_port_desc(host->ports[0], "irq %d", | |
2714 | ATA_PRIMARY_IRQ(pdev)); | |
2715 | } | |
2716 | ||
2717 | if (!ata_port_is_dummy(host->ports[1])) { | |
2718 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2719 | irq_handler, IRQF_SHARED, | |
2720 | drv_name, host); | |
2721 | if (rc) | |
2722 | goto out; | |
2723 | ||
2724 | ata_port_desc(host->ports[1], "irq %d", | |
2725 | ATA_SECONDARY_IRQ(pdev)); | |
2726 | } | |
2727 | } | |
2728 | ||
2729 | rc = ata_host_register(host, sht); | |
2730 | out: | |
2731 | if (rc == 0) | |
2732 | devres_remove_group(dev, NULL); | |
2733 | else | |
2734 | devres_release_group(dev, NULL); | |
2735 | ||
2736 | return rc; | |
2737 | } | |
2738 | ||
1fdffbce | 2739 | /** |
9363c382 | 2740 | * ata_pci_sff_init_one - Initialize/register PCI IDE host controller |
1fdffbce | 2741 | * @pdev: Controller to be initialized |
1626aeb8 | 2742 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 2743 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 2744 | * @host_priv: host private_data |
1fdffbce JG |
2745 | * |
2746 | * This is a helper function which can be called from a driver's | |
2747 | * xxx_init_one() probe function if the hardware uses traditional | |
2748 | * IDE taskfile registers. | |
2749 | * | |
2750 | * This function calls pci_enable_device(), reserves its register | |
2751 | * regions, sets the dma mask, enables bus master mode, and calls | |
2752 | * ata_device_add() | |
2753 | * | |
2ec7df04 AC |
2754 | * ASSUMPTION: |
2755 | * Nobody makes a single channel controller that appears solely as | |
2756 | * the secondary legacy port on PCI. | |
2757 | * | |
1fdffbce JG |
2758 | * LOCKING: |
2759 | * Inherited from PCI layer (may sleep). | |
2760 | * | |
2761 | * RETURNS: | |
2762 | * Zero on success, negative on errno-based value on error. | |
2763 | */ | |
9363c382 TH |
2764 | int ata_pci_sff_init_one(struct pci_dev *pdev, |
2765 | const struct ata_port_info * const * ppi, | |
2766 | struct scsi_host_template *sht, void *host_priv) | |
1fdffbce | 2767 | { |
f0d36efd | 2768 | struct device *dev = &pdev->dev; |
1626aeb8 | 2769 | const struct ata_port_info *pi = NULL; |
0f834de3 | 2770 | struct ata_host *host = NULL; |
1626aeb8 | 2771 | int i, rc; |
1fdffbce JG |
2772 | |
2773 | DPRINTK("ENTER\n"); | |
2774 | ||
1626aeb8 TH |
2775 | /* look up the first valid port_info */ |
2776 | for (i = 0; i < 2 && ppi[i]; i++) { | |
2777 | if (ppi[i]->port_ops != &ata_dummy_port_ops) { | |
2778 | pi = ppi[i]; | |
2779 | break; | |
2780 | } | |
2781 | } | |
f0d36efd | 2782 | |
1626aeb8 TH |
2783 | if (!pi) { |
2784 | dev_printk(KERN_ERR, &pdev->dev, | |
2785 | "no valid port_info specified\n"); | |
2786 | return -EINVAL; | |
2787 | } | |
c791c306 | 2788 | |
1626aeb8 TH |
2789 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2790 | return -ENOMEM; | |
1fdffbce | 2791 | |
f0d36efd | 2792 | rc = pcim_enable_device(pdev); |
1fdffbce | 2793 | if (rc) |
4e6b79fa | 2794 | goto out; |
1fdffbce | 2795 | |
4e6b79fa | 2796 | /* prepare and activate SFF host */ |
9363c382 | 2797 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
d583bc18 | 2798 | if (rc) |
4e6b79fa | 2799 | goto out; |
887125e3 | 2800 | host->private_data = host_priv; |
d491b27b | 2801 | |
d491b27b | 2802 | pci_set_master(pdev); |
9363c382 | 2803 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
4e6b79fa TH |
2804 | out: |
2805 | if (rc == 0) | |
2806 | devres_remove_group(&pdev->dev, NULL); | |
2807 | else | |
2808 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2809 | |
1fdffbce JG |
2810 | return rc; |
2811 | } | |
2812 | ||
2813 | #endif /* CONFIG_PCI */ | |
2814 | ||
624d5c51 TH |
2815 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
2816 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); | |
9363c382 TH |
2817 | EXPORT_SYMBOL_GPL(ata_sff_qc_prep); |
2818 | EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep); | |
2819 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); | |
2820 | EXPORT_SYMBOL_GPL(ata_sff_check_status); | |
a57c1bad AC |
2821 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause); |
2822 | EXPORT_SYMBOL_GPL(ata_sff_pause); | |
9363c382 TH |
2823 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); |
2824 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); | |
2825 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); | |
2826 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); | |
2827 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); | |
2828 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); | |
2829 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); | |
2830 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); | |
2831 | EXPORT_SYMBOL_GPL(ata_sff_irq_clear); | |
2832 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); | |
2833 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); | |
22183bf5 | 2834 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
9363c382 TH |
2835 | EXPORT_SYMBOL_GPL(ata_sff_host_intr); |
2836 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); | |
2837 | EXPORT_SYMBOL_GPL(ata_sff_freeze); | |
2838 | EXPORT_SYMBOL_GPL(ata_sff_thaw); | |
2839 | EXPORT_SYMBOL_GPL(ata_sff_prereset); | |
2840 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); | |
2841 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); | |
2842 | EXPORT_SYMBOL_GPL(ata_sff_softreset); | |
2843 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); | |
2844 | EXPORT_SYMBOL_GPL(ata_sff_postreset); | |
2845 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); | |
2846 | EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd); | |
624d5c51 | 2847 | EXPORT_SYMBOL_GPL(ata_sff_port_start); |
9363c382 TH |
2848 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
2849 | EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter); | |
624d5c51 TH |
2850 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); |
2851 | EXPORT_SYMBOL_GPL(ata_bmdma_start); | |
2852 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); | |
2853 | EXPORT_SYMBOL_GPL(ata_bmdma_status); | |
2854 | EXPORT_SYMBOL_GPL(ata_bus_reset); | |
2855 | #ifdef CONFIG_PCI | |
9363c382 TH |
2856 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); |
2857 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); | |
2858 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); | |
2859 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); | |
2860 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); | |
2861 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); | |
624d5c51 | 2862 | #endif /* CONFIG_PCI */ |