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1fdffbce | 1 | /* |
f3a03b09 | 2 | * libata-sff.c - helper library for PCI IDE BMDMA |
1fdffbce JG |
3 | * |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2006 Red Hat, Inc. All rights reserved. | |
9 | * Copyright 2003-2006 Jeff Garzik | |
10 | * | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware documentation available from http://www.t13.org/ and | |
31 | * http://www.sata-io.org/ | |
32 | * | |
33 | */ | |
34 | ||
1fdffbce | 35 | #include <linux/kernel.h> |
5a0e3ad6 | 36 | #include <linux/gfp.h> |
1fdffbce JG |
37 | #include <linux/pci.h> |
38 | #include <linux/libata.h> | |
624d5c51 | 39 | #include <linux/highmem.h> |
1fdffbce JG |
40 | |
41 | #include "libata.h" | |
42 | ||
c429137a TH |
43 | static struct workqueue_struct *ata_sff_wq; |
44 | ||
624d5c51 TH |
45 | const struct ata_port_operations ata_sff_port_ops = { |
46 | .inherits = &ata_base_port_ops, | |
47 | ||
f47451c4 | 48 | .qc_prep = ata_noop_qc_prep, |
9363c382 | 49 | .qc_issue = ata_sff_qc_issue, |
4c9bf4e7 | 50 | .qc_fill_rtf = ata_sff_qc_fill_rtf, |
9363c382 TH |
51 | |
52 | .freeze = ata_sff_freeze, | |
53 | .thaw = ata_sff_thaw, | |
0aa1113d | 54 | .prereset = ata_sff_prereset, |
9363c382 | 55 | .softreset = ata_sff_softreset, |
57c9efdf | 56 | .hardreset = sata_sff_hardreset, |
203c75b8 | 57 | .postreset = ata_sff_postreset, |
9363c382 | 58 | .error_handler = ata_sff_error_handler, |
9363c382 | 59 | |
5682ed33 TH |
60 | .sff_dev_select = ata_sff_dev_select, |
61 | .sff_check_status = ata_sff_check_status, | |
62 | .sff_tf_load = ata_sff_tf_load, | |
63 | .sff_tf_read = ata_sff_tf_read, | |
64 | .sff_exec_command = ata_sff_exec_command, | |
65 | .sff_data_xfer = ata_sff_data_xfer, | |
8244cd05 | 66 | .sff_drain_fifo = ata_sff_drain_fifo, |
624d5c51 | 67 | |
c96f1732 | 68 | .lost_interrupt = ata_sff_lost_interrupt, |
624d5c51 | 69 | }; |
0fe40ff8 | 70 | EXPORT_SYMBOL_GPL(ata_sff_port_ops); |
624d5c51 | 71 | |
272f7884 | 72 | /** |
9363c382 | 73 | * ata_sff_check_status - Read device status reg & clear interrupt |
272f7884 TH |
74 | * @ap: port where the device is |
75 | * | |
76 | * Reads ATA taskfile status register for currently-selected device | |
77 | * and return its value. This also clears pending interrupts | |
78 | * from this device | |
79 | * | |
80 | * LOCKING: | |
81 | * Inherited from caller. | |
82 | */ | |
9363c382 | 83 | u8 ata_sff_check_status(struct ata_port *ap) |
272f7884 TH |
84 | { |
85 | return ioread8(ap->ioaddr.status_addr); | |
86 | } | |
0fe40ff8 | 87 | EXPORT_SYMBOL_GPL(ata_sff_check_status); |
272f7884 TH |
88 | |
89 | /** | |
9363c382 | 90 | * ata_sff_altstatus - Read device alternate status reg |
272f7884 TH |
91 | * @ap: port where the device is |
92 | * | |
93 | * Reads ATA taskfile alternate status register for | |
94 | * currently-selected device and return its value. | |
95 | * | |
96 | * Note: may NOT be used as the check_altstatus() entry in | |
97 | * ata_port_operations. | |
98 | * | |
99 | * LOCKING: | |
100 | * Inherited from caller. | |
101 | */ | |
a57c1bad | 102 | static u8 ata_sff_altstatus(struct ata_port *ap) |
624d5c51 | 103 | { |
5682ed33 TH |
104 | if (ap->ops->sff_check_altstatus) |
105 | return ap->ops->sff_check_altstatus(ap); | |
624d5c51 TH |
106 | |
107 | return ioread8(ap->ioaddr.altstatus_addr); | |
108 | } | |
109 | ||
a57c1bad AC |
110 | /** |
111 | * ata_sff_irq_status - Check if the device is busy | |
112 | * @ap: port where the device is | |
113 | * | |
114 | * Determine if the port is currently busy. Uses altstatus | |
115 | * if available in order to avoid clearing shared IRQ status | |
116 | * when finding an IRQ source. Non ctl capable devices don't | |
117 | * share interrupt lines fortunately for us. | |
118 | * | |
119 | * LOCKING: | |
120 | * Inherited from caller. | |
121 | */ | |
122 | static u8 ata_sff_irq_status(struct ata_port *ap) | |
123 | { | |
124 | u8 status; | |
125 | ||
126 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
127 | status = ata_sff_altstatus(ap); | |
128 | /* Not us: We are busy */ | |
129 | if (status & ATA_BUSY) | |
0fe40ff8 | 130 | return status; |
a57c1bad AC |
131 | } |
132 | /* Clear INTRQ latch */ | |
6311c90a | 133 | status = ap->ops->sff_check_status(ap); |
a57c1bad AC |
134 | return status; |
135 | } | |
136 | ||
137 | /** | |
138 | * ata_sff_sync - Flush writes | |
139 | * @ap: Port to wait for. | |
140 | * | |
141 | * CAUTION: | |
142 | * If we have an mmio device with no ctl and no altstatus | |
143 | * method this will fail. No such devices are known to exist. | |
144 | * | |
145 | * LOCKING: | |
146 | * Inherited from caller. | |
147 | */ | |
148 | ||
149 | static void ata_sff_sync(struct ata_port *ap) | |
150 | { | |
151 | if (ap->ops->sff_check_altstatus) | |
152 | ap->ops->sff_check_altstatus(ap); | |
153 | else if (ap->ioaddr.altstatus_addr) | |
154 | ioread8(ap->ioaddr.altstatus_addr); | |
155 | } | |
156 | ||
157 | /** | |
158 | * ata_sff_pause - Flush writes and wait 400nS | |
159 | * @ap: Port to pause for. | |
160 | * | |
161 | * CAUTION: | |
162 | * If we have an mmio device with no ctl and no altstatus | |
163 | * method this will fail. No such devices are known to exist. | |
164 | * | |
165 | * LOCKING: | |
166 | * Inherited from caller. | |
167 | */ | |
168 | ||
169 | void ata_sff_pause(struct ata_port *ap) | |
170 | { | |
171 | ata_sff_sync(ap); | |
172 | ndelay(400); | |
173 | } | |
0fe40ff8 | 174 | EXPORT_SYMBOL_GPL(ata_sff_pause); |
a57c1bad AC |
175 | |
176 | /** | |
177 | * ata_sff_dma_pause - Pause before commencing DMA | |
178 | * @ap: Port to pause for. | |
179 | * | |
180 | * Perform I/O fencing and ensure sufficient cycle delays occur | |
181 | * for the HDMA1:0 transition | |
182 | */ | |
0fe40ff8 | 183 | |
a57c1bad AC |
184 | void ata_sff_dma_pause(struct ata_port *ap) |
185 | { | |
186 | if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) { | |
187 | /* An altstatus read will cause the needed delay without | |
188 | messing up the IRQ status */ | |
189 | ata_sff_altstatus(ap); | |
190 | return; | |
191 | } | |
192 | /* There are no DMA controllers without ctl. BUG here to ensure | |
193 | we never violate the HDMA1:0 transition timing and risk | |
194 | corruption. */ | |
195 | BUG(); | |
196 | } | |
0fe40ff8 | 197 | EXPORT_SYMBOL_GPL(ata_sff_dma_pause); |
a57c1bad | 198 | |
624d5c51 | 199 | /** |
9363c382 | 200 | * ata_sff_busy_sleep - sleep until BSY clears, or timeout |
624d5c51 | 201 | * @ap: port containing status register to be polled |
341c2c95 TH |
202 | * @tmout_pat: impatience timeout in msecs |
203 | * @tmout: overall timeout in msecs | |
624d5c51 TH |
204 | * |
205 | * Sleep until ATA Status register bit BSY clears, | |
206 | * or a timeout occurs. | |
207 | * | |
208 | * LOCKING: | |
209 | * Kernel thread context (may sleep). | |
210 | * | |
211 | * RETURNS: | |
212 | * 0 on success, -errno otherwise. | |
213 | */ | |
9363c382 TH |
214 | int ata_sff_busy_sleep(struct ata_port *ap, |
215 | unsigned long tmout_pat, unsigned long tmout) | |
624d5c51 TH |
216 | { |
217 | unsigned long timer_start, timeout; | |
218 | u8 status; | |
219 | ||
9363c382 | 220 | status = ata_sff_busy_wait(ap, ATA_BUSY, 300); |
624d5c51 | 221 | timer_start = jiffies; |
341c2c95 | 222 | timeout = ata_deadline(timer_start, tmout_pat); |
624d5c51 TH |
223 | while (status != 0xff && (status & ATA_BUSY) && |
224 | time_before(jiffies, timeout)) { | |
225 | msleep(50); | |
9363c382 | 226 | status = ata_sff_busy_wait(ap, ATA_BUSY, 3); |
624d5c51 TH |
227 | } |
228 | ||
229 | if (status != 0xff && (status & ATA_BUSY)) | |
230 | ata_port_printk(ap, KERN_WARNING, | |
231 | "port is slow to respond, please be patient " | |
232 | "(Status 0x%x)\n", status); | |
233 | ||
341c2c95 | 234 | timeout = ata_deadline(timer_start, tmout); |
624d5c51 TH |
235 | while (status != 0xff && (status & ATA_BUSY) && |
236 | time_before(jiffies, timeout)) { | |
237 | msleep(50); | |
5682ed33 | 238 | status = ap->ops->sff_check_status(ap); |
624d5c51 TH |
239 | } |
240 | ||
241 | if (status == 0xff) | |
242 | return -ENODEV; | |
243 | ||
244 | if (status & ATA_BUSY) { | |
245 | ata_port_printk(ap, KERN_ERR, "port failed to respond " | |
246 | "(%lu secs, Status 0x%x)\n", | |
341c2c95 | 247 | DIV_ROUND_UP(tmout, 1000), status); |
624d5c51 TH |
248 | return -EBUSY; |
249 | } | |
250 | ||
251 | return 0; | |
252 | } | |
0fe40ff8 | 253 | EXPORT_SYMBOL_GPL(ata_sff_busy_sleep); |
624d5c51 | 254 | |
aa2731ad TH |
255 | static int ata_sff_check_ready(struct ata_link *link) |
256 | { | |
257 | u8 status = link->ap->ops->sff_check_status(link->ap); | |
258 | ||
78ab88f0 | 259 | return ata_check_ready(status); |
aa2731ad TH |
260 | } |
261 | ||
624d5c51 | 262 | /** |
9363c382 | 263 | * ata_sff_wait_ready - sleep until BSY clears, or timeout |
705e76be | 264 | * @link: SFF link to wait ready status for |
624d5c51 TH |
265 | * @deadline: deadline jiffies for the operation |
266 | * | |
267 | * Sleep until ATA Status register bit BSY clears, or timeout | |
268 | * occurs. | |
269 | * | |
270 | * LOCKING: | |
271 | * Kernel thread context (may sleep). | |
272 | * | |
273 | * RETURNS: | |
274 | * 0 on success, -errno otherwise. | |
275 | */ | |
705e76be | 276 | int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline) |
624d5c51 | 277 | { |
aa2731ad | 278 | return ata_wait_ready(link, deadline, ata_sff_check_ready); |
624d5c51 | 279 | } |
0fe40ff8 | 280 | EXPORT_SYMBOL_GPL(ata_sff_wait_ready); |
624d5c51 | 281 | |
41dec29b SS |
282 | /** |
283 | * ata_sff_set_devctl - Write device control reg | |
284 | * @ap: port where the device is | |
285 | * @ctl: value to write | |
286 | * | |
287 | * Writes ATA taskfile device control register. | |
288 | * | |
289 | * Note: may NOT be used as the sff_set_devctl() entry in | |
290 | * ata_port_operations. | |
291 | * | |
292 | * LOCKING: | |
293 | * Inherited from caller. | |
294 | */ | |
295 | static void ata_sff_set_devctl(struct ata_port *ap, u8 ctl) | |
296 | { | |
297 | if (ap->ops->sff_set_devctl) | |
298 | ap->ops->sff_set_devctl(ap, ctl); | |
299 | else | |
300 | iowrite8(ctl, ap->ioaddr.ctl_addr); | |
301 | } | |
302 | ||
624d5c51 | 303 | /** |
9363c382 | 304 | * ata_sff_dev_select - Select device 0/1 on ATA bus |
624d5c51 TH |
305 | * @ap: ATA channel to manipulate |
306 | * @device: ATA device (numbered from zero) to select | |
307 | * | |
308 | * Use the method defined in the ATA specification to | |
309 | * make either device 0, or device 1, active on the | |
310 | * ATA channel. Works with both PIO and MMIO. | |
311 | * | |
312 | * May be used as the dev_select() entry in ata_port_operations. | |
313 | * | |
314 | * LOCKING: | |
315 | * caller. | |
316 | */ | |
9363c382 | 317 | void ata_sff_dev_select(struct ata_port *ap, unsigned int device) |
624d5c51 TH |
318 | { |
319 | u8 tmp; | |
320 | ||
321 | if (device == 0) | |
322 | tmp = ATA_DEVICE_OBS; | |
323 | else | |
324 | tmp = ATA_DEVICE_OBS | ATA_DEV1; | |
325 | ||
326 | iowrite8(tmp, ap->ioaddr.device_addr); | |
9363c382 | 327 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ |
624d5c51 | 328 | } |
0fe40ff8 | 329 | EXPORT_SYMBOL_GPL(ata_sff_dev_select); |
624d5c51 TH |
330 | |
331 | /** | |
332 | * ata_dev_select - Select device 0/1 on ATA bus | |
333 | * @ap: ATA channel to manipulate | |
334 | * @device: ATA device (numbered from zero) to select | |
335 | * @wait: non-zero to wait for Status register BSY bit to clear | |
336 | * @can_sleep: non-zero if context allows sleeping | |
337 | * | |
338 | * Use the method defined in the ATA specification to | |
339 | * make either device 0, or device 1, active on the | |
340 | * ATA channel. | |
341 | * | |
9363c382 TH |
342 | * This is a high-level version of ata_sff_dev_select(), which |
343 | * additionally provides the services of inserting the proper | |
344 | * pauses and status polling, where needed. | |
624d5c51 TH |
345 | * |
346 | * LOCKING: | |
347 | * caller. | |
348 | */ | |
c7a8209f | 349 | static void ata_dev_select(struct ata_port *ap, unsigned int device, |
624d5c51 TH |
350 | unsigned int wait, unsigned int can_sleep) |
351 | { | |
352 | if (ata_msg_probe(ap)) | |
353 | ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, " | |
354 | "device %u, wait %u\n", device, wait); | |
355 | ||
356 | if (wait) | |
357 | ata_wait_idle(ap); | |
358 | ||
5682ed33 | 359 | ap->ops->sff_dev_select(ap, device); |
624d5c51 TH |
360 | |
361 | if (wait) { | |
362 | if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI) | |
363 | msleep(150); | |
364 | ata_wait_idle(ap); | |
365 | } | |
366 | } | |
367 | ||
368 | /** | |
9363c382 | 369 | * ata_sff_irq_on - Enable interrupts on a port. |
624d5c51 TH |
370 | * @ap: Port on which interrupts are enabled. |
371 | * | |
372 | * Enable interrupts on a legacy IDE device using MMIO or PIO, | |
373 | * wait for idle, clear any pending interrupts. | |
374 | * | |
e42a542b SS |
375 | * Note: may NOT be used as the sff_irq_on() entry in |
376 | * ata_port_operations. | |
377 | * | |
624d5c51 TH |
378 | * LOCKING: |
379 | * Inherited from caller. | |
380 | */ | |
e42a542b | 381 | void ata_sff_irq_on(struct ata_port *ap) |
624d5c51 TH |
382 | { |
383 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
e42a542b SS |
384 | |
385 | if (ap->ops->sff_irq_on) { | |
386 | ap->ops->sff_irq_on(ap); | |
387 | return; | |
388 | } | |
624d5c51 TH |
389 | |
390 | ap->ctl &= ~ATA_NIEN; | |
391 | ap->last_ctl = ap->ctl; | |
392 | ||
e42a542b SS |
393 | if (ap->ops->sff_set_devctl || ioaddr->ctl_addr) |
394 | ata_sff_set_devctl(ap, ap->ctl); | |
395 | ata_wait_idle(ap); | |
624d5c51 | 396 | |
37f65b8b TH |
397 | if (ap->ops->sff_irq_clear) |
398 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 399 | } |
0fe40ff8 | 400 | EXPORT_SYMBOL_GPL(ata_sff_irq_on); |
624d5c51 | 401 | |
624d5c51 | 402 | /** |
9363c382 | 403 | * ata_sff_tf_load - send taskfile registers to host controller |
624d5c51 TH |
404 | * @ap: Port to which output is sent |
405 | * @tf: ATA taskfile register set | |
406 | * | |
407 | * Outputs ATA taskfile to standard ATA host controller. | |
408 | * | |
409 | * LOCKING: | |
410 | * Inherited from caller. | |
411 | */ | |
9363c382 | 412 | void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
413 | { |
414 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
415 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
416 | ||
417 | if (tf->ctl != ap->last_ctl) { | |
418 | if (ioaddr->ctl_addr) | |
419 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
420 | ap->last_ctl = tf->ctl; | |
624d5c51 TH |
421 | } |
422 | ||
423 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
efcb3cf7 | 424 | WARN_ON_ONCE(!ioaddr->ctl_addr); |
624d5c51 TH |
425 | iowrite8(tf->hob_feature, ioaddr->feature_addr); |
426 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
427 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
428 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
429 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
430 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
431 | tf->hob_feature, | |
432 | tf->hob_nsect, | |
433 | tf->hob_lbal, | |
434 | tf->hob_lbam, | |
435 | tf->hob_lbah); | |
436 | } | |
437 | ||
438 | if (is_addr) { | |
439 | iowrite8(tf->feature, ioaddr->feature_addr); | |
440 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
441 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
442 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
443 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
444 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
445 | tf->feature, | |
446 | tf->nsect, | |
447 | tf->lbal, | |
448 | tf->lbam, | |
449 | tf->lbah); | |
450 | } | |
451 | ||
452 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
453 | iowrite8(tf->device, ioaddr->device_addr); | |
454 | VPRINTK("device 0x%X\n", tf->device); | |
455 | } | |
624d5c51 | 456 | } |
0fe40ff8 | 457 | EXPORT_SYMBOL_GPL(ata_sff_tf_load); |
624d5c51 TH |
458 | |
459 | /** | |
9363c382 | 460 | * ata_sff_tf_read - input device's ATA taskfile shadow registers |
624d5c51 TH |
461 | * @ap: Port from which input is read |
462 | * @tf: ATA taskfile register set for storing input | |
463 | * | |
464 | * Reads ATA taskfile registers for currently-selected device | |
465 | * into @tf. Assumes the device has a fully SFF compliant task file | |
466 | * layout and behaviour. If you device does not (eg has a different | |
467 | * status method) then you will need to provide a replacement tf_read | |
468 | * | |
469 | * LOCKING: | |
470 | * Inherited from caller. | |
471 | */ | |
9363c382 | 472 | void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
624d5c51 TH |
473 | { |
474 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
475 | ||
9363c382 | 476 | tf->command = ata_sff_check_status(ap); |
624d5c51 TH |
477 | tf->feature = ioread8(ioaddr->error_addr); |
478 | tf->nsect = ioread8(ioaddr->nsect_addr); | |
479 | tf->lbal = ioread8(ioaddr->lbal_addr); | |
480 | tf->lbam = ioread8(ioaddr->lbam_addr); | |
481 | tf->lbah = ioread8(ioaddr->lbah_addr); | |
482 | tf->device = ioread8(ioaddr->device_addr); | |
483 | ||
484 | if (tf->flags & ATA_TFLAG_LBA48) { | |
485 | if (likely(ioaddr->ctl_addr)) { | |
486 | iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
487 | tf->hob_feature = ioread8(ioaddr->error_addr); | |
488 | tf->hob_nsect = ioread8(ioaddr->nsect_addr); | |
489 | tf->hob_lbal = ioread8(ioaddr->lbal_addr); | |
490 | tf->hob_lbam = ioread8(ioaddr->lbam_addr); | |
491 | tf->hob_lbah = ioread8(ioaddr->lbah_addr); | |
492 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
493 | ap->last_ctl = tf->ctl; | |
494 | } else | |
efcb3cf7 | 495 | WARN_ON_ONCE(1); |
624d5c51 TH |
496 | } |
497 | } | |
0fe40ff8 | 498 | EXPORT_SYMBOL_GPL(ata_sff_tf_read); |
624d5c51 TH |
499 | |
500 | /** | |
9363c382 | 501 | * ata_sff_exec_command - issue ATA command to host controller |
624d5c51 TH |
502 | * @ap: port to which command is being issued |
503 | * @tf: ATA taskfile register set | |
504 | * | |
505 | * Issues ATA command, with proper synchronization with interrupt | |
506 | * handler / other threads. | |
507 | * | |
508 | * LOCKING: | |
509 | * spin_lock_irqsave(host lock) | |
510 | */ | |
9363c382 | 511 | void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf) |
624d5c51 TH |
512 | { |
513 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
514 | ||
515 | iowrite8(tf->command, ap->ioaddr.command_addr); | |
9363c382 | 516 | ata_sff_pause(ap); |
624d5c51 | 517 | } |
0fe40ff8 | 518 | EXPORT_SYMBOL_GPL(ata_sff_exec_command); |
624d5c51 TH |
519 | |
520 | /** | |
521 | * ata_tf_to_host - issue ATA taskfile to host controller | |
522 | * @ap: port to which command is being issued | |
523 | * @tf: ATA taskfile register set | |
524 | * | |
525 | * Issues ATA taskfile register set to ATA host controller, | |
526 | * with proper synchronization with interrupt handler and | |
527 | * other threads. | |
528 | * | |
529 | * LOCKING: | |
530 | * spin_lock_irqsave(host lock) | |
531 | */ | |
532 | static inline void ata_tf_to_host(struct ata_port *ap, | |
533 | const struct ata_taskfile *tf) | |
534 | { | |
5682ed33 TH |
535 | ap->ops->sff_tf_load(ap, tf); |
536 | ap->ops->sff_exec_command(ap, tf); | |
624d5c51 TH |
537 | } |
538 | ||
539 | /** | |
9363c382 | 540 | * ata_sff_data_xfer - Transfer data by PIO |
624d5c51 TH |
541 | * @dev: device to target |
542 | * @buf: data buffer | |
543 | * @buflen: buffer length | |
544 | * @rw: read/write | |
545 | * | |
546 | * Transfer data from/to the device data register by PIO. | |
547 | * | |
548 | * LOCKING: | |
549 | * Inherited from caller. | |
550 | * | |
551 | * RETURNS: | |
552 | * Bytes consumed. | |
553 | */ | |
9363c382 TH |
554 | unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf, |
555 | unsigned int buflen, int rw) | |
624d5c51 TH |
556 | { |
557 | struct ata_port *ap = dev->link->ap; | |
558 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
559 | unsigned int words = buflen >> 1; | |
560 | ||
561 | /* Transfer multiple of 2 bytes */ | |
562 | if (rw == READ) | |
563 | ioread16_rep(data_addr, buf, words); | |
564 | else | |
565 | iowrite16_rep(data_addr, buf, words); | |
566 | ||
2102d749 | 567 | /* Transfer trailing byte, if any. */ |
624d5c51 | 568 | if (unlikely(buflen & 0x01)) { |
2102d749 | 569 | unsigned char pad[2]; |
624d5c51 | 570 | |
2102d749 SS |
571 | /* Point buf to the tail of buffer */ |
572 | buf += buflen - 1; | |
573 | ||
574 | /* | |
575 | * Use io*16_rep() accessors here as well to avoid pointlessly | |
972b94ff | 576 | * swapping bytes to and from on the big endian machines... |
2102d749 | 577 | */ |
624d5c51 | 578 | if (rw == READ) { |
2102d749 SS |
579 | ioread16_rep(data_addr, pad, 1); |
580 | *buf = pad[0]; | |
624d5c51 | 581 | } else { |
2102d749 SS |
582 | pad[0] = *buf; |
583 | iowrite16_rep(data_addr, pad, 1); | |
624d5c51 TH |
584 | } |
585 | words++; | |
586 | } | |
587 | ||
588 | return words << 1; | |
589 | } | |
0fe40ff8 | 590 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer); |
624d5c51 | 591 | |
871af121 AC |
592 | /** |
593 | * ata_sff_data_xfer32 - Transfer data by PIO | |
594 | * @dev: device to target | |
595 | * @buf: data buffer | |
596 | * @buflen: buffer length | |
597 | * @rw: read/write | |
598 | * | |
599 | * Transfer data from/to the device data register by PIO using 32bit | |
600 | * I/O operations. | |
601 | * | |
602 | * LOCKING: | |
603 | * Inherited from caller. | |
604 | * | |
605 | * RETURNS: | |
606 | * Bytes consumed. | |
607 | */ | |
608 | ||
609 | unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf, | |
610 | unsigned int buflen, int rw) | |
611 | { | |
612 | struct ata_port *ap = dev->link->ap; | |
613 | void __iomem *data_addr = ap->ioaddr.data_addr; | |
614 | unsigned int words = buflen >> 2; | |
615 | int slop = buflen & 3; | |
972b94ff | 616 | |
e3cf95dd AC |
617 | if (!(ap->pflags & ATA_PFLAG_PIO32)) |
618 | return ata_sff_data_xfer(dev, buf, buflen, rw); | |
871af121 AC |
619 | |
620 | /* Transfer multiple of 4 bytes */ | |
621 | if (rw == READ) | |
622 | ioread32_rep(data_addr, buf, words); | |
623 | else | |
624 | iowrite32_rep(data_addr, buf, words); | |
625 | ||
d1b3525b | 626 | /* Transfer trailing bytes, if any */ |
871af121 | 627 | if (unlikely(slop)) { |
d1b3525b SS |
628 | unsigned char pad[4]; |
629 | ||
630 | /* Point buf to the tail of buffer */ | |
631 | buf += buflen - slop; | |
632 | ||
633 | /* | |
634 | * Use io*_rep() accessors here as well to avoid pointlessly | |
972b94ff | 635 | * swapping bytes to and from on the big endian machines... |
d1b3525b | 636 | */ |
871af121 | 637 | if (rw == READ) { |
d1b3525b SS |
638 | if (slop < 3) |
639 | ioread16_rep(data_addr, pad, 1); | |
640 | else | |
641 | ioread32_rep(data_addr, pad, 1); | |
642 | memcpy(buf, pad, slop); | |
871af121 | 643 | } else { |
d1b3525b SS |
644 | memcpy(pad, buf, slop); |
645 | if (slop < 3) | |
646 | iowrite16_rep(data_addr, pad, 1); | |
647 | else | |
648 | iowrite32_rep(data_addr, pad, 1); | |
871af121 | 649 | } |
871af121 | 650 | } |
d1b3525b | 651 | return (buflen + 1) & ~1; |
871af121 AC |
652 | } |
653 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer32); | |
654 | ||
624d5c51 | 655 | /** |
9363c382 | 656 | * ata_sff_data_xfer_noirq - Transfer data by PIO |
624d5c51 TH |
657 | * @dev: device to target |
658 | * @buf: data buffer | |
659 | * @buflen: buffer length | |
660 | * @rw: read/write | |
661 | * | |
662 | * Transfer data from/to the device data register by PIO. Do the | |
663 | * transfer with interrupts disabled. | |
664 | * | |
665 | * LOCKING: | |
666 | * Inherited from caller. | |
667 | * | |
668 | * RETURNS: | |
669 | * Bytes consumed. | |
670 | */ | |
9363c382 TH |
671 | unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf, |
672 | unsigned int buflen, int rw) | |
624d5c51 TH |
673 | { |
674 | unsigned long flags; | |
675 | unsigned int consumed; | |
676 | ||
677 | local_irq_save(flags); | |
9363c382 | 678 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); |
624d5c51 TH |
679 | local_irq_restore(flags); |
680 | ||
681 | return consumed; | |
682 | } | |
0fe40ff8 | 683 | EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq); |
624d5c51 TH |
684 | |
685 | /** | |
686 | * ata_pio_sector - Transfer a sector of data. | |
687 | * @qc: Command on going | |
688 | * | |
689 | * Transfer qc->sect_size bytes of data from/to the ATA device. | |
690 | * | |
691 | * LOCKING: | |
692 | * Inherited from caller. | |
693 | */ | |
694 | static void ata_pio_sector(struct ata_queued_cmd *qc) | |
695 | { | |
696 | int do_write = (qc->tf.flags & ATA_TFLAG_WRITE); | |
697 | struct ata_port *ap = qc->ap; | |
698 | struct page *page; | |
699 | unsigned int offset; | |
700 | unsigned char *buf; | |
701 | ||
702 | if (qc->curbytes == qc->nbytes - qc->sect_size) | |
703 | ap->hsm_task_state = HSM_ST_LAST; | |
704 | ||
705 | page = sg_page(qc->cursg); | |
706 | offset = qc->cursg->offset + qc->cursg_ofs; | |
707 | ||
708 | /* get the current page and offset */ | |
709 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
710 | offset %= PAGE_SIZE; | |
711 | ||
712 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
713 | ||
714 | if (PageHighMem(page)) { | |
715 | unsigned long flags; | |
716 | ||
717 | /* FIXME: use a bounce buffer */ | |
718 | local_irq_save(flags); | |
719 | buf = kmap_atomic(page, KM_IRQ0); | |
720 | ||
721 | /* do the actual data transfer */ | |
5682ed33 TH |
722 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
723 | do_write); | |
624d5c51 TH |
724 | |
725 | kunmap_atomic(buf, KM_IRQ0); | |
726 | local_irq_restore(flags); | |
727 | } else { | |
728 | buf = page_address(page); | |
5682ed33 TH |
729 | ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size, |
730 | do_write); | |
624d5c51 TH |
731 | } |
732 | ||
3842e835 | 733 | if (!do_write && !PageSlab(page)) |
2d68b7fe CM |
734 | flush_dcache_page(page); |
735 | ||
624d5c51 TH |
736 | qc->curbytes += qc->sect_size; |
737 | qc->cursg_ofs += qc->sect_size; | |
738 | ||
739 | if (qc->cursg_ofs == qc->cursg->length) { | |
740 | qc->cursg = sg_next(qc->cursg); | |
741 | qc->cursg_ofs = 0; | |
742 | } | |
743 | } | |
744 | ||
745 | /** | |
746 | * ata_pio_sectors - Transfer one or many sectors. | |
747 | * @qc: Command on going | |
748 | * | |
749 | * Transfer one or many sectors of data from/to the | |
750 | * ATA device for the DRQ request. | |
751 | * | |
752 | * LOCKING: | |
753 | * Inherited from caller. | |
754 | */ | |
755 | static void ata_pio_sectors(struct ata_queued_cmd *qc) | |
756 | { | |
757 | if (is_multi_taskfile(&qc->tf)) { | |
758 | /* READ/WRITE MULTIPLE */ | |
759 | unsigned int nsect; | |
760 | ||
efcb3cf7 | 761 | WARN_ON_ONCE(qc->dev->multi_count == 0); |
624d5c51 TH |
762 | |
763 | nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size, | |
764 | qc->dev->multi_count); | |
765 | while (nsect--) | |
766 | ata_pio_sector(qc); | |
767 | } else | |
768 | ata_pio_sector(qc); | |
769 | ||
a57c1bad | 770 | ata_sff_sync(qc->ap); /* flush */ |
624d5c51 TH |
771 | } |
772 | ||
773 | /** | |
774 | * atapi_send_cdb - Write CDB bytes to hardware | |
775 | * @ap: Port to which ATAPI device is attached. | |
776 | * @qc: Taskfile currently active | |
777 | * | |
778 | * When device has indicated its readiness to accept | |
779 | * a CDB, this function is called. Send the CDB. | |
780 | * | |
781 | * LOCKING: | |
782 | * caller. | |
783 | */ | |
784 | static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc) | |
785 | { | |
786 | /* send SCSI cdb */ | |
787 | DPRINTK("send cdb\n"); | |
efcb3cf7 | 788 | WARN_ON_ONCE(qc->dev->cdb_len < 12); |
624d5c51 | 789 | |
5682ed33 | 790 | ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1); |
a57c1bad AC |
791 | ata_sff_sync(ap); |
792 | /* FIXME: If the CDB is for DMA do we need to do the transition delay | |
793 | or is bmdma_start guaranteed to do it ? */ | |
624d5c51 TH |
794 | switch (qc->tf.protocol) { |
795 | case ATAPI_PROT_PIO: | |
796 | ap->hsm_task_state = HSM_ST; | |
797 | break; | |
798 | case ATAPI_PROT_NODATA: | |
799 | ap->hsm_task_state = HSM_ST_LAST; | |
800 | break; | |
9a7780c9 | 801 | #ifdef CONFIG_ATA_BMDMA |
624d5c51 TH |
802 | case ATAPI_PROT_DMA: |
803 | ap->hsm_task_state = HSM_ST_LAST; | |
804 | /* initiate bmdma */ | |
805 | ap->ops->bmdma_start(qc); | |
806 | break; | |
9a7780c9 TH |
807 | #endif /* CONFIG_ATA_BMDMA */ |
808 | default: | |
809 | BUG(); | |
624d5c51 TH |
810 | } |
811 | } | |
812 | ||
813 | /** | |
814 | * __atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
815 | * @qc: Command on going | |
816 | * @bytes: number of bytes | |
817 | * | |
818 | * Transfer Transfer data from/to the ATAPI device. | |
819 | * | |
820 | * LOCKING: | |
821 | * Inherited from caller. | |
822 | * | |
823 | */ | |
824 | static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes) | |
825 | { | |
826 | int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ; | |
827 | struct ata_port *ap = qc->ap; | |
828 | struct ata_device *dev = qc->dev; | |
829 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
830 | struct scatterlist *sg; | |
831 | struct page *page; | |
832 | unsigned char *buf; | |
833 | unsigned int offset, count, consumed; | |
834 | ||
835 | next_sg: | |
836 | sg = qc->cursg; | |
837 | if (unlikely(!sg)) { | |
838 | ata_ehi_push_desc(ehi, "unexpected or too much trailing data " | |
839 | "buf=%u cur=%u bytes=%u", | |
840 | qc->nbytes, qc->curbytes, bytes); | |
841 | return -1; | |
842 | } | |
843 | ||
844 | page = sg_page(sg); | |
845 | offset = sg->offset + qc->cursg_ofs; | |
846 | ||
847 | /* get the current page and offset */ | |
848 | page = nth_page(page, (offset >> PAGE_SHIFT)); | |
849 | offset %= PAGE_SIZE; | |
850 | ||
851 | /* don't overrun current sg */ | |
852 | count = min(sg->length - qc->cursg_ofs, bytes); | |
853 | ||
854 | /* don't cross page boundaries */ | |
855 | count = min(count, (unsigned int)PAGE_SIZE - offset); | |
856 | ||
857 | DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read"); | |
858 | ||
859 | if (PageHighMem(page)) { | |
860 | unsigned long flags; | |
861 | ||
862 | /* FIXME: use bounce buffer */ | |
863 | local_irq_save(flags); | |
864 | buf = kmap_atomic(page, KM_IRQ0); | |
865 | ||
866 | /* do the actual data transfer */ | |
0fe40ff8 AC |
867 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
868 | count, rw); | |
624d5c51 TH |
869 | |
870 | kunmap_atomic(buf, KM_IRQ0); | |
871 | local_irq_restore(flags); | |
872 | } else { | |
873 | buf = page_address(page); | |
0fe40ff8 AC |
874 | consumed = ap->ops->sff_data_xfer(dev, buf + offset, |
875 | count, rw); | |
624d5c51 TH |
876 | } |
877 | ||
878 | bytes -= min(bytes, consumed); | |
879 | qc->curbytes += count; | |
880 | qc->cursg_ofs += count; | |
881 | ||
882 | if (qc->cursg_ofs == sg->length) { | |
883 | qc->cursg = sg_next(qc->cursg); | |
884 | qc->cursg_ofs = 0; | |
885 | } | |
886 | ||
a0f79f7a CB |
887 | /* |
888 | * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed); | |
889 | * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN | |
890 | * check correctly as it doesn't know if it is the last request being | |
891 | * made. Somebody should implement a proper sanity check. | |
892 | */ | |
624d5c51 TH |
893 | if (bytes) |
894 | goto next_sg; | |
895 | return 0; | |
896 | } | |
897 | ||
898 | /** | |
899 | * atapi_pio_bytes - Transfer data from/to the ATAPI device. | |
900 | * @qc: Command on going | |
901 | * | |
902 | * Transfer Transfer data from/to the ATAPI device. | |
903 | * | |
904 | * LOCKING: | |
905 | * Inherited from caller. | |
906 | */ | |
907 | static void atapi_pio_bytes(struct ata_queued_cmd *qc) | |
908 | { | |
909 | struct ata_port *ap = qc->ap; | |
910 | struct ata_device *dev = qc->dev; | |
911 | struct ata_eh_info *ehi = &dev->link->eh_info; | |
912 | unsigned int ireason, bc_lo, bc_hi, bytes; | |
913 | int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0; | |
914 | ||
915 | /* Abuse qc->result_tf for temp storage of intermediate TF | |
916 | * here to save some kernel stack usage. | |
917 | * For normal completion, qc->result_tf is not relevant. For | |
918 | * error, qc->result_tf is later overwritten by ata_qc_complete(). | |
919 | * So, the correctness of qc->result_tf is not affected. | |
920 | */ | |
5682ed33 | 921 | ap->ops->sff_tf_read(ap, &qc->result_tf); |
624d5c51 TH |
922 | ireason = qc->result_tf.nsect; |
923 | bc_lo = qc->result_tf.lbam; | |
924 | bc_hi = qc->result_tf.lbah; | |
925 | bytes = (bc_hi << 8) | bc_lo; | |
926 | ||
927 | /* shall be cleared to zero, indicating xfer of data */ | |
928 | if (unlikely(ireason & (1 << 0))) | |
929 | goto atapi_check; | |
930 | ||
931 | /* make sure transfer direction matches expected */ | |
932 | i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0; | |
933 | if (unlikely(do_write != i_write)) | |
934 | goto atapi_check; | |
935 | ||
936 | if (unlikely(!bytes)) | |
937 | goto atapi_check; | |
938 | ||
939 | VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes); | |
940 | ||
941 | if (unlikely(__atapi_pio_bytes(qc, bytes))) | |
942 | goto err_out; | |
a57c1bad | 943 | ata_sff_sync(ap); /* flush */ |
624d5c51 TH |
944 | |
945 | return; | |
946 | ||
947 | atapi_check: | |
948 | ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)", | |
949 | ireason, bytes); | |
950 | err_out: | |
951 | qc->err_mask |= AC_ERR_HSM; | |
952 | ap->hsm_task_state = HSM_ST_ERR; | |
953 | } | |
954 | ||
955 | /** | |
956 | * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue. | |
957 | * @ap: the target ata_port | |
958 | * @qc: qc on going | |
959 | * | |
960 | * RETURNS: | |
961 | * 1 if ok in workqueue, 0 otherwise. | |
962 | */ | |
0fe40ff8 AC |
963 | static inline int ata_hsm_ok_in_wq(struct ata_port *ap, |
964 | struct ata_queued_cmd *qc) | |
624d5c51 TH |
965 | { |
966 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
967 | return 1; | |
968 | ||
969 | if (ap->hsm_task_state == HSM_ST_FIRST) { | |
970 | if (qc->tf.protocol == ATA_PROT_PIO && | |
0fe40ff8 | 971 | (qc->tf.flags & ATA_TFLAG_WRITE)) |
624d5c51 TH |
972 | return 1; |
973 | ||
974 | if (ata_is_atapi(qc->tf.protocol) && | |
0fe40ff8 | 975 | !(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
624d5c51 TH |
976 | return 1; |
977 | } | |
978 | ||
979 | return 0; | |
980 | } | |
981 | ||
982 | /** | |
983 | * ata_hsm_qc_complete - finish a qc running on standard HSM | |
984 | * @qc: Command to complete | |
985 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
986 | * | |
987 | * Finish @qc which is running on standard HSM. | |
988 | * | |
989 | * LOCKING: | |
990 | * If @in_wq is zero, spin_lock_irqsave(host lock). | |
991 | * Otherwise, none on entry and grabs host lock. | |
992 | */ | |
993 | static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq) | |
994 | { | |
995 | struct ata_port *ap = qc->ap; | |
996 | unsigned long flags; | |
997 | ||
998 | if (ap->ops->error_handler) { | |
999 | if (in_wq) { | |
1000 | spin_lock_irqsave(ap->lock, flags); | |
1001 | ||
1002 | /* EH might have kicked in while host lock is | |
1003 | * released. | |
1004 | */ | |
1005 | qc = ata_qc_from_tag(ap, qc->tag); | |
1006 | if (qc) { | |
1007 | if (likely(!(qc->err_mask & AC_ERR_HSM))) { | |
e42a542b | 1008 | ata_sff_irq_on(ap); |
624d5c51 TH |
1009 | ata_qc_complete(qc); |
1010 | } else | |
1011 | ata_port_freeze(ap); | |
1012 | } | |
1013 | ||
1014 | spin_unlock_irqrestore(ap->lock, flags); | |
1015 | } else { | |
1016 | if (likely(!(qc->err_mask & AC_ERR_HSM))) | |
1017 | ata_qc_complete(qc); | |
1018 | else | |
1019 | ata_port_freeze(ap); | |
1020 | } | |
1021 | } else { | |
1022 | if (in_wq) { | |
1023 | spin_lock_irqsave(ap->lock, flags); | |
e42a542b | 1024 | ata_sff_irq_on(ap); |
624d5c51 TH |
1025 | ata_qc_complete(qc); |
1026 | spin_unlock_irqrestore(ap->lock, flags); | |
1027 | } else | |
1028 | ata_qc_complete(qc); | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | /** | |
9363c382 | 1033 | * ata_sff_hsm_move - move the HSM to the next state. |
624d5c51 TH |
1034 | * @ap: the target ata_port |
1035 | * @qc: qc on going | |
1036 | * @status: current device status | |
1037 | * @in_wq: 1 if called from workqueue, 0 otherwise | |
1038 | * | |
1039 | * RETURNS: | |
1040 | * 1 when poll next status needed, 0 otherwise. | |
1041 | */ | |
9363c382 TH |
1042 | int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc, |
1043 | u8 status, int in_wq) | |
624d5c51 | 1044 | { |
a836d3e8 | 1045 | struct ata_eh_info *ehi = &ap->link.eh_info; |
624d5c51 TH |
1046 | unsigned long flags = 0; |
1047 | int poll_next; | |
1048 | ||
efcb3cf7 | 1049 | WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0); |
624d5c51 | 1050 | |
9363c382 | 1051 | /* Make sure ata_sff_qc_issue() does not throw things |
624d5c51 TH |
1052 | * like DMA polling into the workqueue. Notice that |
1053 | * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING). | |
1054 | */ | |
efcb3cf7 | 1055 | WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc)); |
624d5c51 TH |
1056 | |
1057 | fsm_start: | |
1058 | DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n", | |
1059 | ap->print_id, qc->tf.protocol, ap->hsm_task_state, status); | |
1060 | ||
1061 | switch (ap->hsm_task_state) { | |
1062 | case HSM_ST_FIRST: | |
1063 | /* Send first data block or PACKET CDB */ | |
1064 | ||
1065 | /* If polling, we will stay in the work queue after | |
1066 | * sending the data. Otherwise, interrupt handler | |
1067 | * takes over after sending the data. | |
1068 | */ | |
1069 | poll_next = (qc->tf.flags & ATA_TFLAG_POLLING); | |
1070 | ||
1071 | /* check device status */ | |
1072 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1073 | /* handle BSY=0, DRQ=0 as error */ | |
1074 | if (likely(status & (ATA_ERR | ATA_DF))) | |
1075 | /* device stops HSM for abort/error */ | |
1076 | qc->err_mask |= AC_ERR_DEV; | |
a836d3e8 | 1077 | else { |
624d5c51 | 1078 | /* HSM violation. Let EH handle this */ |
a836d3e8 TH |
1079 | ata_ehi_push_desc(ehi, |
1080 | "ST_FIRST: !(DRQ|ERR|DF)"); | |
624d5c51 | 1081 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1082 | } |
624d5c51 TH |
1083 | |
1084 | ap->hsm_task_state = HSM_ST_ERR; | |
1085 | goto fsm_start; | |
1086 | } | |
1087 | ||
1088 | /* Device should not ask for data transfer (DRQ=1) | |
1089 | * when it finds something wrong. | |
1090 | * We ignore DRQ here and stop the HSM by | |
1091 | * changing hsm_task_state to HSM_ST_ERR and | |
1092 | * let the EH abort the command or reset the device. | |
1093 | */ | |
1094 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1095 | /* Some ATAPI tape drives forget to clear the ERR bit | |
1096 | * when doing the next command (mostly request sense). | |
1097 | * We ignore ERR here to workaround and proceed sending | |
1098 | * the CDB. | |
1099 | */ | |
1100 | if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) { | |
a836d3e8 TH |
1101 | ata_ehi_push_desc(ehi, "ST_FIRST: " |
1102 | "DRQ=1 with device error, " | |
1103 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1104 | qc->err_mask |= AC_ERR_HSM; |
1105 | ap->hsm_task_state = HSM_ST_ERR; | |
1106 | goto fsm_start; | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | /* Send the CDB (atapi) or the first data block (ata pio out). | |
1111 | * During the state transition, interrupt handler shouldn't | |
1112 | * be invoked before the data transfer is complete and | |
1113 | * hsm_task_state is changed. Hence, the following locking. | |
1114 | */ | |
1115 | if (in_wq) | |
1116 | spin_lock_irqsave(ap->lock, flags); | |
1117 | ||
1118 | if (qc->tf.protocol == ATA_PROT_PIO) { | |
1119 | /* PIO data out protocol. | |
1120 | * send first data block. | |
1121 | */ | |
1122 | ||
1123 | /* ata_pio_sectors() might change the state | |
1124 | * to HSM_ST_LAST. so, the state is changed here | |
1125 | * before ata_pio_sectors(). | |
1126 | */ | |
1127 | ap->hsm_task_state = HSM_ST; | |
1128 | ata_pio_sectors(qc); | |
1129 | } else | |
1130 | /* send CDB */ | |
1131 | atapi_send_cdb(ap, qc); | |
1132 | ||
1133 | if (in_wq) | |
1134 | spin_unlock_irqrestore(ap->lock, flags); | |
1135 | ||
c429137a | 1136 | /* if polling, ata_sff_pio_task() handles the rest. |
624d5c51 TH |
1137 | * otherwise, interrupt handler takes over from here. |
1138 | */ | |
1139 | break; | |
1140 | ||
1141 | case HSM_ST: | |
1142 | /* complete command or read/write the data register */ | |
1143 | if (qc->tf.protocol == ATAPI_PROT_PIO) { | |
1144 | /* ATAPI PIO protocol */ | |
1145 | if ((status & ATA_DRQ) == 0) { | |
1146 | /* No more data to transfer or device error. | |
1147 | * Device error will be tagged in HSM_ST_LAST. | |
1148 | */ | |
1149 | ap->hsm_task_state = HSM_ST_LAST; | |
1150 | goto fsm_start; | |
1151 | } | |
1152 | ||
1153 | /* Device should not ask for data transfer (DRQ=1) | |
1154 | * when it finds something wrong. | |
1155 | * We ignore DRQ here and stop the HSM by | |
1156 | * changing hsm_task_state to HSM_ST_ERR and | |
1157 | * let the EH abort the command or reset the device. | |
1158 | */ | |
1159 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
a836d3e8 TH |
1160 | ata_ehi_push_desc(ehi, "ST-ATAPI: " |
1161 | "DRQ=1 with device error, " | |
1162 | "dev_stat 0x%X", status); | |
624d5c51 TH |
1163 | qc->err_mask |= AC_ERR_HSM; |
1164 | ap->hsm_task_state = HSM_ST_ERR; | |
1165 | goto fsm_start; | |
1166 | } | |
1167 | ||
1168 | atapi_pio_bytes(qc); | |
1169 | ||
1170 | if (unlikely(ap->hsm_task_state == HSM_ST_ERR)) | |
1171 | /* bad ireason reported by device */ | |
1172 | goto fsm_start; | |
1173 | ||
1174 | } else { | |
1175 | /* ATA PIO protocol */ | |
1176 | if (unlikely((status & ATA_DRQ) == 0)) { | |
1177 | /* handle BSY=0, DRQ=0 as error */ | |
6a6b97d3 | 1178 | if (likely(status & (ATA_ERR | ATA_DF))) { |
624d5c51 TH |
1179 | /* device stops HSM for abort/error */ |
1180 | qc->err_mask |= AC_ERR_DEV; | |
6a6b97d3 TH |
1181 | |
1182 | /* If diagnostic failed and this is | |
1183 | * IDENTIFY, it's likely a phantom | |
1184 | * device. Mark hint. | |
1185 | */ | |
1186 | if (qc->dev->horkage & | |
1187 | ATA_HORKAGE_DIAGNOSTIC) | |
1188 | qc->err_mask |= | |
1189 | AC_ERR_NODEV_HINT; | |
1190 | } else { | |
624d5c51 TH |
1191 | /* HSM violation. Let EH handle this. |
1192 | * Phantom devices also trigger this | |
1193 | * condition. Mark hint. | |
1194 | */ | |
a836d3e8 | 1195 | ata_ehi_push_desc(ehi, "ST-ATA: " |
80ee6f54 | 1196 | "DRQ=0 without device error, " |
a836d3e8 | 1197 | "dev_stat 0x%X", status); |
624d5c51 TH |
1198 | qc->err_mask |= AC_ERR_HSM | |
1199 | AC_ERR_NODEV_HINT; | |
a836d3e8 | 1200 | } |
624d5c51 TH |
1201 | |
1202 | ap->hsm_task_state = HSM_ST_ERR; | |
1203 | goto fsm_start; | |
1204 | } | |
1205 | ||
1206 | /* For PIO reads, some devices may ask for | |
1207 | * data transfer (DRQ=1) alone with ERR=1. | |
1208 | * We respect DRQ here and transfer one | |
1209 | * block of junk data before changing the | |
1210 | * hsm_task_state to HSM_ST_ERR. | |
1211 | * | |
1212 | * For PIO writes, ERR=1 DRQ=1 doesn't make | |
1213 | * sense since the data block has been | |
1214 | * transferred to the device. | |
1215 | */ | |
1216 | if (unlikely(status & (ATA_ERR | ATA_DF))) { | |
1217 | /* data might be corrputed */ | |
1218 | qc->err_mask |= AC_ERR_DEV; | |
1219 | ||
1220 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) { | |
1221 | ata_pio_sectors(qc); | |
1222 | status = ata_wait_idle(ap); | |
1223 | } | |
1224 | ||
a836d3e8 TH |
1225 | if (status & (ATA_BUSY | ATA_DRQ)) { |
1226 | ata_ehi_push_desc(ehi, "ST-ATA: " | |
1227 | "BUSY|DRQ persists on ERR|DF, " | |
1228 | "dev_stat 0x%X", status); | |
624d5c51 | 1229 | qc->err_mask |= AC_ERR_HSM; |
a836d3e8 | 1230 | } |
624d5c51 | 1231 | |
b919930c TH |
1232 | /* There are oddball controllers with |
1233 | * status register stuck at 0x7f and | |
1234 | * lbal/m/h at zero which makes it | |
1235 | * pass all other presence detection | |
1236 | * mechanisms we have. Set NODEV_HINT | |
1237 | * for it. Kernel bz#7241. | |
1238 | */ | |
1239 | if (status == 0x7f) | |
1240 | qc->err_mask |= AC_ERR_NODEV_HINT; | |
1241 | ||
624d5c51 TH |
1242 | /* ata_pio_sectors() might change the |
1243 | * state to HSM_ST_LAST. so, the state | |
1244 | * is changed after ata_pio_sectors(). | |
1245 | */ | |
1246 | ap->hsm_task_state = HSM_ST_ERR; | |
1247 | goto fsm_start; | |
1248 | } | |
1249 | ||
1250 | ata_pio_sectors(qc); | |
1251 | ||
1252 | if (ap->hsm_task_state == HSM_ST_LAST && | |
1253 | (!(qc->tf.flags & ATA_TFLAG_WRITE))) { | |
1254 | /* all data read */ | |
1255 | status = ata_wait_idle(ap); | |
1256 | goto fsm_start; | |
1257 | } | |
1258 | } | |
1259 | ||
1260 | poll_next = 1; | |
1261 | break; | |
1262 | ||
1263 | case HSM_ST_LAST: | |
1264 | if (unlikely(!ata_ok(status))) { | |
1265 | qc->err_mask |= __ac_err_mask(status); | |
1266 | ap->hsm_task_state = HSM_ST_ERR; | |
1267 | goto fsm_start; | |
1268 | } | |
1269 | ||
1270 | /* no more data to transfer */ | |
1271 | DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n", | |
1272 | ap->print_id, qc->dev->devno, status); | |
1273 | ||
efcb3cf7 | 1274 | WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM)); |
624d5c51 TH |
1275 | |
1276 | ap->hsm_task_state = HSM_ST_IDLE; | |
1277 | ||
1278 | /* complete taskfile transaction */ | |
1279 | ata_hsm_qc_complete(qc, in_wq); | |
1280 | ||
1281 | poll_next = 0; | |
1282 | break; | |
1283 | ||
1284 | case HSM_ST_ERR: | |
624d5c51 TH |
1285 | ap->hsm_task_state = HSM_ST_IDLE; |
1286 | ||
1287 | /* complete taskfile transaction */ | |
1288 | ata_hsm_qc_complete(qc, in_wq); | |
1289 | ||
1290 | poll_next = 0; | |
1291 | break; | |
1292 | default: | |
1293 | poll_next = 0; | |
1294 | BUG(); | |
1295 | } | |
1296 | ||
1297 | return poll_next; | |
1298 | } | |
0fe40ff8 | 1299 | EXPORT_SYMBOL_GPL(ata_sff_hsm_move); |
624d5c51 | 1300 | |
c429137a TH |
1301 | void ata_sff_queue_pio_task(struct ata_port *ap, unsigned long delay) |
1302 | { | |
1303 | /* may fail if ata_sff_flush_pio_task() in progress */ | |
1304 | queue_delayed_work(ata_sff_wq, &ap->sff_pio_task, | |
1305 | msecs_to_jiffies(delay)); | |
1306 | } | |
1307 | EXPORT_SYMBOL_GPL(ata_sff_queue_pio_task); | |
1308 | ||
1309 | void ata_sff_flush_pio_task(struct ata_port *ap) | |
1310 | { | |
1311 | DPRINTK("ENTER\n"); | |
1312 | ||
1313 | cancel_rearming_delayed_work(&ap->sff_pio_task); | |
1314 | ap->hsm_task_state = HSM_ST_IDLE; | |
1315 | ||
1316 | if (ata_msg_ctl(ap)) | |
1317 | ata_port_printk(ap, KERN_DEBUG, "%s: EXIT\n", __func__); | |
1318 | } | |
1319 | ||
1320 | static void ata_sff_pio_task(struct work_struct *work) | |
624d5c51 TH |
1321 | { |
1322 | struct ata_port *ap = | |
c429137a TH |
1323 | container_of(work, struct ata_port, sff_pio_task.work); |
1324 | struct ata_queued_cmd *qc; | |
624d5c51 TH |
1325 | u8 status; |
1326 | int poll_next; | |
1327 | ||
c429137a TH |
1328 | /* qc can be NULL if timeout occurred */ |
1329 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
1330 | if (!qc) | |
1331 | return; | |
1332 | ||
624d5c51 | 1333 | fsm_start: |
efcb3cf7 | 1334 | WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE); |
624d5c51 TH |
1335 | |
1336 | /* | |
1337 | * This is purely heuristic. This is a fast path. | |
1338 | * Sometimes when we enter, BSY will be cleared in | |
1339 | * a chk-status or two. If not, the drive is probably seeking | |
1340 | * or something. Snooze for a couple msecs, then | |
1341 | * chk-status again. If still busy, queue delayed work. | |
1342 | */ | |
9363c382 | 1343 | status = ata_sff_busy_wait(ap, ATA_BUSY, 5); |
624d5c51 TH |
1344 | if (status & ATA_BUSY) { |
1345 | msleep(2); | |
9363c382 | 1346 | status = ata_sff_busy_wait(ap, ATA_BUSY, 10); |
624d5c51 | 1347 | if (status & ATA_BUSY) { |
c429137a | 1348 | ata_sff_queue_pio_task(ap, ATA_SHORT_PAUSE); |
624d5c51 TH |
1349 | return; |
1350 | } | |
1351 | } | |
1352 | ||
1353 | /* move the HSM */ | |
9363c382 | 1354 | poll_next = ata_sff_hsm_move(ap, qc, status, 1); |
624d5c51 TH |
1355 | |
1356 | /* another command or interrupt handler | |
1357 | * may be running at this point. | |
1358 | */ | |
1359 | if (poll_next) | |
1360 | goto fsm_start; | |
1361 | } | |
1362 | ||
1363 | /** | |
360ff783 | 1364 | * ata_sff_qc_issue - issue taskfile to a SFF controller |
624d5c51 TH |
1365 | * @qc: command to issue to device |
1366 | * | |
360ff783 TH |
1367 | * This function issues a PIO or NODATA command to a SFF |
1368 | * controller. | |
624d5c51 TH |
1369 | * |
1370 | * LOCKING: | |
1371 | * spin_lock_irqsave(host lock) | |
1372 | * | |
1373 | * RETURNS: | |
1374 | * Zero on success, AC_ERR_* mask on failure | |
1375 | */ | |
9363c382 | 1376 | unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc) |
624d5c51 TH |
1377 | { |
1378 | struct ata_port *ap = qc->ap; | |
1379 | ||
1380 | /* Use polling pio if the LLD doesn't handle | |
1381 | * interrupt driven pio and atapi CDB interrupt. | |
1382 | */ | |
360ff783 TH |
1383 | if (ap->flags & ATA_FLAG_PIO_POLLING) |
1384 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
624d5c51 TH |
1385 | |
1386 | /* select the device */ | |
1387 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
1388 | ||
1389 | /* start the command */ | |
1390 | switch (qc->tf.protocol) { | |
1391 | case ATA_PROT_NODATA: | |
1392 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1393 | ata_qc_set_polling(qc); | |
1394 | ||
1395 | ata_tf_to_host(ap, &qc->tf); | |
1396 | ap->hsm_task_state = HSM_ST_LAST; | |
1397 | ||
1398 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
c429137a | 1399 | ata_sff_queue_pio_task(ap, 0); |
624d5c51 TH |
1400 | |
1401 | break; | |
1402 | ||
624d5c51 TH |
1403 | case ATA_PROT_PIO: |
1404 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1405 | ata_qc_set_polling(qc); | |
1406 | ||
1407 | ata_tf_to_host(ap, &qc->tf); | |
1408 | ||
1409 | if (qc->tf.flags & ATA_TFLAG_WRITE) { | |
1410 | /* PIO data out protocol */ | |
1411 | ap->hsm_task_state = HSM_ST_FIRST; | |
c429137a | 1412 | ata_sff_queue_pio_task(ap, 0); |
624d5c51 | 1413 | |
c429137a TH |
1414 | /* always send first data block using the |
1415 | * ata_sff_pio_task() codepath. | |
624d5c51 TH |
1416 | */ |
1417 | } else { | |
1418 | /* PIO data in protocol */ | |
1419 | ap->hsm_task_state = HSM_ST; | |
1420 | ||
1421 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
c429137a | 1422 | ata_sff_queue_pio_task(ap, 0); |
624d5c51 | 1423 | |
c429137a TH |
1424 | /* if polling, ata_sff_pio_task() handles the |
1425 | * rest. otherwise, interrupt handler takes | |
1426 | * over from here. | |
624d5c51 TH |
1427 | */ |
1428 | } | |
1429 | ||
1430 | break; | |
1431 | ||
1432 | case ATAPI_PROT_PIO: | |
1433 | case ATAPI_PROT_NODATA: | |
1434 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
1435 | ata_qc_set_polling(qc); | |
1436 | ||
1437 | ata_tf_to_host(ap, &qc->tf); | |
1438 | ||
1439 | ap->hsm_task_state = HSM_ST_FIRST; | |
1440 | ||
1441 | /* send cdb by polling if no cdb interrupt */ | |
1442 | if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) || | |
1443 | (qc->tf.flags & ATA_TFLAG_POLLING)) | |
c429137a | 1444 | ata_sff_queue_pio_task(ap, 0); |
624d5c51 TH |
1445 | break; |
1446 | ||
624d5c51 | 1447 | default: |
efcb3cf7 | 1448 | WARN_ON_ONCE(1); |
624d5c51 TH |
1449 | return AC_ERR_SYSTEM; |
1450 | } | |
1451 | ||
1452 | return 0; | |
1453 | } | |
0fe40ff8 | 1454 | EXPORT_SYMBOL_GPL(ata_sff_qc_issue); |
624d5c51 | 1455 | |
22183bf5 TH |
1456 | /** |
1457 | * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read | |
1458 | * @qc: qc to fill result TF for | |
1459 | * | |
1460 | * @qc is finished and result TF needs to be filled. Fill it | |
1461 | * using ->sff_tf_read. | |
1462 | * | |
1463 | * LOCKING: | |
1464 | * spin_lock_irqsave(host lock) | |
1465 | * | |
1466 | * RETURNS: | |
1467 | * true indicating that result TF is successfully filled. | |
1468 | */ | |
1469 | bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc) | |
1470 | { | |
1471 | qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf); | |
1472 | return true; | |
1473 | } | |
0fe40ff8 | 1474 | EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf); |
22183bf5 | 1475 | |
c3b28894 | 1476 | static unsigned int ata_sff_idle_irq(struct ata_port *ap) |
624d5c51 | 1477 | { |
c3b28894 TH |
1478 | ap->stats.idle_irq++; |
1479 | ||
1480 | #ifdef ATA_IRQ_TRAP | |
1481 | if ((ap->stats.idle_irq % 1000) == 0) { | |
1482 | ap->ops->sff_check_status(ap); | |
1483 | if (ap->ops->sff_irq_clear) | |
1484 | ap->ops->sff_irq_clear(ap); | |
1485 | ata_port_printk(ap, KERN_WARNING, "irq trap\n"); | |
1486 | return 1; | |
1487 | } | |
1488 | #endif | |
1489 | return 0; /* irq not handled */ | |
1490 | } | |
1491 | ||
1492 | static unsigned int __ata_sff_port_intr(struct ata_port *ap, | |
1493 | struct ata_queued_cmd *qc, | |
1494 | bool hsmv_on_idle) | |
1495 | { | |
1496 | u8 status; | |
624d5c51 TH |
1497 | |
1498 | VPRINTK("ata%u: protocol %d task_state %d\n", | |
1499 | ap->print_id, qc->tf.protocol, ap->hsm_task_state); | |
1500 | ||
1501 | /* Check whether we are expecting interrupt in this state */ | |
1502 | switch (ap->hsm_task_state) { | |
1503 | case HSM_ST_FIRST: | |
1504 | /* Some pre-ATAPI-4 devices assert INTRQ | |
1505 | * at this state when ready to receive CDB. | |
1506 | */ | |
1507 | ||
1508 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
1509 | * The flag was turned on only for atapi devices. No | |
1510 | * need to check ata_is_atapi(qc->tf.protocol) again. | |
1511 | */ | |
1512 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
c3b28894 | 1513 | return ata_sff_idle_irq(ap); |
624d5c51 TH |
1514 | break; |
1515 | case HSM_ST: | |
c3b28894 | 1516 | case HSM_ST_LAST: |
624d5c51 TH |
1517 | break; |
1518 | default: | |
c3b28894 | 1519 | return ata_sff_idle_irq(ap); |
624d5c51 TH |
1520 | } |
1521 | ||
a57c1bad AC |
1522 | /* check main status, clearing INTRQ if needed */ |
1523 | status = ata_sff_irq_status(ap); | |
332ac7ff | 1524 | if (status & ATA_BUSY) { |
c3b28894 | 1525 | if (hsmv_on_idle) { |
332ac7ff TH |
1526 | /* BMDMA engine is already stopped, we're screwed */ |
1527 | qc->err_mask |= AC_ERR_HSM; | |
1528 | ap->hsm_task_state = HSM_ST_ERR; | |
1529 | } else | |
c3b28894 | 1530 | return ata_sff_idle_irq(ap); |
332ac7ff | 1531 | } |
624d5c51 | 1532 | |
9f2f7210 | 1533 | /* clear irq events */ |
37f65b8b TH |
1534 | if (ap->ops->sff_irq_clear) |
1535 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 1536 | |
9363c382 | 1537 | ata_sff_hsm_move(ap, qc, status, 0); |
624d5c51 | 1538 | |
624d5c51 | 1539 | return 1; /* irq handled */ |
624d5c51 TH |
1540 | } |
1541 | ||
1542 | /** | |
c3b28894 TH |
1543 | * ata_sff_port_intr - Handle SFF port interrupt |
1544 | * @ap: Port on which interrupt arrived (possibly...) | |
1545 | * @qc: Taskfile currently active in engine | |
624d5c51 | 1546 | * |
c3b28894 | 1547 | * Handle port interrupt for given queued command. |
624d5c51 TH |
1548 | * |
1549 | * LOCKING: | |
c3b28894 | 1550 | * spin_lock_irqsave(host lock) |
624d5c51 TH |
1551 | * |
1552 | * RETURNS: | |
c3b28894 | 1553 | * One if interrupt was handled, zero if not (shared irq). |
624d5c51 | 1554 | */ |
c3b28894 TH |
1555 | unsigned int ata_sff_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) |
1556 | { | |
1557 | return __ata_sff_port_intr(ap, qc, false); | |
1558 | } | |
1559 | EXPORT_SYMBOL_GPL(ata_sff_port_intr); | |
1560 | ||
1561 | static inline irqreturn_t __ata_sff_interrupt(int irq, void *dev_instance, | |
1562 | unsigned int (*port_intr)(struct ata_port *, struct ata_queued_cmd *)) | |
624d5c51 TH |
1563 | { |
1564 | struct ata_host *host = dev_instance; | |
332ac7ff | 1565 | bool retried = false; |
624d5c51 | 1566 | unsigned int i; |
332ac7ff | 1567 | unsigned int handled, idle, polling; |
624d5c51 TH |
1568 | unsigned long flags; |
1569 | ||
1570 | /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */ | |
1571 | spin_lock_irqsave(&host->lock, flags); | |
1572 | ||
332ac7ff TH |
1573 | retry: |
1574 | handled = idle = polling = 0; | |
624d5c51 | 1575 | for (i = 0; i < host->n_ports; i++) { |
d88ec2e5 TH |
1576 | struct ata_port *ap = host->ports[i]; |
1577 | struct ata_queued_cmd *qc; | |
624d5c51 | 1578 | |
d88ec2e5 | 1579 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
27943620 TH |
1580 | if (qc) { |
1581 | if (!(qc->tf.flags & ATA_TFLAG_POLLING)) | |
c3b28894 | 1582 | handled |= port_intr(ap, qc); |
27943620 TH |
1583 | else |
1584 | polling |= 1 << i; | |
332ac7ff TH |
1585 | } else |
1586 | idle |= 1 << i; | |
27943620 TH |
1587 | } |
1588 | ||
1589 | /* | |
1590 | * If no port was expecting IRQ but the controller is actually | |
1591 | * asserting IRQ line, nobody cared will ensue. Check IRQ | |
1592 | * pending status if available and clear spurious IRQ. | |
1593 | */ | |
332ac7ff TH |
1594 | if (!handled && !retried) { |
1595 | bool retry = false; | |
1596 | ||
27943620 TH |
1597 | for (i = 0; i < host->n_ports; i++) { |
1598 | struct ata_port *ap = host->ports[i]; | |
1599 | ||
1600 | if (polling & (1 << i)) | |
1601 | continue; | |
1602 | ||
1603 | if (!ap->ops->sff_irq_check || | |
1604 | !ap->ops->sff_irq_check(ap)) | |
1605 | continue; | |
1606 | ||
332ac7ff TH |
1607 | if (idle & (1 << i)) { |
1608 | ap->ops->sff_check_status(ap); | |
37f65b8b TH |
1609 | if (ap->ops->sff_irq_clear) |
1610 | ap->ops->sff_irq_clear(ap); | |
332ac7ff TH |
1611 | } else { |
1612 | /* clear INTRQ and check if BUSY cleared */ | |
1613 | if (!(ap->ops->sff_check_status(ap) & ATA_BUSY)) | |
1614 | retry |= true; | |
1615 | /* | |
1616 | * With command in flight, we can't do | |
1617 | * sff_irq_clear() w/o racing with completion. | |
1618 | */ | |
1619 | } | |
1620 | } | |
1621 | ||
1622 | if (retry) { | |
1623 | retried = true; | |
1624 | goto retry; | |
27943620 | 1625 | } |
624d5c51 TH |
1626 | } |
1627 | ||
1628 | spin_unlock_irqrestore(&host->lock, flags); | |
1629 | ||
1630 | return IRQ_RETVAL(handled); | |
1631 | } | |
c3b28894 TH |
1632 | |
1633 | /** | |
1634 | * ata_sff_interrupt - Default SFF ATA host interrupt handler | |
1635 | * @irq: irq line (unused) | |
1636 | * @dev_instance: pointer to our ata_host information structure | |
1637 | * | |
1638 | * Default interrupt handler for PCI IDE devices. Calls | |
1639 | * ata_sff_port_intr() for each port that is not disabled. | |
1640 | * | |
1641 | * LOCKING: | |
1642 | * Obtains host lock during operation. | |
1643 | * | |
1644 | * RETURNS: | |
1645 | * IRQ_NONE or IRQ_HANDLED. | |
1646 | */ | |
1647 | irqreturn_t ata_sff_interrupt(int irq, void *dev_instance) | |
1648 | { | |
1649 | return __ata_sff_interrupt(irq, dev_instance, ata_sff_port_intr); | |
1650 | } | |
0fe40ff8 | 1651 | EXPORT_SYMBOL_GPL(ata_sff_interrupt); |
624d5c51 | 1652 | |
c96f1732 AC |
1653 | /** |
1654 | * ata_sff_lost_interrupt - Check for an apparent lost interrupt | |
1655 | * @ap: port that appears to have timed out | |
1656 | * | |
1657 | * Called from the libata error handlers when the core code suspects | |
1658 | * an interrupt has been lost. If it has complete anything we can and | |
1659 | * then return. Interface must support altstatus for this faster | |
1660 | * recovery to occur. | |
1661 | * | |
1662 | * Locking: | |
1663 | * Caller holds host lock | |
1664 | */ | |
1665 | ||
1666 | void ata_sff_lost_interrupt(struct ata_port *ap) | |
1667 | { | |
1668 | u8 status; | |
1669 | struct ata_queued_cmd *qc; | |
1670 | ||
1671 | /* Only one outstanding command per SFF channel */ | |
1672 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
3e4ec344 TH |
1673 | /* We cannot lose an interrupt on a non-existent or polled command */ |
1674 | if (!qc || qc->tf.flags & ATA_TFLAG_POLLING) | |
c96f1732 AC |
1675 | return; |
1676 | /* See if the controller thinks it is still busy - if so the command | |
1677 | isn't a lost IRQ but is still in progress */ | |
1678 | status = ata_sff_altstatus(ap); | |
1679 | if (status & ATA_BUSY) | |
1680 | return; | |
1681 | ||
1682 | /* There was a command running, we are no longer busy and we have | |
1683 | no interrupt. */ | |
1684 | ata_port_printk(ap, KERN_WARNING, "lost interrupt (Status 0x%x)\n", | |
1685 | status); | |
1686 | /* Run the host interrupt logic as if the interrupt had not been | |
1687 | lost */ | |
c3b28894 | 1688 | ata_sff_port_intr(ap, qc); |
c96f1732 AC |
1689 | } |
1690 | EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt); | |
1691 | ||
624d5c51 | 1692 | /** |
9363c382 | 1693 | * ata_sff_freeze - Freeze SFF controller port |
624d5c51 TH |
1694 | * @ap: port to freeze |
1695 | * | |
9f2f7210 | 1696 | * Freeze SFF controller port. |
624d5c51 TH |
1697 | * |
1698 | * LOCKING: | |
1699 | * Inherited from caller. | |
1700 | */ | |
9363c382 | 1701 | void ata_sff_freeze(struct ata_port *ap) |
624d5c51 | 1702 | { |
624d5c51 TH |
1703 | ap->ctl |= ATA_NIEN; |
1704 | ap->last_ctl = ap->ctl; | |
1705 | ||
41dec29b SS |
1706 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) |
1707 | ata_sff_set_devctl(ap, ap->ctl); | |
624d5c51 TH |
1708 | |
1709 | /* Under certain circumstances, some controllers raise IRQ on | |
1710 | * ATA_NIEN manipulation. Also, many controllers fail to mask | |
1711 | * previously pending IRQ on ATA_NIEN assertion. Clear it. | |
1712 | */ | |
5682ed33 | 1713 | ap->ops->sff_check_status(ap); |
624d5c51 | 1714 | |
37f65b8b TH |
1715 | if (ap->ops->sff_irq_clear) |
1716 | ap->ops->sff_irq_clear(ap); | |
624d5c51 | 1717 | } |
0fe40ff8 | 1718 | EXPORT_SYMBOL_GPL(ata_sff_freeze); |
624d5c51 TH |
1719 | |
1720 | /** | |
9363c382 | 1721 | * ata_sff_thaw - Thaw SFF controller port |
624d5c51 TH |
1722 | * @ap: port to thaw |
1723 | * | |
9363c382 | 1724 | * Thaw SFF controller port. |
624d5c51 TH |
1725 | * |
1726 | * LOCKING: | |
1727 | * Inherited from caller. | |
1728 | */ | |
9363c382 | 1729 | void ata_sff_thaw(struct ata_port *ap) |
272f7884 | 1730 | { |
624d5c51 | 1731 | /* clear & re-enable interrupts */ |
5682ed33 | 1732 | ap->ops->sff_check_status(ap); |
37f65b8b TH |
1733 | if (ap->ops->sff_irq_clear) |
1734 | ap->ops->sff_irq_clear(ap); | |
e42a542b | 1735 | ata_sff_irq_on(ap); |
272f7884 | 1736 | } |
0fe40ff8 | 1737 | EXPORT_SYMBOL_GPL(ata_sff_thaw); |
272f7884 | 1738 | |
0aa1113d TH |
1739 | /** |
1740 | * ata_sff_prereset - prepare SFF link for reset | |
1741 | * @link: SFF link to be reset | |
1742 | * @deadline: deadline jiffies for the operation | |
1743 | * | |
1744 | * SFF link @link is about to be reset. Initialize it. It first | |
1745 | * calls ata_std_prereset() and wait for !BSY if the port is | |
1746 | * being softreset. | |
1747 | * | |
1748 | * LOCKING: | |
1749 | * Kernel thread context (may sleep) | |
1750 | * | |
1751 | * RETURNS: | |
1752 | * 0 on success, -errno otherwise. | |
1753 | */ | |
1754 | int ata_sff_prereset(struct ata_link *link, unsigned long deadline) | |
1755 | { | |
0aa1113d TH |
1756 | struct ata_eh_context *ehc = &link->eh_context; |
1757 | int rc; | |
1758 | ||
1759 | rc = ata_std_prereset(link, deadline); | |
1760 | if (rc) | |
1761 | return rc; | |
1762 | ||
1763 | /* if we're about to do hardreset, nothing more to do */ | |
1764 | if (ehc->i.action & ATA_EH_HARDRESET) | |
1765 | return 0; | |
1766 | ||
1767 | /* wait for !BSY if we don't know that no device is attached */ | |
1768 | if (!ata_link_offline(link)) { | |
705e76be | 1769 | rc = ata_sff_wait_ready(link, deadline); |
0aa1113d TH |
1770 | if (rc && rc != -ENODEV) { |
1771 | ata_link_printk(link, KERN_WARNING, "device not ready " | |
1772 | "(errno=%d), forcing hardreset\n", rc); | |
1773 | ehc->i.action |= ATA_EH_HARDRESET; | |
1774 | } | |
1775 | } | |
1776 | ||
1777 | return 0; | |
1778 | } | |
0fe40ff8 | 1779 | EXPORT_SYMBOL_GPL(ata_sff_prereset); |
0aa1113d | 1780 | |
90088bb4 | 1781 | /** |
624d5c51 TH |
1782 | * ata_devchk - PATA device presence detection |
1783 | * @ap: ATA channel to examine | |
1784 | * @device: Device to examine (starting at zero) | |
90088bb4 | 1785 | * |
624d5c51 TH |
1786 | * This technique was originally described in |
1787 | * Hale Landis's ATADRVR (www.ata-atapi.com), and | |
1788 | * later found its way into the ATA/ATAPI spec. | |
1789 | * | |
1790 | * Write a pattern to the ATA shadow registers, | |
1791 | * and if a device is present, it will respond by | |
1792 | * correctly storing and echoing back the | |
1793 | * ATA shadow register contents. | |
90088bb4 TH |
1794 | * |
1795 | * LOCKING: | |
624d5c51 | 1796 | * caller. |
90088bb4 | 1797 | */ |
624d5c51 | 1798 | static unsigned int ata_devchk(struct ata_port *ap, unsigned int device) |
90088bb4 TH |
1799 | { |
1800 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
624d5c51 | 1801 | u8 nsect, lbal; |
90088bb4 | 1802 | |
5682ed33 | 1803 | ap->ops->sff_dev_select(ap, device); |
90088bb4 | 1804 | |
624d5c51 TH |
1805 | iowrite8(0x55, ioaddr->nsect_addr); |
1806 | iowrite8(0xaa, ioaddr->lbal_addr); | |
90088bb4 | 1807 | |
624d5c51 TH |
1808 | iowrite8(0xaa, ioaddr->nsect_addr); |
1809 | iowrite8(0x55, ioaddr->lbal_addr); | |
90088bb4 | 1810 | |
624d5c51 TH |
1811 | iowrite8(0x55, ioaddr->nsect_addr); |
1812 | iowrite8(0xaa, ioaddr->lbal_addr); | |
1813 | ||
1814 | nsect = ioread8(ioaddr->nsect_addr); | |
1815 | lbal = ioread8(ioaddr->lbal_addr); | |
1816 | ||
1817 | if ((nsect == 0x55) && (lbal == 0xaa)) | |
1818 | return 1; /* we found a device */ | |
1819 | ||
1820 | return 0; /* nothing found */ | |
90088bb4 TH |
1821 | } |
1822 | ||
272f7884 | 1823 | /** |
9363c382 | 1824 | * ata_sff_dev_classify - Parse returned ATA device signature |
624d5c51 TH |
1825 | * @dev: ATA device to classify (starting at zero) |
1826 | * @present: device seems present | |
1827 | * @r_err: Value of error register on completion | |
272f7884 | 1828 | * |
624d5c51 TH |
1829 | * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs, |
1830 | * an ATA/ATAPI-defined set of values is placed in the ATA | |
1831 | * shadow registers, indicating the results of device detection | |
1832 | * and diagnostics. | |
272f7884 | 1833 | * |
624d5c51 TH |
1834 | * Select the ATA device, and read the values from the ATA shadow |
1835 | * registers. Then parse according to the Error register value, | |
1836 | * and the spec-defined values examined by ata_dev_classify(). | |
272f7884 TH |
1837 | * |
1838 | * LOCKING: | |
624d5c51 TH |
1839 | * caller. |
1840 | * | |
1841 | * RETURNS: | |
1842 | * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE. | |
272f7884 | 1843 | */ |
9363c382 | 1844 | unsigned int ata_sff_dev_classify(struct ata_device *dev, int present, |
624d5c51 | 1845 | u8 *r_err) |
272f7884 | 1846 | { |
624d5c51 TH |
1847 | struct ata_port *ap = dev->link->ap; |
1848 | struct ata_taskfile tf; | |
1849 | unsigned int class; | |
1850 | u8 err; | |
1851 | ||
5682ed33 | 1852 | ap->ops->sff_dev_select(ap, dev->devno); |
624d5c51 TH |
1853 | |
1854 | memset(&tf, 0, sizeof(tf)); | |
1855 | ||
5682ed33 | 1856 | ap->ops->sff_tf_read(ap, &tf); |
624d5c51 TH |
1857 | err = tf.feature; |
1858 | if (r_err) | |
1859 | *r_err = err; | |
1860 | ||
1861 | /* see if device passed diags: continue and warn later */ | |
1862 | if (err == 0) | |
1863 | /* diagnostic fail : do nothing _YET_ */ | |
1864 | dev->horkage |= ATA_HORKAGE_DIAGNOSTIC; | |
1865 | else if (err == 1) | |
1866 | /* do nothing */ ; | |
1867 | else if ((dev->devno == 0) && (err == 0x81)) | |
1868 | /* do nothing */ ; | |
1869 | else | |
1870 | return ATA_DEV_NONE; | |
272f7884 | 1871 | |
624d5c51 TH |
1872 | /* determine if device is ATA or ATAPI */ |
1873 | class = ata_dev_classify(&tf); | |
272f7884 | 1874 | |
624d5c51 TH |
1875 | if (class == ATA_DEV_UNKNOWN) { |
1876 | /* If the device failed diagnostic, it's likely to | |
1877 | * have reported incorrect device signature too. | |
1878 | * Assume ATA device if the device seems present but | |
1879 | * device signature is invalid with diagnostic | |
1880 | * failure. | |
1881 | */ | |
1882 | if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC)) | |
1883 | class = ATA_DEV_ATA; | |
1884 | else | |
1885 | class = ATA_DEV_NONE; | |
5682ed33 TH |
1886 | } else if ((class == ATA_DEV_ATA) && |
1887 | (ap->ops->sff_check_status(ap) == 0)) | |
624d5c51 TH |
1888 | class = ATA_DEV_NONE; |
1889 | ||
1890 | return class; | |
272f7884 | 1891 | } |
0fe40ff8 | 1892 | EXPORT_SYMBOL_GPL(ata_sff_dev_classify); |
272f7884 | 1893 | |
705e76be TH |
1894 | /** |
1895 | * ata_sff_wait_after_reset - wait for devices to become ready after reset | |
1896 | * @link: SFF link which is just reset | |
1897 | * @devmask: mask of present devices | |
1898 | * @deadline: deadline jiffies for the operation | |
1899 | * | |
1900 | * Wait devices attached to SFF @link to become ready after | |
1901 | * reset. It contains preceding 150ms wait to avoid accessing TF | |
1902 | * status register too early. | |
1903 | * | |
1904 | * LOCKING: | |
1905 | * Kernel thread context (may sleep). | |
1906 | * | |
1907 | * RETURNS: | |
1908 | * 0 on success, -ENODEV if some or all of devices in @devmask | |
1909 | * don't seem to exist. -errno on other errors. | |
1910 | */ | |
1911 | int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask, | |
1912 | unsigned long deadline) | |
1fdffbce | 1913 | { |
705e76be | 1914 | struct ata_port *ap = link->ap; |
1fdffbce | 1915 | struct ata_ioports *ioaddr = &ap->ioaddr; |
624d5c51 TH |
1916 | unsigned int dev0 = devmask & (1 << 0); |
1917 | unsigned int dev1 = devmask & (1 << 1); | |
1918 | int rc, ret = 0; | |
1fdffbce | 1919 | |
341c2c95 | 1920 | msleep(ATA_WAIT_AFTER_RESET); |
705e76be TH |
1921 | |
1922 | /* always check readiness of the master device */ | |
1923 | rc = ata_sff_wait_ready(link, deadline); | |
1924 | /* -ENODEV means the odd clown forgot the D7 pulldown resistor | |
1925 | * and TF status is 0xff, bail out on it too. | |
624d5c51 | 1926 | */ |
705e76be TH |
1927 | if (rc) |
1928 | return rc; | |
1fdffbce | 1929 | |
624d5c51 TH |
1930 | /* if device 1 was found in ata_devchk, wait for register |
1931 | * access briefly, then wait for BSY to clear. | |
1932 | */ | |
1933 | if (dev1) { | |
1934 | int i; | |
1fdffbce | 1935 | |
5682ed33 | 1936 | ap->ops->sff_dev_select(ap, 1); |
1fdffbce | 1937 | |
624d5c51 TH |
1938 | /* Wait for register access. Some ATAPI devices fail |
1939 | * to set nsect/lbal after reset, so don't waste too | |
1940 | * much time on it. We're gonna wait for !BSY anyway. | |
1941 | */ | |
1942 | for (i = 0; i < 2; i++) { | |
1943 | u8 nsect, lbal; | |
1944 | ||
1945 | nsect = ioread8(ioaddr->nsect_addr); | |
1946 | lbal = ioread8(ioaddr->lbal_addr); | |
1947 | if ((nsect == 1) && (lbal == 1)) | |
1948 | break; | |
1949 | msleep(50); /* give drive a breather */ | |
1950 | } | |
1951 | ||
705e76be | 1952 | rc = ata_sff_wait_ready(link, deadline); |
624d5c51 TH |
1953 | if (rc) { |
1954 | if (rc != -ENODEV) | |
1955 | return rc; | |
1956 | ret = rc; | |
1957 | } | |
1fdffbce JG |
1958 | } |
1959 | ||
624d5c51 | 1960 | /* is all this really necessary? */ |
5682ed33 | 1961 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 | 1962 | if (dev1) |
5682ed33 | 1963 | ap->ops->sff_dev_select(ap, 1); |
624d5c51 | 1964 | if (dev0) |
5682ed33 | 1965 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
1966 | |
1967 | return ret; | |
1fdffbce | 1968 | } |
0fe40ff8 | 1969 | EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset); |
1fdffbce | 1970 | |
624d5c51 TH |
1971 | static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, |
1972 | unsigned long deadline) | |
2cc432ee | 1973 | { |
624d5c51 | 1974 | struct ata_ioports *ioaddr = &ap->ioaddr; |
2cc432ee | 1975 | |
624d5c51 TH |
1976 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); |
1977 | ||
1978 | /* software reset. causes dev0 to be selected */ | |
1979 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
1980 | udelay(20); /* FIXME: flush */ | |
1981 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
1982 | udelay(20); /* FIXME: flush */ | |
1983 | iowrite8(ap->ctl, ioaddr->ctl_addr); | |
e3e4385f | 1984 | ap->last_ctl = ap->ctl; |
624d5c51 | 1985 | |
705e76be TH |
1986 | /* wait the port to become ready */ |
1987 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | |
2cc432ee JG |
1988 | } |
1989 | ||
6d97dbd7 | 1990 | /** |
9363c382 | 1991 | * ata_sff_softreset - reset host port via ATA SRST |
624d5c51 TH |
1992 | * @link: ATA link to reset |
1993 | * @classes: resulting classes of attached devices | |
1994 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 1995 | * |
624d5c51 | 1996 | * Reset host port using ATA SRST. |
6d97dbd7 TH |
1997 | * |
1998 | * LOCKING: | |
624d5c51 TH |
1999 | * Kernel thread context (may sleep) |
2000 | * | |
2001 | * RETURNS: | |
2002 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2003 | */ |
9363c382 | 2004 | int ata_sff_softreset(struct ata_link *link, unsigned int *classes, |
624d5c51 | 2005 | unsigned long deadline) |
6d97dbd7 | 2006 | { |
624d5c51 TH |
2007 | struct ata_port *ap = link->ap; |
2008 | unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS; | |
2009 | unsigned int devmask = 0; | |
2010 | int rc; | |
2011 | u8 err; | |
6d97dbd7 | 2012 | |
624d5c51 | 2013 | DPRINTK("ENTER\n"); |
6d97dbd7 | 2014 | |
624d5c51 TH |
2015 | /* determine if device 0/1 are present */ |
2016 | if (ata_devchk(ap, 0)) | |
2017 | devmask |= (1 << 0); | |
2018 | if (slave_possible && ata_devchk(ap, 1)) | |
2019 | devmask |= (1 << 1); | |
2020 | ||
2021 | /* select device 0 again */ | |
5682ed33 | 2022 | ap->ops->sff_dev_select(ap, 0); |
624d5c51 TH |
2023 | |
2024 | /* issue bus reset */ | |
2025 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
2026 | rc = ata_bus_softreset(ap, devmask, deadline); | |
2027 | /* if link is occupied, -ENODEV too is an error */ | |
2028 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
2029 | ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); | |
2030 | return rc; | |
2031 | } | |
0f0a3ad3 | 2032 | |
624d5c51 | 2033 | /* determine by signature whether we have ATA or ATAPI devices */ |
9363c382 | 2034 | classes[0] = ata_sff_dev_classify(&link->device[0], |
624d5c51 TH |
2035 | devmask & (1 << 0), &err); |
2036 | if (slave_possible && err != 0x81) | |
9363c382 | 2037 | classes[1] = ata_sff_dev_classify(&link->device[1], |
624d5c51 TH |
2038 | devmask & (1 << 1), &err); |
2039 | ||
624d5c51 TH |
2040 | DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); |
2041 | return 0; | |
6d97dbd7 | 2042 | } |
0fe40ff8 | 2043 | EXPORT_SYMBOL_GPL(ata_sff_softreset); |
6d97dbd7 TH |
2044 | |
2045 | /** | |
9363c382 | 2046 | * sata_sff_hardreset - reset host port via SATA phy reset |
624d5c51 TH |
2047 | * @link: link to reset |
2048 | * @class: resulting class of attached device | |
2049 | * @deadline: deadline jiffies for the operation | |
6d97dbd7 | 2050 | * |
624d5c51 TH |
2051 | * SATA phy-reset host port using DET bits of SControl register, |
2052 | * wait for !BSY and classify the attached device. | |
6d97dbd7 TH |
2053 | * |
2054 | * LOCKING: | |
624d5c51 TH |
2055 | * Kernel thread context (may sleep) |
2056 | * | |
2057 | * RETURNS: | |
2058 | * 0 on success, -errno otherwise. | |
6d97dbd7 | 2059 | */ |
9363c382 | 2060 | int sata_sff_hardreset(struct ata_link *link, unsigned int *class, |
624d5c51 | 2061 | unsigned long deadline) |
6d97dbd7 | 2062 | { |
9dadd45b TH |
2063 | struct ata_eh_context *ehc = &link->eh_context; |
2064 | const unsigned long *timing = sata_ehc_deb_timing(ehc); | |
2065 | bool online; | |
624d5c51 TH |
2066 | int rc; |
2067 | ||
9dadd45b TH |
2068 | rc = sata_link_hardreset(link, timing, deadline, &online, |
2069 | ata_sff_check_ready); | |
9dadd45b TH |
2070 | if (online) |
2071 | *class = ata_sff_dev_classify(link->device, 1, NULL); | |
624d5c51 TH |
2072 | |
2073 | DPRINTK("EXIT, class=%u\n", *class); | |
9dadd45b | 2074 | return rc; |
6d97dbd7 | 2075 | } |
0fe40ff8 | 2076 | EXPORT_SYMBOL_GPL(sata_sff_hardreset); |
6d97dbd7 | 2077 | |
203c75b8 TH |
2078 | /** |
2079 | * ata_sff_postreset - SFF postreset callback | |
2080 | * @link: the target SFF ata_link | |
2081 | * @classes: classes of attached devices | |
2082 | * | |
2083 | * This function is invoked after a successful reset. It first | |
2084 | * calls ata_std_postreset() and performs SFF specific postreset | |
2085 | * processing. | |
2086 | * | |
2087 | * LOCKING: | |
2088 | * Kernel thread context (may sleep) | |
2089 | */ | |
2090 | void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |
2091 | { | |
2092 | struct ata_port *ap = link->ap; | |
2093 | ||
2094 | ata_std_postreset(link, classes); | |
2095 | ||
2096 | /* is double-select really necessary? */ | |
2097 | if (classes[0] != ATA_DEV_NONE) | |
2098 | ap->ops->sff_dev_select(ap, 1); | |
2099 | if (classes[1] != ATA_DEV_NONE) | |
2100 | ap->ops->sff_dev_select(ap, 0); | |
2101 | ||
2102 | /* bail out if no device is present */ | |
2103 | if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) { | |
2104 | DPRINTK("EXIT, no device\n"); | |
2105 | return; | |
2106 | } | |
2107 | ||
2108 | /* set up device control */ | |
41dec29b SS |
2109 | if (ap->ops->sff_set_devctl || ap->ioaddr.ctl_addr) { |
2110 | ata_sff_set_devctl(ap, ap->ctl); | |
e3e4385f SM |
2111 | ap->last_ctl = ap->ctl; |
2112 | } | |
203c75b8 | 2113 | } |
0fe40ff8 | 2114 | EXPORT_SYMBOL_GPL(ata_sff_postreset); |
203c75b8 | 2115 | |
3d47aa8e AC |
2116 | /** |
2117 | * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers | |
2118 | * @qc: command | |
2119 | * | |
2120 | * Drain the FIFO and device of any stuck data following a command | |
3ad2f3fb | 2121 | * failing to complete. In some cases this is necessary before a |
3d47aa8e AC |
2122 | * reset will recover the device. |
2123 | * | |
2124 | */ | |
2125 | ||
2126 | void ata_sff_drain_fifo(struct ata_queued_cmd *qc) | |
2127 | { | |
2128 | int count; | |
2129 | struct ata_port *ap; | |
2130 | ||
2131 | /* We only need to flush incoming data when a command was running */ | |
2132 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) | |
2133 | return; | |
2134 | ||
2135 | ap = qc->ap; | |
2136 | /* Drain up to 64K of data before we give up this recovery method */ | |
2137 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) | |
9a8fd68b | 2138 | && count < 65536; count += 2) |
3d47aa8e AC |
2139 | ioread16(ap->ioaddr.data_addr); |
2140 | ||
2141 | /* Can become DEBUG later */ | |
2142 | if (count) | |
2143 | ata_port_printk(ap, KERN_DEBUG, | |
2144 | "drained %d bytes to clear DRQ.\n", count); | |
2145 | ||
2146 | } | |
2147 | EXPORT_SYMBOL_GPL(ata_sff_drain_fifo); | |
2148 | ||
6d97dbd7 | 2149 | /** |
fe06e5f9 | 2150 | * ata_sff_error_handler - Stock error handler for SFF controller |
6d97dbd7 | 2151 | * @ap: port to handle error for |
6d97dbd7 | 2152 | * |
9363c382 | 2153 | * Stock error handler for SFF controller. It can handle both |
6d97dbd7 TH |
2154 | * PATA and SATA controllers. Many controllers should be able to |
2155 | * use this EH as-is or with some added handling before and | |
2156 | * after. | |
2157 | * | |
6d97dbd7 TH |
2158 | * LOCKING: |
2159 | * Kernel thread context (may sleep) | |
2160 | */ | |
9363c382 | 2161 | void ata_sff_error_handler(struct ata_port *ap) |
6d97dbd7 | 2162 | { |
a1efdaba TH |
2163 | ata_reset_fn_t softreset = ap->ops->softreset; |
2164 | ata_reset_fn_t hardreset = ap->ops->hardreset; | |
6d97dbd7 TH |
2165 | struct ata_queued_cmd *qc; |
2166 | unsigned long flags; | |
6d97dbd7 | 2167 | |
9af5c9c9 | 2168 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); |
6d97dbd7 TH |
2169 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) |
2170 | qc = NULL; | |
2171 | ||
ba6a1308 | 2172 | spin_lock_irqsave(ap->lock, flags); |
6d97dbd7 | 2173 | |
fe06e5f9 TH |
2174 | /* |
2175 | * We *MUST* do FIFO draining before we issue a reset as | |
2176 | * several devices helpfully clear their internal state and | |
2177 | * will lock solid if we touch the data port post reset. Pass | |
2178 | * qc in case anyone wants to do different PIO/DMA recovery or | |
2179 | * has per command fixups | |
3d47aa8e | 2180 | */ |
8244cd05 TH |
2181 | if (ap->ops->sff_drain_fifo) |
2182 | ap->ops->sff_drain_fifo(qc); | |
6d97dbd7 | 2183 | |
ba6a1308 | 2184 | spin_unlock_irqrestore(ap->lock, flags); |
6d97dbd7 | 2185 | |
fe06e5f9 | 2186 | /* ignore ata_sff_softreset if ctl isn't accessible */ |
9363c382 | 2187 | if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr) |
a1efdaba | 2188 | softreset = NULL; |
fe06e5f9 TH |
2189 | |
2190 | /* ignore built-in hardresets if SCR access is not available */ | |
2191 | if ((hardreset == sata_std_hardreset || | |
2192 | hardreset == sata_sff_hardreset) && !sata_scr_valid(&ap->link)) | |
a1efdaba | 2193 | hardreset = NULL; |
6d97dbd7 | 2194 | |
a1efdaba TH |
2195 | ata_do_eh(ap, ap->ops->prereset, softreset, hardreset, |
2196 | ap->ops->postreset); | |
6d97dbd7 | 2197 | } |
0fe40ff8 | 2198 | EXPORT_SYMBOL_GPL(ata_sff_error_handler); |
6d97dbd7 | 2199 | |
624d5c51 | 2200 | /** |
9363c382 | 2201 | * ata_sff_std_ports - initialize ioaddr with standard port offsets. |
624d5c51 TH |
2202 | * @ioaddr: IO address structure to be initialized |
2203 | * | |
2204 | * Utility function which initializes data_addr, error_addr, | |
2205 | * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr, | |
2206 | * device_addr, status_addr, and command_addr to standard offsets | |
2207 | * relative to cmd_addr. | |
2208 | * | |
2209 | * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr. | |
2210 | */ | |
9363c382 | 2211 | void ata_sff_std_ports(struct ata_ioports *ioaddr) |
624d5c51 TH |
2212 | { |
2213 | ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA; | |
2214 | ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR; | |
2215 | ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE; | |
2216 | ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT; | |
2217 | ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL; | |
2218 | ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM; | |
2219 | ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH; | |
2220 | ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE; | |
2221 | ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS; | |
2222 | ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD; | |
2223 | } | |
0fe40ff8 | 2224 | EXPORT_SYMBOL_GPL(ata_sff_std_ports); |
624d5c51 | 2225 | |
1fdffbce | 2226 | #ifdef CONFIG_PCI |
4112e16a | 2227 | |
272f7884 TH |
2228 | static int ata_resources_present(struct pci_dev *pdev, int port) |
2229 | { | |
2230 | int i; | |
2231 | ||
2232 | /* Check the PCI resources for this channel are enabled */ | |
2233 | port = port * 2; | |
0fe40ff8 | 2234 | for (i = 0; i < 2; i++) { |
272f7884 TH |
2235 | if (pci_resource_start(pdev, port + i) == 0 || |
2236 | pci_resource_len(pdev, port + i) == 0) | |
2237 | return 0; | |
2238 | } | |
2239 | return 1; | |
2240 | } | |
2241 | ||
d491b27b | 2242 | /** |
9363c382 | 2243 | * ata_pci_sff_init_host - acquire native PCI ATA resources and init host |
d491b27b | 2244 | * @host: target ATA host |
d491b27b | 2245 | * |
1626aeb8 TH |
2246 | * Acquire native PCI ATA resources for @host and initialize the |
2247 | * first two ports of @host accordingly. Ports marked dummy are | |
2248 | * skipped and allocation failure makes the port dummy. | |
d491b27b | 2249 | * |
d583bc18 TH |
2250 | * Note that native PCI resources are valid even for legacy hosts |
2251 | * as we fix up pdev resources array early in boot, so this | |
2252 | * function can be used for both native and legacy SFF hosts. | |
2253 | * | |
d491b27b TH |
2254 | * LOCKING: |
2255 | * Inherited from calling layer (may sleep). | |
2256 | * | |
2257 | * RETURNS: | |
1626aeb8 TH |
2258 | * 0 if at least one port is initialized, -ENODEV if no port is |
2259 | * available. | |
d491b27b | 2260 | */ |
9363c382 | 2261 | int ata_pci_sff_init_host(struct ata_host *host) |
d491b27b TH |
2262 | { |
2263 | struct device *gdev = host->dev; | |
2264 | struct pci_dev *pdev = to_pci_dev(gdev); | |
1626aeb8 | 2265 | unsigned int mask = 0; |
d491b27b TH |
2266 | int i, rc; |
2267 | ||
d491b27b TH |
2268 | /* request, iomap BARs and init port addresses accordingly */ |
2269 | for (i = 0; i < 2; i++) { | |
2270 | struct ata_port *ap = host->ports[i]; | |
2271 | int base = i * 2; | |
2272 | void __iomem * const *iomap; | |
2273 | ||
1626aeb8 TH |
2274 | if (ata_port_is_dummy(ap)) |
2275 | continue; | |
2276 | ||
2277 | /* Discard disabled ports. Some controllers show | |
2278 | * their unused channels this way. Disabled ports are | |
2279 | * made dummy. | |
2280 | */ | |
2281 | if (!ata_resources_present(pdev, i)) { | |
2282 | ap->ops = &ata_dummy_port_ops; | |
d491b27b | 2283 | continue; |
1626aeb8 | 2284 | } |
d491b27b | 2285 | |
35a10a80 TH |
2286 | rc = pcim_iomap_regions(pdev, 0x3 << base, |
2287 | dev_driver_string(gdev)); | |
d491b27b | 2288 | if (rc) { |
1626aeb8 TH |
2289 | dev_printk(KERN_WARNING, gdev, |
2290 | "failed to request/iomap BARs for port %d " | |
2291 | "(errno=%d)\n", i, rc); | |
d491b27b TH |
2292 | if (rc == -EBUSY) |
2293 | pcim_pin_device(pdev); | |
1626aeb8 TH |
2294 | ap->ops = &ata_dummy_port_ops; |
2295 | continue; | |
d491b27b TH |
2296 | } |
2297 | host->iomap = iomap = pcim_iomap_table(pdev); | |
2298 | ||
2299 | ap->ioaddr.cmd_addr = iomap[base]; | |
2300 | ap->ioaddr.altstatus_addr = | |
2301 | ap->ioaddr.ctl_addr = (void __iomem *) | |
2302 | ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS); | |
9363c382 | 2303 | ata_sff_std_ports(&ap->ioaddr); |
1626aeb8 | 2304 | |
cbcdd875 TH |
2305 | ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx", |
2306 | (unsigned long long)pci_resource_start(pdev, base), | |
2307 | (unsigned long long)pci_resource_start(pdev, base + 1)); | |
2308 | ||
1626aeb8 TH |
2309 | mask |= 1 << i; |
2310 | } | |
2311 | ||
2312 | if (!mask) { | |
2313 | dev_printk(KERN_ERR, gdev, "no available native port\n"); | |
2314 | return -ENODEV; | |
d491b27b TH |
2315 | } |
2316 | ||
2317 | return 0; | |
2318 | } | |
0fe40ff8 | 2319 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_host); |
d491b27b | 2320 | |
21b0ad4f | 2321 | /** |
1c5afdf7 | 2322 | * ata_pci_sff_prepare_host - helper to prepare PCI PIO-only SFF ATA host |
21b0ad4f | 2323 | * @pdev: target PCI device |
1626aeb8 | 2324 | * @ppi: array of port_info, must be enough for two ports |
21b0ad4f TH |
2325 | * @r_host: out argument for the initialized ATA host |
2326 | * | |
1c5afdf7 TH |
2327 | * Helper to allocate PIO-only SFF ATA host for @pdev, acquire |
2328 | * all PCI resources and initialize it accordingly in one go. | |
21b0ad4f TH |
2329 | * |
2330 | * LOCKING: | |
2331 | * Inherited from calling layer (may sleep). | |
2332 | * | |
2333 | * RETURNS: | |
2334 | * 0 on success, -errno otherwise. | |
2335 | */ | |
9363c382 | 2336 | int ata_pci_sff_prepare_host(struct pci_dev *pdev, |
0fe40ff8 | 2337 | const struct ata_port_info * const *ppi, |
d583bc18 | 2338 | struct ata_host **r_host) |
21b0ad4f TH |
2339 | { |
2340 | struct ata_host *host; | |
21b0ad4f TH |
2341 | int rc; |
2342 | ||
2343 | if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) | |
2344 | return -ENOMEM; | |
2345 | ||
2346 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
2347 | if (!host) { | |
2348 | dev_printk(KERN_ERR, &pdev->dev, | |
2349 | "failed to allocate ATA host\n"); | |
2350 | rc = -ENOMEM; | |
2351 | goto err_out; | |
2352 | } | |
2353 | ||
9363c382 | 2354 | rc = ata_pci_sff_init_host(host); |
21b0ad4f TH |
2355 | if (rc) |
2356 | goto err_out; | |
2357 | ||
21b0ad4f TH |
2358 | devres_remove_group(&pdev->dev, NULL); |
2359 | *r_host = host; | |
2360 | return 0; | |
2361 | ||
0fe40ff8 | 2362 | err_out: |
21b0ad4f TH |
2363 | devres_release_group(&pdev->dev, NULL); |
2364 | return rc; | |
2365 | } | |
0fe40ff8 | 2366 | EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host); |
21b0ad4f | 2367 | |
4e6b79fa | 2368 | /** |
9363c382 | 2369 | * ata_pci_sff_activate_host - start SFF host, request IRQ and register it |
4e6b79fa TH |
2370 | * @host: target SFF ATA host |
2371 | * @irq_handler: irq_handler used when requesting IRQ(s) | |
2372 | * @sht: scsi_host_template to use when registering the host | |
2373 | * | |
2374 | * This is the counterpart of ata_host_activate() for SFF ATA | |
2375 | * hosts. This separate helper is necessary because SFF hosts | |
2376 | * use two separate interrupts in legacy mode. | |
2377 | * | |
2378 | * LOCKING: | |
2379 | * Inherited from calling layer (may sleep). | |
2380 | * | |
2381 | * RETURNS: | |
2382 | * 0 on success, -errno otherwise. | |
2383 | */ | |
9363c382 | 2384 | int ata_pci_sff_activate_host(struct ata_host *host, |
4e6b79fa TH |
2385 | irq_handler_t irq_handler, |
2386 | struct scsi_host_template *sht) | |
2387 | { | |
2388 | struct device *dev = host->dev; | |
2389 | struct pci_dev *pdev = to_pci_dev(dev); | |
2390 | const char *drv_name = dev_driver_string(host->dev); | |
2391 | int legacy_mode = 0, rc; | |
2392 | ||
2393 | rc = ata_host_start(host); | |
2394 | if (rc) | |
2395 | return rc; | |
2396 | ||
2397 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
2398 | u8 tmp8, mask; | |
2399 | ||
2400 | /* TODO: What if one channel is in native mode ... */ | |
2401 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8); | |
2402 | mask = (1 << 2) | (1 << 0); | |
2403 | if ((tmp8 & mask) != mask) | |
2404 | legacy_mode = 1; | |
2405 | #if defined(CONFIG_NO_ATA_LEGACY) | |
2406 | /* Some platforms with PCI limits cannot address compat | |
2407 | port space. In that case we punt if their firmware has | |
2408 | left a device in compatibility mode */ | |
2409 | if (legacy_mode) { | |
2410 | printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n"); | |
2411 | return -EOPNOTSUPP; | |
2412 | } | |
2413 | #endif | |
2414 | } | |
2415 | ||
2416 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
2417 | return -ENOMEM; | |
2418 | ||
2419 | if (!legacy_mode && pdev->irq) { | |
2420 | rc = devm_request_irq(dev, pdev->irq, irq_handler, | |
2421 | IRQF_SHARED, drv_name, host); | |
2422 | if (rc) | |
2423 | goto out; | |
2424 | ||
2425 | ata_port_desc(host->ports[0], "irq %d", pdev->irq); | |
2426 | ata_port_desc(host->ports[1], "irq %d", pdev->irq); | |
2427 | } else if (legacy_mode) { | |
2428 | if (!ata_port_is_dummy(host->ports[0])) { | |
2429 | rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev), | |
2430 | irq_handler, IRQF_SHARED, | |
2431 | drv_name, host); | |
2432 | if (rc) | |
2433 | goto out; | |
2434 | ||
2435 | ata_port_desc(host->ports[0], "irq %d", | |
2436 | ATA_PRIMARY_IRQ(pdev)); | |
2437 | } | |
2438 | ||
2439 | if (!ata_port_is_dummy(host->ports[1])) { | |
2440 | rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev), | |
2441 | irq_handler, IRQF_SHARED, | |
2442 | drv_name, host); | |
2443 | if (rc) | |
2444 | goto out; | |
2445 | ||
2446 | ata_port_desc(host->ports[1], "irq %d", | |
2447 | ATA_SECONDARY_IRQ(pdev)); | |
2448 | } | |
2449 | } | |
2450 | ||
2451 | rc = ata_host_register(host, sht); | |
0fe40ff8 | 2452 | out: |
4e6b79fa TH |
2453 | if (rc == 0) |
2454 | devres_remove_group(dev, NULL); | |
2455 | else | |
2456 | devres_release_group(dev, NULL); | |
2457 | ||
2458 | return rc; | |
2459 | } | |
0fe40ff8 | 2460 | EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host); |
4e6b79fa | 2461 | |
1c5afdf7 TH |
2462 | static const struct ata_port_info *ata_sff_find_valid_pi( |
2463 | const struct ata_port_info * const *ppi) | |
2464 | { | |
2465 | int i; | |
2466 | ||
2467 | /* look up the first valid port_info */ | |
2468 | for (i = 0; i < 2 && ppi[i]; i++) | |
2469 | if (ppi[i]->port_ops != &ata_dummy_port_ops) | |
2470 | return ppi[i]; | |
2471 | ||
2472 | return NULL; | |
2473 | } | |
2474 | ||
1fdffbce | 2475 | /** |
1c5afdf7 | 2476 | * ata_pci_sff_init_one - Initialize/register PIO-only PCI IDE controller |
1fdffbce | 2477 | * @pdev: Controller to be initialized |
1626aeb8 | 2478 | * @ppi: array of port_info, must be enough for two ports |
1bd5b715 | 2479 | * @sht: scsi_host_template to use when registering the host |
887125e3 | 2480 | * @host_priv: host private_data |
16ea0fc9 | 2481 | * @hflag: host flags |
1fdffbce JG |
2482 | * |
2483 | * This is a helper function which can be called from a driver's | |
2484 | * xxx_init_one() probe function if the hardware uses traditional | |
1c5afdf7 | 2485 | * IDE taskfile registers and is PIO only. |
1fdffbce | 2486 | * |
2ec7df04 AC |
2487 | * ASSUMPTION: |
2488 | * Nobody makes a single channel controller that appears solely as | |
2489 | * the secondary legacy port on PCI. | |
2490 | * | |
1fdffbce JG |
2491 | * LOCKING: |
2492 | * Inherited from PCI layer (may sleep). | |
2493 | * | |
2494 | * RETURNS: | |
2495 | * Zero on success, negative on errno-based value on error. | |
2496 | */ | |
9363c382 | 2497 | int ata_pci_sff_init_one(struct pci_dev *pdev, |
16ea0fc9 AC |
2498 | const struct ata_port_info * const *ppi, |
2499 | struct scsi_host_template *sht, void *host_priv, int hflag) | |
1fdffbce | 2500 | { |
f0d36efd | 2501 | struct device *dev = &pdev->dev; |
1c5afdf7 | 2502 | const struct ata_port_info *pi; |
0f834de3 | 2503 | struct ata_host *host = NULL; |
1c5afdf7 | 2504 | int rc; |
1fdffbce JG |
2505 | |
2506 | DPRINTK("ENTER\n"); | |
2507 | ||
1c5afdf7 | 2508 | pi = ata_sff_find_valid_pi(ppi); |
1626aeb8 TH |
2509 | if (!pi) { |
2510 | dev_printk(KERN_ERR, &pdev->dev, | |
2511 | "no valid port_info specified\n"); | |
2512 | return -EINVAL; | |
2513 | } | |
c791c306 | 2514 | |
1626aeb8 TH |
2515 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) |
2516 | return -ENOMEM; | |
1fdffbce | 2517 | |
f0d36efd | 2518 | rc = pcim_enable_device(pdev); |
1fdffbce | 2519 | if (rc) |
4e6b79fa | 2520 | goto out; |
1fdffbce | 2521 | |
4e6b79fa | 2522 | /* prepare and activate SFF host */ |
9363c382 | 2523 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
d583bc18 | 2524 | if (rc) |
4e6b79fa | 2525 | goto out; |
887125e3 | 2526 | host->private_data = host_priv; |
16ea0fc9 | 2527 | host->flags |= hflag; |
d491b27b | 2528 | |
1c5afdf7 | 2529 | rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht); |
0fe40ff8 | 2530 | out: |
4e6b79fa TH |
2531 | if (rc == 0) |
2532 | devres_remove_group(&pdev->dev, NULL); | |
2533 | else | |
2534 | devres_release_group(&pdev->dev, NULL); | |
d491b27b | 2535 | |
1fdffbce JG |
2536 | return rc; |
2537 | } | |
0fe40ff8 | 2538 | EXPORT_SYMBOL_GPL(ata_pci_sff_init_one); |
1fdffbce JG |
2539 | |
2540 | #endif /* CONFIG_PCI */ | |
9f2f7210 | 2541 | |
9a7780c9 TH |
2542 | /* |
2543 | * BMDMA support | |
2544 | */ | |
2545 | ||
2546 | #ifdef CONFIG_ATA_BMDMA | |
2547 | ||
9f2f7210 TH |
2548 | const struct ata_port_operations ata_bmdma_port_ops = { |
2549 | .inherits = &ata_sff_port_ops, | |
2550 | ||
fe06e5f9 TH |
2551 | .error_handler = ata_bmdma_error_handler, |
2552 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
2553 | ||
f47451c4 | 2554 | .qc_prep = ata_bmdma_qc_prep, |
360ff783 | 2555 | .qc_issue = ata_bmdma_qc_issue, |
f47451c4 | 2556 | |
37f65b8b | 2557 | .sff_irq_clear = ata_bmdma_irq_clear, |
9f2f7210 TH |
2558 | .bmdma_setup = ata_bmdma_setup, |
2559 | .bmdma_start = ata_bmdma_start, | |
2560 | .bmdma_stop = ata_bmdma_stop, | |
2561 | .bmdma_status = ata_bmdma_status, | |
c7087652 TH |
2562 | |
2563 | .port_start = ata_bmdma_port_start, | |
9f2f7210 TH |
2564 | }; |
2565 | EXPORT_SYMBOL_GPL(ata_bmdma_port_ops); | |
2566 | ||
2567 | const struct ata_port_operations ata_bmdma32_port_ops = { | |
2568 | .inherits = &ata_bmdma_port_ops, | |
2569 | ||
2570 | .sff_data_xfer = ata_sff_data_xfer32, | |
c7087652 | 2571 | .port_start = ata_bmdma_port_start32, |
9f2f7210 TH |
2572 | }; |
2573 | EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops); | |
2574 | ||
f47451c4 TH |
2575 | /** |
2576 | * ata_bmdma_fill_sg - Fill PCI IDE PRD table | |
2577 | * @qc: Metadata associated with taskfile to be transferred | |
2578 | * | |
2579 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
2580 | * associated with the current disk command. | |
2581 | * | |
2582 | * LOCKING: | |
2583 | * spin_lock_irqsave(host lock) | |
2584 | * | |
2585 | */ | |
2586 | static void ata_bmdma_fill_sg(struct ata_queued_cmd *qc) | |
2587 | { | |
2588 | struct ata_port *ap = qc->ap; | |
f60d7011 | 2589 | struct ata_bmdma_prd *prd = ap->bmdma_prd; |
f47451c4 TH |
2590 | struct scatterlist *sg; |
2591 | unsigned int si, pi; | |
2592 | ||
2593 | pi = 0; | |
2594 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
2595 | u32 addr, offset; | |
2596 | u32 sg_len, len; | |
2597 | ||
2598 | /* determine if physical DMA addr spans 64K boundary. | |
2599 | * Note h/w doesn't support 64-bit, so we unconditionally | |
2600 | * truncate dma_addr_t to u32. | |
2601 | */ | |
2602 | addr = (u32) sg_dma_address(sg); | |
2603 | sg_len = sg_dma_len(sg); | |
2604 | ||
2605 | while (sg_len) { | |
2606 | offset = addr & 0xffff; | |
2607 | len = sg_len; | |
2608 | if ((offset + sg_len) > 0x10000) | |
2609 | len = 0x10000 - offset; | |
2610 | ||
f60d7011 TH |
2611 | prd[pi].addr = cpu_to_le32(addr); |
2612 | prd[pi].flags_len = cpu_to_le32(len & 0xffff); | |
f47451c4 TH |
2613 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); |
2614 | ||
2615 | pi++; | |
2616 | sg_len -= len; | |
2617 | addr += len; | |
2618 | } | |
2619 | } | |
2620 | ||
f60d7011 | 2621 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
f47451c4 TH |
2622 | } |
2623 | ||
2624 | /** | |
2625 | * ata_bmdma_fill_sg_dumb - Fill PCI IDE PRD table | |
2626 | * @qc: Metadata associated with taskfile to be transferred | |
2627 | * | |
2628 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
2629 | * associated with the current disk command. Perform the fill | |
2630 | * so that we avoid writing any length 64K records for | |
2631 | * controllers that don't follow the spec. | |
2632 | * | |
2633 | * LOCKING: | |
2634 | * spin_lock_irqsave(host lock) | |
2635 | * | |
2636 | */ | |
2637 | static void ata_bmdma_fill_sg_dumb(struct ata_queued_cmd *qc) | |
2638 | { | |
2639 | struct ata_port *ap = qc->ap; | |
f60d7011 | 2640 | struct ata_bmdma_prd *prd = ap->bmdma_prd; |
f47451c4 TH |
2641 | struct scatterlist *sg; |
2642 | unsigned int si, pi; | |
2643 | ||
2644 | pi = 0; | |
2645 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
2646 | u32 addr, offset; | |
2647 | u32 sg_len, len, blen; | |
2648 | ||
2649 | /* determine if physical DMA addr spans 64K boundary. | |
2650 | * Note h/w doesn't support 64-bit, so we unconditionally | |
2651 | * truncate dma_addr_t to u32. | |
2652 | */ | |
2653 | addr = (u32) sg_dma_address(sg); | |
2654 | sg_len = sg_dma_len(sg); | |
2655 | ||
2656 | while (sg_len) { | |
2657 | offset = addr & 0xffff; | |
2658 | len = sg_len; | |
2659 | if ((offset + sg_len) > 0x10000) | |
2660 | len = 0x10000 - offset; | |
2661 | ||
2662 | blen = len & 0xffff; | |
f60d7011 | 2663 | prd[pi].addr = cpu_to_le32(addr); |
f47451c4 TH |
2664 | if (blen == 0) { |
2665 | /* Some PATA chipsets like the CS5530 can't | |
2666 | cope with 0x0000 meaning 64K as the spec | |
2667 | says */ | |
f60d7011 | 2668 | prd[pi].flags_len = cpu_to_le32(0x8000); |
f47451c4 | 2669 | blen = 0x8000; |
f60d7011 | 2670 | prd[++pi].addr = cpu_to_le32(addr + 0x8000); |
f47451c4 | 2671 | } |
f60d7011 | 2672 | prd[pi].flags_len = cpu_to_le32(blen); |
f47451c4 TH |
2673 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len); |
2674 | ||
2675 | pi++; | |
2676 | sg_len -= len; | |
2677 | addr += len; | |
2678 | } | |
2679 | } | |
2680 | ||
f60d7011 | 2681 | prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); |
f47451c4 TH |
2682 | } |
2683 | ||
2684 | /** | |
2685 | * ata_bmdma_qc_prep - Prepare taskfile for submission | |
2686 | * @qc: Metadata associated with taskfile to be prepared | |
2687 | * | |
2688 | * Prepare ATA taskfile for submission. | |
2689 | * | |
2690 | * LOCKING: | |
2691 | * spin_lock_irqsave(host lock) | |
2692 | */ | |
2693 | void ata_bmdma_qc_prep(struct ata_queued_cmd *qc) | |
2694 | { | |
2695 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
2696 | return; | |
2697 | ||
2698 | ata_bmdma_fill_sg(qc); | |
2699 | } | |
2700 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_prep); | |
2701 | ||
2702 | /** | |
2703 | * ata_bmdma_dumb_qc_prep - Prepare taskfile for submission | |
2704 | * @qc: Metadata associated with taskfile to be prepared | |
2705 | * | |
2706 | * Prepare ATA taskfile for submission. | |
2707 | * | |
2708 | * LOCKING: | |
2709 | * spin_lock_irqsave(host lock) | |
2710 | */ | |
2711 | void ata_bmdma_dumb_qc_prep(struct ata_queued_cmd *qc) | |
2712 | { | |
2713 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
2714 | return; | |
2715 | ||
2716 | ata_bmdma_fill_sg_dumb(qc); | |
2717 | } | |
2718 | EXPORT_SYMBOL_GPL(ata_bmdma_dumb_qc_prep); | |
2719 | ||
360ff783 TH |
2720 | /** |
2721 | * ata_bmdma_qc_issue - issue taskfile to a BMDMA controller | |
2722 | * @qc: command to issue to device | |
2723 | * | |
2724 | * This function issues a PIO, NODATA or DMA command to a | |
2725 | * SFF/BMDMA controller. PIO and NODATA are handled by | |
2726 | * ata_sff_qc_issue(). | |
2727 | * | |
2728 | * LOCKING: | |
2729 | * spin_lock_irqsave(host lock) | |
2730 | * | |
2731 | * RETURNS: | |
2732 | * Zero on success, AC_ERR_* mask on failure | |
2733 | */ | |
2734 | unsigned int ata_bmdma_qc_issue(struct ata_queued_cmd *qc) | |
2735 | { | |
2736 | struct ata_port *ap = qc->ap; | |
2737 | ||
360ff783 TH |
2738 | /* defer PIO handling to sff_qc_issue */ |
2739 | if (!ata_is_dma(qc->tf.protocol)) | |
2740 | return ata_sff_qc_issue(qc); | |
2741 | ||
2742 | /* select the device */ | |
2743 | ata_dev_select(ap, qc->dev->devno, 1, 0); | |
2744 | ||
2745 | /* start the command */ | |
2746 | switch (qc->tf.protocol) { | |
2747 | case ATA_PROT_DMA: | |
2748 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); | |
2749 | ||
2750 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ | |
2751 | ap->ops->bmdma_setup(qc); /* set up bmdma */ | |
2752 | ap->ops->bmdma_start(qc); /* initiate bmdma */ | |
2753 | ap->hsm_task_state = HSM_ST_LAST; | |
2754 | break; | |
2755 | ||
2756 | case ATAPI_PROT_DMA: | |
2757 | WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING); | |
2758 | ||
2759 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ | |
2760 | ap->ops->bmdma_setup(qc); /* set up bmdma */ | |
2761 | ap->hsm_task_state = HSM_ST_FIRST; | |
2762 | ||
2763 | /* send cdb by polling if no cdb interrupt */ | |
2764 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
2765 | ata_sff_queue_pio_task(ap, 0); | |
2766 | break; | |
2767 | ||
2768 | default: | |
2769 | WARN_ON(1); | |
2770 | return AC_ERR_SYSTEM; | |
2771 | } | |
2772 | ||
2773 | return 0; | |
2774 | } | |
2775 | EXPORT_SYMBOL_GPL(ata_bmdma_qc_issue); | |
2776 | ||
c3b28894 TH |
2777 | /** |
2778 | * ata_bmdma_port_intr - Handle BMDMA port interrupt | |
2779 | * @ap: Port on which interrupt arrived (possibly...) | |
2780 | * @qc: Taskfile currently active in engine | |
2781 | * | |
2782 | * Handle port interrupt for given queued command. | |
2783 | * | |
2784 | * LOCKING: | |
2785 | * spin_lock_irqsave(host lock) | |
2786 | * | |
2787 | * RETURNS: | |
2788 | * One if interrupt was handled, zero if not (shared irq). | |
2789 | */ | |
2790 | unsigned int ata_bmdma_port_intr(struct ata_port *ap, struct ata_queued_cmd *qc) | |
2791 | { | |
2792 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
2793 | u8 host_stat = 0; | |
2794 | bool bmdma_stopped = false; | |
2795 | unsigned int handled; | |
2796 | ||
2797 | if (ap->hsm_task_state == HSM_ST_LAST && ata_is_dma(qc->tf.protocol)) { | |
2798 | /* check status of DMA engine */ | |
2799 | host_stat = ap->ops->bmdma_status(ap); | |
2800 | VPRINTK("ata%u: host_stat 0x%X\n", ap->print_id, host_stat); | |
2801 | ||
2802 | /* if it's not our irq... */ | |
2803 | if (!(host_stat & ATA_DMA_INTR)) | |
2804 | return ata_sff_idle_irq(ap); | |
2805 | ||
2806 | /* before we do anything else, clear DMA-Start bit */ | |
2807 | ap->ops->bmdma_stop(qc); | |
2808 | bmdma_stopped = true; | |
2809 | ||
2810 | if (unlikely(host_stat & ATA_DMA_ERR)) { | |
2811 | /* error when transfering data to/from memory */ | |
2812 | qc->err_mask |= AC_ERR_HOST_BUS; | |
2813 | ap->hsm_task_state = HSM_ST_ERR; | |
2814 | } | |
2815 | } | |
2816 | ||
2817 | handled = __ata_sff_port_intr(ap, qc, bmdma_stopped); | |
2818 | ||
2819 | if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) | |
2820 | ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat); | |
2821 | ||
2822 | return handled; | |
2823 | } | |
2824 | EXPORT_SYMBOL_GPL(ata_bmdma_port_intr); | |
2825 | ||
2826 | /** | |
2827 | * ata_bmdma_interrupt - Default BMDMA ATA host interrupt handler | |
2828 | * @irq: irq line (unused) | |
2829 | * @dev_instance: pointer to our ata_host information structure | |
2830 | * | |
2831 | * Default interrupt handler for PCI IDE devices. Calls | |
2832 | * ata_bmdma_port_intr() for each port that is not disabled. | |
2833 | * | |
2834 | * LOCKING: | |
2835 | * Obtains host lock during operation. | |
2836 | * | |
2837 | * RETURNS: | |
2838 | * IRQ_NONE or IRQ_HANDLED. | |
2839 | */ | |
2840 | irqreturn_t ata_bmdma_interrupt(int irq, void *dev_instance) | |
2841 | { | |
2842 | return __ata_sff_interrupt(irq, dev_instance, ata_bmdma_port_intr); | |
2843 | } | |
2844 | EXPORT_SYMBOL_GPL(ata_bmdma_interrupt); | |
2845 | ||
fe06e5f9 TH |
2846 | /** |
2847 | * ata_bmdma_error_handler - Stock error handler for BMDMA controller | |
2848 | * @ap: port to handle error for | |
2849 | * | |
2850 | * Stock error handler for BMDMA controller. It can handle both | |
2851 | * PATA and SATA controllers. Most BMDMA controllers should be | |
2852 | * able to use this EH as-is or with some added handling before | |
2853 | * and after. | |
2854 | * | |
2855 | * LOCKING: | |
2856 | * Kernel thread context (may sleep) | |
2857 | */ | |
2858 | void ata_bmdma_error_handler(struct ata_port *ap) | |
2859 | { | |
2860 | struct ata_queued_cmd *qc; | |
2861 | unsigned long flags; | |
2862 | bool thaw = false; | |
2863 | ||
2864 | qc = __ata_qc_from_tag(ap, ap->link.active_tag); | |
2865 | if (qc && !(qc->flags & ATA_QCFLAG_FAILED)) | |
2866 | qc = NULL; | |
2867 | ||
2868 | /* reset PIO HSM and stop DMA engine */ | |
2869 | spin_lock_irqsave(ap->lock, flags); | |
2870 | ||
2871 | if (qc && ata_is_dma(qc->tf.protocol)) { | |
2872 | u8 host_stat; | |
2873 | ||
2874 | host_stat = ap->ops->bmdma_status(ap); | |
2875 | ||
2876 | /* BMDMA controllers indicate host bus error by | |
2877 | * setting DMA_ERR bit and timing out. As it wasn't | |
2878 | * really a timeout event, adjust error mask and | |
2879 | * cancel frozen state. | |
2880 | */ | |
2881 | if (qc->err_mask == AC_ERR_TIMEOUT && (host_stat & ATA_DMA_ERR)) { | |
2882 | qc->err_mask = AC_ERR_HOST_BUS; | |
2883 | thaw = true; | |
2884 | } | |
2885 | ||
2886 | ap->ops->bmdma_stop(qc); | |
2887 | ||
2888 | /* if we're gonna thaw, make sure IRQ is clear */ | |
2889 | if (thaw) { | |
2890 | ap->ops->sff_check_status(ap); | |
37f65b8b TH |
2891 | if (ap->ops->sff_irq_clear) |
2892 | ap->ops->sff_irq_clear(ap); | |
fe06e5f9 TH |
2893 | } |
2894 | } | |
2895 | ||
2896 | spin_unlock_irqrestore(ap->lock, flags); | |
2897 | ||
2898 | if (thaw) | |
2899 | ata_eh_thaw_port(ap); | |
2900 | ||
2901 | ata_sff_error_handler(ap); | |
2902 | } | |
2903 | EXPORT_SYMBOL_GPL(ata_bmdma_error_handler); | |
2904 | ||
2905 | /** | |
2906 | * ata_bmdma_post_internal_cmd - Stock post_internal_cmd for BMDMA | |
2907 | * @qc: internal command to clean up | |
2908 | * | |
2909 | * LOCKING: | |
2910 | * Kernel thread context (may sleep) | |
2911 | */ | |
2912 | void ata_bmdma_post_internal_cmd(struct ata_queued_cmd *qc) | |
2913 | { | |
2914 | struct ata_port *ap = qc->ap; | |
2915 | unsigned long flags; | |
2916 | ||
2917 | if (ata_is_dma(qc->tf.protocol)) { | |
2918 | spin_lock_irqsave(ap->lock, flags); | |
2919 | ap->ops->bmdma_stop(qc); | |
2920 | spin_unlock_irqrestore(ap->lock, flags); | |
2921 | } | |
2922 | } | |
2923 | EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd); | |
2924 | ||
37f65b8b TH |
2925 | /** |
2926 | * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt. | |
2927 | * @ap: Port associated with this ATA transaction. | |
2928 | * | |
2929 | * Clear interrupt and error flags in DMA status register. | |
2930 | * | |
2931 | * May be used as the irq_clear() entry in ata_port_operations. | |
2932 | * | |
2933 | * LOCKING: | |
2934 | * spin_lock_irqsave(host lock) | |
2935 | */ | |
2936 | void ata_bmdma_irq_clear(struct ata_port *ap) | |
2937 | { | |
2938 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
2939 | ||
2940 | if (!mmio) | |
2941 | return; | |
2942 | ||
2943 | iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS); | |
2944 | } | |
2945 | EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear); | |
2946 | ||
9f2f7210 TH |
2947 | /** |
2948 | * ata_bmdma_setup - Set up PCI IDE BMDMA transaction | |
2949 | * @qc: Info associated with this ATA transaction. | |
2950 | * | |
2951 | * LOCKING: | |
2952 | * spin_lock_irqsave(host lock) | |
2953 | */ | |
2954 | void ata_bmdma_setup(struct ata_queued_cmd *qc) | |
2955 | { | |
2956 | struct ata_port *ap = qc->ap; | |
2957 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
2958 | u8 dmactl; | |
2959 | ||
2960 | /* load PRD table addr. */ | |
2961 | mb(); /* make sure PRD table writes are visible to controller */ | |
f60d7011 | 2962 | iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS); |
9f2f7210 TH |
2963 | |
2964 | /* specify data direction, triple-check start bit is clear */ | |
2965 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2966 | dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); | |
2967 | if (!rw) | |
2968 | dmactl |= ATA_DMA_WR; | |
2969 | iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2970 | ||
2971 | /* issue r/w command */ | |
2972 | ap->ops->sff_exec_command(ap, &qc->tf); | |
2973 | } | |
2974 | EXPORT_SYMBOL_GPL(ata_bmdma_setup); | |
2975 | ||
2976 | /** | |
2977 | * ata_bmdma_start - Start a PCI IDE BMDMA transaction | |
2978 | * @qc: Info associated with this ATA transaction. | |
2979 | * | |
2980 | * LOCKING: | |
2981 | * spin_lock_irqsave(host lock) | |
2982 | */ | |
2983 | void ata_bmdma_start(struct ata_queued_cmd *qc) | |
2984 | { | |
2985 | struct ata_port *ap = qc->ap; | |
2986 | u8 dmactl; | |
2987 | ||
2988 | /* start host DMA transaction */ | |
2989 | dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2990 | iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD); | |
2991 | ||
2992 | /* Strictly, one may wish to issue an ioread8() here, to | |
2993 | * flush the mmio write. However, control also passes | |
2994 | * to the hardware at this point, and it will interrupt | |
2995 | * us when we are to resume control. So, in effect, | |
2996 | * we don't care when the mmio write flushes. | |
2997 | * Further, a read of the DMA status register _immediately_ | |
2998 | * following the write may not be what certain flaky hardware | |
2999 | * is expected, so I think it is best to not add a readb() | |
3000 | * without first all the MMIO ATA cards/mobos. | |
3001 | * Or maybe I'm just being paranoid. | |
3002 | * | |
3003 | * FIXME: The posting of this write means I/O starts are | |
3004 | * unneccessarily delayed for MMIO | |
3005 | */ | |
3006 | } | |
3007 | EXPORT_SYMBOL_GPL(ata_bmdma_start); | |
3008 | ||
3009 | /** | |
3010 | * ata_bmdma_stop - Stop PCI IDE BMDMA transfer | |
3011 | * @qc: Command we are ending DMA for | |
3012 | * | |
3013 | * Clears the ATA_DMA_START flag in the dma control register | |
3014 | * | |
3015 | * May be used as the bmdma_stop() entry in ata_port_operations. | |
3016 | * | |
3017 | * LOCKING: | |
3018 | * spin_lock_irqsave(host lock) | |
3019 | */ | |
3020 | void ata_bmdma_stop(struct ata_queued_cmd *qc) | |
3021 | { | |
3022 | struct ata_port *ap = qc->ap; | |
3023 | void __iomem *mmio = ap->ioaddr.bmdma_addr; | |
3024 | ||
3025 | /* clear start/stop bit */ | |
3026 | iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START, | |
3027 | mmio + ATA_DMA_CMD); | |
3028 | ||
3029 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
3030 | ata_sff_dma_pause(ap); | |
3031 | } | |
3032 | EXPORT_SYMBOL_GPL(ata_bmdma_stop); | |
3033 | ||
3034 | /** | |
3035 | * ata_bmdma_status - Read PCI IDE BMDMA status | |
3036 | * @ap: Port associated with this ATA transaction. | |
3037 | * | |
3038 | * Read and return BMDMA status register. | |
3039 | * | |
3040 | * May be used as the bmdma_status() entry in ata_port_operations. | |
3041 | * | |
3042 | * LOCKING: | |
3043 | * spin_lock_irqsave(host lock) | |
3044 | */ | |
3045 | u8 ata_bmdma_status(struct ata_port *ap) | |
3046 | { | |
3047 | return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS); | |
3048 | } | |
3049 | EXPORT_SYMBOL_GPL(ata_bmdma_status); | |
3050 | ||
c7087652 TH |
3051 | |
3052 | /** | |
3053 | * ata_bmdma_port_start - Set port up for bmdma. | |
3054 | * @ap: Port to initialize | |
3055 | * | |
3056 | * Called just after data structures for each port are | |
3057 | * initialized. Allocates space for PRD table. | |
3058 | * | |
3059 | * May be used as the port_start() entry in ata_port_operations. | |
3060 | * | |
3061 | * LOCKING: | |
3062 | * Inherited from caller. | |
3063 | */ | |
3064 | int ata_bmdma_port_start(struct ata_port *ap) | |
3065 | { | |
3066 | if (ap->mwdma_mask || ap->udma_mask) { | |
f60d7011 TH |
3067 | ap->bmdma_prd = |
3068 | dmam_alloc_coherent(ap->host->dev, ATA_PRD_TBL_SZ, | |
3069 | &ap->bmdma_prd_dma, GFP_KERNEL); | |
3070 | if (!ap->bmdma_prd) | |
c7087652 TH |
3071 | return -ENOMEM; |
3072 | } | |
3073 | ||
3074 | return 0; | |
3075 | } | |
3076 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start); | |
3077 | ||
3078 | /** | |
3079 | * ata_bmdma_port_start32 - Set port up for dma. | |
3080 | * @ap: Port to initialize | |
3081 | * | |
3082 | * Called just after data structures for each port are | |
3083 | * initialized. Enables 32bit PIO and allocates space for PRD | |
3084 | * table. | |
3085 | * | |
3086 | * May be used as the port_start() entry in ata_port_operations for | |
3087 | * devices that are capable of 32bit PIO. | |
3088 | * | |
3089 | * LOCKING: | |
3090 | * Inherited from caller. | |
3091 | */ | |
3092 | int ata_bmdma_port_start32(struct ata_port *ap) | |
3093 | { | |
3094 | ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE; | |
3095 | return ata_bmdma_port_start(ap); | |
3096 | } | |
3097 | EXPORT_SYMBOL_GPL(ata_bmdma_port_start32); | |
3098 | ||
9f2f7210 TH |
3099 | #ifdef CONFIG_PCI |
3100 | ||
3101 | /** | |
3102 | * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex | |
3103 | * @pdev: PCI device | |
3104 | * | |
3105 | * Some PCI ATA devices report simplex mode but in fact can be told to | |
3106 | * enter non simplex mode. This implements the necessary logic to | |
3107 | * perform the task on such devices. Calling it on other devices will | |
3108 | * have -undefined- behaviour. | |
3109 | */ | |
3110 | int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev) | |
3111 | { | |
3112 | unsigned long bmdma = pci_resource_start(pdev, 4); | |
3113 | u8 simplex; | |
3114 | ||
3115 | if (bmdma == 0) | |
3116 | return -ENOENT; | |
3117 | ||
3118 | simplex = inb(bmdma + 0x02); | |
3119 | outb(simplex & 0x60, bmdma + 0x02); | |
3120 | simplex = inb(bmdma + 0x02); | |
3121 | if (simplex & 0x80) | |
3122 | return -EOPNOTSUPP; | |
3123 | return 0; | |
3124 | } | |
3125 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex); | |
3126 | ||
c7087652 TH |
3127 | static void ata_bmdma_nodma(struct ata_host *host, const char *reason) |
3128 | { | |
3129 | int i; | |
3130 | ||
3131 | dev_printk(KERN_ERR, host->dev, "BMDMA: %s, falling back to PIO\n", | |
3132 | reason); | |
3133 | ||
3134 | for (i = 0; i < 2; i++) { | |
3135 | host->ports[i]->mwdma_mask = 0; | |
3136 | host->ports[i]->udma_mask = 0; | |
3137 | } | |
3138 | } | |
3139 | ||
9f2f7210 TH |
3140 | /** |
3141 | * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host | |
3142 | * @host: target ATA host | |
3143 | * | |
3144 | * Acquire PCI BMDMA resources and initialize @host accordingly. | |
3145 | * | |
3146 | * LOCKING: | |
3147 | * Inherited from calling layer (may sleep). | |
9f2f7210 | 3148 | */ |
c7087652 | 3149 | void ata_pci_bmdma_init(struct ata_host *host) |
9f2f7210 TH |
3150 | { |
3151 | struct device *gdev = host->dev; | |
3152 | struct pci_dev *pdev = to_pci_dev(gdev); | |
3153 | int i, rc; | |
3154 | ||
3155 | /* No BAR4 allocation: No DMA */ | |
c7087652 TH |
3156 | if (pci_resource_start(pdev, 4) == 0) { |
3157 | ata_bmdma_nodma(host, "BAR4 is zero"); | |
3158 | return; | |
3159 | } | |
9f2f7210 | 3160 | |
c7087652 TH |
3161 | /* |
3162 | * Some controllers require BMDMA region to be initialized | |
3163 | * even if DMA is not in use to clear IRQ status via | |
3164 | * ->sff_irq_clear method. Try to initialize bmdma_addr | |
3165 | * regardless of dma masks. | |
3166 | */ | |
9f2f7210 TH |
3167 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
3168 | if (rc) | |
c7087652 TH |
3169 | ata_bmdma_nodma(host, "failed to set dma mask"); |
3170 | if (!rc) { | |
3171 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
3172 | if (rc) | |
3173 | ata_bmdma_nodma(host, | |
3174 | "failed to set consistent dma mask"); | |
3175 | } | |
9f2f7210 TH |
3176 | |
3177 | /* request and iomap DMA region */ | |
3178 | rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev)); | |
3179 | if (rc) { | |
c7087652 TH |
3180 | ata_bmdma_nodma(host, "failed to request/iomap BAR4"); |
3181 | return; | |
9f2f7210 TH |
3182 | } |
3183 | host->iomap = pcim_iomap_table(pdev); | |
3184 | ||
3185 | for (i = 0; i < 2; i++) { | |
3186 | struct ata_port *ap = host->ports[i]; | |
3187 | void __iomem *bmdma = host->iomap[4] + 8 * i; | |
3188 | ||
3189 | if (ata_port_is_dummy(ap)) | |
3190 | continue; | |
3191 | ||
3192 | ap->ioaddr.bmdma_addr = bmdma; | |
3193 | if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) && | |
3194 | (ioread8(bmdma + 2) & 0x80)) | |
3195 | host->flags |= ATA_HOST_SIMPLEX; | |
3196 | ||
3197 | ata_port_desc(ap, "bmdma 0x%llx", | |
3198 | (unsigned long long)pci_resource_start(pdev, 4) + 8 * i); | |
3199 | } | |
9f2f7210 TH |
3200 | } |
3201 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init); | |
3202 | ||
1c5afdf7 TH |
3203 | /** |
3204 | * ata_pci_bmdma_prepare_host - helper to prepare PCI BMDMA ATA host | |
3205 | * @pdev: target PCI device | |
3206 | * @ppi: array of port_info, must be enough for two ports | |
3207 | * @r_host: out argument for the initialized ATA host | |
3208 | * | |
3209 | * Helper to allocate BMDMA ATA host for @pdev, acquire all PCI | |
3210 | * resources and initialize it accordingly in one go. | |
3211 | * | |
3212 | * LOCKING: | |
3213 | * Inherited from calling layer (may sleep). | |
3214 | * | |
3215 | * RETURNS: | |
3216 | * 0 on success, -errno otherwise. | |
3217 | */ | |
3218 | int ata_pci_bmdma_prepare_host(struct pci_dev *pdev, | |
3219 | const struct ata_port_info * const * ppi, | |
3220 | struct ata_host **r_host) | |
3221 | { | |
3222 | int rc; | |
3223 | ||
3224 | rc = ata_pci_sff_prepare_host(pdev, ppi, r_host); | |
3225 | if (rc) | |
3226 | return rc; | |
3227 | ||
3228 | ata_pci_bmdma_init(*r_host); | |
3229 | return 0; | |
3230 | } | |
3231 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_prepare_host); | |
3232 | ||
3233 | /** | |
3234 | * ata_pci_bmdma_init_one - Initialize/register BMDMA PCI IDE controller | |
3235 | * @pdev: Controller to be initialized | |
3236 | * @ppi: array of port_info, must be enough for two ports | |
3237 | * @sht: scsi_host_template to use when registering the host | |
3238 | * @host_priv: host private_data | |
3239 | * @hflags: host flags | |
3240 | * | |
3241 | * This function is similar to ata_pci_sff_init_one() but also | |
3242 | * takes care of BMDMA initialization. | |
3243 | * | |
3244 | * LOCKING: | |
3245 | * Inherited from PCI layer (may sleep). | |
3246 | * | |
3247 | * RETURNS: | |
3248 | * Zero on success, negative on errno-based value on error. | |
3249 | */ | |
3250 | int ata_pci_bmdma_init_one(struct pci_dev *pdev, | |
3251 | const struct ata_port_info * const * ppi, | |
3252 | struct scsi_host_template *sht, void *host_priv, | |
3253 | int hflags) | |
3254 | { | |
3255 | struct device *dev = &pdev->dev; | |
3256 | const struct ata_port_info *pi; | |
3257 | struct ata_host *host = NULL; | |
3258 | int rc; | |
3259 | ||
3260 | DPRINTK("ENTER\n"); | |
3261 | ||
3262 | pi = ata_sff_find_valid_pi(ppi); | |
3263 | if (!pi) { | |
3264 | dev_printk(KERN_ERR, &pdev->dev, | |
3265 | "no valid port_info specified\n"); | |
3266 | return -EINVAL; | |
3267 | } | |
3268 | ||
3269 | if (!devres_open_group(dev, NULL, GFP_KERNEL)) | |
3270 | return -ENOMEM; | |
3271 | ||
3272 | rc = pcim_enable_device(pdev); | |
3273 | if (rc) | |
3274 | goto out; | |
3275 | ||
3276 | /* prepare and activate BMDMA host */ | |
3277 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); | |
3278 | if (rc) | |
3279 | goto out; | |
3280 | host->private_data = host_priv; | |
3281 | host->flags |= hflags; | |
3282 | ||
3283 | pci_set_master(pdev); | |
3284 | rc = ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); | |
3285 | out: | |
3286 | if (rc == 0) | |
3287 | devres_remove_group(&pdev->dev, NULL); | |
3288 | else | |
3289 | devres_release_group(&pdev->dev, NULL); | |
3290 | ||
3291 | return rc; | |
3292 | } | |
3293 | EXPORT_SYMBOL_GPL(ata_pci_bmdma_init_one); | |
3294 | ||
9f2f7210 | 3295 | #endif /* CONFIG_PCI */ |
9a7780c9 | 3296 | #endif /* CONFIG_ATA_BMDMA */ |
270390e1 TH |
3297 | |
3298 | /** | |
3299 | * ata_sff_port_init - Initialize SFF/BMDMA ATA port | |
3300 | * @ap: Port to initialize | |
3301 | * | |
3302 | * Called on port allocation to initialize SFF/BMDMA specific | |
3303 | * fields. | |
3304 | * | |
3305 | * LOCKING: | |
3306 | * None. | |
3307 | */ | |
3308 | void ata_sff_port_init(struct ata_port *ap) | |
3309 | { | |
c429137a | 3310 | INIT_DELAYED_WORK(&ap->sff_pio_task, ata_sff_pio_task); |
5fe7454a TH |
3311 | ap->ctl = ATA_DEVCTL_OBS; |
3312 | ap->last_ctl = 0xFF; | |
270390e1 TH |
3313 | } |
3314 | ||
3315 | int __init ata_sff_init(void) | |
3316 | { | |
ad72cf98 | 3317 | ata_sff_wq = alloc_workqueue("ata_sff", WQ_RESCUER, WQ_MAX_ACTIVE); |
c429137a TH |
3318 | if (!ata_sff_wq) |
3319 | return -ENOMEM; | |
3320 | ||
270390e1 TH |
3321 | return 0; |
3322 | } | |
3323 | ||
3324 | void __exit ata_sff_exit(void) | |
3325 | { | |
c429137a | 3326 | destroy_workqueue(ata_sff_wq); |
270390e1 | 3327 | } |