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918d7b7c SM |
1 | /* |
2 | * PATA driver for AT91SAM9260 Static Memory Controller | |
3 | * with CompactFlash interface in True IDE mode | |
4 | * | |
5 | * Copyright (C) 2009 Matyukevich Sergey | |
6 | * | |
7 | * Based on: | |
8 | * * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c | |
9 | * * pata_at32 driver by Kristoffer Nyborg Gregertsen | |
10 | * * at91_ide driver by Stanislaw Gruszka | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License version 2 | |
14 | * as published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/blkdev.h> | |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
918d7b7c SM |
23 | #include <scsi/scsi_host.h> |
24 | #include <linux/ata.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/libata.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/ata_platform.h> | |
29 | ||
918d7b7c | 30 | #include <mach/at91sam9_smc.h> |
918d7b7c SM |
31 | #include <mach/board.h> |
32 | #include <mach/gpio.h> | |
33 | ||
34 | ||
35 | #define DRV_NAME "pata_at91" | |
36 | #define DRV_VERSION "0.1" | |
37 | ||
38 | #define CF_IDE_OFFSET 0x00c00000 | |
39 | #define CF_ALT_IDE_OFFSET 0x00e00000 | |
40 | #define CF_IDE_RES_SIZE 0x08 | |
41 | ||
42 | struct at91_ide_info { | |
43 | unsigned long mode; | |
44 | unsigned int cs; | |
45 | ||
7d084d96 SM |
46 | struct clk *mck; |
47 | ||
918d7b7c SM |
48 | void __iomem *ide_addr; |
49 | void __iomem *alt_addr; | |
50 | }; | |
51 | ||
7d084d96 | 52 | static const struct ata_timing initial_timing = |
918d7b7c SM |
53 | {XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0}; |
54 | ||
7d084d96 | 55 | static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz) |
918d7b7c SM |
56 | { |
57 | unsigned long mul; | |
58 | ||
7d084d96 SM |
59 | /* |
60 | * cycles = x [nsec] * f [Hz] / 10^9 [ns in sec] = | |
61 | * x * (f / 1_000_000_000) = | |
62 | * x * ((f * 65536) / 1_000_000_000) / 65536 = | |
63 | * x * (((f / 10_000) * 65536) / 100_000) / 65536 = | |
64 | */ | |
918d7b7c | 65 | |
7d084d96 SM |
66 | mul = (mck_hz / 10000) << 16; |
67 | mul /= 100000; | |
918d7b7c | 68 | |
7d084d96 | 69 | return (ns * mul + 65536) >> 16; /* rounding */ |
918d7b7c SM |
70 | } |
71 | ||
72 | static void set_smc_mode(struct at91_ide_info *info) | |
73 | { | |
7d084d96 SM |
74 | at91_sys_write(AT91_SMC_MODE(info->cs), info->mode); |
75 | return; | |
918d7b7c SM |
76 | } |
77 | ||
78 | static void set_smc_timing(struct device *dev, | |
79 | struct at91_ide_info *info, const struct ata_timing *ata) | |
80 | { | |
7d084d96 SM |
81 | unsigned long read_cycle, write_cycle, active, recover; |
82 | unsigned long nrd_setup, nrd_pulse, nrd_recover; | |
83 | unsigned long nwe_setup, nwe_pulse; | |
918d7b7c | 84 | |
7d084d96 SM |
85 | unsigned long ncs_write_setup, ncs_write_pulse; |
86 | unsigned long ncs_read_setup, ncs_read_pulse; | |
918d7b7c | 87 | |
7d084d96 | 88 | unsigned long mck_hz; |
918d7b7c SM |
89 | |
90 | read_cycle = ata->cyc8b; | |
91 | nrd_setup = ata->setup; | |
92 | nrd_pulse = ata->act8b; | |
93 | nrd_recover = ata->rec8b; | |
94 | ||
7d084d96 | 95 | mck_hz = clk_get_rate(info->mck); |
918d7b7c SM |
96 | |
97 | read_cycle = calc_mck_cycles(read_cycle, mck_hz); | |
98 | nrd_setup = calc_mck_cycles(nrd_setup, mck_hz); | |
99 | nrd_pulse = calc_mck_cycles(nrd_pulse, mck_hz); | |
100 | nrd_recover = calc_mck_cycles(nrd_recover, mck_hz); | |
101 | ||
918d7b7c SM |
102 | active = nrd_setup + nrd_pulse; |
103 | recover = read_cycle - active; | |
104 | ||
105 | /* Need at least two cycles recovery */ | |
106 | if (recover < 2) | |
107 | read_cycle = active + 2; | |
108 | ||
109 | /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */ | |
110 | ncs_read_setup = 1; | |
111 | ncs_read_pulse = read_cycle - 2; | |
112 | ||
113 | /* Write timings same as read timings */ | |
114 | write_cycle = read_cycle; | |
115 | nwe_setup = nrd_setup; | |
116 | nwe_pulse = nrd_pulse; | |
117 | ncs_write_setup = ncs_read_setup; | |
118 | ncs_write_pulse = ncs_read_pulse; | |
119 | ||
7d084d96 | 120 | dev_dbg(dev, "ATA timings: nrd_setup = %lu nrd_pulse = %lu nrd_cycle = %lu\n", |
918d7b7c | 121 | nrd_setup, nrd_pulse, read_cycle); |
7d084d96 | 122 | dev_dbg(dev, "ATA timings: nwe_setup = %lu nwe_pulse = %lu nwe_cycle = %lu\n", |
918d7b7c | 123 | nwe_setup, nwe_pulse, write_cycle); |
7d084d96 | 124 | dev_dbg(dev, "ATA timings: ncs_read_setup = %lu ncs_read_pulse = %lu\n", |
918d7b7c | 125 | ncs_read_setup, ncs_read_pulse); |
7d084d96 | 126 | dev_dbg(dev, "ATA timings: ncs_write_setup = %lu ncs_write_pulse = %lu\n", |
918d7b7c SM |
127 | ncs_write_setup, ncs_write_pulse); |
128 | ||
129 | at91_sys_write(AT91_SMC_SETUP(info->cs), | |
130 | AT91_SMC_NWESETUP_(nwe_setup) | | |
131 | AT91_SMC_NRDSETUP_(nrd_setup) | | |
132 | AT91_SMC_NCS_WRSETUP_(ncs_write_setup) | | |
133 | AT91_SMC_NCS_RDSETUP_(ncs_read_setup)); | |
134 | ||
135 | at91_sys_write(AT91_SMC_PULSE(info->cs), | |
136 | AT91_SMC_NWEPULSE_(nwe_pulse) | | |
137 | AT91_SMC_NRDPULSE_(nrd_pulse) | | |
138 | AT91_SMC_NCS_WRPULSE_(ncs_write_pulse) | | |
139 | AT91_SMC_NCS_RDPULSE_(ncs_read_pulse)); | |
140 | ||
141 | at91_sys_write(AT91_SMC_CYCLE(info->cs), | |
142 | AT91_SMC_NWECYCLE_(write_cycle) | | |
143 | AT91_SMC_NRDCYCLE_(read_cycle)); | |
144 | ||
145 | return; | |
146 | } | |
147 | ||
148 | static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
149 | { | |
150 | struct at91_ide_info *info = ap->host->private_data; | |
151 | struct ata_timing timing; | |
152 | int ret; | |
153 | ||
154 | /* Compute ATA timing and set it to SMC */ | |
155 | ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0); | |
156 | if (ret) { | |
429e3861 JG |
157 | dev_warn(ap->dev, "Failed to compute ATA timing %d, " |
158 | "set PIO_0 timing\n", ret); | |
918d7b7c SM |
159 | set_smc_timing(ap->dev, info, &initial_timing); |
160 | } else { | |
161 | set_smc_timing(ap->dev, info, &timing); | |
162 | } | |
163 | ||
164 | /* Setup SMC mode */ | |
165 | set_smc_mode(info); | |
166 | ||
167 | return; | |
168 | } | |
169 | ||
170 | static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev, | |
171 | unsigned char *buf, unsigned int buflen, int rw) | |
172 | { | |
173 | struct at91_ide_info *info = dev->link->ap->host->private_data; | |
174 | unsigned int consumed; | |
175 | unsigned long flags; | |
176 | unsigned int mode; | |
177 | ||
178 | local_irq_save(flags); | |
179 | mode = at91_sys_read(AT91_SMC_MODE(info->cs)); | |
180 | ||
181 | /* set 16bit mode before writing data */ | |
182 | at91_sys_write(AT91_SMC_MODE(info->cs), | |
183 | (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_16); | |
184 | ||
185 | consumed = ata_sff_data_xfer(dev, buf, buflen, rw); | |
186 | ||
187 | /* restore 8bit mode after data is written */ | |
188 | at91_sys_write(AT91_SMC_MODE(info->cs), | |
189 | (mode & ~AT91_SMC_DBW) | AT91_SMC_DBW_8); | |
190 | ||
191 | local_irq_restore(flags); | |
192 | return consumed; | |
193 | } | |
194 | ||
195 | static struct scsi_host_template pata_at91_sht = { | |
196 | ATA_PIO_SHT(DRV_NAME), | |
197 | }; | |
198 | ||
199 | static struct ata_port_operations pata_at91_port_ops = { | |
200 | .inherits = &ata_sff_port_ops, | |
201 | ||
202 | .sff_data_xfer = pata_at91_data_xfer_noirq, | |
203 | .set_piomode = pata_at91_set_piomode, | |
204 | .cable_detect = ata_cable_40wire, | |
205 | .port_start = ATA_OP_NULL, | |
206 | }; | |
207 | ||
208 | static int __devinit pata_at91_probe(struct platform_device *pdev) | |
209 | { | |
210 | struct at91_cf_data *board = pdev->dev.platform_data; | |
211 | struct device *dev = &pdev->dev; | |
212 | struct at91_ide_info *info; | |
213 | struct resource *mem_res; | |
214 | struct ata_host *host; | |
215 | struct ata_port *ap; | |
7d084d96 | 216 | |
918d7b7c SM |
217 | int irq_flags = 0; |
218 | int irq = 0; | |
219 | int ret; | |
220 | ||
221 | /* get platform resources: IO/CTL memories and irq/rst pins */ | |
222 | ||
223 | if (pdev->num_resources != 1) { | |
224 | dev_err(&pdev->dev, "invalid number of resources\n"); | |
225 | return -EINVAL; | |
226 | } | |
227 | ||
228 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
229 | ||
230 | if (!mem_res) { | |
231 | dev_err(dev, "failed to get mem resource\n"); | |
232 | return -EINVAL; | |
233 | } | |
234 | ||
235 | irq = board->irq_pin; | |
236 | ||
237 | /* init ata host */ | |
238 | ||
239 | host = ata_host_alloc(dev, 1); | |
240 | ||
241 | if (!host) | |
242 | return -ENOMEM; | |
243 | ||
244 | ap = host->ports[0]; | |
245 | ap->ops = &pata_at91_port_ops; | |
246 | ap->flags |= ATA_FLAG_SLAVE_POSS; | |
247 | ap->pio_mask = ATA_PIO4; | |
248 | ||
249 | if (!irq) { | |
250 | ap->flags |= ATA_FLAG_PIO_POLLING; | |
251 | ata_port_desc(ap, "no IRQ, using PIO polling"); | |
252 | } | |
253 | ||
df9eba8c | 254 | info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); |
918d7b7c SM |
255 | |
256 | if (!info) { | |
257 | dev_err(dev, "failed to allocate memory for private data\n"); | |
258 | return -ENOMEM; | |
259 | } | |
260 | ||
7d084d96 SM |
261 | info->mck = clk_get(NULL, "mck"); |
262 | ||
263 | if (IS_ERR(info->mck)) { | |
264 | dev_err(dev, "failed to get access to mck clock\n"); | |
265 | return -ENODEV; | |
266 | } | |
267 | ||
918d7b7c SM |
268 | info->cs = board->chipselect; |
269 | info->mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | | |
270 | AT91_SMC_EXNWMODE_READY | AT91_SMC_BAT_SELECT | | |
271 | AT91_SMC_DBW_8 | AT91_SMC_TDF_(0); | |
272 | ||
273 | info->ide_addr = devm_ioremap(dev, | |
274 | mem_res->start + CF_IDE_OFFSET, CF_IDE_RES_SIZE); | |
275 | ||
276 | if (!info->ide_addr) { | |
277 | dev_err(dev, "failed to map IO base\n"); | |
278 | ret = -ENOMEM; | |
df9eba8c | 279 | goto err_put; |
918d7b7c SM |
280 | } |
281 | ||
282 | info->alt_addr = devm_ioremap(dev, | |
283 | mem_res->start + CF_ALT_IDE_OFFSET, CF_IDE_RES_SIZE); | |
284 | ||
285 | if (!info->alt_addr) { | |
286 | dev_err(dev, "failed to map CTL base\n"); | |
287 | ret = -ENOMEM; | |
df9eba8c | 288 | goto err_put; |
918d7b7c SM |
289 | } |
290 | ||
291 | ap->ioaddr.cmd_addr = info->ide_addr; | |
292 | ap->ioaddr.ctl_addr = info->alt_addr + 0x06; | |
293 | ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr; | |
294 | ||
295 | ata_sff_std_ports(&ap->ioaddr); | |
296 | ||
297 | ata_port_desc(ap, "mmio cmd 0x%llx ctl 0x%llx", | |
298 | (unsigned long long)mem_res->start + CF_IDE_OFFSET, | |
299 | (unsigned long long)mem_res->start + CF_ALT_IDE_OFFSET); | |
300 | ||
301 | host->private_data = info; | |
302 | ||
303 | return ata_host_activate(host, irq ? gpio_to_irq(irq) : 0, | |
304 | irq ? ata_sff_interrupt : NULL, | |
305 | irq_flags, &pata_at91_sht); | |
306 | ||
df9eba8c | 307 | err_put: |
7d084d96 | 308 | clk_put(info->mck); |
918d7b7c SM |
309 | return ret; |
310 | } | |
311 | ||
312 | static int __devexit pata_at91_remove(struct platform_device *pdev) | |
313 | { | |
314 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
1e1f421a | 315 | struct at91_ide_info *info; |
918d7b7c SM |
316 | |
317 | if (!host) | |
318 | return 0; | |
1e1f421a | 319 | info = host->private_data; |
918d7b7c SM |
320 | |
321 | ata_host_detach(host); | |
322 | ||
323 | if (!info) | |
324 | return 0; | |
325 | ||
7d084d96 | 326 | clk_put(info->mck); |
918d7b7c | 327 | |
918d7b7c SM |
328 | return 0; |
329 | } | |
330 | ||
331 | static struct platform_driver pata_at91_driver = { | |
332 | .probe = pata_at91_probe, | |
333 | .remove = __devexit_p(pata_at91_remove), | |
334 | .driver = { | |
335 | .name = DRV_NAME, | |
336 | .owner = THIS_MODULE, | |
337 | }, | |
338 | }; | |
339 | ||
340 | static int __init pata_at91_init(void) | |
341 | { | |
342 | return platform_driver_register(&pata_at91_driver); | |
343 | } | |
344 | ||
345 | static void __exit pata_at91_exit(void) | |
346 | { | |
347 | platform_driver_unregister(&pata_at91_driver); | |
348 | } | |
349 | ||
350 | ||
351 | module_init(pata_at91_init); | |
352 | module_exit(pata_at91_exit); | |
353 | ||
354 | ||
355 | MODULE_LICENSE("GPL"); | |
356 | MODULE_DESCRIPTION("Driver for CF in True IDE mode on AT91SAM9260 SoC"); | |
357 | MODULE_AUTHOR("Matyukevich Sergey"); | |
358 | MODULE_VERSION(DRV_VERSION); | |
359 |