]>
Commit | Line | Data |
---|---|---|
669a5db4 JG |
1 | /* |
2 | * pata_atiixp.c - ATI PATA for new ATA layer | |
3 | * (C) 2005 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * Based on | |
7 | * | |
8 | * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004 | |
9 | * | |
10 | * Copyright (C) 2003 ATI Inc. <hyu@ati.com> | |
11 | * Copyright (C) 2004 Bartlomiej Zolnierkiewicz | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/blkdev.h> | |
20 | #include <linux/delay.h> | |
21 | #include <scsi/scsi_host.h> | |
22 | #include <linux/libata.h> | |
23 | ||
24 | #define DRV_NAME "pata_atiixp" | |
84708606 | 25 | #define DRV_VERSION "0.4.5" |
669a5db4 JG |
26 | |
27 | enum { | |
28 | ATIIXP_IDE_PIO_TIMING = 0x40, | |
29 | ATIIXP_IDE_MWDMA_TIMING = 0x44, | |
30 | ATIIXP_IDE_PIO_CONTROL = 0x48, | |
31 | ATIIXP_IDE_PIO_MODE = 0x4a, | |
32 | ATIIXP_IDE_UDMA_CONTROL = 0x54, | |
33 | ATIIXP_IDE_UDMA_MODE = 0x56 | |
34 | }; | |
35 | ||
d4b2bab4 | 36 | static int atiixp_pre_reset(struct ata_port *ap, unsigned long deadline) |
669a5db4 | 37 | { |
54494f3a | 38 | static const struct pci_bits atiixp_enable_bits[] = { |
669a5db4 JG |
39 | { 0x48, 1, 0x01, 0x00 }, |
40 | { 0x48, 1, 0x08, 0x00 } | |
41 | }; | |
84708606 | 42 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
669a5db4 | 43 | |
c961922b AC |
44 | if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no])) |
45 | return -ENOENT; | |
46 | ||
d4b2bab4 | 47 | return ata_std_prereset(ap, deadline); |
669a5db4 JG |
48 | } |
49 | ||
50 | static void atiixp_error_handler(struct ata_port *ap) | |
51 | { | |
52 | ata_bmdma_drive_eh(ap, atiixp_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
53 | } | |
54 | ||
84708606 AC |
55 | static int atiixp_cable_detect(struct ata_port *ap) |
56 | { | |
57 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
58 | u8 udma; | |
59 | ||
60 | /* Hack from drivers/ide/pci. Really we want to know how to do the | |
61 | raw detection not play follow the bios mode guess */ | |
62 | pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); | |
63 | if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40) | |
64 | return ATA_CBL_PATA80; | |
65 | return ATA_CBL_PATA40; | |
66 | } | |
67 | ||
669a5db4 JG |
68 | /** |
69 | * atiixp_set_pio_timing - set initial PIO mode data | |
70 | * @ap: ATA interface | |
71 | * @adev: ATA device | |
72 | * | |
73 | * Called by both the pio and dma setup functions to set the controller | |
74 | * timings for PIO transfers. We must load both the mode number and | |
75 | * timing values into the controller. | |
76 | */ | |
77 | ||
78 | static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio) | |
79 | { | |
80 | static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 }; | |
81 | ||
82 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
83 | int dn = 2 * ap->port_no + adev->devno; | |
84 | ||
85 | /* Check this is correct - the order is odd in both drivers */ | |
86 | int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1); | |
87 | u16 pio_mode_data, pio_timing_data; | |
88 | ||
89 | pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data); | |
90 | pio_mode_data &= ~(0x7 << (4 * dn)); | |
91 | pio_mode_data |= pio << (4 * dn); | |
92 | pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data); | |
93 | ||
94 | pci_read_config_word(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data); | |
95 | pio_mode_data &= ~(0xFF << timing_shift); | |
96 | pio_mode_data |= (pio_timings[pio] << timing_shift); | |
97 | pci_write_config_word(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data); | |
98 | } | |
99 | ||
100 | /** | |
101 | * atiixp_set_piomode - set initial PIO mode data | |
102 | * @ap: ATA interface | |
103 | * @adev: ATA device | |
104 | * | |
105 | * Called to do the PIO mode setup. We use a shared helper for this | |
106 | * as the DMA setup must also adjust the PIO timing information. | |
107 | */ | |
108 | ||
109 | static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
110 | { | |
111 | atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0); | |
112 | } | |
113 | ||
114 | /** | |
115 | * atiixp_set_dmamode - set initial DMA mode data | |
116 | * @ap: ATA interface | |
117 | * @adev: ATA device | |
118 | * | |
119 | * Called to do the DMA mode setup. We use timing tables for most | |
120 | * modes but must tune an appropriate PIO mode to match. | |
121 | */ | |
122 | ||
123 | static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
124 | { | |
125 | static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 }; | |
126 | ||
127 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
128 | int dma = adev->dma_mode; | |
129 | int dn = 2 * ap->port_no + adev->devno; | |
130 | int wanted_pio; | |
131 | ||
132 | if (adev->dma_mode >= XFER_UDMA_0) { | |
133 | u16 udma_mode_data; | |
134 | ||
135 | dma -= XFER_UDMA_0; | |
136 | ||
137 | pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data); | |
138 | udma_mode_data &= ~(0x7 << (4 * dn)); | |
139 | udma_mode_data |= dma << (4 * dn); | |
140 | pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data); | |
141 | } else { | |
142 | u16 mwdma_timing_data; | |
143 | /* Check this is correct - the order is odd in both drivers */ | |
144 | int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1); | |
145 | ||
146 | dma -= XFER_MW_DMA_0; | |
147 | ||
148 | pci_read_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, &mwdma_timing_data); | |
149 | mwdma_timing_data &= ~(0xFF << timing_shift); | |
150 | mwdma_timing_data |= (mwdma_timings[dma] << timing_shift); | |
151 | pci_write_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, mwdma_timing_data); | |
152 | } | |
153 | /* | |
154 | * We must now look at the PIO mode situation. We may need to | |
155 | * adjust the PIO mode to keep the timings acceptable | |
156 | */ | |
157 | if (adev->dma_mode >= XFER_MW_DMA_2) | |
158 | wanted_pio = 4; | |
159 | else if (adev->dma_mode == XFER_MW_DMA_1) | |
160 | wanted_pio = 3; | |
161 | else if (adev->dma_mode == XFER_MW_DMA_0) | |
162 | wanted_pio = 0; | |
163 | else BUG(); | |
164 | ||
165 | if (adev->pio_mode != wanted_pio) | |
166 | atiixp_set_pio_timing(ap, adev, wanted_pio); | |
167 | } | |
168 | ||
169 | /** | |
170 | * atiixp_bmdma_start - DMA start callback | |
171 | * @qc: Command in progress | |
172 | * | |
173 | * When DMA begins we need to ensure that the UDMA control | |
174 | * register for the channel is correctly set. | |
175 | */ | |
176 | ||
177 | static void atiixp_bmdma_start(struct ata_queued_cmd *qc) | |
178 | { | |
179 | struct ata_port *ap = qc->ap; | |
180 | struct ata_device *adev = qc->dev; | |
181 | ||
182 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
183 | int dn = (2 * ap->port_no) + adev->devno; | |
184 | u16 tmp16; | |
185 | ||
186 | pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); | |
187 | if (adev->dma_mode >= XFER_UDMA_0) | |
188 | tmp16 |= (1 << dn); | |
189 | else | |
190 | tmp16 &= ~(1 << dn); | |
191 | pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16); | |
192 | ata_bmdma_start(qc); | |
193 | } | |
194 | ||
195 | /** | |
196 | * atiixp_dma_stop - DMA stop callback | |
197 | * @qc: Command in progress | |
198 | * | |
199 | * DMA has completed. Clear the UDMA flag as the next operations will | |
200 | * be PIO ones not UDMA data transfer. | |
201 | */ | |
202 | ||
203 | static void atiixp_bmdma_stop(struct ata_queued_cmd *qc) | |
204 | { | |
205 | struct ata_port *ap = qc->ap; | |
206 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
207 | int dn = (2 * ap->port_no) + qc->dev->devno; | |
208 | u16 tmp16; | |
209 | ||
210 | pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); | |
211 | tmp16 &= ~(1 << dn); | |
212 | pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16); | |
213 | ata_bmdma_stop(qc); | |
214 | } | |
215 | ||
216 | static struct scsi_host_template atiixp_sht = { | |
217 | .module = THIS_MODULE, | |
218 | .name = DRV_NAME, | |
219 | .ioctl = ata_scsi_ioctl, | |
220 | .queuecommand = ata_scsi_queuecmd, | |
221 | .can_queue = ATA_DEF_QUEUE, | |
222 | .this_id = ATA_SHT_THIS_ID, | |
223 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
224 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
225 | .emulated = ATA_SHT_EMULATED, | |
226 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
227 | .proc_name = DRV_NAME, | |
228 | .dma_boundary = ATA_DMA_BOUNDARY, | |
229 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 230 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
231 | .bios_param = ata_std_bios_param, |
232 | }; | |
233 | ||
234 | static struct ata_port_operations atiixp_port_ops = { | |
235 | .port_disable = ata_port_disable, | |
236 | .set_piomode = atiixp_set_piomode, | |
237 | .set_dmamode = atiixp_set_dmamode, | |
238 | .mode_filter = ata_pci_default_filter, | |
239 | .tf_load = ata_tf_load, | |
240 | .tf_read = ata_tf_read, | |
241 | .check_status = ata_check_status, | |
242 | .exec_command = ata_exec_command, | |
243 | .dev_select = ata_std_dev_select, | |
244 | ||
245 | .freeze = ata_bmdma_freeze, | |
246 | .thaw = ata_bmdma_thaw, | |
247 | .error_handler = atiixp_error_handler, | |
248 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
84708606 | 249 | .cable_detect = atiixp_cable_detect, |
669a5db4 JG |
250 | |
251 | .bmdma_setup = ata_bmdma_setup, | |
252 | .bmdma_start = atiixp_bmdma_start, | |
253 | .bmdma_stop = atiixp_bmdma_stop, | |
254 | .bmdma_status = ata_bmdma_status, | |
255 | ||
256 | .qc_prep = ata_qc_prep, | |
257 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 258 | |
0d5ff566 | 259 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
260 | |
261 | .irq_handler = ata_interrupt, | |
262 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
263 | .irq_on = ata_irq_on, |
264 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
265 | |
266 | .port_start = ata_port_start, | |
669a5db4 JG |
267 | }; |
268 | ||
269 | static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id) | |
270 | { | |
1626aeb8 | 271 | static const struct ata_port_info info = { |
669a5db4 JG |
272 | .sht = &atiixp_sht, |
273 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, | |
274 | .pio_mask = 0x1f, | |
275 | .mwdma_mask = 0x06, /* No MWDMA0 support */ | |
276 | .udma_mask = 0x3F, | |
277 | .port_ops = &atiixp_port_ops | |
278 | }; | |
1626aeb8 TH |
279 | const struct ata_port_info *ppi[] = { &info, NULL }; |
280 | return ata_pci_init_one(dev, ppi); | |
669a5db4 JG |
281 | } |
282 | ||
2d2744fc JG |
283 | static const struct pci_device_id atiixp[] = { |
284 | { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), }, | |
285 | { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), }, | |
286 | { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), }, | |
287 | { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), }, | |
288 | ||
289 | { }, | |
669a5db4 JG |
290 | }; |
291 | ||
292 | static struct pci_driver atiixp_pci_driver = { | |
293 | .name = DRV_NAME, | |
294 | .id_table = atiixp, | |
295 | .probe = atiixp_init_one, | |
30ced0f0 | 296 | .remove = ata_pci_remove_one, |
438ac6d5 | 297 | #ifdef CONFIG_PM |
30ced0f0 AC |
298 | .resume = ata_pci_device_resume, |
299 | .suspend = ata_pci_device_suspend, | |
438ac6d5 | 300 | #endif |
669a5db4 JG |
301 | }; |
302 | ||
303 | static int __init atiixp_init(void) | |
304 | { | |
305 | return pci_register_driver(&atiixp_pci_driver); | |
306 | } | |
307 | ||
308 | ||
309 | static void __exit atiixp_exit(void) | |
310 | { | |
311 | pci_unregister_driver(&atiixp_pci_driver); | |
312 | } | |
313 | ||
669a5db4 JG |
314 | MODULE_AUTHOR("Alan Cox"); |
315 | MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400"); | |
316 | MODULE_LICENSE("GPL"); | |
317 | MODULE_DEVICE_TABLE(pci, atiixp); | |
318 | MODULE_VERSION(DRV_VERSION); | |
319 | ||
320 | module_init(atiixp_init); | |
321 | module_exit(atiixp_exit); |