[mirror_ubuntu-bionic-kernel.git] / drivers / ata / pata_bk3710.c

/*
 * Palmchip BK3710 PATA controller driver
 *
 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Based on palm_bk3710.c:
 *
 * Copyright (C) 2006 Texas Instruments.
 * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/ata.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/libata.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/types.h>

#define DRV_NAME "pata_bk3710"

#define BK3710_TF_OFFSET	0x1F0
#define BK3710_CTL_OFFSET	0x3F6

#define BK3710_BMISP		0x02
#define BK3710_IDETIMP		0x40
#define BK3710_UDMACTL		0x48
#define BK3710_MISCCTL		0x50
#define BK3710_REGSTB		0x54
#define BK3710_REGRCVR		0x58
#define BK3710_DATSTB		0x5C
#define BK3710_DATRCVR		0x60
#define BK3710_DMASTB		0x64
#define BK3710_DMARCVR		0x68
#define BK3710_UDMASTB		0x6C
#define BK3710_UDMATRP		0x70
#define BK3710_UDMAENV		0x74
#define BK3710_IORDYTMP		0x78

static struct scsi_host_template pata_bk3710_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static unsigned int ideclk_period; /* in nanoseconds */

struct pata_bk3710_udmatiming {
	unsigned int rptime;	/* tRP -- Ready to pause time (nsec) */
	unsigned int cycletime;	/* tCYCTYP2/2 -- avg Cycle Time (nsec) */
				/* tENV is always a minimum of 20 nsec */
};

static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
	{ 160, 240 / 2 },	/* UDMA Mode 0 */
	{ 125, 160 / 2 },	/* UDMA Mode 1 */
	{ 100, 120 / 2 },	/* UDMA Mode 2 */
	{ 100,  90 / 2 },	/* UDMA Mode 3 */
	{ 100,  60 / 2 },	/* UDMA Mode 4 */
	{  85,  40 / 2 },	/* UDMA Mode 5 */
};

static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
				    unsigned int mode)
{
	u32 val32;
	u16 val16;
	u8 tenv, trp, t0;

	/* DMA Data Setup */
	t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
			  ideclk_period) - 1;
	tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
	trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
			   ideclk_period) - 1;

	/* udmastb Ultra DMA Access Strobe Width */
	val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
	val32 |= t0 << (dev ? 8 : 0);
	iowrite32(val32, base + BK3710_UDMASTB);

	/* udmatrp Ultra DMA Ready to Pause Time */
	val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
	val32 |= trp << (dev ? 8 : 0);
	iowrite32(val32, base + BK3710_UDMATRP);

	/* udmaenv Ultra DMA envelop Time */
	val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
	val32 |= tenv << (dev ? 8 : 0);
	iowrite32(val32, base + BK3710_UDMAENV);

	/* Enable UDMA for Device */
	val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev);
	iowrite16(val16, base + BK3710_UDMACTL);
}

static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
				     unsigned short min_cycle,
				     unsigned int mode)
{
	const struct ata_timing *t;
	int cycletime;
	u32 val32;
	u16 val16;
	u8 td, tkw, t0;

	t = ata_timing_find_mode(mode);
	cycletime = max_t(int, t->cycle, min_cycle);

	/* DMA Data Setup */
	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
	td = DIV_ROUND_UP(t->active, ideclk_period);
	tkw = t0 - td - 1;
	td--;

	val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
	val32 |= td << (dev ? 8 : 0);
	iowrite32(val32, base + BK3710_DMASTB);

	val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
	val32 |= tkw << (dev ? 8 : 0);
	iowrite32(val32, base + BK3710_DMARCVR);

	/* Disable UDMA for Device */
	val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
	iowrite16(val16, base + BK3710_UDMACTL);
}

static void pata_bk3710_set_dmamode(struct ata_port *ap,
				    struct ata_device *adev)
{
	void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
	int is_slave = adev->devno;
	const u8 xferspeed = adev->dma_mode;

	if (xferspeed >= XFER_UDMA_0)
		pata_bk3710_setudmamode(base, is_slave,
					xferspeed - XFER_UDMA_0);
	else
		pata_bk3710_setmwdmamode(base, is_slave,
					 adev->id[ATA_ID_EIDE_DMA_MIN],
					 xferspeed);
}

static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair,
				   unsigned int dev, unsigned int cycletime,
				   unsigned int mode)
{
	const struct ata_timing *t;
	u32 val32;
	u8 t2, t2i, t0;

	t = ata_timing_find_mode(XFER_PIO_0 + mode);

	/* PIO Data Setup */
	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
	t2 = DIV_ROUND_UP(t->active, ideclk_period);

	t2i = t0 - t2 - 1;
	t2--;

	val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
	val32 |= t2 << (dev ? 8 : 0);
	iowrite32(val32, base + BK3710_DATSTB);

	val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
	val32 |= t2i << (dev ? 8 : 0);
	iowrite32(val32, base + BK3710_DATRCVR);

	/* FIXME: this is broken also in the old driver */
	if (pair) {
		u8 mode2 = pair->pio_mode - XFER_PIO_0;

		if (mode2 < mode)
			mode = mode2;
	}

	/* TASKFILE Setup */
	t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
	t2 = DIV_ROUND_UP(t->act8b, ideclk_period);

	t2i = t0 - t2 - 1;
	t2--;

	val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
	val32 |= t2 << (dev ? 8 : 0);
	iowrite32(val32, base + BK3710_REGSTB);

	val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
	val32 |= t2i << (dev ? 8 : 0);
	iowrite32(val32, base + BK3710_REGRCVR);
}

static void pata_bk3710_set_piomode(struct ata_port *ap,
				    struct ata_device *adev)
{
	void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
	struct ata_device *pair = ata_dev_pair(adev);
	const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
	const u16 *id = adev->id;
	unsigned int cycle_time = 0;
	int is_slave = adev->devno;
	const u8 pio = adev->pio_mode - XFER_PIO_0;

	if (id[ATA_ID_FIELD_VALID] & 2) {
		if (ata_id_has_iordy(id))
			cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
		else
			cycle_time = id[ATA_ID_EIDE_PIO];

		/* conservative "downgrade" for all pre-ATA2 drives */
		if (pio < 3 && cycle_time < t->cycle)
			cycle_time = 0; /* use standard timing */
	}

	if (!cycle_time)
		cycle_time = t->cycle;

	pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
}

static void pata_bk3710_chipinit(void __iomem *base)
{
	/*
	 * REVISIT:  the ATA reset signal needs to be managed through a
	 * GPIO, which means it should come from platform_data.  Until
	 * we get and use such information, we have to trust that things
	 * have been reset before we get here.
	 */

	/*
	 * Program the IDETIMP Register Value based on the following assumptions
	 *
	 * (ATA_IDETIMP_IDEEN		, ENABLE ) |
	 * (ATA_IDETIMP_PREPOST1	, DISABLE) |
	 * (ATA_IDETIMP_PREPOST0	, DISABLE) |
	 *
	 * DM6446 silicon rev 2.1 and earlier have no observed net benefit
	 * from enabling prefetch/postwrite.
	 */
	iowrite16(BIT(15), base + BK3710_IDETIMP);

	/*
	 * UDMACTL Ultra-ATA DMA Control
	 * (ATA_UDMACTL_UDMAP1	, 0 ) |
	 * (ATA_UDMACTL_UDMAP0	, 0 )
	 *
	 */
	iowrite16(0, base + BK3710_UDMACTL);

	/*
	 * MISCCTL Miscellaneous Conrol Register
	 * (ATA_MISCCTL_HWNHLD1P	, 1 cycle)
	 * (ATA_MISCCTL_HWNHLD0P	, 1 cycle)
	 * (ATA_MISCCTL_TIMORIDE	, 1)
	 */
	iowrite32(0x001, base + BK3710_MISCCTL);

	/*
	 * IORDYTMP IORDY Timer for Primary Register
	 * (ATA_IORDYTMP_IORDYTMP	, DISABLE)
	 */
	iowrite32(0, base + BK3710_IORDYTMP);

	/*
	 * Configure BMISP Register
	 * (ATA_BMISP_DMAEN1	, DISABLE )	|
	 * (ATA_BMISP_DMAEN0	, DISABLE )	|
	 * (ATA_BMISP_IORDYINT	, CLEAR)	|
	 * (ATA_BMISP_INTRSTAT	, CLEAR)	|
	 * (ATA_BMISP_DMAERROR	, CLEAR)
	 */
	iowrite16(0xE, base + BK3710_BMISP);

	pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
	pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
}

static struct ata_port_operations pata_bk3710_ports_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= ata_cable_80wire,

	.set_piomode		= pata_bk3710_set_piomode,
	.set_dmamode		= pata_bk3710_set_dmamode,
};

static int __init pata_bk3710_probe(struct platform_device *pdev)
{
	struct clk *clk;
	struct resource *mem;
	struct ata_host *host;
	struct ata_port *ap;
	void __iomem *base;
	unsigned long rate;
	int irq;

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return -ENODEV;

	clk_enable(clk);
	rate = clk_get_rate(clk);
	if (!rate)
		return -EINVAL;

	/* NOTE:  round *down* to meet minimum timings; we count in clocks */
	ideclk_period = 1000000000UL / rate;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		pr_err(DRV_NAME ": failed to get IRQ resource\n");
		return irq;
	}

	base = devm_ioremap_resource(&pdev->dev, mem);
	if (IS_ERR(base))
		return PTR_ERR(base);

	/* configure the Palmchip controller */
	pata_bk3710_chipinit(base);

	/* allocate host */
	host = ata_host_alloc(&pdev->dev, 1);
	if (!host)
		return -ENOMEM;
	ap = host->ports[0];

	ap->ops = &pata_bk3710_ports_ops;
	ap->pio_mask = ATA_PIO4;
	ap->mwdma_mask = ATA_MWDMA2;
	ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
	ap->flags |= ATA_FLAG_SLAVE_POSS;

	ap->ioaddr.data_addr		= base + BK3710_TF_OFFSET;
	ap->ioaddr.error_addr		= base + BK3710_TF_OFFSET + 1;
	ap->ioaddr.feature_addr		= base + BK3710_TF_OFFSET + 1;
	ap->ioaddr.nsect_addr		= base + BK3710_TF_OFFSET + 2;
	ap->ioaddr.lbal_addr		= base + BK3710_TF_OFFSET + 3;
	ap->ioaddr.lbam_addr		= base + BK3710_TF_OFFSET + 4;
	ap->ioaddr.lbah_addr		= base + BK3710_TF_OFFSET + 5;
	ap->ioaddr.device_addr		= base + BK3710_TF_OFFSET + 6;
	ap->ioaddr.status_addr		= base + BK3710_TF_OFFSET + 7;
	ap->ioaddr.command_addr		= base + BK3710_TF_OFFSET + 7;

	ap->ioaddr.altstatus_addr	= base + BK3710_CTL_OFFSET;
	ap->ioaddr.ctl_addr		= base + BK3710_CTL_OFFSET;

	ap->ioaddr.bmdma_addr		= base;

	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
		      (unsigned long)base + BK3710_TF_OFFSET,
		      (unsigned long)base + BK3710_CTL_OFFSET);

	/* activate */
	return ata_host_activate(host, irq, ata_sff_interrupt, 0,
				 &pata_bk3710_sht);
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:palm_bk3710");

static struct platform_driver pata_bk3710_driver = {
	.driver = {
		.name = "palm_bk3710",
	},
};

static int __init pata_bk3710_init(void)
{
	return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
}

module_init(pata_bk3710_init);
MODULE_LICENSE("GPL");
Commit	Line	Data
76a40ca8 BZ	1	/*
	2	* Palmchip BK3710 PATA controller driver
	3	*
	4	* Copyright (c) 2017 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Based on palm_bk3710.c:
	8	*
	9	* Copyright (C) 2006 Texas Instruments.
	10	* Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
	11	*
	12	* This file is subject to the terms and conditions of the GNU General Public
	13	* License. See the file "COPYING" in the main directory of this archive
	14	* for more details.
	15	*/
	16
	17	#include <linux/ata.h>
	18	#include <linux/clk.h>
	19	#include <linux/delay.h>
	20	#include <linux/init.h>
	21	#include <linux/ioport.h>
	22	#include <linux/kernel.h>
	23	#include <linux/libata.h>
	24	#include <linux/module.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/types.h>
	27
	28	#define DRV_NAME "pata_bk3710"
	29
	30	#define BK3710_TF_OFFSET 0x1F0
	31	#define BK3710_CTL_OFFSET 0x3F6
	32
	33	#define BK3710_BMISP 0x02
	34	#define BK3710_IDETIMP 0x40
	35	#define BK3710_UDMACTL 0x48
	36	#define BK3710_MISCCTL 0x50
	37	#define BK3710_REGSTB 0x54
	38	#define BK3710_REGRCVR 0x58
	39	#define BK3710_DATSTB 0x5C
	40	#define BK3710_DATRCVR 0x60
	41	#define BK3710_DMASTB 0x64
	42	#define BK3710_DMARCVR 0x68
	43	#define BK3710_UDMASTB 0x6C
	44	#define BK3710_UDMATRP 0x70
	45	#define BK3710_UDMAENV 0x74
	46	#define BK3710_IORDYTMP 0x78
	47
	48	static struct scsi_host_template pata_bk3710_sht = {
	49	ATA_BMDMA_SHT(DRV_NAME),
	50	};
	51
	52	static unsigned int ideclk_period; /* in nanoseconds */
	53
	54	struct pata_bk3710_udmatiming {
	55	unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
	56	unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
	57	/* tENV is always a minimum of 20 nsec */
	58	};
	59
	60	static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
	61	{ 160, 240 / 2 }, /* UDMA Mode 0 */
	62	{ 125, 160 / 2 }, /* UDMA Mode 1 */
	63	{ 100, 120 / 2 }, /* UDMA Mode 2 */
	64	{ 100, 90 / 2 }, /* UDMA Mode 3 */
65	{ 100, 60 / 2 }, /* UDMA Mode 4 */
66	{ 85, 40 / 2 }, /* UDMA Mode 5 */
67	};
68
69	static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
70	unsigned int mode)
71	{
72	u32 val32;
73	u16 val16;
74	u8 tenv, trp, t0;
75
76	/* DMA Data Setup */
77	t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
78	ideclk_period) - 1;
79	tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
80	trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
81	ideclk_period) - 1;
82
83	/* udmastb Ultra DMA Access Strobe Width */
84	val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
85	val32 \|= t0 << (dev ? 8 : 0);
86	iowrite32(val32, base + BK3710_UDMASTB);
87
88	/* udmatrp Ultra DMA Ready to Pause Time */
89	val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
90	val32 \|= trp << (dev ? 8 : 0);
91	iowrite32(val32, base + BK3710_UDMATRP);
92
93	/* udmaenv Ultra DMA envelop Time */
94	val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
95	val32 \|= tenv << (dev ? 8 : 0);
96	iowrite32(val32, base + BK3710_UDMAENV);
97
98	/* Enable UDMA for Device */
99	val16 = ioread16(base + BK3710_UDMACTL) \| (1 << dev);
100	iowrite16(val16, base + BK3710_UDMACTL);
101	}
102
103	static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
104	unsigned short min_cycle,
105	unsigned int mode)
106	{
107	const struct ata_timing *t;
108	int cycletime;
109	u32 val32;
110	u16 val16;
111	u8 td, tkw, t0;
112
113	t = ata_timing_find_mode(mode);
114	cycletime = max_t(int, t->cycle, min_cycle);
115
116	/* DMA Data Setup */
117	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
118	td = DIV_ROUND_UP(t->active, ideclk_period);
119	tkw = t0 - td - 1;
120	td--;
121
122	val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
123	val32 \|= td << (dev ? 8 : 0);
124	iowrite32(val32, base + BK3710_DMASTB);
125
126	val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
127	val32 \|= tkw << (dev ? 8 : 0);
128	iowrite32(val32, base + BK3710_DMARCVR);
129
130	/* Disable UDMA for Device */
131	val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
132	iowrite16(val16, base + BK3710_UDMACTL);
133	}
134
135	static void pata_bk3710_set_dmamode(struct ata_port *ap,
136	struct ata_device *adev)
137	{
138	void __iomem base = (void __iomem )ap->ioaddr.bmdma_addr;
139	int is_slave = adev->devno;
140	const u8 xferspeed = adev->dma_mode;
141
142	if (xferspeed >= XFER_UDMA_0)
143	pata_bk3710_setudmamode(base, is_slave,
144	xferspeed - XFER_UDMA_0);
145	else
146	pata_bk3710_setmwdmamode(base, is_slave,
147	adev->id[ATA_ID_EIDE_DMA_MIN],
148	xferspeed);
149	}
150
151	static void pata_bk3710_setpiomode(void __iomem base, struct ata_device pair,
152	unsigned int dev, unsigned int cycletime,
153	unsigned int mode)
154	{
155	const struct ata_timing *t;
156	u32 val32;
157	u8 t2, t2i, t0;
158
159	t = ata_timing_find_mode(XFER_PIO_0 + mode);
160
161	/* PIO Data Setup */
162	t0 = DIV_ROUND_UP(cycletime, ideclk_period);
163	t2 = DIV_ROUND_UP(t->active, ideclk_period);
164
165	t2i = t0 - t2 - 1;
166	t2--;
167
168	val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
169	val32 \|= t2 << (dev ? 8 : 0);
170	iowrite32(val32, base + BK3710_DATSTB);
171
172	val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
173	val32 \|= t2i << (dev ? 8 : 0);
174	iowrite32(val32, base + BK3710_DATRCVR);
175
176	/* FIXME: this is broken also in the old driver */
177	if (pair) {
178	u8 mode2 = pair->pio_mode - XFER_PIO_0;
179
180	if (mode2 < mode)
181	mode = mode2;
182	}
183
184	/* TASKFILE Setup */
185	t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
186	t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
187
188	t2i = t0 - t2 - 1;
189	t2--;
190
191	val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
192	val32 \|= t2 << (dev ? 8 : 0);
193	iowrite32(val32, base + BK3710_REGSTB);
194
195	val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
196	val32 \|= t2i << (dev ? 8 : 0);
197	iowrite32(val32, base + BK3710_REGRCVR);
198	}
199
200	static void pata_bk3710_set_piomode(struct ata_port *ap,
201	struct ata_device *adev)
202	{
203	void __iomem base = (void __iomem )ap->ioaddr.bmdma_addr;
204	struct ata_device *pair = ata_dev_pair(adev);
205	const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
206	const u16 *id = adev->id;
207	unsigned int cycle_time = 0;
208	int is_slave = adev->devno;
209	const u8 pio = adev->pio_mode - XFER_PIO_0;
210
211	if (id[ATA_ID_FIELD_VALID] & 2) {
212	if (ata_id_has_iordy(id))
213	cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
214	else
215	cycle_time = id[ATA_ID_EIDE_PIO];
216
217	/* conservative "downgrade" for all pre-ATA2 drives */
218	if (pio < 3 && cycle_time < t->cycle)
219	cycle_time = 0; /* use standard timing */
220	}
221
222	if (!cycle_time)
223	cycle_time = t->cycle;
224
225	pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
226	}
227
228	static void pata_bk3710_chipinit(void __iomem *base)
229	{
230	/*
231	* REVISIT: the ATA reset signal needs to be managed through a
232	* GPIO, which means it should come from platform_data. Until
233	* we get and use such information, we have to trust that things
234	* have been reset before we get here.
235	*/
236
237	/*
238	* Program the IDETIMP Register Value based on the following assumptions
239	*
240	* (ATA_IDETIMP_IDEEN , ENABLE ) \|
241	* (ATA_IDETIMP_PREPOST1 , DISABLE) \|
242	* (ATA_IDETIMP_PREPOST0 , DISABLE) \|
243	*
244	* DM6446 silicon rev 2.1 and earlier have no observed net benefit
245	* from enabling prefetch/postwrite.
246	*/
247	iowrite16(BIT(15), base + BK3710_IDETIMP);
248
249	/*
250	* UDMACTL Ultra-ATA DMA Control
251	* (ATA_UDMACTL_UDMAP1 , 0 ) \|
252	* (ATA_UDMACTL_UDMAP0 , 0 )
253	*
254	*/
255	iowrite16(0, base + BK3710_UDMACTL);
256
257	/*
258	* MISCCTL Miscellaneous Conrol Register
259	* (ATA_MISCCTL_HWNHLD1P , 1 cycle)
260	* (ATA_MISCCTL_HWNHLD0P , 1 cycle)
261	* (ATA_MISCCTL_TIMORIDE , 1)
262	*/
263	iowrite32(0x001, base + BK3710_MISCCTL);
264
265	/*
266	* IORDYTMP IORDY Timer for Primary Register
c217ff26	267	* (ATA_IORDYTMP_IORDYTMP , DISABLE)
76a40ca8	268	*/
c217ff26	269	iowrite32(0, base + BK3710_IORDYTMP);
76a40ca8 BZ	270
	271	/*
	272	* Configure BMISP Register
	273	* (ATA_BMISP_DMAEN1 , DISABLE ) \|
	274	* (ATA_BMISP_DMAEN0 , DISABLE ) \|
	275	* (ATA_BMISP_IORDYINT , CLEAR) \|
	276	* (ATA_BMISP_INTRSTAT , CLEAR) \|
	277	* (ATA_BMISP_DMAERROR , CLEAR)
	278	*/
396ff64d	279	iowrite16(0xE, base + BK3710_BMISP);
76a40ca8 BZ	280
	281	pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
	282	pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
	283	}
	284
	285	static struct ata_port_operations pata_bk3710_ports_ops = {
	286	.inherits = &ata_bmdma_port_ops,
	287	.cable_detect = ata_cable_80wire,
	288
	289	.set_piomode = pata_bk3710_set_piomode,
	290	.set_dmamode = pata_bk3710_set_dmamode,
	291	};
	292
	293	static int __init pata_bk3710_probe(struct platform_device *pdev)
	294	{
	295	struct clk *clk;
	296	struct resource *mem;
	297	struct ata_host *host;
	298	struct ata_port *ap;
	299	void __iomem *base;
	300	unsigned long rate;
	301	int irq;
	302
	303	clk = devm_clk_get(&pdev->dev, NULL);
	304	if (IS_ERR(clk))
	305	return -ENODEV;
	306
	307	clk_enable(clk);
	308	rate = clk_get_rate(clk);
	309	if (!rate)
	310	return -EINVAL;
	311
	312	/* NOTE: round down to meet minimum timings; we count in clocks */
	313	ideclk_period = 1000000000UL / rate;
	314
	315	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	316
	317	irq = platform_get_irq(pdev, 0);
	318	if (irq < 0) {
	319	pr_err(DRV_NAME ": failed to get IRQ resource\n");
	320	return irq;
	321	}
	322
	323	base = devm_ioremap_resource(&pdev->dev, mem);
	324	if (IS_ERR(base))
	325	return PTR_ERR(base);
	326
	327	/* configure the Palmchip controller */
	328	pata_bk3710_chipinit(base);
	329
	330	/* allocate host */
	331	host = ata_host_alloc(&pdev->dev, 1);
	332	if (!host)
	333	return -ENOMEM;
	334	ap = host->ports[0];
	335
	336	ap->ops = &pata_bk3710_ports_ops;
	337	ap->pio_mask = ATA_PIO4;
	338	ap->mwdma_mask = ATA_MWDMA2;
	339	ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
	340	ap->flags \|= ATA_FLAG_SLAVE_POSS;
	341
	342	ap->ioaddr.data_addr = base + BK3710_TF_OFFSET;
	343	ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1;
344	ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1;
345	ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2;
346	ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3;
347	ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4;
348	ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5;
349	ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6;
350	ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7;
351	ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7;
352
353	ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET;
354	ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET;
355
356	ap->ioaddr.bmdma_addr = base;
357
358	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
359	(unsigned long)base + BK3710_TF_OFFSET,
360	(unsigned long)base + BK3710_CTL_OFFSET);
361
362	/* activate */
363	return ata_host_activate(host, irq, ata_sff_interrupt, 0,
364	&pata_bk3710_sht);
365	}
366
367	/* work with hotplug and coldplug */
368	MODULE_ALIAS("platform:palm_bk3710");
369
370	static struct platform_driver pata_bk3710_driver = {
371	.driver = {
372	.name = "palm_bk3710",
373	},
374	};
375
376	static int __init pata_bk3710_init(void)
377	{
378	return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
379	}
380
381	module_init(pata_bk3710_init);
382	MODULE_LICENSE("GPL");