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669a5db4 JG |
1 | /* |
2 | * IDE tuning and bus mastering support for the CS5510/CS5520 | |
3 | * chipsets | |
4 | * | |
5 | * The CS5510/CS5520 are slightly unusual devices. Unlike the | |
6 | * typical IDE controllers they do bus mastering with the drive in | |
7 | * PIO mode and smarter silicon. | |
8 | * | |
9 | * The practical upshot of this is that we must always tune the | |
10 | * drive for the right PIO mode. We must also ignore all the blacklists | |
11 | * and the drive bus mastering DMA information. Also to confuse matters | |
12 | * further we can do DMA on PIO only drives. | |
13 | * | |
14 | * DMA on the 5510 also requires we disable_hlt() during DMA on early | |
15 | * revisions. | |
16 | * | |
17 | * *** This driver is strictly experimental *** | |
18 | * | |
19 | * (c) Copyright Red Hat Inc 2002 | |
20 | * | |
21 | * This program is free software; you can redistribute it and/or modify it | |
22 | * under the terms of the GNU General Public License as published by the | |
23 | * Free Software Foundation; either version 2, or (at your option) any | |
24 | * later version. | |
25 | * | |
26 | * This program is distributed in the hope that it will be useful, but | |
27 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
28 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
29 | * General Public License for more details. | |
30 | * | |
31 | * Documentation: | |
25985edc | 32 | * Not publicly available. |
669a5db4 JG |
33 | */ |
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
40 | #include <scsi/scsi_host.h> | |
41 | #include <linux/libata.h> | |
42 | ||
43 | #define DRV_NAME "pata_cs5520" | |
2a3103ce | 44 | #define DRV_VERSION "0.6.6" |
669a5db4 JG |
45 | |
46 | struct pio_clocks | |
47 | { | |
48 | int address; | |
49 | int assert; | |
50 | int recovery; | |
51 | }; | |
52 | ||
53 | static const struct pio_clocks cs5520_pio_clocks[]={ | |
54 | {3, 6, 11}, | |
55 | {2, 5, 6}, | |
56 | {1, 4, 3}, | |
57 | {1, 3, 2}, | |
58 | {1, 2, 1} | |
59 | }; | |
60 | ||
61 | /** | |
62 | * cs5520_set_timings - program PIO timings | |
63 | * @ap: ATA port | |
64 | * @adev: ATA device | |
65 | * | |
66 | * Program the PIO mode timings for the controller according to the pio | |
67 | * clocking table. | |
68 | */ | |
69 | ||
70 | static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio) | |
71 | { | |
72 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
73 | int slave = adev->devno; | |
74 | ||
75 | pio -= XFER_PIO_0; | |
76 | ||
77 | /* Channel command timing */ | |
78 | pci_write_config_byte(pdev, 0x62 + ap->port_no, | |
79 | (cs5520_pio_clocks[pio].recovery << 4) | | |
80 | (cs5520_pio_clocks[pio].assert)); | |
81 | /* FIXME: should these use address ? */ | |
82 | /* Read command timing */ | |
83 | pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave, | |
84 | (cs5520_pio_clocks[pio].recovery << 4) | | |
85 | (cs5520_pio_clocks[pio].assert)); | |
86 | /* Write command timing */ | |
87 | pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave, | |
88 | (cs5520_pio_clocks[pio].recovery << 4) | | |
89 | (cs5520_pio_clocks[pio].assert)); | |
90 | } | |
91 | ||
669a5db4 JG |
92 | /** |
93 | * cs5520_set_piomode - program PIO timings | |
94 | * @ap: ATA port | |
95 | * @adev: ATA device | |
96 | * | |
97 | * Program the PIO mode timings for the controller according to the pio | |
940a68de | 98 | * clocking table. |
669a5db4 JG |
99 | */ |
100 | ||
101 | static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
102 | { | |
103 | cs5520_set_timings(ap, adev, adev->pio_mode); | |
104 | } | |
105 | ||
669a5db4 | 106 | static struct scsi_host_template cs5520_sht = { |
68d1d07b | 107 | ATA_BMDMA_SHT(DRV_NAME), |
d26fc955 | 108 | .sg_tablesize = LIBATA_DUMB_MAX_PRD, |
669a5db4 JG |
109 | }; |
110 | ||
111 | static struct ata_port_operations cs5520_port_ops = { | |
029cfd6b | 112 | .inherits = &ata_bmdma_port_ops, |
f47451c4 | 113 | .qc_prep = ata_bmdma_dumb_qc_prep, |
029cfd6b | 114 | .cable_detect = ata_cable_40wire, |
669a5db4 | 115 | .set_piomode = cs5520_set_piomode, |
669a5db4 JG |
116 | }; |
117 | ||
0ec24914 | 118 | static int cs5520_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
669a5db4 | 119 | { |
cbcdd875 TH |
120 | static const unsigned int cmd_port[] = { 0x1F0, 0x170 }; |
121 | static const unsigned int ctl_port[] = { 0x3F6, 0x376 }; | |
5d728824 TH |
122 | struct ata_port_info pi = { |
123 | .flags = ATA_FLAG_SLAVE_POSS, | |
14bdef98 | 124 | .pio_mask = ATA_PIO4, |
5d728824 TH |
125 | .port_ops = &cs5520_port_ops, |
126 | }; | |
127 | const struct ata_port_info *ppi[2]; | |
669a5db4 | 128 | u8 pcicfg; |
4ca4e439 | 129 | void __iomem *iomap[5]; |
5d728824 TH |
130 | struct ata_host *host; |
131 | struct ata_ioports *ioaddr; | |
132 | int i, rc; | |
669a5db4 | 133 | |
f08048e9 TH |
134 | rc = pcim_enable_device(pdev); |
135 | if (rc) | |
136 | return rc; | |
137 | ||
669a5db4 | 138 | /* IDE port enable bits */ |
5d728824 | 139 | pci_read_config_byte(pdev, 0x60, &pcicfg); |
669a5db4 JG |
140 | |
141 | /* Check if the ATA ports are enabled */ | |
142 | if ((pcicfg & 3) == 0) | |
143 | return -ENODEV; | |
144 | ||
5d728824 TH |
145 | ppi[0] = ppi[1] = &ata_dummy_port_info; |
146 | if (pcicfg & 1) | |
147 | ppi[0] = π | |
148 | if (pcicfg & 2) | |
149 | ppi[1] = π | |
150 | ||
669a5db4 | 151 | if ((pcicfg & 0x40) == 0) { |
a44fec1f | 152 | dev_warn(&pdev->dev, "DMA mode disabled. Enabling.\n"); |
5d728824 | 153 | pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); |
669a5db4 JG |
154 | } |
155 | ||
5d728824 TH |
156 | pi.mwdma_mask = id->driver_data; |
157 | ||
158 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); | |
159 | if (!host) | |
160 | return -ENOMEM; | |
161 | ||
669a5db4 | 162 | /* Perform set up for DMA */ |
09483916 | 163 | if (pci_enable_device_io(pdev)) { |
669a5db4 JG |
164 | printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n"); |
165 | return -ENODEV; | |
166 | } | |
5d728824 | 167 | |
284901a9 | 168 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { |
669a5db4 JG |
169 | printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n"); |
170 | return -ENODEV; | |
171 | } | |
284901a9 | 172 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { |
669a5db4 JG |
173 | printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n"); |
174 | return -ENODEV; | |
175 | } | |
176 | ||
5d728824 | 177 | /* Map IO ports and initialize host accordingly */ |
cbcdd875 TH |
178 | iomap[0] = devm_ioport_map(&pdev->dev, cmd_port[0], 8); |
179 | iomap[1] = devm_ioport_map(&pdev->dev, ctl_port[0], 1); | |
180 | iomap[2] = devm_ioport_map(&pdev->dev, cmd_port[1], 8); | |
181 | iomap[3] = devm_ioport_map(&pdev->dev, ctl_port[1], 1); | |
5d728824 | 182 | iomap[4] = pcim_iomap(pdev, 2, 0); |
0d5ff566 TH |
183 | |
184 | if (!iomap[0] || !iomap[1] || !iomap[2] || !iomap[3] || !iomap[4]) | |
185 | return -ENOMEM; | |
186 | ||
5d728824 TH |
187 | ioaddr = &host->ports[0]->ioaddr; |
188 | ioaddr->cmd_addr = iomap[0]; | |
189 | ioaddr->ctl_addr = iomap[1]; | |
190 | ioaddr->altstatus_addr = iomap[1]; | |
191 | ioaddr->bmdma_addr = iomap[4]; | |
9363c382 | 192 | ata_sff_std_ports(ioaddr); |
5d728824 | 193 | |
cbcdd875 TH |
194 | ata_port_desc(host->ports[0], |
195 | "cmd 0x%x ctl 0x%x", cmd_port[0], ctl_port[0]); | |
196 | ata_port_pbar_desc(host->ports[0], 4, 0, "bmdma"); | |
197 | ||
5d728824 TH |
198 | ioaddr = &host->ports[1]->ioaddr; |
199 | ioaddr->cmd_addr = iomap[2]; | |
200 | ioaddr->ctl_addr = iomap[3]; | |
201 | ioaddr->altstatus_addr = iomap[3]; | |
202 | ioaddr->bmdma_addr = iomap[4] + 8; | |
9363c382 | 203 | ata_sff_std_ports(ioaddr); |
5d728824 | 204 | |
cbcdd875 TH |
205 | ata_port_desc(host->ports[1], |
206 | "cmd 0x%x ctl 0x%x", cmd_port[1], ctl_port[1]); | |
207 | ata_port_pbar_desc(host->ports[1], 4, 8, "bmdma"); | |
208 | ||
5d728824 TH |
209 | /* activate the host */ |
210 | pci_set_master(pdev); | |
211 | rc = ata_host_start(host); | |
212 | if (rc) | |
213 | return rc; | |
214 | ||
215 | for (i = 0; i < 2; i++) { | |
216 | static const int irq[] = { 14, 15 }; | |
8c6b065b | 217 | struct ata_port *ap = host->ports[i]; |
5d728824 TH |
218 | |
219 | if (ata_port_is_dummy(ap)) | |
220 | continue; | |
221 | ||
222 | rc = devm_request_irq(&pdev->dev, irq[ap->port_no], | |
c3b28894 | 223 | ata_bmdma_interrupt, 0, DRV_NAME, host); |
5d728824 TH |
224 | if (rc) |
225 | return rc; | |
4031826b | 226 | |
cbcdd875 | 227 | ata_port_desc(ap, "irq %d", irq[i]); |
5d728824 TH |
228 | } |
229 | ||
230 | return ata_host_register(host, &cs5520_sht); | |
669a5db4 JG |
231 | } |
232 | ||
438ac6d5 | 233 | #ifdef CONFIG_PM |
8501120f AC |
234 | /** |
235 | * cs5520_reinit_one - device resume | |
236 | * @pdev: PCI device | |
237 | * | |
238 | * Do any reconfiguration work needed by a resume from RAM. We need | |
239 | * to restore DMA mode support on BIOSen which disabled it | |
240 | */ | |
f20b16ff | 241 | |
8501120f AC |
242 | static int cs5520_reinit_one(struct pci_dev *pdev) |
243 | { | |
0a86e1c8 | 244 | struct ata_host *host = pci_get_drvdata(pdev); |
8501120f | 245 | u8 pcicfg; |
f08048e9 TH |
246 | int rc; |
247 | ||
248 | rc = ata_pci_device_do_resume(pdev); | |
249 | if (rc) | |
250 | return rc; | |
251 | ||
8501120f AC |
252 | pci_read_config_byte(pdev, 0x60, &pcicfg); |
253 | if ((pcicfg & 0x40) == 0) | |
254 | pci_write_config_byte(pdev, 0x60, pcicfg | 0x40); | |
f08048e9 TH |
255 | |
256 | ata_host_resume(host); | |
257 | return 0; | |
8501120f | 258 | } |
aa6de494 AC |
259 | |
260 | /** | |
261 | * cs5520_pci_device_suspend - device suspend | |
262 | * @pdev: PCI device | |
263 | * | |
264 | * We have to cut and waste bits from the standard method because | |
265 | * the 5520 is a bit odd and not just a pure ATA device. As a result | |
266 | * we must not disable it. The needed code is short and this avoids | |
267 | * chip specific mess in the core code. | |
268 | */ | |
269 | ||
270 | static int cs5520_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
271 | { | |
0a86e1c8 | 272 | struct ata_host *host = pci_get_drvdata(pdev); |
aa6de494 AC |
273 | int rc = 0; |
274 | ||
275 | rc = ata_host_suspend(host, mesg); | |
276 | if (rc) | |
277 | return rc; | |
278 | ||
279 | pci_save_state(pdev); | |
280 | return 0; | |
281 | } | |
438ac6d5 | 282 | #endif /* CONFIG_PM */ |
a84471fe | 283 | |
669a5db4 JG |
284 | /* For now keep DMA off. We can set it for all but A rev CS5510 once the |
285 | core ATA code can handle it */ | |
286 | ||
2d2744fc JG |
287 | static const struct pci_device_id pata_cs5520[] = { |
288 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), }, | |
289 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), }, | |
290 | ||
291 | { }, | |
669a5db4 JG |
292 | }; |
293 | ||
294 | static struct pci_driver cs5520_pci_driver = { | |
295 | .name = DRV_NAME, | |
296 | .id_table = pata_cs5520, | |
297 | .probe = cs5520_init_one, | |
2855568b | 298 | .remove = ata_pci_remove_one, |
438ac6d5 | 299 | #ifdef CONFIG_PM |
aa6de494 | 300 | .suspend = cs5520_pci_device_suspend, |
8501120f | 301 | .resume = cs5520_reinit_one, |
438ac6d5 | 302 | #endif |
669a5db4 JG |
303 | }; |
304 | ||
2fc75da0 | 305 | module_pci_driver(cs5520_pci_driver); |
669a5db4 JG |
306 | |
307 | MODULE_AUTHOR("Alan Cox"); | |
308 | MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520"); | |
309 | MODULE_LICENSE("GPL"); | |
310 | MODULE_DEVICE_TABLE(pci, pata_cs5520); | |
311 | MODULE_VERSION(DRV_VERSION); |