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669a5db4 JG |
1 | /* |
2 | * pata_efar.c - EFAR PIIX clone controller driver | |
3 | * | |
4 | * (C) 2005 Red Hat <alan@redhat.com> | |
5 | * | |
6 | * Some parts based on ata_piix.c by Jeff Garzik and others. | |
7 | * | |
8 | * The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later | |
9 | * Intel ICH controllers the EFAR widened the UDMA mode register bits | |
10 | * and doesn't require the funky clock selection. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/blkdev.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/device.h> | |
20 | #include <scsi/scsi_host.h> | |
21 | #include <linux/libata.h> | |
22 | #include <linux/ata.h> | |
23 | ||
24 | #define DRV_NAME "pata_efar" | |
6bfed3fb | 25 | #define DRV_VERSION "0.4.4" |
669a5db4 JG |
26 | |
27 | /** | |
6bfed3fb | 28 | * efar_pre_reset - Enable bits |
cc0680a5 | 29 | * @link: ATA link |
d4b2bab4 | 30 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
31 | * |
32 | * Perform cable detection for the EFAR ATA interface. This is | |
33 | * different to the PIIX arrangement | |
34 | */ | |
35 | ||
cc0680a5 | 36 | static int efar_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 JG |
37 | { |
38 | static const struct pci_bits efar_enable_bits[] = { | |
39 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
40 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
41 | }; | |
cc0680a5 | 42 | struct ata_port *ap = link->ap; |
669a5db4 | 43 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
669a5db4 | 44 | |
c961922b AC |
45 | if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no])) |
46 | return -ENOENT; | |
47 | ||
cc0680a5 | 48 | return ata_std_prereset(link, deadline); |
669a5db4 JG |
49 | } |
50 | ||
51 | /** | |
52 | * efar_probe_reset - Probe specified port on PATA host controller | |
53 | * @ap: Port to probe | |
54 | * | |
55 | * LOCKING: | |
56 | * None (inherited from caller). | |
57 | */ | |
58 | ||
59 | static void efar_error_handler(struct ata_port *ap) | |
60 | { | |
61 | ata_bmdma_drive_eh(ap, efar_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
62 | } | |
63 | ||
6bfed3fb AC |
64 | /** |
65 | * efar_cable_detect - check for 40/80 pin | |
66 | * @ap: Port | |
67 | * | |
68 | * Perform cable detection for the EFAR ATA interface. This is | |
69 | * different to the PIIX arrangement | |
70 | */ | |
71 | ||
72 | static int efar_cable_detect(struct ata_port *ap) | |
73 | { | |
74 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
75 | u8 tmp; | |
76 | ||
77 | pci_read_config_byte(pdev, 0x47, &tmp); | |
78 | if (tmp & (2 >> ap->port_no)) | |
79 | return ATA_CBL_PATA40; | |
80 | return ATA_CBL_PATA80; | |
81 | } | |
82 | ||
669a5db4 JG |
83 | /** |
84 | * efar_set_piomode - Initialize host controller PATA PIO timings | |
85 | * @ap: Port whose timings we are configuring | |
86 | * @adev: um | |
87 | * | |
88 | * Set PIO mode for device, in host controller PCI config space. | |
89 | * | |
90 | * LOCKING: | |
91 | * None (inherited from caller). | |
92 | */ | |
93 | ||
94 | static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
95 | { | |
96 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
97 | struct pci_dev *dev = to_pci_dev(ap->host->dev); | |
98 | unsigned int idetm_port= ap->port_no ? 0x42 : 0x40; | |
99 | u16 idetm_data; | |
100 | int control = 0; | |
101 | ||
102 | /* | |
103 | * See Intel Document 298600-004 for the timing programing rules | |
104 | * for PIIX/ICH. The EFAR is a clone so very similar | |
105 | */ | |
106 | ||
107 | static const /* ISP RTC */ | |
108 | u8 timings[][2] = { { 0, 0 }, | |
109 | { 0, 0 }, | |
110 | { 1, 0 }, | |
111 | { 2, 1 }, | |
112 | { 2, 3 }, }; | |
113 | ||
114 | if (pio > 2) | |
115 | control |= 1; /* TIME1 enable */ | |
116 | if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */ | |
117 | control |= 2; /* IE enable */ | |
118 | /* Intel specifies that the PPE functionality is for disk only */ | |
119 | if (adev->class == ATA_DEV_ATA) | |
120 | control |= 4; /* PPE enable */ | |
121 | ||
122 | pci_read_config_word(dev, idetm_port, &idetm_data); | |
123 | ||
124 | /* Enable PPE, IE and TIME as appropriate */ | |
125 | ||
126 | if (adev->devno == 0) { | |
127 | idetm_data &= 0xCCF0; | |
128 | idetm_data |= control; | |
129 | idetm_data |= (timings[pio][0] << 12) | | |
130 | (timings[pio][1] << 8); | |
131 | } else { | |
132 | int shift = 4 * ap->port_no; | |
133 | u8 slave_data; | |
134 | ||
135 | idetm_data &= 0xCC0F; | |
136 | idetm_data |= (control << 4); | |
137 | ||
138 | /* Slave timing in seperate register */ | |
139 | pci_read_config_byte(dev, 0x44, &slave_data); | |
140 | slave_data &= 0x0F << shift; | |
141 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift; | |
142 | pci_write_config_byte(dev, 0x44, slave_data); | |
143 | } | |
144 | ||
145 | idetm_data |= 0x4000; /* Ensure SITRE is enabled */ | |
146 | pci_write_config_word(dev, idetm_port, idetm_data); | |
147 | } | |
148 | ||
149 | /** | |
150 | * efar_set_dmamode - Initialize host controller PATA DMA timings | |
151 | * @ap: Port whose timings we are configuring | |
152 | * @adev: Device to program | |
153 | * | |
154 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
155 | * | |
156 | * LOCKING: | |
157 | * None (inherited from caller). | |
158 | */ | |
159 | ||
160 | static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
161 | { | |
162 | struct pci_dev *dev = to_pci_dev(ap->host->dev); | |
163 | u8 master_port = ap->port_no ? 0x42 : 0x40; | |
164 | u16 master_data; | |
165 | u8 speed = adev->dma_mode; | |
166 | int devid = adev->devno + 2 * ap->port_no; | |
167 | u8 udma_enable; | |
168 | ||
169 | static const /* ISP RTC */ | |
170 | u8 timings[][2] = { { 0, 0 }, | |
171 | { 0, 0 }, | |
172 | { 1, 0 }, | |
173 | { 2, 1 }, | |
174 | { 2, 3 }, }; | |
175 | ||
176 | pci_read_config_word(dev, master_port, &master_data); | |
177 | pci_read_config_byte(dev, 0x48, &udma_enable); | |
178 | ||
179 | if (speed >= XFER_UDMA_0) { | |
180 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; | |
181 | u16 udma_timing; | |
182 | ||
183 | udma_enable |= (1 << devid); | |
184 | ||
185 | /* Load the UDMA mode number */ | |
186 | pci_read_config_word(dev, 0x4A, &udma_timing); | |
187 | udma_timing &= ~(7 << (4 * devid)); | |
188 | udma_timing |= udma << (4 * devid); | |
189 | pci_write_config_word(dev, 0x4A, udma_timing); | |
190 | } else { | |
191 | /* | |
192 | * MWDMA is driven by the PIO timings. We must also enable | |
193 | * IORDY unconditionally along with TIME1. PPE has already | |
194 | * been set when the PIO timing was set. | |
195 | */ | |
196 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
197 | unsigned int control; | |
198 | u8 slave_data; | |
199 | const unsigned int needed_pio[3] = { | |
200 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
201 | }; | |
202 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
203 | ||
204 | control = 3; /* IORDY|TIME1 */ | |
205 | ||
206 | /* If the drive MWDMA is faster than it can do PIO then | |
207 | we must force PIO into PIO0 */ | |
208 | ||
209 | if (adev->pio_mode < needed_pio[mwdma]) | |
210 | /* Enable DMA timing only */ | |
211 | control |= 8; /* PIO cycles in PIO0 */ | |
212 | ||
213 | if (adev->devno) { /* Slave */ | |
214 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ | |
215 | master_data |= control << 4; | |
216 | pci_read_config_byte(dev, 0x44, &slave_data); | |
217 | slave_data &= (0x0F + 0xE1 * ap->port_no); | |
218 | /* Load the matching timing */ | |
219 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); | |
220 | pci_write_config_byte(dev, 0x44, slave_data); | |
221 | } else { /* Master */ | |
222 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY | |
223 | and master timing bits */ | |
224 | master_data |= control; | |
225 | master_data |= | |
226 | (timings[pio][0] << 12) | | |
227 | (timings[pio][1] << 8); | |
228 | } | |
229 | udma_enable &= ~(1 << devid); | |
230 | pci_write_config_word(dev, master_port, master_data); | |
231 | } | |
232 | pci_write_config_byte(dev, 0x48, udma_enable); | |
233 | } | |
234 | ||
235 | static struct scsi_host_template efar_sht = { | |
236 | .module = THIS_MODULE, | |
237 | .name = DRV_NAME, | |
238 | .ioctl = ata_scsi_ioctl, | |
239 | .queuecommand = ata_scsi_queuecmd, | |
240 | .can_queue = ATA_DEF_QUEUE, | |
241 | .this_id = ATA_SHT_THIS_ID, | |
242 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
243 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
244 | .emulated = ATA_SHT_EMULATED, | |
245 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
246 | .proc_name = DRV_NAME, | |
247 | .dma_boundary = ATA_DMA_BOUNDARY, | |
248 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 249 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
250 | .bios_param = ata_std_bios_param, |
251 | }; | |
252 | ||
253 | static const struct ata_port_operations efar_ops = { | |
669a5db4 JG |
254 | .set_piomode = efar_set_piomode, |
255 | .set_dmamode = efar_set_dmamode, | |
256 | .mode_filter = ata_pci_default_filter, | |
257 | ||
258 | .tf_load = ata_tf_load, | |
259 | .tf_read = ata_tf_read, | |
260 | .check_status = ata_check_status, | |
261 | .exec_command = ata_exec_command, | |
262 | .dev_select = ata_std_dev_select, | |
263 | ||
264 | .freeze = ata_bmdma_freeze, | |
265 | .thaw = ata_bmdma_thaw, | |
266 | .error_handler = efar_error_handler, | |
267 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
6bfed3fb | 268 | .cable_detect = efar_cable_detect, |
669a5db4 JG |
269 | |
270 | .bmdma_setup = ata_bmdma_setup, | |
271 | .bmdma_start = ata_bmdma_start, | |
272 | .bmdma_stop = ata_bmdma_stop, | |
273 | .bmdma_status = ata_bmdma_status, | |
274 | .qc_prep = ata_qc_prep, | |
275 | .qc_issue = ata_qc_issue_prot, | |
0d5ff566 | 276 | .data_xfer = ata_data_xfer, |
669a5db4 | 277 | |
669a5db4 JG |
278 | .irq_handler = ata_interrupt, |
279 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 | 280 | .irq_on = ata_irq_on, |
669a5db4 | 281 | |
81ad1837 | 282 | .port_start = ata_sff_port_start, |
669a5db4 JG |
283 | }; |
284 | ||
285 | ||
286 | /** | |
287 | * efar_init_one - Register EFAR ATA PCI device with kernel services | |
288 | * @pdev: PCI device to register | |
289 | * @ent: Entry in efar_pci_tbl matching with @pdev | |
290 | * | |
291 | * Called from kernel PCI layer. | |
292 | * | |
293 | * LOCKING: | |
294 | * Inherited from PCI layer (may sleep). | |
295 | * | |
296 | * RETURNS: | |
297 | * Zero on success, or -ERRNO value. | |
298 | */ | |
299 | ||
300 | static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
301 | { | |
302 | static int printed_version; | |
1626aeb8 | 303 | static const struct ata_port_info info = { |
669a5db4 | 304 | .sht = &efar_sht, |
1d2808fd | 305 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
306 | .pio_mask = 0x1f, /* pio0-4 */ |
307 | .mwdma_mask = 0x07, /* mwdma1-2 */ | |
308 | .udma_mask = 0x0f, /* UDMA 66 */ | |
309 | .port_ops = &efar_ops, | |
310 | }; | |
1626aeb8 | 311 | const struct ata_port_info *ppi[] = { &info, NULL }; |
669a5db4 JG |
312 | |
313 | if (!printed_version++) | |
314 | dev_printk(KERN_DEBUG, &pdev->dev, | |
315 | "version " DRV_VERSION "\n"); | |
316 | ||
1626aeb8 | 317 | return ata_pci_init_one(pdev, ppi); |
669a5db4 JG |
318 | } |
319 | ||
320 | static const struct pci_device_id efar_pci_tbl[] = { | |
2d2744fc JG |
321 | { PCI_VDEVICE(EFAR, 0x9130), }, |
322 | ||
669a5db4 JG |
323 | { } /* terminate list */ |
324 | }; | |
325 | ||
326 | static struct pci_driver efar_pci_driver = { | |
327 | .name = DRV_NAME, | |
328 | .id_table = efar_pci_tbl, | |
329 | .probe = efar_init_one, | |
330 | .remove = ata_pci_remove_one, | |
438ac6d5 | 331 | #ifdef CONFIG_PM |
30ced0f0 AC |
332 | .suspend = ata_pci_device_suspend, |
333 | .resume = ata_pci_device_resume, | |
438ac6d5 | 334 | #endif |
669a5db4 JG |
335 | }; |
336 | ||
337 | static int __init efar_init(void) | |
338 | { | |
339 | return pci_register_driver(&efar_pci_driver); | |
340 | } | |
341 | ||
342 | static void __exit efar_exit(void) | |
343 | { | |
344 | pci_unregister_driver(&efar_pci_driver); | |
345 | } | |
346 | ||
669a5db4 JG |
347 | module_init(efar_init); |
348 | module_exit(efar_exit); | |
349 | ||
350 | MODULE_AUTHOR("Alan Cox"); | |
351 | MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones"); | |
352 | MODULE_LICENSE("GPL"); | |
353 | MODULE_DEVICE_TABLE(pci, efar_pci_tbl); | |
354 | MODULE_VERSION(DRV_VERSION); | |
355 |