[mirror_ubuntu-bionic-kernel.git] / drivers / ata / pata_hpt366.c

/*
 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
 *
 * This driver is heavily based upon:
 *
 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
 *
 *
 * TODO
 *	Maybe PLL mode
 *	Look into engine reset on timeout errors. Should not be
 *		required.
 */


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt366"
#define DRV_VERSION	"0.6.2"

struct hpt_clock {
	u8	xfer_mode;
	u32	timing;
};

/* key for bus clock timings
 * bit
 * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
 *        DMA. cycles = value + 1
 * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
 *        DMA. cycles = value + 1
 * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
 *        register access.
 * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
 *        register access.
 * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
 *        during task file register access.
 * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
 *        xfer.
 * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
 *        register access.
 * 28     UDMA enable
 * 29     DMA enable
 * 30     PIO_MST enable. if set, the chip is in bus master mode during
 *        PIO.
 * 31     FIFO enable.
 */

static const struct hpt_clock hpt366_40[] = {
	{	XFER_UDMA_4,	0x900fd943	},
	{	XFER_UDMA_3,	0x900ad943	},
	{	XFER_UDMA_2,	0x900bd943	},
	{	XFER_UDMA_1,	0x9008d943	},
	{	XFER_UDMA_0,	0x9008d943	},

	{	XFER_MW_DMA_2,	0xa008d943	},
	{	XFER_MW_DMA_1,	0xa010d955	},
	{	XFER_MW_DMA_0,	0xa010d9fc	},

	{	XFER_PIO_4,	0xc008d963	},
	{	XFER_PIO_3,	0xc010d974	},
	{	XFER_PIO_2,	0xc010d997	},
	{	XFER_PIO_1,	0xc010d9c7	},
	{	XFER_PIO_0,	0xc018d9d9	},
	{	0,		0x0120d9d9	}
};

static const struct hpt_clock hpt366_33[] = {
	{	XFER_UDMA_4,	0x90c9a731	},
	{	XFER_UDMA_3,	0x90cfa731	},
	{	XFER_UDMA_2,	0x90caa731	},
	{	XFER_UDMA_1,	0x90cba731	},
	{	XFER_UDMA_0,	0x90c8a731	},

	{	XFER_MW_DMA_2,	0xa0c8a731	},
	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
	{	XFER_MW_DMA_0,	0xa0c8a797	},

	{	XFER_PIO_4,	0xc0c8a731	},
	{	XFER_PIO_3,	0xc0c8a742	},
	{	XFER_PIO_2,	0xc0d0a753	},
	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
	{	0,		0x0120a7a7	}
};

static const struct hpt_clock hpt366_25[] = {
	{	XFER_UDMA_4,	0x90c98521	},
	{	XFER_UDMA_3,	0x90cf8521	},
	{	XFER_UDMA_2,	0x90cf8521	},
	{	XFER_UDMA_1,	0x90cb8521	},
	{	XFER_UDMA_0,	0x90cb8521	},

	{	XFER_MW_DMA_2,	0xa0ca8521	},
	{	XFER_MW_DMA_1,	0xa0ca8532	},
	{	XFER_MW_DMA_0,	0xa0ca8575	},

	{	XFER_PIO_4,	0xc0ca8521	},
	{	XFER_PIO_3,	0xc0ca8532	},
	{	XFER_PIO_2,	0xc0ca8542	},
	{	XFER_PIO_1,	0xc0d08572	},
	{	XFER_PIO_0,	0xc0d08585	},
	{	0,		0x01208585	}
};

static const char *bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

static const char *bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char *bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
{
	unsigned char model_num[ATA_ID_PROD_LEN + 1];
	int i = 0;

	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	while (list[i] != NULL) {
		if (!strcmp(list[i], model_num)) {
			printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
				modestr, list[i]);
			return 1;
		}
		i++;
	}
	return 0;
}

/**
 *	hpt366_filter	-	mode selection filter
 *	@adev: ATA device
 *
 *	Block UDMA on devices that cause trouble with this controller.
 */

static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA) {
		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
			mask &= ~ATA_MASK_UDMA;
		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
	} else if (adev->class == ATA_DEV_ATAPI)
		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);

	return ata_bmdma_mode_filter(adev, mask);
}

static int hpt36x_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 ata66;

	/*
	 * Each channel of pata_hpt366 occupies separate PCI function
	 * as the primary channel and bit1 indicates the cable type.
	 */
	pci_read_config_byte(pdev, 0x5A, &ata66);
	if (ata66 & 2)
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
			    u8 mode)
{
	struct hpt_clock *clocks = ap->host->private_data;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
	u32 addr2 = 0x51 + 4 * ap->port_no;
	u32 mask, reg;
	u8 fast;

	/* Fast interrupt prediction disable, hold off interrupt disable */
	pci_read_config_byte(pdev, addr2, &fast);
	if (fast & 0x80) {
		fast &= ~0x80;
		pci_write_config_byte(pdev, addr2, fast);
	}

	/* determine timing mask and find matching clock entry */
	if (mode < XFER_MW_DMA_0)
		mask = 0xc1f8ffff;
	else if (mode < XFER_UDMA_0)
		mask = 0x303800ff;
	else
		mask = 0x30070000;

	while (clocks->xfer_mode) {
		if (clocks->xfer_mode == mode)
			break;
		clocks++;
	}
	if (!clocks->xfer_mode)
		BUG();

	/*
	 * Combine new mode bits with old config bits and disable
	 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	 * problems handling I/O errors later.
	 */
	pci_read_config_dword(pdev, addr1, &reg);
	reg = ((reg & ~mask) | (clocks->timing & mask)) & ~0xc0000000;
	pci_write_config_dword(pdev, addr1, reg);
}

/**
 *	hpt366_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Perform PIO mode setup.
 */

static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->pio_mode);
}

/**
 *	hpt366_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 */

static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->dma_mode);
}

static struct scsi_host_template hpt36x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

/*
 *	Configuration for HPT366/68
 */

static struct ata_port_operations hpt366_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= hpt36x_cable_detect,
	.mode_filter	= hpt366_filter,
	.set_piomode	= hpt366_set_piomode,
	.set_dmamode	= hpt366_set_dmamode,
};

/**
 *	hpt36x_init_chipset	-	common chip setup
 *	@dev: PCI device
 *
 *	Perform the chip setup work that must be done at both init and
 *	resume time
 */

static void hpt36x_init_chipset(struct pci_dev *dev)
{
	u8 drive_fast;
	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);

	pci_read_config_byte(dev, 0x51, &drive_fast);
	if (drive_fast & 0x80)
		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
}

/**
 *	hpt36x_init_one		-	Initialise an HPT366/368
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Initialise an HPT36x device. There are some interesting complications
 *	here. Firstly the chip may report 366 and be one of several variants.
 *	Secondly all the timings depend on the clock for the chip which we must
 *	detect and look up
 *
 *	This is the known chip mappings. It may be missing a couple of later
 *	releases.
 *
 *	Chip version		PCI		Rev	Notes
 *	HPT366			4 (HPT366)	0	UDMA66
 *	HPT366			4 (HPT366)	1	UDMA66
 *	HPT368			4 (HPT366)	2	UDMA66
 *	HPT37x/30x		4 (HPT366)	3+	Other driver
 *
 */

static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_hpt366 = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA4,
		.port_ops = &hpt366_port_ops
	};
	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };

	void *hpriv = NULL;
	u32 class_rev;
	u32 reg1;
	int rc;

	rc = pcim_enable_device(dev);
	if (rc)
		return rc;

	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
	class_rev &= 0xFF;

	/* May be a later chip in disguise. Check */
	/* Newer chips are not in the HPT36x driver. Ignore them */
	if (class_rev > 2)
			return -ENODEV;

	hpt36x_init_chipset(dev);

	pci_read_config_dword(dev, 0x40,  &reg1);

	/* PCI clocking determines the ATA timing values to use */
	/* info_hpt366 is safe against re-entry so we can scribble on it */
	switch((reg1 & 0x700) >> 8) {
		case 9:
			hpriv = &hpt366_40;
			break;
		case 5:
			hpriv = &hpt366_25;
			break;
		default:
			hpriv = &hpt366_33;
			break;
	}
	/* Now kick off ATA set up */
	return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
}

#ifdef CONFIG_PM
static int hpt36x_reinit_one(struct pci_dev *dev)
{
	struct ata_host *host = dev_get_drvdata(&dev->dev);
	int rc;

	rc = ata_pci_device_do_resume(dev);
	if (rc)
		return rc;
	hpt36x_init_chipset(dev);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id hpt36x[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
	{ },
};

static struct pci_driver hpt36x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= hpt36x,
	.probe 		= hpt36x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= hpt36x_reinit_one,
#endif
};

static int __init hpt36x_init(void)
{
	return pci_register_driver(&hpt36x_pci_driver);
}

static void __exit hpt36x_exit(void)
{
	pci_unregister_driver(&hpt36x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt36x);
MODULE_VERSION(DRV_VERSION);

module_init(hpt36x_init);
module_exit(hpt36x_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
	3	*
	4	* This driver is heavily based upon:
	5	*
	6	* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
	7	*
	8	* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
	9	* Portions Copyright (C) 2001 Sun Microsystems, Inc.
	10	* Portions Copyright (C) 2003 Red Hat Inc
	11	*
	12	*
	13	* TODO
	14	* Maybe PLL mode
	15	* Look into engine reset on timeout errors. Should not be
	16	* required.
	17	*/
	18
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/pci.h>
	23	#include <linux/init.h>
	24	#include <linux/blkdev.h>
	25	#include <linux/delay.h>
	26	#include <scsi/scsi_host.h>
	27	#include <linux/libata.h>
	28
	29	#define DRV_NAME "pata_hpt366"
6ddd6861	30	#define DRV_VERSION "0.6.2"
669a5db4 JG	31
669a5db4 JG	32	struct hpt_clock {
6ecb6f25	33	u8 xfer_mode;
669a5db4 JG	34	u32 timing;
	35	};
	36
	37	/* key for bus clock timings
	38	* bit
	39	* 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
	40	* DMA. cycles = value + 1
	41	* 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
	42	* DMA. cycles = value + 1
	43	* 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
	44	* register access.
	45	* 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
	46	* register access.
	47	* 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
	48	* during task file register access.
	49	* 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
	50	* xfer.
	51	* 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
	52	* register access.
	53	* 28 UDMA enable
	54	* 29 DMA enable
	55	* 30 PIO_MST enable. if set, the chip is in bus master mode during
	56	* PIO.
	57	* 31 FIFO enable.
	58	*/
	59
	60	static const struct hpt_clock hpt366_40[] = {
	61	{ XFER_UDMA_4, 0x900fd943 },
	62	{ XFER_UDMA_3, 0x900ad943 },
	63	{ XFER_UDMA_2, 0x900bd943 },
	64	{ XFER_UDMA_1, 0x9008d943 },
	65	{ XFER_UDMA_0, 0x9008d943 },
	66
	67	{ XFER_MW_DMA_2, 0xa008d943 },
	68	{ XFER_MW_DMA_1, 0xa010d955 },
	69	{ XFER_MW_DMA_0, 0xa010d9fc },
	70
	71	{ XFER_PIO_4, 0xc008d963 },
	72	{ XFER_PIO_3, 0xc010d974 },
	73	{ XFER_PIO_2, 0xc010d997 },
	74	{ XFER_PIO_1, 0xc010d9c7 },
	75	{ XFER_PIO_0, 0xc018d9d9 },
	76	{ 0, 0x0120d9d9 }
	77	};
	78
	79	static const struct hpt_clock hpt366_33[] = {
	80	{ XFER_UDMA_4, 0x90c9a731 },
	81	{ XFER_UDMA_3, 0x90cfa731 },
	82	{ XFER_UDMA_2, 0x90caa731 },
	83	{ XFER_UDMA_1, 0x90cba731 },
	84	{ XFER_UDMA_0, 0x90c8a731 },
	85
	86	{ XFER_MW_DMA_2, 0xa0c8a731 },
	87	{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
	88	{ XFER_MW_DMA_0, 0xa0c8a797 },
	89
	90	{ XFER_PIO_4, 0xc0c8a731 },
	91	{ XFER_PIO_3, 0xc0c8a742 },
	92	{ XFER_PIO_2, 0xc0d0a753 },
	93	{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
	94	{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
	95	{ 0, 0x0120a7a7 }
	96	};
	97
98	static const struct hpt_clock hpt366_25[] = {
99	{ XFER_UDMA_4, 0x90c98521 },
100	{ XFER_UDMA_3, 0x90cf8521 },
101	{ XFER_UDMA_2, 0x90cf8521 },
102	{ XFER_UDMA_1, 0x90cb8521 },
103	{ XFER_UDMA_0, 0x90cb8521 },
104
105	{ XFER_MW_DMA_2, 0xa0ca8521 },
106	{ XFER_MW_DMA_1, 0xa0ca8532 },
107	{ XFER_MW_DMA_0, 0xa0ca8575 },
108
109	{ XFER_PIO_4, 0xc0ca8521 },
110	{ XFER_PIO_3, 0xc0ca8532 },
111	{ XFER_PIO_2, 0xc0ca8542 },
112	{ XFER_PIO_1, 0xc0d08572 },
113	{ XFER_PIO_0, 0xc0d08585 },
114	{ 0, 0x01208585 }
115	};
116
117	static const char *bad_ata33[] = {
118	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121	"Maxtor 90510D4",
122	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125	NULL
126	};
127
128	static const char *bad_ata66_4[] = {
129	"IBM-DTLA-307075",
130	"IBM-DTLA-307060",
131	"IBM-DTLA-307045",
132	"IBM-DTLA-307030",
133	"IBM-DTLA-307020",
134	"IBM-DTLA-307015",
135	"IBM-DTLA-305040",
136	"IBM-DTLA-305030",
137	"IBM-DTLA-305020",
138	"IC35L010AVER07-0",
139	"IC35L020AVER07-0",
140	"IC35L030AVER07-0",
141	"IC35L040AVER07-0",
142	"IC35L060AVER07-0",
143	"WDC AC310200R",
144	NULL
145	};
146
147	static const char *bad_ata66_3[] = {
148	"WDC AC310200R",
149	NULL
150	};
151
152	static int hpt_dma_blacklisted(const struct ata_device dev, char modestr, const char *list[])
153	{
8bfa79fc	154	unsigned char model_num[ATA_ID_PROD_LEN + 1];
669a5db4 JG	155	int i = 0;
669a5db4 JG	156
8bfa79fc	157	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
669a5db4	158
8bfa79fc TH	159	while (list[i] != NULL) {
8bfa79fc TH	160	if (!strcmp(list[i], model_num)) {
85cd7251	161	printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
669a5db4 JG	162	modestr, list[i]);
	163	return 1;
	164	}
	165	i++;
	166	}
	167	return 0;
	168	}
	169
	170	/**
	171	* hpt366_filter - mode selection filter
669a5db4 JG	172	* @adev: ATA device
	173	*
	174	* Block UDMA on devices that cause trouble with this controller.
	175	*/
85cd7251	176
a76b62ca	177	static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	178	{
	179	if (adev->class == ATA_DEV_ATA) {
	180	if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
	181	mask &= ~ATA_MASK_UDMA;
	182	if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
6ddd6861	183	mask &= ~(0xF8 << ATA_SHIFT_UDMA);
669a5db4	184	if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
6ddd6861	185	mask &= ~(0xF0 << ATA_SHIFT_UDMA);
3ee89f17 TH	186	} else if (adev->class == ATA_DEV_ATAPI)
	187	mask &= ~(ATA_MASK_MWDMA \| ATA_MASK_UDMA);
	188
9363c382	189	return ata_bmdma_mode_filter(adev, mask);
669a5db4 JG	190	}
669a5db4 JG	191
fecfda5d AC	192	static int hpt36x_cable_detect(struct ata_port *ap)
fecfda5d AC	193	{
fecfda5d	194	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
bab5b32a	195	u8 ata66;
fecfda5d	196
bab5b32a TH	197	/*
	198	* Each channel of pata_hpt366 occupies separate PCI function
	199	* as the primary channel and bit1 indicates the cable type.
	200	*/
fecfda5d	201	pci_read_config_byte(pdev, 0x5A, &ata66);
bab5b32a	202	if (ata66 & 2)
fecfda5d AC	203	return ATA_CBL_PATA40;
	204	return ATA_CBL_PATA80;
	205	}
	206
6ecb6f25 TH	207	static void hpt366_set_mode(struct ata_port ap, struct ata_device adev,
6ecb6f25 TH	208	u8 mode)
669a5db4	209	{
6ecb6f25	210	struct hpt_clock *clocks = ap->host->private_data;
669a5db4	211	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
6ecb6f25 TH	212	u32 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
	213	u32 addr2 = 0x51 + 4 * ap->port_no;
	214	u32 mask, reg;
669a5db4 JG	215	u8 fast;
669a5db4 JG	216
669a5db4 JG	217	/* Fast interrupt prediction disable, hold off interrupt disable */
	218	pci_read_config_byte(pdev, addr2, &fast);
	219	if (fast & 0x80) {
	220	fast &= ~0x80;
	221	pci_write_config_byte(pdev, addr2, fast);
	222	}
85cd7251	223
6ecb6f25 TH	224	/* determine timing mask and find matching clock entry */
	225	if (mode < XFER_MW_DMA_0)
	226	mask = 0xc1f8ffff;
	227	else if (mode < XFER_UDMA_0)
	228	mask = 0x303800ff;
	229	else
	230	mask = 0x30070000;
	231
	232	while (clocks->xfer_mode) {
	233	if (clocks->xfer_mode == mode)
	234	break;
	235	clocks++;
	236	}
	237	if (!clocks->xfer_mode)
	238	BUG();
	239
	240	/*
	241	* Combine new mode bits with old config bits and disable
	242	* on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	243	* problems handling I/O errors later.
	244	*/
669a5db4	245	pci_read_config_dword(pdev, addr1, &reg);
6ecb6f25 TH	246	reg = ((reg & ~mask) \| (clocks->timing & mask)) & ~0xc0000000;
	247	pci_write_config_dword(pdev, addr1, reg);
	248	}
	249
	250	/**
	251	* hpt366_set_piomode - PIO setup
	252	* @ap: ATA interface
	253	* @adev: device on the interface
	254	*
	255	* Perform PIO mode setup.
	256	*/
	257
	258	static void hpt366_set_piomode(struct ata_port ap, struct ata_device adev)
	259	{
	260	hpt366_set_mode(ap, adev, adev->pio_mode);
669a5db4 JG	261	}
	262
	263	/**
	264	* hpt366_set_dmamode - DMA timing setup
	265	* @ap: ATA interface
	266	* @adev: Device being configured
	267	*
	268	* Set up the channel for MWDMA or UDMA modes. Much the same as with
	269	* PIO, load the mode number and then set MWDMA or UDMA flag.
	270	*/
85cd7251	271
669a5db4 JG	272	static void hpt366_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	273	{
6ecb6f25	274	hpt366_set_mode(ap, adev, adev->dma_mode);
669a5db4 JG	275	}
	276
	277	static struct scsi_host_template hpt36x_sht = {
68d1d07b	278	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	279	};
	280
	281	/*
	282	* Configuration for HPT366/68
	283	*/
85cd7251	284
669a5db4	285	static struct ata_port_operations hpt366_port_ops = {
029cfd6b TH	286	.inherits = &ata_bmdma_port_ops,
	287	.cable_detect = hpt36x_cable_detect,
	288	.mode_filter = hpt366_filter,
669a5db4 JG	289	.set_piomode = hpt366_set_piomode,
669a5db4 JG	290	.set_dmamode = hpt366_set_dmamode,
85cd7251	291	};
669a5db4	292
aa54ab1e AC	293	/**
	294	* hpt36x_init_chipset - common chip setup
	295	* @dev: PCI device
	296	*
	297	* Perform the chip setup work that must be done at both init and
	298	* resume time
	299	*/
	300
	301	static void hpt36x_init_chipset(struct pci_dev *dev)
	302	{
	303	u8 drive_fast;
	304	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	305	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	306	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	307	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
	308
	309	pci_read_config_byte(dev, 0x51, &drive_fast);
	310	if (drive_fast & 0x80)
	311	pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
	312	}
	313
669a5db4 JG	314	/**
	315	* hpt36x_init_one - Initialise an HPT366/368
	316	* @dev: PCI device
	317	* @id: Entry in match table
	318	*
	319	* Initialise an HPT36x device. There are some interesting complications
	320	* here. Firstly the chip may report 366 and be one of several variants.
	321	* Secondly all the timings depend on the clock for the chip which we must
	322	* detect and look up
	323	*
	324	* This is the known chip mappings. It may be missing a couple of later
	325	* releases.
	326	*
	327	* Chip version PCI Rev Notes
	328	* HPT366 4 (HPT366) 0 UDMA66
	329	* HPT366 4 (HPT366) 1 UDMA66
	330	* HPT368 4 (HPT366) 2 UDMA66
	331	* HPT37x/30x 4 (HPT366) 3+ Other driver
	332	*
	333	*/
85cd7251	334
669a5db4 JG	335	static int hpt36x_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	336	{
1626aeb8	337	static const struct ata_port_info info_hpt366 = {
1d2808fd	338	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	339	.pio_mask = ATA_PIO4,
14bdef98 EIB	340	.mwdma_mask = ATA_MWDMA2,
bf6263a8	341	.udma_mask = ATA_UDMA4,
669a5db4 JG	342	.port_ops = &hpt366_port_ops
669a5db4 JG	343	};
887125e3	344	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
669a5db4	345
887125e3	346	void *hpriv = NULL;
669a5db4 JG	347	u32 class_rev;
669a5db4 JG	348	u32 reg1;
f08048e9 TH	349	int rc;
	350
	351	rc = pcim_enable_device(dev);
	352	if (rc)
	353	return rc;
669a5db4 JG	354
	355	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
	356	class_rev &= 0xFF;
85cd7251	357
669a5db4 JG	358	/* May be a later chip in disguise. Check */
	359	/* Newer chips are not in the HPT36x driver. Ignore them */
	360	if (class_rev > 2)
	361	return -ENODEV;
	362
aa54ab1e	363	hpt36x_init_chipset(dev);
669a5db4 JG	364
669a5db4 JG	365	pci_read_config_dword(dev, 0x40, &reg1);
85cd7251	366
669a5db4 JG	367	/* PCI clocking determines the ATA timing values to use */
669a5db4 JG	368	/* info_hpt366 is safe against re-entry so we can scribble on it */
2c136efc	369	switch((reg1 & 0x700) >> 8) {
2456eb81	370	case 9:
887125e3	371	hpriv = &hpt366_40;
669a5db4	372	break;
2456eb81	373	case 5:
887125e3	374	hpriv = &hpt366_25;
669a5db4 JG	375	break;
669a5db4 JG	376	default:
887125e3	377	hpriv = &hpt366_33;
669a5db4 JG	378	break;
	379	}
	380	/* Now kick off ATA set up */
9363c382	381	return ata_pci_sff_init_one(dev, ppi, &hpt36x_sht, hpriv);
669a5db4 JG	382	}
669a5db4 JG	383
438ac6d5	384	#ifdef CONFIG_PM
aa54ab1e AC	385	static int hpt36x_reinit_one(struct pci_dev *dev)
aa54ab1e AC	386	{
f08048e9 TH	387	struct ata_host *host = dev_get_drvdata(&dev->dev);
	388	int rc;
	389
	390	rc = ata_pci_device_do_resume(dev);
	391	if (rc)
	392	return rc;
aa54ab1e	393	hpt36x_init_chipset(dev);
f08048e9 TH	394	ata_host_resume(host);
f08048e9 TH	395	return 0;
aa54ab1e	396	}
438ac6d5	397	#endif
aa54ab1e	398
2d2744fc JG	399	static const struct pci_device_id hpt36x[] = {
2d2744fc JG	400	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
2d2744fc	401	{ },
669a5db4 JG	402	};
	403
	404	static struct pci_driver hpt36x_pci_driver = {
2d2744fc	405	.name = DRV_NAME,
669a5db4 JG	406	.id_table = hpt36x,
669a5db4 JG	407	.probe = hpt36x_init_one,
aa54ab1e	408	.remove = ata_pci_remove_one,
438ac6d5	409	#ifdef CONFIG_PM
aa54ab1e AC	410	.suspend = ata_pci_device_suspend,
aa54ab1e AC	411	.resume = hpt36x_reinit_one,
438ac6d5	412	#endif
669a5db4 JG	413	};
	414
	415	static int __init hpt36x_init(void)
	416	{
	417	return pci_register_driver(&hpt36x_pci_driver);
	418	}
	419
669a5db4 JG	420	static void __exit hpt36x_exit(void)
	421	{
	422	pci_unregister_driver(&hpt36x_pci_driver);
	423	}
	424
669a5db4 JG	425	MODULE_AUTHOR("Alan Cox");
	426	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
	427	MODULE_LICENSE("GPL");
	428	MODULE_DEVICE_TABLE(pci, hpt36x);
	429	MODULE_VERSION(DRV_VERSION);
	430
	431	module_init(hpt36x_init);
	432	module_exit(hpt36x_exit);