[mirror_ubuntu-bionic-kernel.git] / drivers / ata / pata_hpt366.c

/*
 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
 *
 * This driver is heavily based upon:
 *
 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
 *
 *
 * TODO
 *	Maybe PLL mode
 *	Look into engine reset on timeout errors. Should not be
 *		required.
 */


#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt366"
#define DRV_VERSION	"0.5"

struct hpt_clock {
	u8	xfer_speed;
	u32	timing;
};

/* key for bus clock timings
 * bit
 * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
 *        DMA. cycles = value + 1
 * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
 *        DMA. cycles = value + 1
 * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
 *        register access.
 * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
 *        register access.
 * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
 *        during task file register access.
 * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
 *        xfer.
 * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
 *        register access.
 * 28     UDMA enable
 * 29     DMA enable
 * 30     PIO_MST enable. if set, the chip is in bus master mode during
 *        PIO.
 * 31     FIFO enable.
 */

static const struct hpt_clock hpt366_40[] = {
	{	XFER_UDMA_4,	0x900fd943	},
	{	XFER_UDMA_3,	0x900ad943	},
	{	XFER_UDMA_2,	0x900bd943	},
	{	XFER_UDMA_1,	0x9008d943	},
	{	XFER_UDMA_0,	0x9008d943	},

	{	XFER_MW_DMA_2,	0xa008d943	},
	{	XFER_MW_DMA_1,	0xa010d955	},
	{	XFER_MW_DMA_0,	0xa010d9fc	},

	{	XFER_PIO_4,	0xc008d963	},
	{	XFER_PIO_3,	0xc010d974	},
	{	XFER_PIO_2,	0xc010d997	},
	{	XFER_PIO_1,	0xc010d9c7	},
	{	XFER_PIO_0,	0xc018d9d9	},
	{	0,		0x0120d9d9	}
};

static const struct hpt_clock hpt366_33[] = {
	{	XFER_UDMA_4,	0x90c9a731	},
	{	XFER_UDMA_3,	0x90cfa731	},
	{	XFER_UDMA_2,	0x90caa731	},
	{	XFER_UDMA_1,	0x90cba731	},
	{	XFER_UDMA_0,	0x90c8a731	},

	{	XFER_MW_DMA_2,	0xa0c8a731	},
	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
	{	XFER_MW_DMA_0,	0xa0c8a797	},

	{	XFER_PIO_4,	0xc0c8a731	},
	{	XFER_PIO_3,	0xc0c8a742	},
	{	XFER_PIO_2,	0xc0d0a753	},
	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
	{	0,		0x0120a7a7	}
};

static const struct hpt_clock hpt366_25[] = {
	{	XFER_UDMA_4,	0x90c98521	},
	{	XFER_UDMA_3,	0x90cf8521	},
	{	XFER_UDMA_2,	0x90cf8521	},
	{	XFER_UDMA_1,	0x90cb8521	},
	{	XFER_UDMA_0,	0x90cb8521	},

	{	XFER_MW_DMA_2,	0xa0ca8521	},
	{	XFER_MW_DMA_1,	0xa0ca8532	},
	{	XFER_MW_DMA_0,	0xa0ca8575	},

	{	XFER_PIO_4,	0xc0ca8521	},
	{	XFER_PIO_3,	0xc0ca8532	},
	{	XFER_PIO_2,	0xc0ca8542	},
	{	XFER_PIO_1,	0xc0d08572	},
	{	XFER_PIO_0,	0xc0d08585	},
	{	0,		0x01208585	}
};

static const char *bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

static const char *bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char *bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
{
	unsigned char model_num[40];
	char *s;
	unsigned int len;
	int i = 0;

	ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
	s = &model_num[0];
	len = strnlen(s, sizeof(model_num));

	/* ATAPI specifies that empty space is blank-filled; remove blanks */
	while ((len > 0) && (s[len - 1] == ' ')) {
		len--;
		s[len] = 0;
	}

	while(list[i] != NULL) {
		if (!strncmp(list[i], s, len)) {
			printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n", 
				modestr, list[i]);
			return 1;
		}
		i++;
	}
	return 0;
}

/**
 *	hpt366_filter	-	mode selection filter
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Block UDMA on devices that cause trouble with this controller.
 */
 
static unsigned long hpt366_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA) {
		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
			mask &= ~ATA_MASK_UDMA;
		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
			mask &= ~(0x07 << ATA_SHIFT_UDMA);
		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
			mask &= ~(0x0F << ATA_SHIFT_UDMA);
	}
	return ata_pci_default_filter(ap, adev, mask);
}

/**
 *	hpt36x_find_mode	-	reset the hpt36x bus
 *	@ap: ATA port
 *	@speed: transfer mode
 *
 *	Return the 32bit register programming information for this channel
 *	that matches the speed provided.
 */
 
static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
{
	struct hpt_clock *clocks = ap->host->private_data;
	
	while(clocks->xfer_speed) {
		if (clocks->xfer_speed == speed)
			return clocks->timing;
		clocks++;
	}
	BUG();
	return 0xffffffffU;	/* silence compiler warning */
}
	
static int hpt36x_pre_reset(struct ata_port *ap)
{
	u8 ata66;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	
	pci_read_config_byte(pdev, 0x5A, &ata66);
	if (ata66 & (1 << ap->port_no))
		ap->cbl = ATA_CBL_PATA40;
	else
		ap->cbl = ATA_CBL_PATA80;
	return ata_std_prereset(ap);
}

/**
 *	hpt36x_error_handler	-	reset the hpt36x bus
 *	@ap: ATA port to reset
 *
 *	Perform the reset handling for the 366/368
 */
 
static void hpt36x_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
}

/**
 *	hpt366_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Perform PIO mode setup. 
 */
 
static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 addr1, addr2;
	u32 reg;
	u32 mode;
	u8 fast;

	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
	addr2 = 0x51 + 4 * ap->port_no;
	
	/* Fast interrupt prediction disable, hold off interrupt disable */
	pci_read_config_byte(pdev, addr2, &fast);
	if (fast & 0x80) {
		fast &= ~0x80;
		pci_write_config_byte(pdev, addr2, fast);
	}
	
	pci_read_config_dword(pdev, addr1, &reg);
	mode = hpt36x_find_mode(ap, adev->pio_mode);
	mode &= ~0x8000000;	/* No FIFO in PIO */
	mode &= ~0x30070000;	/* Leave config bits alone */
	reg &= 0x30070000;	/* Strip timing bits */
	pci_write_config_dword(pdev, addr1, reg | mode);
}

/**
 *	hpt366_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 */
 
static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 addr1, addr2;
	u32 reg;
	u32 mode;
	u8 fast;

	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
	addr2 = 0x51 + 4 * ap->port_no;
	
	/* Fast interrupt prediction disable, hold off interrupt disable */
	pci_read_config_byte(pdev, addr2, &fast);
	if (fast & 0x80) {
		fast &= ~0x80;
		pci_write_config_byte(pdev, addr2, fast);
	}
	
	pci_read_config_dword(pdev, addr1, &reg);
	mode = hpt36x_find_mode(ap, adev->dma_mode);
	mode |= 0x8000000;	/* FIFO in MWDMA or UDMA */
	mode &= ~0xC0000000;	/* Leave config bits alone */
	reg &= 0xC0000000;	/* Strip timing bits */
	pci_write_config_dword(pdev, addr1, reg | mode);
}

static struct scsi_host_template hpt36x_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
};

/*
 *	Configuration for HPT366/68
 */
 
static struct ata_port_operations hpt366_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= hpt366_set_piomode,
	.set_dmamode	= hpt366_set_dmamode,
	.mode_filter	= hpt366_filter,
	
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= hpt36x_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,
	.eng_timeout	= ata_eng_timeout,
	.data_xfer	= ata_pio_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,

	.port_start	= ata_port_start,
	.port_stop	= ata_port_stop,
	.host_stop	= ata_host_stop
};	

/**
 *	hpt36x_init_one		-	Initialise an HPT366/368
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Initialise an HPT36x device. There are some interesting complications
 *	here. Firstly the chip may report 366 and be one of several variants.
 *	Secondly all the timings depend on the clock for the chip which we must
 *	detect and look up
 *
 *	This is the known chip mappings. It may be missing a couple of later
 *	releases.
 *
 *	Chip version		PCI		Rev	Notes
 *	HPT366			4 (HPT366)	0	UDMA66
 *	HPT366			4 (HPT366)	1	UDMA66
 *	HPT368			4 (HPT366)	2	UDMA66
 *	HPT37x/30x		4 (HPT366)	3+	Other driver
 *
 */
 
static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static struct ata_port_info info_hpt366 = {
		.sht = &hpt36x_sht,
		.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask = 0x1f,
		.mwdma_mask = 0x07,
		.udma_mask = 0x1f,
		.port_ops = &hpt366_port_ops
	};
	struct ata_port_info *port_info[2] = {&info_hpt366, &info_hpt366};

	u32 class_rev;
	u32 reg1;
	u8 drive_fast;

	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
	class_rev &= 0xFF;
	
	/* May be a later chip in disguise. Check */
	/* Newer chips are not in the HPT36x driver. Ignore them */
	if (class_rev > 2)
			return -ENODEV;

	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);

	pci_read_config_byte(dev, 0x51, &drive_fast);
	if (drive_fast & 0x80)
		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);

	pci_read_config_dword(dev, 0x40,  &reg1);
	
	/* PCI clocking determines the ATA timing values to use */
	/* info_hpt366 is safe against re-entry so we can scribble on it */
	switch(reg1 & 0x700) {
		case 5:
			info_hpt366.private_data = &hpt366_40;
			break;
		case 9:
			info_hpt366.private_data = &hpt366_25;
			break;
		default:
			info_hpt366.private_data = &hpt366_33;
			break;
	}
	/* Now kick off ATA set up */
	return ata_pci_init_one(dev, port_info, 2);
}

static struct pci_device_id hpt36x[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366), },
	{ 0, },
};

static struct pci_driver hpt36x_pci_driver = {
        .name 		= DRV_NAME,
	.id_table	= hpt36x,
	.probe 		= hpt36x_init_one,
	.remove		= ata_pci_remove_one
};

static int __init hpt36x_init(void)
{
	return pci_register_driver(&hpt36x_pci_driver);
}


static void __exit hpt36x_exit(void)
{
	pci_unregister_driver(&hpt36x_pci_driver);
}


MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt36x);
MODULE_VERSION(DRV_VERSION);

module_init(hpt36x_init);
module_exit(hpt36x_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
	3	*
	4	* This driver is heavily based upon:
	5	*
	6	* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
	7	*
	8	* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
	9	* Portions Copyright (C) 2001 Sun Microsystems, Inc.
	10	* Portions Copyright (C) 2003 Red Hat Inc
	11	*
	12	*
	13	* TODO
	14	* Maybe PLL mode
	15	* Look into engine reset on timeout errors. Should not be
	16	* required.
	17	*/
	18
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/pci.h>
	23	#include <linux/init.h>
	24	#include <linux/blkdev.h>
	25	#include <linux/delay.h>
	26	#include <scsi/scsi_host.h>
	27	#include <linux/libata.h>
	28
	29	#define DRV_NAME "pata_hpt366"
	30	#define DRV_VERSION "0.5"
	31
	32	struct hpt_clock {
	33	u8 xfer_speed;
	34	u32 timing;
	35	};
	36
	37	/* key for bus clock timings
	38	* bit
	39	* 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
	40	* DMA. cycles = value + 1
	41	* 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
	42	* DMA. cycles = value + 1
	43	* 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
	44	* register access.
	45	* 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
	46	* register access.
	47	* 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
	48	* during task file register access.
	49	* 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
	50	* xfer.
	51	* 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
	52	* register access.
	53	* 28 UDMA enable
	54	* 29 DMA enable
	55	* 30 PIO_MST enable. if set, the chip is in bus master mode during
	56	* PIO.
	57	* 31 FIFO enable.
	58	*/
	59
	60	static const struct hpt_clock hpt366_40[] = {
	61	{ XFER_UDMA_4, 0x900fd943 },
	62	{ XFER_UDMA_3, 0x900ad943 },
	63	{ XFER_UDMA_2, 0x900bd943 },
	64	{ XFER_UDMA_1, 0x9008d943 },
65	{ XFER_UDMA_0, 0x9008d943 },
66
67	{ XFER_MW_DMA_2, 0xa008d943 },
68	{ XFER_MW_DMA_1, 0xa010d955 },
69	{ XFER_MW_DMA_0, 0xa010d9fc },
70
71	{ XFER_PIO_4, 0xc008d963 },
72	{ XFER_PIO_3, 0xc010d974 },
73	{ XFER_PIO_2, 0xc010d997 },
74	{ XFER_PIO_1, 0xc010d9c7 },
75	{ XFER_PIO_0, 0xc018d9d9 },
76	{ 0, 0x0120d9d9 }
77	};
78
79	static const struct hpt_clock hpt366_33[] = {
80	{ XFER_UDMA_4, 0x90c9a731 },
81	{ XFER_UDMA_3, 0x90cfa731 },
82	{ XFER_UDMA_2, 0x90caa731 },
83	{ XFER_UDMA_1, 0x90cba731 },
84	{ XFER_UDMA_0, 0x90c8a731 },
85
86	{ XFER_MW_DMA_2, 0xa0c8a731 },
87	{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
88	{ XFER_MW_DMA_0, 0xa0c8a797 },
89
90	{ XFER_PIO_4, 0xc0c8a731 },
91	{ XFER_PIO_3, 0xc0c8a742 },
92	{ XFER_PIO_2, 0xc0d0a753 },
93	{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
94	{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
95	{ 0, 0x0120a7a7 }
96	};
97
98	static const struct hpt_clock hpt366_25[] = {
99	{ XFER_UDMA_4, 0x90c98521 },
100	{ XFER_UDMA_3, 0x90cf8521 },
101	{ XFER_UDMA_2, 0x90cf8521 },
102	{ XFER_UDMA_1, 0x90cb8521 },
103	{ XFER_UDMA_0, 0x90cb8521 },
104
105	{ XFER_MW_DMA_2, 0xa0ca8521 },
106	{ XFER_MW_DMA_1, 0xa0ca8532 },
107	{ XFER_MW_DMA_0, 0xa0ca8575 },
108
109	{ XFER_PIO_4, 0xc0ca8521 },
110	{ XFER_PIO_3, 0xc0ca8532 },
111	{ XFER_PIO_2, 0xc0ca8542 },
112	{ XFER_PIO_1, 0xc0d08572 },
113	{ XFER_PIO_0, 0xc0d08585 },
114	{ 0, 0x01208585 }
115	};
116
117	static const char *bad_ata33[] = {
118	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
119	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
120	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
121	"Maxtor 90510D4",
122	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
123	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
124	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
125	NULL
126	};
127
128	static const char *bad_ata66_4[] = {
129	"IBM-DTLA-307075",
130	"IBM-DTLA-307060",
131	"IBM-DTLA-307045",
132	"IBM-DTLA-307030",
133	"IBM-DTLA-307020",
134	"IBM-DTLA-307015",
135	"IBM-DTLA-305040",
136	"IBM-DTLA-305030",
137	"IBM-DTLA-305020",
138	"IC35L010AVER07-0",
139	"IC35L020AVER07-0",
140	"IC35L030AVER07-0",
141	"IC35L040AVER07-0",
142	"IC35L060AVER07-0",
143	"WDC AC310200R",
144	NULL
145	};
146
147	static const char *bad_ata66_3[] = {
148	"WDC AC310200R",
149	NULL
150	};
151
152	static int hpt_dma_blacklisted(const struct ata_device dev, char modestr, const char *list[])
153	{
154	unsigned char model_num[40];
155	char *s;
156	unsigned int len;
157	int i = 0;
158
159	ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
160	s = &model_num[0];
161	len = strnlen(s, sizeof(model_num));
162
163	/* ATAPI specifies that empty space is blank-filled; remove blanks */
164	while ((len > 0) && (s[len - 1] == ' ')) {
165	len--;
166	s[len] = 0;
167	}
168
169	while(list[i] != NULL) {
170	if (!strncmp(list[i], s, len)) {
171	printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
172	modestr, list[i]);
173	return 1;
174	}
175	i++;
176	}
177	return 0;
178	}
179
180	/**
181	* hpt366_filter - mode selection filter
182	* @ap: ATA interface
183	* @adev: ATA device
184	*
185	* Block UDMA on devices that cause trouble with this controller.
186	*/
187
188	static unsigned long hpt366_filter(const struct ata_port ap, struct ata_device adev, unsigned long mask)
189	{
190	if (adev->class == ATA_DEV_ATA) {
191	if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
192	mask &= ~ATA_MASK_UDMA;
193	if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
194	mask &= ~(0x07 << ATA_SHIFT_UDMA);
195	if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
196	mask &= ~(0x0F << ATA_SHIFT_UDMA);
197	}
198	return ata_pci_default_filter(ap, adev, mask);
199	}
200
201	/**
202	* hpt36x_find_mode - reset the hpt36x bus
203	* @ap: ATA port
204	* @speed: transfer mode
205	*
206	* Return the 32bit register programming information for this channel
207	* that matches the speed provided.
208	*/
209
210	static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
211	{
212	struct hpt_clock *clocks = ap->host->private_data;
213
214	while(clocks->xfer_speed) {
215	if (clocks->xfer_speed == speed)
216	return clocks->timing;
217	clocks++;
218	}
219	BUG();
220	return 0xffffffffU; /* silence compiler warning */
221	}
222
223	static int hpt36x_pre_reset(struct ata_port *ap)
224	{
225	u8 ata66;
226	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
227
228	pci_read_config_byte(pdev, 0x5A, &ata66);
229	if (ata66 & (1 << ap->port_no))
230	ap->cbl = ATA_CBL_PATA40;
231	else
232	ap->cbl = ATA_CBL_PATA80;
233	return ata_std_prereset(ap);
234	}
235
236	/**
237	* hpt36x_error_handler - reset the hpt36x bus
238	* @ap: ATA port to reset
239	*
240	* Perform the reset handling for the 366/368
241	*/
242
243	static void hpt36x_error_handler(struct ata_port *ap)
244	{
245	ata_bmdma_drive_eh(ap, hpt36x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
246	}
247
248	/**
249	* hpt366_set_piomode - PIO setup
250	* @ap: ATA interface
251	* @adev: device on the interface
252	*
253	* Perform PIO mode setup.
254	*/
255
256	static void hpt366_set_piomode(struct ata_port ap, struct ata_device adev)
257	{
258	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
259	u32 addr1, addr2;
260	u32 reg;
261	u32 mode;
262	u8 fast;
263
264	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
265	addr2 = 0x51 + 4 * ap->port_no;
266
267	/* Fast interrupt prediction disable, hold off interrupt disable */
268	pci_read_config_byte(pdev, addr2, &fast);
269	if (fast & 0x80) {
270	fast &= ~0x80;
271	pci_write_config_byte(pdev, addr2, fast);
272	}
273
274	pci_read_config_dword(pdev, addr1, &reg);
275	mode = hpt36x_find_mode(ap, adev->pio_mode);
276	mode &= ~0x8000000; /* No FIFO in PIO */
277	mode &= ~0x30070000; /* Leave config bits alone */
278	reg &= 0x30070000; /* Strip timing bits */
279	pci_write_config_dword(pdev, addr1, reg \| mode);
280	}
281
282	/**
283	* hpt366_set_dmamode - DMA timing setup
284	* @ap: ATA interface
285	* @adev: Device being configured
286	*
287	* Set up the channel for MWDMA or UDMA modes. Much the same as with
288	* PIO, load the mode number and then set MWDMA or UDMA flag.
289	*/
290
291	static void hpt366_set_dmamode(struct ata_port ap, struct ata_device adev)
292	{
293	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
294	u32 addr1, addr2;
295	u32 reg;
296	u32 mode;
297	u8 fast;
298
299	addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
300	addr2 = 0x51 + 4 * ap->port_no;
301
302	/* Fast interrupt prediction disable, hold off interrupt disable */
303	pci_read_config_byte(pdev, addr2, &fast);
304	if (fast & 0x80) {
305	fast &= ~0x80;
306	pci_write_config_byte(pdev, addr2, fast);
307	}
308
309	pci_read_config_dword(pdev, addr1, &reg);
310	mode = hpt36x_find_mode(ap, adev->dma_mode);
311	mode \|= 0x8000000; /* FIFO in MWDMA or UDMA */
312	mode &= ~0xC0000000; /* Leave config bits alone */
313	reg &= 0xC0000000; /* Strip timing bits */
314	pci_write_config_dword(pdev, addr1, reg \| mode);
315	}
316
317	static struct scsi_host_template hpt36x_sht = {
318	.module = THIS_MODULE,
319	.name = DRV_NAME,
320	.ioctl = ata_scsi_ioctl,
321	.queuecommand = ata_scsi_queuecmd,
322	.can_queue = ATA_DEF_QUEUE,
323	.this_id = ATA_SHT_THIS_ID,
324	.sg_tablesize = LIBATA_MAX_PRD,
325	.max_sectors = ATA_MAX_SECTORS,
326	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
327	.emulated = ATA_SHT_EMULATED,
328	.use_clustering = ATA_SHT_USE_CLUSTERING,
329	.proc_name = DRV_NAME,
330	.dma_boundary = ATA_DMA_BOUNDARY,
331	.slave_configure = ata_scsi_slave_config,
332	.bios_param = ata_std_bios_param,
333	};
334
335	/*
336	* Configuration for HPT366/68
337	*/
338
339	static struct ata_port_operations hpt366_port_ops = {
340	.port_disable = ata_port_disable,
341	.set_piomode = hpt366_set_piomode,
342	.set_dmamode = hpt366_set_dmamode,
343	.mode_filter = hpt366_filter,
344
345	.tf_load = ata_tf_load,
346	.tf_read = ata_tf_read,
347	.check_status = ata_check_status,
348	.exec_command = ata_exec_command,
349	.dev_select = ata_std_dev_select,
350
351	.freeze = ata_bmdma_freeze,
352	.thaw = ata_bmdma_thaw,
353	.error_handler = hpt36x_error_handler,
354	.post_internal_cmd = ata_bmdma_post_internal_cmd,
355
356	.bmdma_setup = ata_bmdma_setup,
357	.bmdma_start = ata_bmdma_start,
358	.bmdma_stop = ata_bmdma_stop,
359	.bmdma_status = ata_bmdma_status,
360
361	.qc_prep = ata_qc_prep,
362	.qc_issue = ata_qc_issue_prot,
363	.eng_timeout = ata_eng_timeout,
364	.data_xfer = ata_pio_data_xfer,
365
366	.irq_handler = ata_interrupt,
367	.irq_clear = ata_bmdma_irq_clear,
368
369	.port_start = ata_port_start,
370	.port_stop = ata_port_stop,
371	.host_stop = ata_host_stop
372	};
373
374	/**
375	* hpt36x_init_one - Initialise an HPT366/368
376	* @dev: PCI device
377	* @id: Entry in match table
378	*
379	* Initialise an HPT36x device. There are some interesting complications
380	* here. Firstly the chip may report 366 and be one of several variants.
381	* Secondly all the timings depend on the clock for the chip which we must
382	* detect and look up
383	*
384	* This is the known chip mappings. It may be missing a couple of later
385	* releases.
386	*
387	* Chip version PCI Rev Notes
388	* HPT366 4 (HPT366) 0 UDMA66
389	* HPT366 4 (HPT366) 1 UDMA66
390	* HPT368 4 (HPT366) 2 UDMA66
391	* HPT37x/30x 4 (HPT366) 3+ Other driver
392	*
393	*/
394
395	static int hpt36x_init_one(struct pci_dev dev, const struct pci_device_id id)
396	{
397	static struct ata_port_info info_hpt366 = {
398	.sht = &hpt36x_sht,
399	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
400	.pio_mask = 0x1f,
401	.mwdma_mask = 0x07,
402	.udma_mask = 0x1f,
403	.port_ops = &hpt366_port_ops
404	};
405	struct ata_port_info *port_info[2] = {&info_hpt366, &info_hpt366};
406
407	u32 class_rev;
408	u32 reg1;
409	u8 drive_fast;
410
411	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
412	class_rev &= 0xFF;
413
414	/* May be a later chip in disguise. Check */
415	/* Newer chips are not in the HPT36x driver. Ignore them */
416	if (class_rev > 2)
417	return -ENODEV;
418
419	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
420	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
421	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
422	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
423
424	pci_read_config_byte(dev, 0x51, &drive_fast);
425	if (drive_fast & 0x80)
426	pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
427
428	pci_read_config_dword(dev, 0x40, &reg1);
429
430	/* PCI clocking determines the ATA timing values to use */
431	/* info_hpt366 is safe against re-entry so we can scribble on it */
432	switch(reg1 & 0x700) {
433	case 5:
434	info_hpt366.private_data = &hpt366_40;
435	break;
436	case 9:
437	info_hpt366.private_data = &hpt366_25;
438	break;
439	default:
440	info_hpt366.private_data = &hpt366_33;
441	break;
442	}
443	/* Now kick off ATA set up */
444	return ata_pci_init_one(dev, port_info, 2);
445	}
446
447	static struct pci_device_id hpt36x[] = {
448	{ PCI_DEVICE(PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366), },
449	{ 0, },
450	};
451
452	static struct pci_driver hpt36x_pci_driver = {
453	.name = DRV_NAME,
454	.id_table = hpt36x,
455	.probe = hpt36x_init_one,
456	.remove = ata_pci_remove_one
457	};
458
459	static int __init hpt36x_init(void)
460	{
461	return pci_register_driver(&hpt36x_pci_driver);
462	}
463
464
465	static void __exit hpt36x_exit(void)
466	{
467	pci_unregister_driver(&hpt36x_pci_driver);
468	}
469
470
471	MODULE_AUTHOR("Alan Cox");
472	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
473	MODULE_LICENSE("GPL");
474	MODULE_DEVICE_TABLE(pci, hpt36x);
475	MODULE_VERSION(DRV_VERSION);
476
477	module_init(hpt36x_init);
478	module_exit(hpt36x_exit);