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libata: update libata LLDs to use devres
[mirror_ubuntu-hirsute-kernel.git] / drivers / ata / pata_hpt37x.c
CommitLineData
669a5db4
JG		 1/*
2 * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
3 *
4 * This driver is heavily based upon:
5 *
6 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
7 *
8 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
9 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
10 * Portions Copyright (C) 2003 Red Hat Inc
11 *
12 * TODO
13 * PLL mode
14 * Look into engine reset on timeout errors. Should not be
15 * required.
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26
27#define DRV_NAME "pata_hpt37x"
6929da44 28#define DRV_VERSION "0.5.2"
669a5db4
JG		 29
30struct hpt_clock {
31 u8 xfer_speed;
32 u32 timing;
33};
34
35struct hpt_chip {
36 const char *name;
37 unsigned int base;
38 struct hpt_clock const *clocks[4];
39};
40
41/* key for bus clock timings
42 * bit
43 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
44 * DMA. cycles = value + 1
45 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
46 * DMA. cycles = value + 1
47 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
48 * register access.
49 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
50 * register access.
51 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
52 * during task file register access.
53 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
54 * xfer.
55 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
56 * register access.
57 * 28 UDMA enable
58 * 29 DMA enable
59 * 30 PIO_MST enable. if set, the chip is in bus master mode during
60 * PIO.
61 * 31 FIFO enable.
62 */
63
64/* from highpoint documentation. these are old values */
65static const struct hpt_clock hpt370_timings_33[] = {
66/* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */
67 { XFER_UDMA_5, 0x16454e31 },
68 { XFER_UDMA_4, 0x16454e31 },
69 { XFER_UDMA_3, 0x166d4e31 },
70 { XFER_UDMA_2, 0x16494e31 },
71 { XFER_UDMA_1, 0x164d4e31 },
72 { XFER_UDMA_0, 0x16514e31 },
73
74 { XFER_MW_DMA_2, 0x26514e21 },
75 { XFER_MW_DMA_1, 0x26514e33 },
76 { XFER_MW_DMA_0, 0x26514e97 },
77
78 { XFER_PIO_4, 0x06514e21 },
79 { XFER_PIO_3, 0x06514e22 },
80 { XFER_PIO_2, 0x06514e33 },
81 { XFER_PIO_1, 0x06914e43 },
82 { XFER_PIO_0, 0x06914e57 },
83 { 0, 0x06514e57 }
84};
85
86static const struct hpt_clock hpt370_timings_66[] = {
87 { XFER_UDMA_5, 0x14846231 },
88 { XFER_UDMA_4, 0x14886231 },
89 { XFER_UDMA_3, 0x148c6231 },
90 { XFER_UDMA_2, 0x148c6231 },
91 { XFER_UDMA_1, 0x14906231 },
92 { XFER_UDMA_0, 0x14986231 },
93
94 { XFER_MW_DMA_2, 0x26514e21 },
95 { XFER_MW_DMA_1, 0x26514e33 },
96 { XFER_MW_DMA_0, 0x26514e97 },
97
98 { XFER_PIO_4, 0x06514e21 },
99 { XFER_PIO_3, 0x06514e22 },
100 { XFER_PIO_2, 0x06514e33 },
101 { XFER_PIO_1, 0x06914e43 },
102 { XFER_PIO_0, 0x06914e57 },
103 { 0, 0x06514e57 }
104};
105
106/* these are the current (4 sep 2001) timings from highpoint */
107static const struct hpt_clock hpt370a_timings_33[] = {
108 { XFER_UDMA_5, 0x12446231 },
109 { XFER_UDMA_4, 0x12446231 },
110 { XFER_UDMA_3, 0x126c6231 },
111 { XFER_UDMA_2, 0x12486231 },
112 { XFER_UDMA_1, 0x124c6233 },
113 { XFER_UDMA_0, 0x12506297 },
114
115 { XFER_MW_DMA_2, 0x22406c31 },
116 { XFER_MW_DMA_1, 0x22406c33 },
117 { XFER_MW_DMA_0, 0x22406c97 },
118
119 { XFER_PIO_4, 0x06414e31 },
120 { XFER_PIO_3, 0x06414e42 },
121 { XFER_PIO_2, 0x06414e53 },
122 { XFER_PIO_1, 0x06814e93 },
123 { XFER_PIO_0, 0x06814ea7 },
124 { 0, 0x06814ea7 }
125};
126
127/* 2x 33MHz timings */
128static const struct hpt_clock hpt370a_timings_66[] = {
129 { XFER_UDMA_5, 0x1488e673 },
130 { XFER_UDMA_4, 0x1488e673 },
131 { XFER_UDMA_3, 0x1498e673 },
132 { XFER_UDMA_2, 0x1490e673 },
133 { XFER_UDMA_1, 0x1498e677 },
134 { XFER_UDMA_0, 0x14a0e73f },
135
136 { XFER_MW_DMA_2, 0x2480fa73 },
85cd7251 137 { XFER_MW_DMA_1, 0x2480fa77 },
669a5db4
JG		 138 { XFER_MW_DMA_0, 0x2480fb3f },
139
140 { XFER_PIO_4, 0x0c82be73 },
141 { XFER_PIO_3, 0x0c82be95 },
142 { XFER_PIO_2, 0x0c82beb7 },
143 { XFER_PIO_1, 0x0d02bf37 },
144 { XFER_PIO_0, 0x0d02bf5f },
145 { 0, 0x0d02bf5f }
146};
147
148static const struct hpt_clock hpt370a_timings_50[] = {
149 { XFER_UDMA_5, 0x12848242 },
150 { XFER_UDMA_4, 0x12ac8242 },
151 { XFER_UDMA_3, 0x128c8242 },
152 { XFER_UDMA_2, 0x120c8242 },
153 { XFER_UDMA_1, 0x12148254 },
154 { XFER_UDMA_0, 0x121882ea },
155
156 { XFER_MW_DMA_2, 0x22808242 },
157 { XFER_MW_DMA_1, 0x22808254 },
158 { XFER_MW_DMA_0, 0x228082ea },
159
160 { XFER_PIO_4, 0x0a81f442 },
161 { XFER_PIO_3, 0x0a81f443 },
162 { XFER_PIO_2, 0x0a81f454 },
163 { XFER_PIO_1, 0x0ac1f465 },
164 { XFER_PIO_0, 0x0ac1f48a },
165 { 0, 0x0ac1f48a }
166};
167
168static const struct hpt_clock hpt372_timings_33[] = {
169 { XFER_UDMA_6, 0x1c81dc62 },
170 { XFER_UDMA_5, 0x1c6ddc62 },
171 { XFER_UDMA_4, 0x1c8ddc62 },
172 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */
173 { XFER_UDMA_2, 0x1c91dc62 },
174 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */
175 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */
176
177 { XFER_MW_DMA_2, 0x2c829262 },
178 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
179 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
180
181 { XFER_PIO_4, 0x0c829c62 },
182 { XFER_PIO_3, 0x0c829c84 },
183 { XFER_PIO_2, 0x0c829ca6 },
184 { XFER_PIO_1, 0x0d029d26 },
185 { XFER_PIO_0, 0x0d029d5e },
186 { 0, 0x0d029d5e }
187};
188
189static const struct hpt_clock hpt372_timings_50[] = {
190 { XFER_UDMA_5, 0x12848242 },
191 { XFER_UDMA_4, 0x12ac8242 },
192 { XFER_UDMA_3, 0x128c8242 },
193 { XFER_UDMA_2, 0x120c8242 },
194 { XFER_UDMA_1, 0x12148254 },
195 { XFER_UDMA_0, 0x121882ea },
196
197 { XFER_MW_DMA_2, 0x22808242 },
198 { XFER_MW_DMA_1, 0x22808254 },
199 { XFER_MW_DMA_0, 0x228082ea },
200
201 { XFER_PIO_4, 0x0a81f442 },
202 { XFER_PIO_3, 0x0a81f443 },
203 { XFER_PIO_2, 0x0a81f454 },
204 { XFER_PIO_1, 0x0ac1f465 },
205 { XFER_PIO_0, 0x0ac1f48a },
206 { 0, 0x0a81f443 }
207};
208
209static const struct hpt_clock hpt372_timings_66[] = {
210 { XFER_UDMA_6, 0x1c869c62 },
211 { XFER_UDMA_5, 0x1cae9c62 },
212 { XFER_UDMA_4, 0x1c8a9c62 },
213 { XFER_UDMA_3, 0x1c8e9c62 },
214 { XFER_UDMA_2, 0x1c929c62 },
215 { XFER_UDMA_1, 0x1c9a9c62 },
216 { XFER_UDMA_0, 0x1c829c62 },
217
218 { XFER_MW_DMA_2, 0x2c829c62 },
219 { XFER_MW_DMA_1, 0x2c829c66 },
220 { XFER_MW_DMA_0, 0x2c829d2e },
221
222 { XFER_PIO_4, 0x0c829c62 },
223 { XFER_PIO_3, 0x0c829c84 },
224 { XFER_PIO_2, 0x0c829ca6 },
225 { XFER_PIO_1, 0x0d029d26 },
226 { XFER_PIO_0, 0x0d029d5e },
227 { 0, 0x0d029d26 }
228};
229
230static const struct hpt_clock hpt374_timings_33[] = {
231 { XFER_UDMA_6, 0x12808242 },
232 { XFER_UDMA_5, 0x12848242 },
233 { XFER_UDMA_4, 0x12ac8242 },
234 { XFER_UDMA_3, 0x128c8242 },
235 { XFER_UDMA_2, 0x120c8242 },
236 { XFER_UDMA_1, 0x12148254 },
237 { XFER_UDMA_0, 0x121882ea },
238
239 { XFER_MW_DMA_2, 0x22808242 },
240 { XFER_MW_DMA_1, 0x22808254 },
241 { XFER_MW_DMA_0, 0x228082ea },
242
243 { XFER_PIO_4, 0x0a81f442 },
244 { XFER_PIO_3, 0x0a81f443 },
245 { XFER_PIO_2, 0x0a81f454 },
246 { XFER_PIO_1, 0x0ac1f465 },
247 { XFER_PIO_0, 0x0ac1f48a },
248 { 0, 0x06814e93 }
249};
250
251static const struct hpt_chip hpt370 = {
252 "HPT370",
253 48,
254 {
255 hpt370_timings_33,
256 NULL,
257 NULL,
258 hpt370_timings_66
259 }
260};
261
262static const struct hpt_chip hpt370a = {
263 "HPT370A",
264 48,
265 {
266 hpt370a_timings_33,
267 NULL,
268 hpt370a_timings_50,
269 hpt370a_timings_66
270 }
271};
272
273static const struct hpt_chip hpt372 = {
274 "HPT372",
275 55,
276 {
277 hpt372_timings_33,
278 NULL,
279 hpt372_timings_50,
280 hpt372_timings_66
281 }
282};
283
284static const struct hpt_chip hpt302 = {
285 "HPT302",
286 66,
287 {
288 hpt372_timings_33,
289 NULL,
290 hpt372_timings_50,
291 hpt372_timings_66
292 }
293};
294
295static const struct hpt_chip hpt371 = {
296 "HPT371",
297 66,
298 {
299 hpt372_timings_33,
300 NULL,
301 hpt372_timings_50,
302 hpt372_timings_66
303 }
304};
305
306static const struct hpt_chip hpt372a = {
307 "HPT372A",
308 66,
309 {
310 hpt372_timings_33,
311 NULL,
312 hpt372_timings_50,
313 hpt372_timings_66
314 }
315};
316
317static const struct hpt_chip hpt374 = {
318 "HPT374",
319 48,
320 {
321 hpt374_timings_33,
322 NULL,
323 NULL,
324 NULL
325 }
326};
327
328/**
329 * hpt37x_find_mode - reset the hpt37x bus
330 * @ap: ATA port
331 * @speed: transfer mode
332 *
333 * Return the 32bit register programming information for this channel
334 * that matches the speed provided.
335 */
85cd7251 336
669a5db4
JG		 337static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
338{
339 struct hpt_clock *clocks = ap->host->private_data;
85cd7251 340
669a5db4
JG		 341 while(clocks->xfer_speed) {
342 if (clocks->xfer_speed == speed)
343 return clocks->timing;
344 clocks++;
345 }
346 BUG();
347 return 0xffffffffU; /* silence compiler warning */
348}
349
350static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
351{
8bfa79fc 352 unsigned char model_num[ATA_ID_PROD_LEN + 1];
669a5db4
JG		 353 int i = 0;
354
8bfa79fc 355 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
669a5db4 356
8bfa79fc
TH		 357 while (list[i] != NULL) {
358 if (!strcmp(list[i], model_num)) {
85cd7251 359 printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
669a5db4
JG		 360 modestr, list[i]);
361 return 1;
362 }
363 i++;
364 }
365 return 0;
366}
367
368static const char *bad_ata33[] = {
369 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
370 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
371 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
372 "Maxtor 90510D4",
373 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
374 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
375 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
376 NULL
377};
378
379static const char *bad_ata100_5[] = {
380 "IBM-DTLA-307075",
381 "IBM-DTLA-307060",
382 "IBM-DTLA-307045",
383 "IBM-DTLA-307030",
384 "IBM-DTLA-307020",
385 "IBM-DTLA-307015",
386 "IBM-DTLA-305040",
387 "IBM-DTLA-305030",
388 "IBM-DTLA-305020",
389 "IC35L010AVER07-0",
390 "IC35L020AVER07-0",
391 "IC35L030AVER07-0",
392 "IC35L040AVER07-0",
393 "IC35L060AVER07-0",
394 "WDC AC310200R",
395 NULL
396};
397
398/**
399 * hpt370_filter - mode selection filter
400 * @ap: ATA interface
401 * @adev: ATA device
402 *
403 * Block UDMA on devices that cause trouble with this controller.
404 */
85cd7251 405
669a5db4
JG		 406static unsigned long hpt370_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
407{
6929da44 408 if (adev->class == ATA_DEV_ATA) {
669a5db4
JG		 409 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
410 mask &= ~ATA_MASK_UDMA;
411 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
412 mask &= ~(0x1F << ATA_SHIFT_UDMA);
413 }
414 return ata_pci_default_filter(ap, adev, mask);
415}
416
417/**
418 * hpt370a_filter - mode selection filter
419 * @ap: ATA interface
420 * @adev: ATA device
421 *
422 * Block UDMA on devices that cause trouble with this controller.
423 */
85cd7251 424
669a5db4
JG		 425static unsigned long hpt370a_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask)
426{
427 if (adev->class != ATA_DEV_ATA) {
428 if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
429 mask &= ~ (0x1F << ATA_SHIFT_UDMA);
430 }
431 return ata_pci_default_filter(ap, adev, mask);
432}
85cd7251 433
669a5db4
JG		 434/**
435 * hpt37x_pre_reset - reset the hpt37x bus
436 * @ap: ATA port to reset
437 *
438 * Perform the initial reset handling for the 370/372 and 374 func 0
439 */
85cd7251 440
669a5db4
JG		 441static int hpt37x_pre_reset(struct ata_port *ap)
442{
443 u8 scr2, ata66;
444 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
b5bf24b9
AC		 445 static const struct pci_bits hpt37x_enable_bits[] = {
446 { 0x50, 1, 0x04, 0x04 },
447 { 0x54, 1, 0x04, 0x04 }
448 };
449 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
450 return -ENOENT;
f20b16ff 451
669a5db4
JG		 452 pci_read_config_byte(pdev, 0x5B, &scr2);
453 pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
454 /* Cable register now active */
455 pci_read_config_byte(pdev, 0x5A, &ata66);
456 /* Restore state */
457 pci_write_config_byte(pdev, 0x5B, scr2);
85cd7251 458
669a5db4
JG		 459 if (ata66 & (1 << ap->port_no))
460 ap->cbl = ATA_CBL_PATA40;
461 else
462 ap->cbl = ATA_CBL_PATA80;
463
464 /* Reset the state machine */
85cd7251
JG		 465 pci_write_config_byte(pdev, 0x50, 0x37);
466 pci_write_config_byte(pdev, 0x54, 0x37);
669a5db4 467 udelay(100);
85cd7251 468
669a5db4
JG		 469 return ata_std_prereset(ap);
470}
471
472/**
473 * hpt37x_error_handler - reset the hpt374
474 * @ap: ATA port to reset
475 *
476 * Perform probe for HPT37x, except for HPT374 channel 2
477 */
85cd7251 478
669a5db4
JG		 479static void hpt37x_error_handler(struct ata_port *ap)
480{
481 ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
482}
483
484static int hpt374_pre_reset(struct ata_port *ap)
485{
b5bf24b9
AC		 486 static const struct pci_bits hpt37x_enable_bits[] = {
487 { 0x50, 1, 0x04, 0x04 },
488 { 0x54, 1, 0x04, 0x04 }
489 };
669a5db4
JG		 490 u16 mcr3, mcr6;
491 u8 ata66;
669a5db4 492 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
b5bf24b9
AC		 493
494 if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
495 return -ENOENT;
f20b16ff 496
669a5db4
JG		 497 /* Do the extra channel work */
498 pci_read_config_word(pdev, 0x52, &mcr3);
499 pci_read_config_word(pdev, 0x56, &mcr6);
500 /* Set bit 15 of 0x52 to enable TCBLID as input
501 Set bit 15 of 0x56 to enable FCBLID as input
502 */
503 pci_write_config_word(pdev, 0x52, mcr3 | 0x8000);
504 pci_write_config_word(pdev, 0x56, mcr6 | 0x8000);
505 pci_read_config_byte(pdev, 0x5A, &ata66);
506 /* Reset TCBLID/FCBLID to output */
507 pci_write_config_word(pdev, 0x52, mcr3);
508 pci_write_config_word(pdev, 0x56, mcr6);
85cd7251 509
669a5db4
JG		 510 if (ata66 & (1 << ap->port_no))
511 ap->cbl = ATA_CBL_PATA40;
512 else
513 ap->cbl = ATA_CBL_PATA80;
514
515 /* Reset the state machine */
85cd7251
JG		 516 pci_write_config_byte(pdev, 0x50, 0x37);
517 pci_write_config_byte(pdev, 0x54, 0x37);
669a5db4 518 udelay(100);
85cd7251 519
669a5db4
JG		 520 return ata_std_prereset(ap);
521}
522
523/**
524 * hpt374_error_handler - reset the hpt374
525 * @classes:
526 *
527 * The 374 cable detect is a little different due to the extra
528 * channels. The function 0 channels work like usual but function 1
529 * is special
530 */
85cd7251 531
669a5db4
JG		 532static void hpt374_error_handler(struct ata_port *ap)
533{
534 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
85cd7251 535
669a5db4
JG		 536 if (!(PCI_FUNC(pdev->devfn) & 1))
537 hpt37x_error_handler(ap);
538 else
539 ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
540}
541
542/**
543 * hpt370_set_piomode - PIO setup
544 * @ap: ATA interface
545 * @adev: device on the interface
546 *
85cd7251 547 * Perform PIO mode setup.
669a5db4 548 */
85cd7251 549
669a5db4
JG		 550static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev)
551{
552 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
553 u32 addr1, addr2;
554 u32 reg;
555 u32 mode;
556 u8 fast;
557
558 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
559 addr2 = 0x51 + 4 * ap->port_no;
85cd7251 560
669a5db4
JG		 561 /* Fast interrupt prediction disable, hold off interrupt disable */
562 pci_read_config_byte(pdev, addr2, &fast);
563 fast &= ~0x02;
564 fast |= 0x01;
565 pci_write_config_byte(pdev, addr2, fast);
85cd7251 566
669a5db4
JG		 567 pci_read_config_dword(pdev, addr1, &reg);
568 mode = hpt37x_find_mode(ap, adev->pio_mode);
569 mode &= ~0x8000000; /* No FIFO in PIO */
570 mode &= ~0x30070000; /* Leave config bits alone */
571 reg &= 0x30070000; /* Strip timing bits */
572 pci_write_config_dword(pdev, addr1, reg | mode);
573}
574
575/**
576 * hpt370_set_dmamode - DMA timing setup
577 * @ap: ATA interface
578 * @adev: Device being configured
579 *
580 * Set up the channel for MWDMA or UDMA modes. Much the same as with
581 * PIO, load the mode number and then set MWDMA or UDMA flag.
582 */
85cd7251 583
669a5db4
JG		 584static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev)
585{
586 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
587 u32 addr1, addr2;
588 u32 reg;
589 u32 mode;
590 u8 fast;
591
592 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
593 addr2 = 0x51 + 4 * ap->port_no;
85cd7251 594
669a5db4
JG		 595 /* Fast interrupt prediction disable, hold off interrupt disable */
596 pci_read_config_byte(pdev, addr2, &fast);
597 fast &= ~0x02;
598 fast |= 0x01;
599 pci_write_config_byte(pdev, addr2, fast);
85cd7251 600
669a5db4
JG		 601 pci_read_config_dword(pdev, addr1, &reg);
602 mode = hpt37x_find_mode(ap, adev->dma_mode);
603 mode |= 0x8000000; /* FIFO in MWDMA or UDMA */
604 mode &= ~0xC0000000; /* Leave config bits alone */
605 reg &= 0xC0000000; /* Strip timing bits */
606 pci_write_config_dword(pdev, addr1, reg | mode);
607}
608
609/**
610 * hpt370_bmdma_start - DMA engine begin
611 * @qc: ATA command
612 *
613 * The 370 and 370A want us to reset the DMA engine each time we
614 * use it. The 372 and later are fine.
615 */
85cd7251 616
669a5db4
JG		 617static void hpt370_bmdma_start(struct ata_queued_cmd *qc)
618{
619 struct ata_port *ap = qc->ap;
620 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
621 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
622 udelay(10);
623 ata_bmdma_start(qc);
624}
625
626/**
627 * hpt370_bmdma_end - DMA engine stop
628 * @qc: ATA command
629 *
630 * Work around the HPT370 DMA engine.
631 */
85cd7251 632
669a5db4
JG		 633static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
634{
635 struct ata_port *ap = qc->ap;
636 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
637 u8 dma_stat = inb(ap->ioaddr.bmdma_addr + 2);
638 u8 dma_cmd;
639 unsigned long bmdma = ap->ioaddr.bmdma_addr;
85cd7251 640
669a5db4
JG		 641 if (dma_stat & 0x01) {
642 udelay(20);
643 dma_stat = inb(bmdma + 2);
644 }
645 if (dma_stat & 0x01) {
646 /* Clear the engine */
647 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
648 udelay(10);
649 /* Stop DMA */
650 dma_cmd = inb(bmdma );
651 outb(dma_cmd & 0xFE, bmdma);
652 /* Clear Error */
653 dma_stat = inb(bmdma + 2);
654 outb(dma_stat | 0x06 , bmdma + 2);
655 /* Clear the engine */
656 pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
657 udelay(10);
658 }
659 ata_bmdma_stop(qc);
660}
661
662/**
663 * hpt372_set_piomode - PIO setup
664 * @ap: ATA interface
665 * @adev: device on the interface
666 *
85cd7251 667 * Perform PIO mode setup.
669a5db4 668 */
85cd7251 669
669a5db4
JG		 670static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev)
671{
672 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
673 u32 addr1, addr2;
674 u32 reg;
675 u32 mode;
676 u8 fast;
677
678 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
679 addr2 = 0x51 + 4 * ap->port_no;
85cd7251 680
669a5db4
JG		 681 /* Fast interrupt prediction disable, hold off interrupt disable */
682 pci_read_config_byte(pdev, addr2, &fast);
683 fast &= ~0x07;
684 pci_write_config_byte(pdev, addr2, fast);
85cd7251 685
669a5db4
JG		 686 pci_read_config_dword(pdev, addr1, &reg);
687 mode = hpt37x_find_mode(ap, adev->pio_mode);
85cd7251 688
669a5db4
JG		 689 printk("Find mode for %d reports %X\n", adev->pio_mode, mode);
690 mode &= ~0x80000000; /* No FIFO in PIO */
691 mode &= ~0x30070000; /* Leave config bits alone */
692 reg &= 0x30070000; /* Strip timing bits */
693 pci_write_config_dword(pdev, addr1, reg | mode);
694}
695
696/**
697 * hpt372_set_dmamode - DMA timing setup
698 * @ap: ATA interface
699 * @adev: Device being configured
700 *
701 * Set up the channel for MWDMA or UDMA modes. Much the same as with
702 * PIO, load the mode number and then set MWDMA or UDMA flag.
703 */
85cd7251 704
669a5db4
JG		 705static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev)
706{
707 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
708 u32 addr1, addr2;
709 u32 reg;
710 u32 mode;
711 u8 fast;
712
713 addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
714 addr2 = 0x51 + 4 * ap->port_no;
85cd7251 715
669a5db4
JG		 716 /* Fast interrupt prediction disable, hold off interrupt disable */
717 pci_read_config_byte(pdev, addr2, &fast);
718 fast &= ~0x07;
719 pci_write_config_byte(pdev, addr2, fast);
85cd7251 720
669a5db4
JG		 721 pci_read_config_dword(pdev, addr1, &reg);
722 mode = hpt37x_find_mode(ap, adev->dma_mode);
723 printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode);
724 mode &= ~0xC0000000; /* Leave config bits alone */
725 mode |= 0x80000000; /* FIFO in MWDMA or UDMA */
726 reg &= 0xC0000000; /* Strip timing bits */
727 pci_write_config_dword(pdev, addr1, reg | mode);
728}
729
730/**
731 * hpt37x_bmdma_end - DMA engine stop
732 * @qc: ATA command
733 *
734 * Clean up after the HPT372 and later DMA engine
735 */
85cd7251 736
669a5db4
JG		 737static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
738{
739 struct ata_port *ap = qc->ap;
740 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
6929da44 741 int mscreg = 0x50 + 4 * ap->port_no;
669a5db4 742 u8 bwsr_stat, msc_stat;
85cd7251 743
669a5db4
JG		 744 pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
745 pci_read_config_byte(pdev, mscreg, &msc_stat);
746 if (bwsr_stat & (1 << ap->port_no))
747 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
748 ata_bmdma_stop(qc);
749}
750
751
752static struct scsi_host_template hpt37x_sht = {
753 .module = THIS_MODULE,
754 .name = DRV_NAME,
755 .ioctl = ata_scsi_ioctl,
756 .queuecommand = ata_scsi_queuecmd,
757 .can_queue = ATA_DEF_QUEUE,
758 .this_id = ATA_SHT_THIS_ID,
759 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 760 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
761 .emulated = ATA_SHT_EMULATED,
762 .use_clustering = ATA_SHT_USE_CLUSTERING,
763 .proc_name = DRV_NAME,
764 .dma_boundary = ATA_DMA_BOUNDARY,
765 .slave_configure = ata_scsi_slave_config,
afdfe899 766 .slave_destroy = ata_scsi_slave_destroy,
669a5db4
JG		 767 .bios_param = ata_std_bios_param,
768};
769
770/*
771 * Configuration for HPT370
772 */
85cd7251 773
669a5db4
JG		 774static struct ata_port_operations hpt370_port_ops = {
775 .port_disable = ata_port_disable,
776 .set_piomode = hpt370_set_piomode,
777 .set_dmamode = hpt370_set_dmamode,
778 .mode_filter = hpt370_filter,
85cd7251 779
669a5db4
JG		 780 .tf_load = ata_tf_load,
781 .tf_read = ata_tf_read,
782 .check_status = ata_check_status,
783 .exec_command = ata_exec_command,
784 .dev_select = ata_std_dev_select,
785
786 .freeze = ata_bmdma_freeze,
787 .thaw = ata_bmdma_thaw,
788 .error_handler = hpt37x_error_handler,
789 .post_internal_cmd = ata_bmdma_post_internal_cmd,
790
791 .bmdma_setup = ata_bmdma_setup,
792 .bmdma_start = hpt370_bmdma_start,
793 .bmdma_stop = hpt370_bmdma_stop,
794 .bmdma_status = ata_bmdma_status,
795
796 .qc_prep = ata_qc_prep,
797 .qc_issue = ata_qc_issue_prot,
bda30288 798
669a5db4
JG		 799 .data_xfer = ata_pio_data_xfer,
800
801 .irq_handler = ata_interrupt,
802 .irq_clear = ata_bmdma_irq_clear,
803
804 .port_start = ata_port_start,
85cd7251 805};
669a5db4
JG		 806
807/*
808 * Configuration for HPT370A. Close to 370 but less filters
809 */
85cd7251 810
669a5db4
JG		 811static struct ata_port_operations hpt370a_port_ops = {
812 .port_disable = ata_port_disable,
813 .set_piomode = hpt370_set_piomode,
814 .set_dmamode = hpt370_set_dmamode,
815 .mode_filter = hpt370a_filter,
85cd7251 816
669a5db4
JG		 817 .tf_load = ata_tf_load,
818 .tf_read = ata_tf_read,
819 .check_status = ata_check_status,
820 .exec_command = ata_exec_command,
821 .dev_select = ata_std_dev_select,
822
823 .freeze = ata_bmdma_freeze,
824 .thaw = ata_bmdma_thaw,
825 .error_handler = hpt37x_error_handler,
826 .post_internal_cmd = ata_bmdma_post_internal_cmd,
827
828 .bmdma_setup = ata_bmdma_setup,
829 .bmdma_start = hpt370_bmdma_start,
830 .bmdma_stop = hpt370_bmdma_stop,
831 .bmdma_status = ata_bmdma_status,
832
833 .qc_prep = ata_qc_prep,
834 .qc_issue = ata_qc_issue_prot,
bda30288 835
669a5db4
JG		 836 .data_xfer = ata_pio_data_xfer,
837
838 .irq_handler = ata_interrupt,
839 .irq_clear = ata_bmdma_irq_clear,
840
841 .port_start = ata_port_start,
85cd7251 842};
669a5db4
JG		 843
844/*
845 * Configuration for HPT372, HPT371, HPT302. Slightly different PIO
846 * and DMA mode setting functionality.
847 */
85cd7251 848
669a5db4
JG		 849static struct ata_port_operations hpt372_port_ops = {
850 .port_disable = ata_port_disable,
851 .set_piomode = hpt372_set_piomode,
852 .set_dmamode = hpt372_set_dmamode,
853 .mode_filter = ata_pci_default_filter,
85cd7251 854
669a5db4
JG		 855 .tf_load = ata_tf_load,
856 .tf_read = ata_tf_read,
857 .check_status = ata_check_status,
858 .exec_command = ata_exec_command,
859 .dev_select = ata_std_dev_select,
860
861 .freeze = ata_bmdma_freeze,
862 .thaw = ata_bmdma_thaw,
863 .error_handler = hpt37x_error_handler,
864 .post_internal_cmd = ata_bmdma_post_internal_cmd,
865
866 .bmdma_setup = ata_bmdma_setup,
867 .bmdma_start = ata_bmdma_start,
868 .bmdma_stop = hpt37x_bmdma_stop,
869 .bmdma_status = ata_bmdma_status,
870
871 .qc_prep = ata_qc_prep,
872 .qc_issue = ata_qc_issue_prot,
bda30288 873
669a5db4
JG		 874 .data_xfer = ata_pio_data_xfer,
875
876 .irq_handler = ata_interrupt,
877 .irq_clear = ata_bmdma_irq_clear,
878
879 .port_start = ata_port_start,
85cd7251 880};
669a5db4
JG		 881
882/*
883 * Configuration for HPT374. Mode setting works like 372 and friends
884 * but we have a different cable detection procedure.
885 */
85cd7251 886
669a5db4
JG		 887static struct ata_port_operations hpt374_port_ops = {
888 .port_disable = ata_port_disable,
889 .set_piomode = hpt372_set_piomode,
890 .set_dmamode = hpt372_set_dmamode,
891 .mode_filter = ata_pci_default_filter,
85cd7251 892
669a5db4
JG		 893 .tf_load = ata_tf_load,
894 .tf_read = ata_tf_read,
895 .check_status = ata_check_status,
896 .exec_command = ata_exec_command,
897 .dev_select = ata_std_dev_select,
898
899 .freeze = ata_bmdma_freeze,
900 .thaw = ata_bmdma_thaw,
901 .error_handler = hpt374_error_handler,
902 .post_internal_cmd = ata_bmdma_post_internal_cmd,
903
904 .bmdma_setup = ata_bmdma_setup,
905 .bmdma_start = ata_bmdma_start,
906 .bmdma_stop = hpt37x_bmdma_stop,
907 .bmdma_status = ata_bmdma_status,
908
909 .qc_prep = ata_qc_prep,
910 .qc_issue = ata_qc_issue_prot,
bda30288 911
669a5db4
JG		 912 .data_xfer = ata_pio_data_xfer,
913
914 .irq_handler = ata_interrupt,
915 .irq_clear = ata_bmdma_irq_clear,
916
917 .port_start = ata_port_start,
85cd7251 918};
669a5db4
JG		 919
920/**
921 * htp37x_clock_slot - Turn timing to PC clock entry
922 * @freq: Reported frequency timing
923 * @base: Base timing
924 *
925 * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50
926 * and 3 for 66Mhz)
927 */
85cd7251 928
669a5db4
JG		 929static int hpt37x_clock_slot(unsigned int freq, unsigned int base)
930{
931 unsigned int f = (base * freq) / 192; /* Mhz */
932 if (f < 40)
933 return 0; /* 33Mhz slot */
934 if (f < 45)
935 return 1; /* 40Mhz slot */
936 if (f < 55)
937 return 2; /* 50Mhz slot */
938 return 3; /* 60Mhz slot */
939}
940
941/**
942 * hpt37x_calibrate_dpll - Calibrate the DPLL loop
85cd7251 943 * @dev: PCI device
669a5db4
JG		 944 *
945 * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
946 * succeeds
947 */
948
949static int hpt37x_calibrate_dpll(struct pci_dev *dev)
950{
951 u8 reg5b;
952 u32 reg5c;
953 int tries;
85cd7251 954
669a5db4
JG		 955 for(tries = 0; tries < 0x5000; tries++) {
956 udelay(50);
957 pci_read_config_byte(dev, 0x5b, &reg5b);
958 if (reg5b & 0x80) {
959 /* See if it stays set */
960 for(tries = 0; tries < 0x1000; tries ++) {
961 pci_read_config_byte(dev, 0x5b, &reg5b);
962 /* Failed ? */
963 if ((reg5b & 0x80) == 0)
964 return 0;
965 }
966 /* Turn off tuning, we have the DPLL set */
967 pci_read_config_dword(dev, 0x5c, &reg5c);
968 pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100);
969 return 1;
970 }
971 }
972 /* Never went stable */
973 return 0;
974}
975/**
976 * hpt37x_init_one - Initialise an HPT37X/302
977 * @dev: PCI device
978 * @id: Entry in match table
979 *
980 * Initialise an HPT37x device. There are some interesting complications
981 * here. Firstly the chip may report 366 and be one of several variants.
982 * Secondly all the timings depend on the clock for the chip which we must
983 * detect and look up
984 *
985 * This is the known chip mappings. It may be missing a couple of later
986 * releases.
987 *
988 * Chip version PCI Rev Notes
989 * HPT366 4 (HPT366) 0 Other driver
990 * HPT366 4 (HPT366) 1 Other driver
991 * HPT368 4 (HPT366) 2 Other driver
992 * HPT370 4 (HPT366) 3 UDMA100
993 * HPT370A 4 (HPT366) 4 UDMA100
994 * HPT372 4 (HPT366) 5 UDMA133 (1)
995 * HPT372N 4 (HPT366) 6 Other driver
996 * HPT372A 5 (HPT372) 1 UDMA133 (1)
997 * HPT372N 5 (HPT372) 2 Other driver
998 * HPT302 6 (HPT302) 1 UDMA133
999 * HPT302N 6 (HPT302) 2 Other driver
1000 * HPT371 7 (HPT371) * UDMA133
1001 * HPT374 8 (HPT374) * UDMA133 4 channel
1002 * HPT372N 9 (HPT372N) * Other driver
1003 *
1004 * (1) UDMA133 support depends on the bus clock
1005 */
85cd7251 1006
669a5db4
JG		 1007static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1008{
1009 /* HPT370 - UDMA100 */
1010 static struct ata_port_info info_hpt370 = {
1011 .sht = &hpt37x_sht,
1012 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1013 .pio_mask = 0x1f,
1014 .mwdma_mask = 0x07,
1015 .udma_mask = 0x3f,
1016 .port_ops = &hpt370_port_ops
1017 };
1018 /* HPT370A - UDMA100 */
1019 static struct ata_port_info info_hpt370a = {
1020 .sht = &hpt37x_sht,
1021 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1022 .pio_mask = 0x1f,
1023 .mwdma_mask = 0x07,
1024 .udma_mask = 0x3f,
1025 .port_ops = &hpt370a_port_ops
1026 };
1027 /* HPT371, 372 and friends - UDMA133 */
1028 static struct ata_port_info info_hpt372 = {
1029 .sht = &hpt37x_sht,
1030 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1031 .pio_mask = 0x1f,
1032 .mwdma_mask = 0x07,
1033 .udma_mask = 0x7f,
1034 .port_ops = &hpt372_port_ops
1035 };
1036 /* HPT371, 372 and friends - UDMA100 at 50MHz clock */
1037 static struct ata_port_info info_hpt372_50 = {
1038 .sht = &hpt37x_sht,
1039 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1040 .pio_mask = 0x1f,
1041 .mwdma_mask = 0x07,
1042 .udma_mask = 0x3f,
1043 .port_ops = &hpt372_port_ops
1044 };
1045 /* HPT374 - UDMA133 */
1046 static struct ata_port_info info_hpt374 = {
1047 .sht = &hpt37x_sht,
1048 .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST,
1049 .pio_mask = 0x1f,
1050 .mwdma_mask = 0x07,
1051 .udma_mask = 0x7f,
1052 .port_ops = &hpt374_port_ops
1053 };
1054
1055 static const int MHz[4] = { 33, 40, 50, 66 };
1056
1057 struct ata_port_info *port_info[2];
1058 struct ata_port_info *port;
1059
1060 u8 irqmask;
1061 u32 class_rev;
1062 u32 freq;
1063
1064 const struct hpt_chip *chip_table;
1065 int clock_slot;
1066
1067 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1068 class_rev &= 0xFF;
85cd7251 1069
669a5db4
JG		 1070 if (dev->device == PCI_DEVICE_ID_TTI_HPT366) {
1071 /* May be a later chip in disguise. Check */
1072 /* Older chips are in the HPT366 driver. Ignore them */
1073 if (class_rev < 3)
1074 return -ENODEV;
1075 /* N series chips have their own driver. Ignore */
1076 if (class_rev == 6)
1077 return -ENODEV;
1078
85cd7251 1079 switch(class_rev) {
669a5db4
JG		 1080 case 3:
1081 port = &info_hpt370;
1082 chip_table = &hpt370;
1083 break;
1084 case 4:
1085 port = &info_hpt370a;
1086 chip_table = &hpt370a;
1087 break;
1088 case 5:
1089 port = &info_hpt372;
1090 chip_table = &hpt372;
1091 break;
1092 default:
1093 printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev);
1094 return -ENODEV;
1095 }
1096 } else {
1097 switch(dev->device) {
1098 case PCI_DEVICE_ID_TTI_HPT372:
1099 /* 372N if rev >= 2*/
1100 if (class_rev >= 2)
1101 return -ENODEV;
1102 port = &info_hpt372;
1103 chip_table = &hpt372a;
1104 break;
1105 case PCI_DEVICE_ID_TTI_HPT302:
1106 /* 302N if rev > 1 */
1107 if (class_rev > 1)
1108 return -ENODEV;
1109 port = &info_hpt372;
1110 /* Check this */
1111 chip_table = &hpt302;
1112 break;
1113 case PCI_DEVICE_ID_TTI_HPT371:
1114 port = &info_hpt372;
1115 chip_table = &hpt371;
1116 break;
1117 case PCI_DEVICE_ID_TTI_HPT374:
1118 chip_table = &hpt374;
1119 port = &info_hpt374;
1120 break;
1121 default:
1122 printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device);
1123 return -ENODEV;
1124 }
1125 }
1126 /* Ok so this is a chip we support */
1127
1128 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1129 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1130 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1131 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1132
1133 pci_read_config_byte(dev, 0x5A, &irqmask);
1134 irqmask &= ~0x10;
1135 pci_write_config_byte(dev, 0x5a, irqmask);
1136
1137 /*
1138 * default to pci clock. make sure MA15/16 are set to output
1139 * to prevent drives having problems with 40-pin cables. Needed
1140 * for some drives such as IBM-DTLA which will not enter ready
1141 * state on reset when PDIAG is a input.
1142 */
1143
85cd7251
JG		 1144 pci_write_config_byte(dev, 0x5b, 0x23);
1145
669a5db4
JG		 1146 pci_read_config_dword(dev, 0x70, &freq);
1147 if ((freq >> 12) != 0xABCDE) {
1148 int i;
1149 u8 sr;
1150 u32 total = 0;
85cd7251 1151
669a5db4 1152 printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n");
85cd7251 1153
669a5db4
JG		 1154 /* This is the process the HPT371 BIOS is reported to use */
1155 for(i = 0; i < 128; i++) {
1156 pci_read_config_byte(dev, 0x78, &sr);
1157 total += sr;
1158 udelay(15);
1159 }
1160 freq = total / 128;
1161 }
1162 freq &= 0x1FF;
85cd7251 1163
669a5db4
JG		 1164 /*
1165 * Turn the frequency check into a band and then find a timing
1166 * table to match it.
1167 */
85cd7251 1168
669a5db4
JG		 1169 clock_slot = hpt37x_clock_slot(freq, chip_table->base);
1170 if (chip_table->clocks[clock_slot] == NULL) {
1171 /*
1172 * We need to try PLL mode instead
1173 */
1174 unsigned int f_low = (MHz[clock_slot] * chip_table->base) / 192;
1175 unsigned int f_high = f_low + 2;
1176 int adjust;
85cd7251 1177
669a5db4
JG		 1178 for(adjust = 0; adjust < 8; adjust++) {
1179 if (hpt37x_calibrate_dpll(dev))
1180 break;
1181 /* See if it'll settle at a fractionally different clock */
1182 if ((adjust & 3) == 3) {
1183 f_low --;
1184 f_high ++;
1185 }
1186 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
1187 }
1188 if (adjust == 8) {
1189 printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n");
1190 return -ENODEV;
1191 }
1192 /* Check if this works for all cases */
1193 port->private_data = (void *)hpt370_timings_66;
85cd7251 1194
669a5db4
JG		 1195 printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]);
1196 } else {
1197 port->private_data = (void *)chip_table->clocks[clock_slot];
1198 /*
1199 * Perform a final fixup. The 371 and 372 clock determines
1200 * if UDMA133 is available.
1201 */
85cd7251 1202
669a5db4
JG		 1203 if (clock_slot == 2 && chip_table == &hpt372) { /* 50Mhz */
1204 printk(KERN_WARNING "pata_hpt37x: No UDMA133 support available with 50MHz bus clock.\n");
1205 if (port == &info_hpt372)
1206 port = &info_hpt372_50;
1207 else BUG();
1208 }
1209 printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]);
1210 }
85cd7251 1211 port_info[0] = port_info[1] = port;
669a5db4
JG		 1212 /* Now kick off ATA set up */
1213 return ata_pci_init_one(dev, port_info, 2);
1214}
1215
2d2744fc
JG		 1216static const struct pci_device_id hpt37x[] = {
1217 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1218 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1219 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1220 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1221 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1222
1223 { },
669a5db4
JG		 1224};
1225
1226static struct pci_driver hpt37x_pci_driver = {
2d2744fc 1227 .name = DRV_NAME,
669a5db4
JG		 1228 .id_table = hpt37x,
1229 .probe = hpt37x_init_one,
1230 .remove = ata_pci_remove_one
1231};
1232
1233static int __init hpt37x_init(void)
1234{
1235 return pci_register_driver(&hpt37x_pci_driver);
1236}
1237
669a5db4
JG		 1238static void __exit hpt37x_exit(void)
1239{
1240 pci_unregister_driver(&hpt37x_pci_driver);
1241}
1242
669a5db4
JG		 1243MODULE_AUTHOR("Alan Cox");
1244MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1245MODULE_LICENSE("GPL");
1246MODULE_DEVICE_TABLE(pci, hpt37x);
1247MODULE_VERSION(DRV_VERSION);
1248
1249module_init(hpt37x_init);
1250module_exit(hpt37x_exit);
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