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Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. | |
3 | * | |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
fcc2f69a | 11 | * Portions Copyright (C) 2005-2006 MontaVista Software, Inc. |
669a5db4 JG |
12 | * |
13 | * TODO | |
14 | * PLL mode | |
15 | * Look into engine reset on timeout errors. Should not be | |
16 | * required. | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/pci.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <scsi/scsi_host.h> | |
26 | #include <linux/libata.h> | |
27 | ||
28 | #define DRV_NAME "pata_hpt37x" | |
fcc2f69a | 29 | #define DRV_VERSION "0.6.4" |
669a5db4 JG |
30 | |
31 | struct hpt_clock { | |
32 | u8 xfer_speed; | |
33 | u32 timing; | |
34 | }; | |
35 | ||
36 | struct hpt_chip { | |
37 | const char *name; | |
38 | unsigned int base; | |
39 | struct hpt_clock const *clocks[4]; | |
40 | }; | |
41 | ||
42 | /* key for bus clock timings | |
43 | * bit | |
44 | * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW | |
45 | * DMA. cycles = value + 1 | |
46 | * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW | |
47 | * DMA. cycles = value + 1 | |
48 | * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file | |
49 | * register access. | |
50 | * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file | |
51 | * register access. | |
52 | * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. | |
53 | * during task file register access. | |
54 | * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA | |
55 | * xfer. | |
56 | * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task | |
57 | * register access. | |
58 | * 28 UDMA enable | |
59 | * 29 DMA enable | |
60 | * 30 PIO_MST enable. if set, the chip is in bus master mode during | |
61 | * PIO. | |
62 | * 31 FIFO enable. | |
63 | */ | |
64 | ||
fcc2f69a AC |
65 | static struct hpt_clock hpt37x_timings_33[] = { |
66 | { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */ | |
67 | { XFER_UDMA_5, 0x12446231 }, | |
68 | { XFER_UDMA_4, 0x12446231 }, | |
69 | { XFER_UDMA_3, 0x126c6231 }, | |
70 | { XFER_UDMA_2, 0x12486231 }, | |
71 | { XFER_UDMA_1, 0x124c6233 }, | |
72 | { XFER_UDMA_0, 0x12506297 }, | |
73 | ||
74 | { XFER_MW_DMA_2, 0x22406c31 }, | |
75 | { XFER_MW_DMA_1, 0x22406c33 }, | |
76 | { XFER_MW_DMA_0, 0x22406c97 }, | |
77 | ||
78 | { XFER_PIO_4, 0x06414e31 }, | |
79 | { XFER_PIO_3, 0x06414e42 }, | |
80 | { XFER_PIO_2, 0x06414e53 }, | |
81 | { XFER_PIO_1, 0x06814e93 }, | |
82 | { XFER_PIO_0, 0x06814ea7 } | |
669a5db4 JG |
83 | }; |
84 | ||
fcc2f69a AC |
85 | static struct hpt_clock hpt37x_timings_50[] = { |
86 | { XFER_UDMA_6, 0x12848242 }, | |
87 | { XFER_UDMA_5, 0x12848242 }, | |
88 | { XFER_UDMA_4, 0x12ac8242 }, | |
89 | { XFER_UDMA_3, 0x128c8242 }, | |
90 | { XFER_UDMA_2, 0x120c8242 }, | |
91 | { XFER_UDMA_1, 0x12148254 }, | |
92 | { XFER_UDMA_0, 0x121882ea }, | |
93 | ||
94 | { XFER_MW_DMA_2, 0x22808242 }, | |
95 | { XFER_MW_DMA_1, 0x22808254 }, | |
96 | { XFER_MW_DMA_0, 0x228082ea }, | |
97 | ||
98 | { XFER_PIO_4, 0x0a81f442 }, | |
99 | { XFER_PIO_3, 0x0a81f443 }, | |
100 | { XFER_PIO_2, 0x0a81f454 }, | |
101 | { XFER_PIO_1, 0x0ac1f465 }, | |
102 | { XFER_PIO_0, 0x0ac1f48a } | |
669a5db4 JG |
103 | }; |
104 | ||
fcc2f69a AC |
105 | static struct hpt_clock hpt37x_timings_66[] = { |
106 | { XFER_UDMA_6, 0x1c869c62 }, | |
107 | { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */ | |
108 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
109 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
110 | { XFER_UDMA_2, 0x1c929c62 }, | |
111 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
112 | { XFER_UDMA_0, 0x1c829c62 }, | |
113 | ||
114 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
115 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
116 | { XFER_MW_DMA_0, 0x2c829d2e }, | |
117 | ||
118 | { XFER_PIO_4, 0x0c829c62 }, | |
119 | { XFER_PIO_3, 0x0c829c84 }, | |
120 | { XFER_PIO_2, 0x0c829ca6 }, | |
121 | { XFER_PIO_1, 0x0d029d26 }, | |
122 | { XFER_PIO_0, 0x0d029d5e } | |
669a5db4 JG |
123 | }; |
124 | ||
669a5db4 JG |
125 | |
126 | static const struct hpt_chip hpt370 = { | |
127 | "HPT370", | |
128 | 48, | |
129 | { | |
fcc2f69a | 130 | hpt37x_timings_33, |
669a5db4 JG |
131 | NULL, |
132 | NULL, | |
fcc2f69a | 133 | hpt37x_timings_66 |
669a5db4 JG |
134 | } |
135 | }; | |
136 | ||
137 | static const struct hpt_chip hpt370a = { | |
138 | "HPT370A", | |
139 | 48, | |
140 | { | |
fcc2f69a | 141 | hpt37x_timings_33, |
669a5db4 | 142 | NULL, |
fcc2f69a AC |
143 | hpt37x_timings_50, |
144 | hpt37x_timings_66 | |
669a5db4 JG |
145 | } |
146 | }; | |
147 | ||
148 | static const struct hpt_chip hpt372 = { | |
149 | "HPT372", | |
150 | 55, | |
151 | { | |
fcc2f69a | 152 | hpt37x_timings_33, |
669a5db4 | 153 | NULL, |
fcc2f69a AC |
154 | hpt37x_timings_50, |
155 | hpt37x_timings_66 | |
669a5db4 JG |
156 | } |
157 | }; | |
158 | ||
159 | static const struct hpt_chip hpt302 = { | |
160 | "HPT302", | |
161 | 66, | |
162 | { | |
fcc2f69a | 163 | hpt37x_timings_33, |
669a5db4 | 164 | NULL, |
fcc2f69a AC |
165 | hpt37x_timings_50, |
166 | hpt37x_timings_66 | |
669a5db4 JG |
167 | } |
168 | }; | |
169 | ||
170 | static const struct hpt_chip hpt371 = { | |
171 | "HPT371", | |
172 | 66, | |
173 | { | |
fcc2f69a | 174 | hpt37x_timings_33, |
669a5db4 | 175 | NULL, |
fcc2f69a AC |
176 | hpt37x_timings_50, |
177 | hpt37x_timings_66 | |
669a5db4 JG |
178 | } |
179 | }; | |
180 | ||
181 | static const struct hpt_chip hpt372a = { | |
182 | "HPT372A", | |
183 | 66, | |
184 | { | |
fcc2f69a | 185 | hpt37x_timings_33, |
669a5db4 | 186 | NULL, |
fcc2f69a AC |
187 | hpt37x_timings_50, |
188 | hpt37x_timings_66 | |
669a5db4 JG |
189 | } |
190 | }; | |
191 | ||
192 | static const struct hpt_chip hpt374 = { | |
193 | "HPT374", | |
194 | 48, | |
195 | { | |
fcc2f69a | 196 | hpt37x_timings_33, |
669a5db4 JG |
197 | NULL, |
198 | NULL, | |
199 | NULL | |
200 | } | |
201 | }; | |
202 | ||
203 | /** | |
204 | * hpt37x_find_mode - reset the hpt37x bus | |
205 | * @ap: ATA port | |
206 | * @speed: transfer mode | |
207 | * | |
208 | * Return the 32bit register programming information for this channel | |
209 | * that matches the speed provided. | |
210 | */ | |
85cd7251 | 211 | |
669a5db4 JG |
212 | static u32 hpt37x_find_mode(struct ata_port *ap, int speed) |
213 | { | |
214 | struct hpt_clock *clocks = ap->host->private_data; | |
85cd7251 | 215 | |
669a5db4 JG |
216 | while(clocks->xfer_speed) { |
217 | if (clocks->xfer_speed == speed) | |
218 | return clocks->timing; | |
219 | clocks++; | |
220 | } | |
221 | BUG(); | |
222 | return 0xffffffffU; /* silence compiler warning */ | |
223 | } | |
224 | ||
225 | static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[]) | |
226 | { | |
8bfa79fc | 227 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
669a5db4 JG |
228 | int i = 0; |
229 | ||
8bfa79fc | 230 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
669a5db4 | 231 | |
8bfa79fc TH |
232 | while (list[i] != NULL) { |
233 | if (!strcmp(list[i], model_num)) { | |
85cd7251 | 234 | printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n", |
669a5db4 JG |
235 | modestr, list[i]); |
236 | return 1; | |
237 | } | |
238 | i++; | |
239 | } | |
240 | return 0; | |
241 | } | |
242 | ||
243 | static const char *bad_ata33[] = { | |
244 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", | |
245 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
246 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
247 | "Maxtor 90510D4", | |
248 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
249 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
250 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
251 | NULL | |
252 | }; | |
253 | ||
254 | static const char *bad_ata100_5[] = { | |
255 | "IBM-DTLA-307075", | |
256 | "IBM-DTLA-307060", | |
257 | "IBM-DTLA-307045", | |
258 | "IBM-DTLA-307030", | |
259 | "IBM-DTLA-307020", | |
260 | "IBM-DTLA-307015", | |
261 | "IBM-DTLA-305040", | |
262 | "IBM-DTLA-305030", | |
263 | "IBM-DTLA-305020", | |
264 | "IC35L010AVER07-0", | |
265 | "IC35L020AVER07-0", | |
266 | "IC35L030AVER07-0", | |
267 | "IC35L040AVER07-0", | |
268 | "IC35L060AVER07-0", | |
269 | "WDC AC310200R", | |
270 | NULL | |
271 | }; | |
272 | ||
273 | /** | |
274 | * hpt370_filter - mode selection filter | |
275 | * @ap: ATA interface | |
276 | * @adev: ATA device | |
277 | * | |
278 | * Block UDMA on devices that cause trouble with this controller. | |
279 | */ | |
85cd7251 | 280 | |
669a5db4 JG |
281 | static unsigned long hpt370_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask) |
282 | { | |
6929da44 | 283 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 JG |
284 | if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) |
285 | mask &= ~ATA_MASK_UDMA; | |
286 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) | |
287 | mask &= ~(0x1F << ATA_SHIFT_UDMA); | |
288 | } | |
289 | return ata_pci_default_filter(ap, adev, mask); | |
290 | } | |
291 | ||
292 | /** | |
293 | * hpt370a_filter - mode selection filter | |
294 | * @ap: ATA interface | |
295 | * @adev: ATA device | |
296 | * | |
297 | * Block UDMA on devices that cause trouble with this controller. | |
298 | */ | |
85cd7251 | 299 | |
669a5db4 JG |
300 | static unsigned long hpt370a_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask) |
301 | { | |
302 | if (adev->class != ATA_DEV_ATA) { | |
303 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) | |
304 | mask &= ~ (0x1F << ATA_SHIFT_UDMA); | |
305 | } | |
306 | return ata_pci_default_filter(ap, adev, mask); | |
307 | } | |
85cd7251 | 308 | |
669a5db4 JG |
309 | /** |
310 | * hpt37x_pre_reset - reset the hpt37x bus | |
311 | * @ap: ATA port to reset | |
312 | * | |
313 | * Perform the initial reset handling for the 370/372 and 374 func 0 | |
314 | */ | |
85cd7251 | 315 | |
669a5db4 JG |
316 | static int hpt37x_pre_reset(struct ata_port *ap) |
317 | { | |
318 | u8 scr2, ata66; | |
319 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
b5bf24b9 AC |
320 | static const struct pci_bits hpt37x_enable_bits[] = { |
321 | { 0x50, 1, 0x04, 0x04 }, | |
322 | { 0x54, 1, 0x04, 0x04 } | |
323 | }; | |
324 | if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) | |
325 | return -ENOENT; | |
f20b16ff | 326 | |
669a5db4 JG |
327 | pci_read_config_byte(pdev, 0x5B, &scr2); |
328 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
329 | /* Cable register now active */ | |
330 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
331 | /* Restore state */ | |
332 | pci_write_config_byte(pdev, 0x5B, scr2); | |
85cd7251 | 333 | |
669a5db4 JG |
334 | if (ata66 & (1 << ap->port_no)) |
335 | ap->cbl = ATA_CBL_PATA40; | |
336 | else | |
337 | ap->cbl = ATA_CBL_PATA80; | |
338 | ||
339 | /* Reset the state machine */ | |
fcc2f69a | 340 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 341 | udelay(100); |
85cd7251 | 342 | |
669a5db4 JG |
343 | return ata_std_prereset(ap); |
344 | } | |
345 | ||
346 | /** | |
347 | * hpt37x_error_handler - reset the hpt374 | |
348 | * @ap: ATA port to reset | |
349 | * | |
350 | * Perform probe for HPT37x, except for HPT374 channel 2 | |
351 | */ | |
85cd7251 | 352 | |
669a5db4 JG |
353 | static void hpt37x_error_handler(struct ata_port *ap) |
354 | { | |
355 | ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
356 | } | |
357 | ||
358 | static int hpt374_pre_reset(struct ata_port *ap) | |
359 | { | |
b5bf24b9 AC |
360 | static const struct pci_bits hpt37x_enable_bits[] = { |
361 | { 0x50, 1, 0x04, 0x04 }, | |
362 | { 0x54, 1, 0x04, 0x04 } | |
363 | }; | |
669a5db4 JG |
364 | u16 mcr3, mcr6; |
365 | u8 ata66; | |
669a5db4 | 366 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
b5bf24b9 AC |
367 | |
368 | if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) | |
369 | return -ENOENT; | |
f20b16ff | 370 | |
669a5db4 JG |
371 | /* Do the extra channel work */ |
372 | pci_read_config_word(pdev, 0x52, &mcr3); | |
373 | pci_read_config_word(pdev, 0x56, &mcr6); | |
374 | /* Set bit 15 of 0x52 to enable TCBLID as input | |
375 | Set bit 15 of 0x56 to enable FCBLID as input | |
376 | */ | |
377 | pci_write_config_word(pdev, 0x52, mcr3 | 0x8000); | |
378 | pci_write_config_word(pdev, 0x56, mcr6 | 0x8000); | |
379 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
380 | /* Reset TCBLID/FCBLID to output */ | |
381 | pci_write_config_word(pdev, 0x52, mcr3); | |
382 | pci_write_config_word(pdev, 0x56, mcr6); | |
85cd7251 | 383 | |
669a5db4 JG |
384 | if (ata66 & (1 << ap->port_no)) |
385 | ap->cbl = ATA_CBL_PATA40; | |
386 | else | |
387 | ap->cbl = ATA_CBL_PATA80; | |
388 | ||
389 | /* Reset the state machine */ | |
fcc2f69a | 390 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 391 | udelay(100); |
85cd7251 | 392 | |
669a5db4 JG |
393 | return ata_std_prereset(ap); |
394 | } | |
395 | ||
396 | /** | |
397 | * hpt374_error_handler - reset the hpt374 | |
398 | * @classes: | |
399 | * | |
400 | * The 374 cable detect is a little different due to the extra | |
401 | * channels. The function 0 channels work like usual but function 1 | |
402 | * is special | |
403 | */ | |
85cd7251 | 404 | |
669a5db4 JG |
405 | static void hpt374_error_handler(struct ata_port *ap) |
406 | { | |
407 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
85cd7251 | 408 | |
669a5db4 JG |
409 | if (!(PCI_FUNC(pdev->devfn) & 1)) |
410 | hpt37x_error_handler(ap); | |
411 | else | |
412 | ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
413 | } | |
414 | ||
415 | /** | |
416 | * hpt370_set_piomode - PIO setup | |
417 | * @ap: ATA interface | |
418 | * @adev: device on the interface | |
419 | * | |
85cd7251 | 420 | * Perform PIO mode setup. |
669a5db4 | 421 | */ |
85cd7251 | 422 | |
669a5db4 JG |
423 | static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) |
424 | { | |
425 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
426 | u32 addr1, addr2; | |
427 | u32 reg; | |
428 | u32 mode; | |
429 | u8 fast; | |
430 | ||
431 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
432 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 433 | |
669a5db4 JG |
434 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
435 | pci_read_config_byte(pdev, addr2, &fast); | |
436 | fast &= ~0x02; | |
437 | fast |= 0x01; | |
438 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 439 | |
669a5db4 JG |
440 | pci_read_config_dword(pdev, addr1, ®); |
441 | mode = hpt37x_find_mode(ap, adev->pio_mode); | |
442 | mode &= ~0x8000000; /* No FIFO in PIO */ | |
443 | mode &= ~0x30070000; /* Leave config bits alone */ | |
444 | reg &= 0x30070000; /* Strip timing bits */ | |
445 | pci_write_config_dword(pdev, addr1, reg | mode); | |
446 | } | |
447 | ||
448 | /** | |
449 | * hpt370_set_dmamode - DMA timing setup | |
450 | * @ap: ATA interface | |
451 | * @adev: Device being configured | |
452 | * | |
453 | * Set up the channel for MWDMA or UDMA modes. Much the same as with | |
454 | * PIO, load the mode number and then set MWDMA or UDMA flag. | |
455 | */ | |
85cd7251 | 456 | |
669a5db4 JG |
457 | static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
458 | { | |
459 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
460 | u32 addr1, addr2; | |
461 | u32 reg; | |
462 | u32 mode; | |
463 | u8 fast; | |
464 | ||
465 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
466 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 467 | |
669a5db4 JG |
468 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
469 | pci_read_config_byte(pdev, addr2, &fast); | |
470 | fast &= ~0x02; | |
471 | fast |= 0x01; | |
472 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 473 | |
669a5db4 JG |
474 | pci_read_config_dword(pdev, addr1, ®); |
475 | mode = hpt37x_find_mode(ap, adev->dma_mode); | |
476 | mode |= 0x8000000; /* FIFO in MWDMA or UDMA */ | |
477 | mode &= ~0xC0000000; /* Leave config bits alone */ | |
478 | reg &= 0xC0000000; /* Strip timing bits */ | |
479 | pci_write_config_dword(pdev, addr1, reg | mode); | |
480 | } | |
481 | ||
482 | /** | |
483 | * hpt370_bmdma_start - DMA engine begin | |
484 | * @qc: ATA command | |
485 | * | |
486 | * The 370 and 370A want us to reset the DMA engine each time we | |
487 | * use it. The 372 and later are fine. | |
488 | */ | |
85cd7251 | 489 | |
669a5db4 JG |
490 | static void hpt370_bmdma_start(struct ata_queued_cmd *qc) |
491 | { | |
492 | struct ata_port *ap = qc->ap; | |
493 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
494 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
495 | udelay(10); | |
496 | ata_bmdma_start(qc); | |
497 | } | |
498 | ||
499 | /** | |
500 | * hpt370_bmdma_end - DMA engine stop | |
501 | * @qc: ATA command | |
502 | * | |
503 | * Work around the HPT370 DMA engine. | |
504 | */ | |
85cd7251 | 505 | |
669a5db4 JG |
506 | static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) |
507 | { | |
508 | struct ata_port *ap = qc->ap; | |
509 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
0d5ff566 | 510 | u8 dma_stat = ioread8(ap->ioaddr.bmdma_addr + 2); |
669a5db4 | 511 | u8 dma_cmd; |
0d5ff566 | 512 | void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
85cd7251 | 513 | |
669a5db4 JG |
514 | if (dma_stat & 0x01) { |
515 | udelay(20); | |
0d5ff566 | 516 | dma_stat = ioread8(bmdma + 2); |
669a5db4 JG |
517 | } |
518 | if (dma_stat & 0x01) { | |
519 | /* Clear the engine */ | |
520 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
521 | udelay(10); | |
522 | /* Stop DMA */ | |
0d5ff566 TH |
523 | dma_cmd = ioread8(bmdma ); |
524 | iowrite8(dma_cmd & 0xFE, bmdma); | |
669a5db4 | 525 | /* Clear Error */ |
0d5ff566 TH |
526 | dma_stat = ioread8(bmdma + 2); |
527 | iowrite8(dma_stat | 0x06 , bmdma + 2); | |
669a5db4 JG |
528 | /* Clear the engine */ |
529 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
530 | udelay(10); | |
531 | } | |
532 | ata_bmdma_stop(qc); | |
533 | } | |
534 | ||
535 | /** | |
536 | * hpt372_set_piomode - PIO setup | |
537 | * @ap: ATA interface | |
538 | * @adev: device on the interface | |
539 | * | |
85cd7251 | 540 | * Perform PIO mode setup. |
669a5db4 | 541 | */ |
85cd7251 | 542 | |
669a5db4 JG |
543 | static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) |
544 | { | |
545 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
546 | u32 addr1, addr2; | |
547 | u32 reg; | |
548 | u32 mode; | |
549 | u8 fast; | |
550 | ||
551 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
552 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 553 | |
669a5db4 JG |
554 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
555 | pci_read_config_byte(pdev, addr2, &fast); | |
556 | fast &= ~0x07; | |
557 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 558 | |
669a5db4 JG |
559 | pci_read_config_dword(pdev, addr1, ®); |
560 | mode = hpt37x_find_mode(ap, adev->pio_mode); | |
85cd7251 | 561 | |
669a5db4 JG |
562 | printk("Find mode for %d reports %X\n", adev->pio_mode, mode); |
563 | mode &= ~0x80000000; /* No FIFO in PIO */ | |
564 | mode &= ~0x30070000; /* Leave config bits alone */ | |
565 | reg &= 0x30070000; /* Strip timing bits */ | |
566 | pci_write_config_dword(pdev, addr1, reg | mode); | |
567 | } | |
568 | ||
569 | /** | |
570 | * hpt372_set_dmamode - DMA timing setup | |
571 | * @ap: ATA interface | |
572 | * @adev: Device being configured | |
573 | * | |
574 | * Set up the channel for MWDMA or UDMA modes. Much the same as with | |
575 | * PIO, load the mode number and then set MWDMA or UDMA flag. | |
576 | */ | |
85cd7251 | 577 | |
669a5db4 JG |
578 | static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
579 | { | |
580 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
581 | u32 addr1, addr2; | |
582 | u32 reg; | |
583 | u32 mode; | |
584 | u8 fast; | |
585 | ||
586 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
587 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 588 | |
669a5db4 JG |
589 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
590 | pci_read_config_byte(pdev, addr2, &fast); | |
591 | fast &= ~0x07; | |
592 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 593 | |
669a5db4 JG |
594 | pci_read_config_dword(pdev, addr1, ®); |
595 | mode = hpt37x_find_mode(ap, adev->dma_mode); | |
596 | printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode); | |
597 | mode &= ~0xC0000000; /* Leave config bits alone */ | |
598 | mode |= 0x80000000; /* FIFO in MWDMA or UDMA */ | |
599 | reg &= 0xC0000000; /* Strip timing bits */ | |
600 | pci_write_config_dword(pdev, addr1, reg | mode); | |
601 | } | |
602 | ||
603 | /** | |
604 | * hpt37x_bmdma_end - DMA engine stop | |
605 | * @qc: ATA command | |
606 | * | |
607 | * Clean up after the HPT372 and later DMA engine | |
608 | */ | |
85cd7251 | 609 | |
669a5db4 JG |
610 | static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) |
611 | { | |
612 | struct ata_port *ap = qc->ap; | |
613 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
6929da44 | 614 | int mscreg = 0x50 + 4 * ap->port_no; |
669a5db4 | 615 | u8 bwsr_stat, msc_stat; |
85cd7251 | 616 | |
669a5db4 JG |
617 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
618 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
619 | if (bwsr_stat & (1 << ap->port_no)) | |
620 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
621 | ata_bmdma_stop(qc); | |
622 | } | |
623 | ||
624 | ||
625 | static struct scsi_host_template hpt37x_sht = { | |
626 | .module = THIS_MODULE, | |
627 | .name = DRV_NAME, | |
628 | .ioctl = ata_scsi_ioctl, | |
629 | .queuecommand = ata_scsi_queuecmd, | |
630 | .can_queue = ATA_DEF_QUEUE, | |
631 | .this_id = ATA_SHT_THIS_ID, | |
632 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
633 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
634 | .emulated = ATA_SHT_EMULATED, | |
635 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
636 | .proc_name = DRV_NAME, | |
637 | .dma_boundary = ATA_DMA_BOUNDARY, | |
638 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 639 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
640 | .bios_param = ata_std_bios_param, |
641 | }; | |
642 | ||
643 | /* | |
644 | * Configuration for HPT370 | |
645 | */ | |
85cd7251 | 646 | |
669a5db4 JG |
647 | static struct ata_port_operations hpt370_port_ops = { |
648 | .port_disable = ata_port_disable, | |
649 | .set_piomode = hpt370_set_piomode, | |
650 | .set_dmamode = hpt370_set_dmamode, | |
651 | .mode_filter = hpt370_filter, | |
85cd7251 | 652 | |
669a5db4 JG |
653 | .tf_load = ata_tf_load, |
654 | .tf_read = ata_tf_read, | |
655 | .check_status = ata_check_status, | |
656 | .exec_command = ata_exec_command, | |
657 | .dev_select = ata_std_dev_select, | |
658 | ||
659 | .freeze = ata_bmdma_freeze, | |
660 | .thaw = ata_bmdma_thaw, | |
661 | .error_handler = hpt37x_error_handler, | |
662 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
663 | ||
664 | .bmdma_setup = ata_bmdma_setup, | |
665 | .bmdma_start = hpt370_bmdma_start, | |
666 | .bmdma_stop = hpt370_bmdma_stop, | |
667 | .bmdma_status = ata_bmdma_status, | |
668 | ||
669 | .qc_prep = ata_qc_prep, | |
670 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 671 | |
0d5ff566 | 672 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
673 | |
674 | .irq_handler = ata_interrupt, | |
675 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
676 | .irq_on = ata_irq_on, |
677 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
678 | |
679 | .port_start = ata_port_start, | |
85cd7251 | 680 | }; |
669a5db4 JG |
681 | |
682 | /* | |
683 | * Configuration for HPT370A. Close to 370 but less filters | |
684 | */ | |
85cd7251 | 685 | |
669a5db4 JG |
686 | static struct ata_port_operations hpt370a_port_ops = { |
687 | .port_disable = ata_port_disable, | |
688 | .set_piomode = hpt370_set_piomode, | |
689 | .set_dmamode = hpt370_set_dmamode, | |
690 | .mode_filter = hpt370a_filter, | |
85cd7251 | 691 | |
669a5db4 JG |
692 | .tf_load = ata_tf_load, |
693 | .tf_read = ata_tf_read, | |
694 | .check_status = ata_check_status, | |
695 | .exec_command = ata_exec_command, | |
696 | .dev_select = ata_std_dev_select, | |
697 | ||
698 | .freeze = ata_bmdma_freeze, | |
699 | .thaw = ata_bmdma_thaw, | |
700 | .error_handler = hpt37x_error_handler, | |
701 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
702 | ||
703 | .bmdma_setup = ata_bmdma_setup, | |
704 | .bmdma_start = hpt370_bmdma_start, | |
705 | .bmdma_stop = hpt370_bmdma_stop, | |
706 | .bmdma_status = ata_bmdma_status, | |
707 | ||
708 | .qc_prep = ata_qc_prep, | |
709 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 710 | |
0d5ff566 | 711 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
712 | |
713 | .irq_handler = ata_interrupt, | |
714 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
715 | .irq_on = ata_irq_on, |
716 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
717 | |
718 | .port_start = ata_port_start, | |
85cd7251 | 719 | }; |
669a5db4 JG |
720 | |
721 | /* | |
722 | * Configuration for HPT372, HPT371, HPT302. Slightly different PIO | |
723 | * and DMA mode setting functionality. | |
724 | */ | |
85cd7251 | 725 | |
669a5db4 JG |
726 | static struct ata_port_operations hpt372_port_ops = { |
727 | .port_disable = ata_port_disable, | |
728 | .set_piomode = hpt372_set_piomode, | |
729 | .set_dmamode = hpt372_set_dmamode, | |
730 | .mode_filter = ata_pci_default_filter, | |
85cd7251 | 731 | |
669a5db4 JG |
732 | .tf_load = ata_tf_load, |
733 | .tf_read = ata_tf_read, | |
734 | .check_status = ata_check_status, | |
735 | .exec_command = ata_exec_command, | |
736 | .dev_select = ata_std_dev_select, | |
737 | ||
738 | .freeze = ata_bmdma_freeze, | |
739 | .thaw = ata_bmdma_thaw, | |
740 | .error_handler = hpt37x_error_handler, | |
741 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
742 | ||
743 | .bmdma_setup = ata_bmdma_setup, | |
744 | .bmdma_start = ata_bmdma_start, | |
745 | .bmdma_stop = hpt37x_bmdma_stop, | |
746 | .bmdma_status = ata_bmdma_status, | |
747 | ||
748 | .qc_prep = ata_qc_prep, | |
749 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 750 | |
0d5ff566 | 751 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
752 | |
753 | .irq_handler = ata_interrupt, | |
754 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
755 | .irq_on = ata_irq_on, |
756 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
757 | |
758 | .port_start = ata_port_start, | |
85cd7251 | 759 | }; |
669a5db4 JG |
760 | |
761 | /* | |
762 | * Configuration for HPT374. Mode setting works like 372 and friends | |
763 | * but we have a different cable detection procedure. | |
764 | */ | |
85cd7251 | 765 | |
669a5db4 JG |
766 | static struct ata_port_operations hpt374_port_ops = { |
767 | .port_disable = ata_port_disable, | |
768 | .set_piomode = hpt372_set_piomode, | |
769 | .set_dmamode = hpt372_set_dmamode, | |
770 | .mode_filter = ata_pci_default_filter, | |
85cd7251 | 771 | |
669a5db4 JG |
772 | .tf_load = ata_tf_load, |
773 | .tf_read = ata_tf_read, | |
774 | .check_status = ata_check_status, | |
775 | .exec_command = ata_exec_command, | |
776 | .dev_select = ata_std_dev_select, | |
777 | ||
778 | .freeze = ata_bmdma_freeze, | |
779 | .thaw = ata_bmdma_thaw, | |
780 | .error_handler = hpt374_error_handler, | |
781 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
782 | ||
783 | .bmdma_setup = ata_bmdma_setup, | |
784 | .bmdma_start = ata_bmdma_start, | |
785 | .bmdma_stop = hpt37x_bmdma_stop, | |
786 | .bmdma_status = ata_bmdma_status, | |
787 | ||
788 | .qc_prep = ata_qc_prep, | |
789 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 790 | |
0d5ff566 | 791 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
792 | |
793 | .irq_handler = ata_interrupt, | |
794 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
795 | .irq_on = ata_irq_on, |
796 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
797 | |
798 | .port_start = ata_port_start, | |
85cd7251 | 799 | }; |
669a5db4 JG |
800 | |
801 | /** | |
802 | * htp37x_clock_slot - Turn timing to PC clock entry | |
803 | * @freq: Reported frequency timing | |
804 | * @base: Base timing | |
805 | * | |
806 | * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 | |
807 | * and 3 for 66Mhz) | |
808 | */ | |
85cd7251 | 809 | |
669a5db4 JG |
810 | static int hpt37x_clock_slot(unsigned int freq, unsigned int base) |
811 | { | |
812 | unsigned int f = (base * freq) / 192; /* Mhz */ | |
813 | if (f < 40) | |
814 | return 0; /* 33Mhz slot */ | |
815 | if (f < 45) | |
816 | return 1; /* 40Mhz slot */ | |
817 | if (f < 55) | |
818 | return 2; /* 50Mhz slot */ | |
819 | return 3; /* 60Mhz slot */ | |
820 | } | |
821 | ||
822 | /** | |
823 | * hpt37x_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 824 | * @dev: PCI device |
669a5db4 JG |
825 | * |
826 | * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this | |
827 | * succeeds | |
828 | */ | |
829 | ||
830 | static int hpt37x_calibrate_dpll(struct pci_dev *dev) | |
831 | { | |
832 | u8 reg5b; | |
833 | u32 reg5c; | |
834 | int tries; | |
85cd7251 | 835 | |
669a5db4 JG |
836 | for(tries = 0; tries < 0x5000; tries++) { |
837 | udelay(50); | |
838 | pci_read_config_byte(dev, 0x5b, ®5b); | |
839 | if (reg5b & 0x80) { | |
840 | /* See if it stays set */ | |
841 | for(tries = 0; tries < 0x1000; tries ++) { | |
842 | pci_read_config_byte(dev, 0x5b, ®5b); | |
843 | /* Failed ? */ | |
844 | if ((reg5b & 0x80) == 0) | |
845 | return 0; | |
846 | } | |
847 | /* Turn off tuning, we have the DPLL set */ | |
848 | pci_read_config_dword(dev, 0x5c, ®5c); | |
849 | pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); | |
850 | return 1; | |
851 | } | |
852 | } | |
853 | /* Never went stable */ | |
854 | return 0; | |
855 | } | |
856 | /** | |
857 | * hpt37x_init_one - Initialise an HPT37X/302 | |
858 | * @dev: PCI device | |
859 | * @id: Entry in match table | |
860 | * | |
861 | * Initialise an HPT37x device. There are some interesting complications | |
862 | * here. Firstly the chip may report 366 and be one of several variants. | |
863 | * Secondly all the timings depend on the clock for the chip which we must | |
864 | * detect and look up | |
865 | * | |
866 | * This is the known chip mappings. It may be missing a couple of later | |
867 | * releases. | |
868 | * | |
869 | * Chip version PCI Rev Notes | |
870 | * HPT366 4 (HPT366) 0 Other driver | |
871 | * HPT366 4 (HPT366) 1 Other driver | |
872 | * HPT368 4 (HPT366) 2 Other driver | |
873 | * HPT370 4 (HPT366) 3 UDMA100 | |
874 | * HPT370A 4 (HPT366) 4 UDMA100 | |
875 | * HPT372 4 (HPT366) 5 UDMA133 (1) | |
876 | * HPT372N 4 (HPT366) 6 Other driver | |
877 | * HPT372A 5 (HPT372) 1 UDMA133 (1) | |
878 | * HPT372N 5 (HPT372) 2 Other driver | |
879 | * HPT302 6 (HPT302) 1 UDMA133 | |
880 | * HPT302N 6 (HPT302) 2 Other driver | |
881 | * HPT371 7 (HPT371) * UDMA133 | |
882 | * HPT374 8 (HPT374) * UDMA133 4 channel | |
883 | * HPT372N 9 (HPT372N) * Other driver | |
884 | * | |
885 | * (1) UDMA133 support depends on the bus clock | |
886 | */ | |
85cd7251 | 887 | |
669a5db4 JG |
888 | static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
889 | { | |
890 | /* HPT370 - UDMA100 */ | |
891 | static struct ata_port_info info_hpt370 = { | |
892 | .sht = &hpt37x_sht, | |
893 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
894 | .pio_mask = 0x1f, | |
895 | .mwdma_mask = 0x07, | |
896 | .udma_mask = 0x3f, | |
897 | .port_ops = &hpt370_port_ops | |
898 | }; | |
899 | /* HPT370A - UDMA100 */ | |
900 | static struct ata_port_info info_hpt370a = { | |
901 | .sht = &hpt37x_sht, | |
902 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
903 | .pio_mask = 0x1f, | |
904 | .mwdma_mask = 0x07, | |
905 | .udma_mask = 0x3f, | |
906 | .port_ops = &hpt370a_port_ops | |
907 | }; | |
fcc2f69a AC |
908 | /* HPT370 - UDMA100 */ |
909 | static struct ata_port_info info_hpt370_33 = { | |
910 | .sht = &hpt37x_sht, | |
911 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
912 | .pio_mask = 0x1f, | |
913 | .mwdma_mask = 0x07, | |
914 | .udma_mask = 0x0f, | |
915 | .port_ops = &hpt370_port_ops | |
916 | }; | |
917 | /* HPT370A - UDMA100 */ | |
918 | static struct ata_port_info info_hpt370a_33 = { | |
919 | .sht = &hpt37x_sht, | |
920 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
921 | .pio_mask = 0x1f, | |
922 | .mwdma_mask = 0x07, | |
923 | .udma_mask = 0x0f, | |
924 | .port_ops = &hpt370a_port_ops | |
925 | }; | |
669a5db4 JG |
926 | /* HPT371, 372 and friends - UDMA133 */ |
927 | static struct ata_port_info info_hpt372 = { | |
928 | .sht = &hpt37x_sht, | |
929 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
930 | .pio_mask = 0x1f, | |
931 | .mwdma_mask = 0x07, | |
932 | .udma_mask = 0x7f, | |
933 | .port_ops = &hpt372_port_ops | |
934 | }; | |
935 | /* HPT371, 372 and friends - UDMA100 at 50MHz clock */ | |
936 | static struct ata_port_info info_hpt372_50 = { | |
937 | .sht = &hpt37x_sht, | |
938 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
939 | .pio_mask = 0x1f, | |
940 | .mwdma_mask = 0x07, | |
941 | .udma_mask = 0x3f, | |
942 | .port_ops = &hpt372_port_ops | |
943 | }; | |
944 | /* HPT374 - UDMA133 */ | |
945 | static struct ata_port_info info_hpt374 = { | |
946 | .sht = &hpt37x_sht, | |
947 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
948 | .pio_mask = 0x1f, | |
949 | .mwdma_mask = 0x07, | |
950 | .udma_mask = 0x7f, | |
951 | .port_ops = &hpt374_port_ops | |
952 | }; | |
953 | ||
954 | static const int MHz[4] = { 33, 40, 50, 66 }; | |
955 | ||
956 | struct ata_port_info *port_info[2]; | |
957 | struct ata_port_info *port; | |
958 | ||
959 | u8 irqmask; | |
960 | u32 class_rev; | |
fcc2f69a | 961 | u8 mcr1; |
669a5db4 | 962 | u32 freq; |
fcc2f69a AC |
963 | int prefer_dpll = 1; |
964 | ||
965 | unsigned long iobase = pci_resource_start(dev, 4); | |
669a5db4 JG |
966 | |
967 | const struct hpt_chip *chip_table; | |
968 | int clock_slot; | |
969 | ||
970 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
971 | class_rev &= 0xFF; | |
85cd7251 | 972 | |
669a5db4 JG |
973 | if (dev->device == PCI_DEVICE_ID_TTI_HPT366) { |
974 | /* May be a later chip in disguise. Check */ | |
975 | /* Older chips are in the HPT366 driver. Ignore them */ | |
976 | if (class_rev < 3) | |
977 | return -ENODEV; | |
978 | /* N series chips have their own driver. Ignore */ | |
979 | if (class_rev == 6) | |
980 | return -ENODEV; | |
981 | ||
85cd7251 | 982 | switch(class_rev) { |
669a5db4 JG |
983 | case 3: |
984 | port = &info_hpt370; | |
985 | chip_table = &hpt370; | |
fcc2f69a | 986 | prefer_dpll = 0; |
669a5db4 JG |
987 | break; |
988 | case 4: | |
989 | port = &info_hpt370a; | |
990 | chip_table = &hpt370a; | |
fcc2f69a | 991 | prefer_dpll = 0; |
669a5db4 JG |
992 | break; |
993 | case 5: | |
994 | port = &info_hpt372; | |
995 | chip_table = &hpt372; | |
996 | break; | |
997 | default: | |
998 | printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev); | |
999 | return -ENODEV; | |
1000 | } | |
1001 | } else { | |
1002 | switch(dev->device) { | |
1003 | case PCI_DEVICE_ID_TTI_HPT372: | |
1004 | /* 372N if rev >= 2*/ | |
1005 | if (class_rev >= 2) | |
1006 | return -ENODEV; | |
1007 | port = &info_hpt372; | |
1008 | chip_table = &hpt372a; | |
1009 | break; | |
1010 | case PCI_DEVICE_ID_TTI_HPT302: | |
1011 | /* 302N if rev > 1 */ | |
1012 | if (class_rev > 1) | |
1013 | return -ENODEV; | |
1014 | port = &info_hpt372; | |
1015 | /* Check this */ | |
1016 | chip_table = &hpt302; | |
1017 | break; | |
1018 | case PCI_DEVICE_ID_TTI_HPT371: | |
fcc2f69a AC |
1019 | if (class_rev > 1) |
1020 | return -ENODEV; | |
669a5db4 JG |
1021 | port = &info_hpt372; |
1022 | chip_table = &hpt371; | |
fcc2f69a AC |
1023 | /* Single channel device, paster is not present |
1024 | but the NIOS (or us for non x86) must mark it | |
1025 | absent */ | |
1026 | pci_read_config_byte(dev, 0x50, &mcr1); | |
1027 | mcr1 &= ~0x04; | |
1028 | pci_write_config_byte(dev, 0x50, mcr1); | |
669a5db4 JG |
1029 | break; |
1030 | case PCI_DEVICE_ID_TTI_HPT374: | |
1031 | chip_table = &hpt374; | |
1032 | port = &info_hpt374; | |
1033 | break; | |
1034 | default: | |
1035 | printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device); | |
1036 | return -ENODEV; | |
1037 | } | |
1038 | } | |
1039 | /* Ok so this is a chip we support */ | |
1040 | ||
1041 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
1042 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
1043 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
1044 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
1045 | ||
1046 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
1047 | irqmask &= ~0x10; | |
1048 | pci_write_config_byte(dev, 0x5a, irqmask); | |
1049 | ||
1050 | /* | |
1051 | * default to pci clock. make sure MA15/16 are set to output | |
1052 | * to prevent drives having problems with 40-pin cables. Needed | |
1053 | * for some drives such as IBM-DTLA which will not enter ready | |
1054 | * state on reset when PDIAG is a input. | |
1055 | */ | |
1056 | ||
85cd7251 | 1057 | pci_write_config_byte(dev, 0x5b, 0x23); |
fcc2f69a AC |
1058 | |
1059 | /* | |
1060 | * HighPoint does this for HPT372A. | |
1061 | * NOTE: This register is only writeable via I/O space. | |
1062 | */ | |
1063 | if (chip_table == &hpt372a) | |
1064 | outb(0x0e, iobase + 0x9c); | |
85cd7251 | 1065 | |
fcc2f69a AC |
1066 | /* Some devices do not let this value be accessed via PCI space |
1067 | according to the old driver */ | |
1068 | ||
1069 | freq = inl(iobase + 0x90); | |
669a5db4 JG |
1070 | if ((freq >> 12) != 0xABCDE) { |
1071 | int i; | |
1072 | u8 sr; | |
1073 | u32 total = 0; | |
85cd7251 | 1074 | |
669a5db4 | 1075 | printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n"); |
85cd7251 | 1076 | |
669a5db4 JG |
1077 | /* This is the process the HPT371 BIOS is reported to use */ |
1078 | for(i = 0; i < 128; i++) { | |
1079 | pci_read_config_byte(dev, 0x78, &sr); | |
fcc2f69a | 1080 | total += sr & 0x1FF; |
669a5db4 JG |
1081 | udelay(15); |
1082 | } | |
1083 | freq = total / 128; | |
1084 | } | |
1085 | freq &= 0x1FF; | |
85cd7251 | 1086 | |
669a5db4 JG |
1087 | /* |
1088 | * Turn the frequency check into a band and then find a timing | |
1089 | * table to match it. | |
1090 | */ | |
fcc2f69a | 1091 | |
669a5db4 | 1092 | clock_slot = hpt37x_clock_slot(freq, chip_table->base); |
fcc2f69a | 1093 | if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) { |
669a5db4 JG |
1094 | /* |
1095 | * We need to try PLL mode instead | |
fcc2f69a AC |
1096 | * |
1097 | * For non UDMA133 capable devices we should | |
1098 | * use a 50MHz DPLL by choice | |
669a5db4 | 1099 | */ |
fcc2f69a | 1100 | unsigned int f_low, f_high; |
669a5db4 | 1101 | int adjust; |
fcc2f69a AC |
1102 | |
1103 | clock_slot = 2; | |
1104 | if (port->udma_mask & 0xE0) | |
1105 | clock_slot = 3; | |
1106 | ||
1107 | f_low = (MHz[clock_slot] * chip_table->base) / 192; | |
1108 | f_high = f_low + 2; | |
1109 | ||
1110 | /* Select the DPLL clock. */ | |
1111 | pci_write_config_byte(dev, 0x5b, 0x21); | |
85cd7251 | 1112 | |
669a5db4 JG |
1113 | for(adjust = 0; adjust < 8; adjust++) { |
1114 | if (hpt37x_calibrate_dpll(dev)) | |
1115 | break; | |
1116 | /* See if it'll settle at a fractionally different clock */ | |
1117 | if ((adjust & 3) == 3) { | |
1118 | f_low --; | |
1119 | f_high ++; | |
1120 | } | |
1121 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); | |
1122 | } | |
1123 | if (adjust == 8) { | |
1124 | printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n"); | |
1125 | return -ENODEV; | |
1126 | } | |
fcc2f69a AC |
1127 | if (clock_slot == 3) |
1128 | port->private_data = (void *)hpt37x_timings_66; | |
1129 | else | |
1130 | port->private_data = (void *)hpt37x_timings_50; | |
85cd7251 | 1131 | |
669a5db4 JG |
1132 | printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]); |
1133 | } else { | |
1134 | port->private_data = (void *)chip_table->clocks[clock_slot]; | |
1135 | /* | |
1136 | * Perform a final fixup. The 371 and 372 clock determines | |
fcc2f69a | 1137 | * if UDMA133 is available. (FIXME: should we use DPLL then ?) |
669a5db4 | 1138 | */ |
85cd7251 | 1139 | |
669a5db4 JG |
1140 | if (clock_slot == 2 && chip_table == &hpt372) { /* 50Mhz */ |
1141 | printk(KERN_WARNING "pata_hpt37x: No UDMA133 support available with 50MHz bus clock.\n"); | |
1142 | if (port == &info_hpt372) | |
1143 | port = &info_hpt372_50; | |
1144 | else BUG(); | |
1145 | } | |
fcc2f69a AC |
1146 | if (clock_slot < 2 && port == &info_hpt370) |
1147 | port = &info_hpt370_33; | |
1148 | if (clock_slot < 2 && port == &info_hpt370a) | |
1149 | port = &info_hpt370a_33; | |
669a5db4 JG |
1150 | printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]); |
1151 | } | |
fcc2f69a | 1152 | |
85cd7251 | 1153 | port_info[0] = port_info[1] = port; |
669a5db4 JG |
1154 | /* Now kick off ATA set up */ |
1155 | return ata_pci_init_one(dev, port_info, 2); | |
1156 | } | |
1157 | ||
2d2744fc JG |
1158 | static const struct pci_device_id hpt37x[] = { |
1159 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
1160 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, | |
1161 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, | |
1162 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, | |
1163 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
1164 | ||
1165 | { }, | |
669a5db4 JG |
1166 | }; |
1167 | ||
1168 | static struct pci_driver hpt37x_pci_driver = { | |
2d2744fc | 1169 | .name = DRV_NAME, |
669a5db4 JG |
1170 | .id_table = hpt37x, |
1171 | .probe = hpt37x_init_one, | |
1172 | .remove = ata_pci_remove_one | |
1173 | }; | |
1174 | ||
1175 | static int __init hpt37x_init(void) | |
1176 | { | |
1177 | return pci_register_driver(&hpt37x_pci_driver); | |
1178 | } | |
1179 | ||
669a5db4 JG |
1180 | static void __exit hpt37x_exit(void) |
1181 | { | |
1182 | pci_unregister_driver(&hpt37x_pci_driver); | |
1183 | } | |
1184 | ||
669a5db4 JG |
1185 | MODULE_AUTHOR("Alan Cox"); |
1186 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); | |
1187 | MODULE_LICENSE("GPL"); | |
1188 | MODULE_DEVICE_TABLE(pci, hpt37x); | |
1189 | MODULE_VERSION(DRV_VERSION); | |
1190 | ||
1191 | module_init(hpt37x_init); | |
1192 | module_exit(hpt37x_exit); |