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669a5db4 JG |
1 | /* |
2 | * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers. | |
3 | * | |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
11 | * | |
12 | * TODO | |
13 | * PLL mode | |
14 | * Look into engine reset on timeout errors. Should not be | |
15 | * required. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/blkdev.h> | |
23 | #include <linux/delay.h> | |
24 | #include <scsi/scsi_host.h> | |
25 | #include <linux/libata.h> | |
26 | ||
27 | #define DRV_NAME "pata_hpt37x" | |
6929da44 | 28 | #define DRV_VERSION "0.5.2" |
669a5db4 JG |
29 | |
30 | struct hpt_clock { | |
31 | u8 xfer_speed; | |
32 | u32 timing; | |
33 | }; | |
34 | ||
35 | struct hpt_chip { | |
36 | const char *name; | |
37 | unsigned int base; | |
38 | struct hpt_clock const *clocks[4]; | |
39 | }; | |
40 | ||
41 | /* key for bus clock timings | |
42 | * bit | |
43 | * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW | |
44 | * DMA. cycles = value + 1 | |
45 | * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW | |
46 | * DMA. cycles = value + 1 | |
47 | * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file | |
48 | * register access. | |
49 | * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file | |
50 | * register access. | |
51 | * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer. | |
52 | * during task file register access. | |
53 | * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA | |
54 | * xfer. | |
55 | * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task | |
56 | * register access. | |
57 | * 28 UDMA enable | |
58 | * 29 DMA enable | |
59 | * 30 PIO_MST enable. if set, the chip is in bus master mode during | |
60 | * PIO. | |
61 | * 31 FIFO enable. | |
62 | */ | |
63 | ||
64 | /* from highpoint documentation. these are old values */ | |
65 | static const struct hpt_clock hpt370_timings_33[] = { | |
66 | /* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */ | |
67 | { XFER_UDMA_5, 0x16454e31 }, | |
68 | { XFER_UDMA_4, 0x16454e31 }, | |
69 | { XFER_UDMA_3, 0x166d4e31 }, | |
70 | { XFER_UDMA_2, 0x16494e31 }, | |
71 | { XFER_UDMA_1, 0x164d4e31 }, | |
72 | { XFER_UDMA_0, 0x16514e31 }, | |
73 | ||
74 | { XFER_MW_DMA_2, 0x26514e21 }, | |
75 | { XFER_MW_DMA_1, 0x26514e33 }, | |
76 | { XFER_MW_DMA_0, 0x26514e97 }, | |
77 | ||
78 | { XFER_PIO_4, 0x06514e21 }, | |
79 | { XFER_PIO_3, 0x06514e22 }, | |
80 | { XFER_PIO_2, 0x06514e33 }, | |
81 | { XFER_PIO_1, 0x06914e43 }, | |
82 | { XFER_PIO_0, 0x06914e57 }, | |
83 | { 0, 0x06514e57 } | |
84 | }; | |
85 | ||
86 | static const struct hpt_clock hpt370_timings_66[] = { | |
87 | { XFER_UDMA_5, 0x14846231 }, | |
88 | { XFER_UDMA_4, 0x14886231 }, | |
89 | { XFER_UDMA_3, 0x148c6231 }, | |
90 | { XFER_UDMA_2, 0x148c6231 }, | |
91 | { XFER_UDMA_1, 0x14906231 }, | |
92 | { XFER_UDMA_0, 0x14986231 }, | |
93 | ||
94 | { XFER_MW_DMA_2, 0x26514e21 }, | |
95 | { XFER_MW_DMA_1, 0x26514e33 }, | |
96 | { XFER_MW_DMA_0, 0x26514e97 }, | |
97 | ||
98 | { XFER_PIO_4, 0x06514e21 }, | |
99 | { XFER_PIO_3, 0x06514e22 }, | |
100 | { XFER_PIO_2, 0x06514e33 }, | |
101 | { XFER_PIO_1, 0x06914e43 }, | |
102 | { XFER_PIO_0, 0x06914e57 }, | |
103 | { 0, 0x06514e57 } | |
104 | }; | |
105 | ||
106 | /* these are the current (4 sep 2001) timings from highpoint */ | |
107 | static const struct hpt_clock hpt370a_timings_33[] = { | |
108 | { XFER_UDMA_5, 0x12446231 }, | |
109 | { XFER_UDMA_4, 0x12446231 }, | |
110 | { XFER_UDMA_3, 0x126c6231 }, | |
111 | { XFER_UDMA_2, 0x12486231 }, | |
112 | { XFER_UDMA_1, 0x124c6233 }, | |
113 | { XFER_UDMA_0, 0x12506297 }, | |
114 | ||
115 | { XFER_MW_DMA_2, 0x22406c31 }, | |
116 | { XFER_MW_DMA_1, 0x22406c33 }, | |
117 | { XFER_MW_DMA_0, 0x22406c97 }, | |
118 | ||
119 | { XFER_PIO_4, 0x06414e31 }, | |
120 | { XFER_PIO_3, 0x06414e42 }, | |
121 | { XFER_PIO_2, 0x06414e53 }, | |
122 | { XFER_PIO_1, 0x06814e93 }, | |
123 | { XFER_PIO_0, 0x06814ea7 }, | |
124 | { 0, 0x06814ea7 } | |
125 | }; | |
126 | ||
127 | /* 2x 33MHz timings */ | |
128 | static const struct hpt_clock hpt370a_timings_66[] = { | |
129 | { XFER_UDMA_5, 0x1488e673 }, | |
130 | { XFER_UDMA_4, 0x1488e673 }, | |
131 | { XFER_UDMA_3, 0x1498e673 }, | |
132 | { XFER_UDMA_2, 0x1490e673 }, | |
133 | { XFER_UDMA_1, 0x1498e677 }, | |
134 | { XFER_UDMA_0, 0x14a0e73f }, | |
135 | ||
136 | { XFER_MW_DMA_2, 0x2480fa73 }, | |
85cd7251 | 137 | { XFER_MW_DMA_1, 0x2480fa77 }, |
669a5db4 JG |
138 | { XFER_MW_DMA_0, 0x2480fb3f }, |
139 | ||
140 | { XFER_PIO_4, 0x0c82be73 }, | |
141 | { XFER_PIO_3, 0x0c82be95 }, | |
142 | { XFER_PIO_2, 0x0c82beb7 }, | |
143 | { XFER_PIO_1, 0x0d02bf37 }, | |
144 | { XFER_PIO_0, 0x0d02bf5f }, | |
145 | { 0, 0x0d02bf5f } | |
146 | }; | |
147 | ||
148 | static const struct hpt_clock hpt370a_timings_50[] = { | |
149 | { XFER_UDMA_5, 0x12848242 }, | |
150 | { XFER_UDMA_4, 0x12ac8242 }, | |
151 | { XFER_UDMA_3, 0x128c8242 }, | |
152 | { XFER_UDMA_2, 0x120c8242 }, | |
153 | { XFER_UDMA_1, 0x12148254 }, | |
154 | { XFER_UDMA_0, 0x121882ea }, | |
155 | ||
156 | { XFER_MW_DMA_2, 0x22808242 }, | |
157 | { XFER_MW_DMA_1, 0x22808254 }, | |
158 | { XFER_MW_DMA_0, 0x228082ea }, | |
159 | ||
160 | { XFER_PIO_4, 0x0a81f442 }, | |
161 | { XFER_PIO_3, 0x0a81f443 }, | |
162 | { XFER_PIO_2, 0x0a81f454 }, | |
163 | { XFER_PIO_1, 0x0ac1f465 }, | |
164 | { XFER_PIO_0, 0x0ac1f48a }, | |
165 | { 0, 0x0ac1f48a } | |
166 | }; | |
167 | ||
168 | static const struct hpt_clock hpt372_timings_33[] = { | |
169 | { XFER_UDMA_6, 0x1c81dc62 }, | |
170 | { XFER_UDMA_5, 0x1c6ddc62 }, | |
171 | { XFER_UDMA_4, 0x1c8ddc62 }, | |
172 | { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */ | |
173 | { XFER_UDMA_2, 0x1c91dc62 }, | |
174 | { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */ | |
175 | { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */ | |
176 | ||
177 | { XFER_MW_DMA_2, 0x2c829262 }, | |
178 | { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */ | |
179 | { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */ | |
180 | ||
181 | { XFER_PIO_4, 0x0c829c62 }, | |
182 | { XFER_PIO_3, 0x0c829c84 }, | |
183 | { XFER_PIO_2, 0x0c829ca6 }, | |
184 | { XFER_PIO_1, 0x0d029d26 }, | |
185 | { XFER_PIO_0, 0x0d029d5e }, | |
186 | { 0, 0x0d029d5e } | |
187 | }; | |
188 | ||
189 | static const struct hpt_clock hpt372_timings_50[] = { | |
190 | { XFER_UDMA_5, 0x12848242 }, | |
191 | { XFER_UDMA_4, 0x12ac8242 }, | |
192 | { XFER_UDMA_3, 0x128c8242 }, | |
193 | { XFER_UDMA_2, 0x120c8242 }, | |
194 | { XFER_UDMA_1, 0x12148254 }, | |
195 | { XFER_UDMA_0, 0x121882ea }, | |
196 | ||
197 | { XFER_MW_DMA_2, 0x22808242 }, | |
198 | { XFER_MW_DMA_1, 0x22808254 }, | |
199 | { XFER_MW_DMA_0, 0x228082ea }, | |
200 | ||
201 | { XFER_PIO_4, 0x0a81f442 }, | |
202 | { XFER_PIO_3, 0x0a81f443 }, | |
203 | { XFER_PIO_2, 0x0a81f454 }, | |
204 | { XFER_PIO_1, 0x0ac1f465 }, | |
205 | { XFER_PIO_0, 0x0ac1f48a }, | |
206 | { 0, 0x0a81f443 } | |
207 | }; | |
208 | ||
209 | static const struct hpt_clock hpt372_timings_66[] = { | |
210 | { XFER_UDMA_6, 0x1c869c62 }, | |
211 | { XFER_UDMA_5, 0x1cae9c62 }, | |
212 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
213 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
214 | { XFER_UDMA_2, 0x1c929c62 }, | |
215 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
216 | { XFER_UDMA_0, 0x1c829c62 }, | |
217 | ||
218 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
219 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
220 | { XFER_MW_DMA_0, 0x2c829d2e }, | |
221 | ||
222 | { XFER_PIO_4, 0x0c829c62 }, | |
223 | { XFER_PIO_3, 0x0c829c84 }, | |
224 | { XFER_PIO_2, 0x0c829ca6 }, | |
225 | { XFER_PIO_1, 0x0d029d26 }, | |
226 | { XFER_PIO_0, 0x0d029d5e }, | |
227 | { 0, 0x0d029d26 } | |
228 | }; | |
229 | ||
230 | static const struct hpt_clock hpt374_timings_33[] = { | |
231 | { XFER_UDMA_6, 0x12808242 }, | |
232 | { XFER_UDMA_5, 0x12848242 }, | |
233 | { XFER_UDMA_4, 0x12ac8242 }, | |
234 | { XFER_UDMA_3, 0x128c8242 }, | |
235 | { XFER_UDMA_2, 0x120c8242 }, | |
236 | { XFER_UDMA_1, 0x12148254 }, | |
237 | { XFER_UDMA_0, 0x121882ea }, | |
238 | ||
239 | { XFER_MW_DMA_2, 0x22808242 }, | |
240 | { XFER_MW_DMA_1, 0x22808254 }, | |
241 | { XFER_MW_DMA_0, 0x228082ea }, | |
242 | ||
243 | { XFER_PIO_4, 0x0a81f442 }, | |
244 | { XFER_PIO_3, 0x0a81f443 }, | |
245 | { XFER_PIO_2, 0x0a81f454 }, | |
246 | { XFER_PIO_1, 0x0ac1f465 }, | |
247 | { XFER_PIO_0, 0x0ac1f48a }, | |
248 | { 0, 0x06814e93 } | |
249 | }; | |
250 | ||
251 | static const struct hpt_chip hpt370 = { | |
252 | "HPT370", | |
253 | 48, | |
254 | { | |
255 | hpt370_timings_33, | |
256 | NULL, | |
257 | NULL, | |
258 | hpt370_timings_66 | |
259 | } | |
260 | }; | |
261 | ||
262 | static const struct hpt_chip hpt370a = { | |
263 | "HPT370A", | |
264 | 48, | |
265 | { | |
266 | hpt370a_timings_33, | |
267 | NULL, | |
268 | hpt370a_timings_50, | |
269 | hpt370a_timings_66 | |
270 | } | |
271 | }; | |
272 | ||
273 | static const struct hpt_chip hpt372 = { | |
274 | "HPT372", | |
275 | 55, | |
276 | { | |
277 | hpt372_timings_33, | |
278 | NULL, | |
279 | hpt372_timings_50, | |
280 | hpt372_timings_66 | |
281 | } | |
282 | }; | |
283 | ||
284 | static const struct hpt_chip hpt302 = { | |
285 | "HPT302", | |
286 | 66, | |
287 | { | |
288 | hpt372_timings_33, | |
289 | NULL, | |
290 | hpt372_timings_50, | |
291 | hpt372_timings_66 | |
292 | } | |
293 | }; | |
294 | ||
295 | static const struct hpt_chip hpt371 = { | |
296 | "HPT371", | |
297 | 66, | |
298 | { | |
299 | hpt372_timings_33, | |
300 | NULL, | |
301 | hpt372_timings_50, | |
302 | hpt372_timings_66 | |
303 | } | |
304 | }; | |
305 | ||
306 | static const struct hpt_chip hpt372a = { | |
307 | "HPT372A", | |
308 | 66, | |
309 | { | |
310 | hpt372_timings_33, | |
311 | NULL, | |
312 | hpt372_timings_50, | |
313 | hpt372_timings_66 | |
314 | } | |
315 | }; | |
316 | ||
317 | static const struct hpt_chip hpt374 = { | |
318 | "HPT374", | |
319 | 48, | |
320 | { | |
321 | hpt374_timings_33, | |
322 | NULL, | |
323 | NULL, | |
324 | NULL | |
325 | } | |
326 | }; | |
327 | ||
328 | /** | |
329 | * hpt37x_find_mode - reset the hpt37x bus | |
330 | * @ap: ATA port | |
331 | * @speed: transfer mode | |
332 | * | |
333 | * Return the 32bit register programming information for this channel | |
334 | * that matches the speed provided. | |
335 | */ | |
85cd7251 | 336 | |
669a5db4 JG |
337 | static u32 hpt37x_find_mode(struct ata_port *ap, int speed) |
338 | { | |
339 | struct hpt_clock *clocks = ap->host->private_data; | |
85cd7251 | 340 | |
669a5db4 JG |
341 | while(clocks->xfer_speed) { |
342 | if (clocks->xfer_speed == speed) | |
343 | return clocks->timing; | |
344 | clocks++; | |
345 | } | |
346 | BUG(); | |
347 | return 0xffffffffU; /* silence compiler warning */ | |
348 | } | |
349 | ||
350 | static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[]) | |
351 | { | |
352 | unsigned char model_num[40]; | |
353 | char *s; | |
354 | unsigned int len; | |
355 | int i = 0; | |
356 | ||
357 | ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS, | |
358 | sizeof(model_num)); | |
359 | s = &model_num[0]; | |
360 | len = strnlen(s, sizeof(model_num)); | |
361 | ||
362 | /* ATAPI specifies that empty space is blank-filled; remove blanks */ | |
363 | while ((len > 0) && (s[len - 1] == ' ')) { | |
364 | len--; | |
365 | s[len] = 0; | |
366 | } | |
367 | ||
368 | while(list[i] != NULL) { | |
369 | if (!strncmp(list[i], s, len)) { | |
85cd7251 | 370 | printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n", |
669a5db4 JG |
371 | modestr, list[i]); |
372 | return 1; | |
373 | } | |
374 | i++; | |
375 | } | |
376 | return 0; | |
377 | } | |
378 | ||
379 | static const char *bad_ata33[] = { | |
380 | "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", | |
381 | "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", | |
382 | "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", | |
383 | "Maxtor 90510D4", | |
384 | "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", | |
385 | "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", | |
386 | "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", | |
387 | NULL | |
388 | }; | |
389 | ||
390 | static const char *bad_ata100_5[] = { | |
391 | "IBM-DTLA-307075", | |
392 | "IBM-DTLA-307060", | |
393 | "IBM-DTLA-307045", | |
394 | "IBM-DTLA-307030", | |
395 | "IBM-DTLA-307020", | |
396 | "IBM-DTLA-307015", | |
397 | "IBM-DTLA-305040", | |
398 | "IBM-DTLA-305030", | |
399 | "IBM-DTLA-305020", | |
400 | "IC35L010AVER07-0", | |
401 | "IC35L020AVER07-0", | |
402 | "IC35L030AVER07-0", | |
403 | "IC35L040AVER07-0", | |
404 | "IC35L060AVER07-0", | |
405 | "WDC AC310200R", | |
406 | NULL | |
407 | }; | |
408 | ||
409 | /** | |
410 | * hpt370_filter - mode selection filter | |
411 | * @ap: ATA interface | |
412 | * @adev: ATA device | |
413 | * | |
414 | * Block UDMA on devices that cause trouble with this controller. | |
415 | */ | |
85cd7251 | 416 | |
669a5db4 JG |
417 | static unsigned long hpt370_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask) |
418 | { | |
6929da44 | 419 | if (adev->class == ATA_DEV_ATA) { |
669a5db4 JG |
420 | if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) |
421 | mask &= ~ATA_MASK_UDMA; | |
422 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) | |
423 | mask &= ~(0x1F << ATA_SHIFT_UDMA); | |
424 | } | |
425 | return ata_pci_default_filter(ap, adev, mask); | |
426 | } | |
427 | ||
428 | /** | |
429 | * hpt370a_filter - mode selection filter | |
430 | * @ap: ATA interface | |
431 | * @adev: ATA device | |
432 | * | |
433 | * Block UDMA on devices that cause trouble with this controller. | |
434 | */ | |
85cd7251 | 435 | |
669a5db4 JG |
436 | static unsigned long hpt370a_filter(const struct ata_port *ap, struct ata_device *adev, unsigned long mask) |
437 | { | |
438 | if (adev->class != ATA_DEV_ATA) { | |
439 | if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5)) | |
440 | mask &= ~ (0x1F << ATA_SHIFT_UDMA); | |
441 | } | |
442 | return ata_pci_default_filter(ap, adev, mask); | |
443 | } | |
85cd7251 | 444 | |
669a5db4 JG |
445 | /** |
446 | * hpt37x_pre_reset - reset the hpt37x bus | |
447 | * @ap: ATA port to reset | |
448 | * | |
449 | * Perform the initial reset handling for the 370/372 and 374 func 0 | |
450 | */ | |
85cd7251 | 451 | |
669a5db4 JG |
452 | static int hpt37x_pre_reset(struct ata_port *ap) |
453 | { | |
454 | u8 scr2, ata66; | |
455 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
b5bf24b9 AC |
456 | static const struct pci_bits hpt37x_enable_bits[] = { |
457 | { 0x50, 1, 0x04, 0x04 }, | |
458 | { 0x54, 1, 0x04, 0x04 } | |
459 | }; | |
460 | if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) | |
461 | return -ENOENT; | |
f20b16ff | 462 | |
669a5db4 JG |
463 | pci_read_config_byte(pdev, 0x5B, &scr2); |
464 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
465 | /* Cable register now active */ | |
466 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
467 | /* Restore state */ | |
468 | pci_write_config_byte(pdev, 0x5B, scr2); | |
85cd7251 | 469 | |
669a5db4 JG |
470 | if (ata66 & (1 << ap->port_no)) |
471 | ap->cbl = ATA_CBL_PATA40; | |
472 | else | |
473 | ap->cbl = ATA_CBL_PATA80; | |
474 | ||
475 | /* Reset the state machine */ | |
85cd7251 JG |
476 | pci_write_config_byte(pdev, 0x50, 0x37); |
477 | pci_write_config_byte(pdev, 0x54, 0x37); | |
669a5db4 | 478 | udelay(100); |
85cd7251 | 479 | |
669a5db4 JG |
480 | return ata_std_prereset(ap); |
481 | } | |
482 | ||
483 | /** | |
484 | * hpt37x_error_handler - reset the hpt374 | |
485 | * @ap: ATA port to reset | |
486 | * | |
487 | * Perform probe for HPT37x, except for HPT374 channel 2 | |
488 | */ | |
85cd7251 | 489 | |
669a5db4 JG |
490 | static void hpt37x_error_handler(struct ata_port *ap) |
491 | { | |
492 | ata_bmdma_drive_eh(ap, hpt37x_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
493 | } | |
494 | ||
495 | static int hpt374_pre_reset(struct ata_port *ap) | |
496 | { | |
b5bf24b9 AC |
497 | static const struct pci_bits hpt37x_enable_bits[] = { |
498 | { 0x50, 1, 0x04, 0x04 }, | |
499 | { 0x54, 1, 0x04, 0x04 } | |
500 | }; | |
669a5db4 JG |
501 | u16 mcr3, mcr6; |
502 | u8 ata66; | |
669a5db4 | 503 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
b5bf24b9 AC |
504 | |
505 | if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no])) | |
506 | return -ENOENT; | |
f20b16ff | 507 | |
669a5db4 JG |
508 | /* Do the extra channel work */ |
509 | pci_read_config_word(pdev, 0x52, &mcr3); | |
510 | pci_read_config_word(pdev, 0x56, &mcr6); | |
511 | /* Set bit 15 of 0x52 to enable TCBLID as input | |
512 | Set bit 15 of 0x56 to enable FCBLID as input | |
513 | */ | |
514 | pci_write_config_word(pdev, 0x52, mcr3 | 0x8000); | |
515 | pci_write_config_word(pdev, 0x56, mcr6 | 0x8000); | |
516 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
517 | /* Reset TCBLID/FCBLID to output */ | |
518 | pci_write_config_word(pdev, 0x52, mcr3); | |
519 | pci_write_config_word(pdev, 0x56, mcr6); | |
85cd7251 | 520 | |
669a5db4 JG |
521 | if (ata66 & (1 << ap->port_no)) |
522 | ap->cbl = ATA_CBL_PATA40; | |
523 | else | |
524 | ap->cbl = ATA_CBL_PATA80; | |
525 | ||
526 | /* Reset the state machine */ | |
85cd7251 JG |
527 | pci_write_config_byte(pdev, 0x50, 0x37); |
528 | pci_write_config_byte(pdev, 0x54, 0x37); | |
669a5db4 | 529 | udelay(100); |
85cd7251 | 530 | |
669a5db4 JG |
531 | return ata_std_prereset(ap); |
532 | } | |
533 | ||
534 | /** | |
535 | * hpt374_error_handler - reset the hpt374 | |
536 | * @classes: | |
537 | * | |
538 | * The 374 cable detect is a little different due to the extra | |
539 | * channels. The function 0 channels work like usual but function 1 | |
540 | * is special | |
541 | */ | |
85cd7251 | 542 | |
669a5db4 JG |
543 | static void hpt374_error_handler(struct ata_port *ap) |
544 | { | |
545 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
85cd7251 | 546 | |
669a5db4 JG |
547 | if (!(PCI_FUNC(pdev->devfn) & 1)) |
548 | hpt37x_error_handler(ap); | |
549 | else | |
550 | ata_bmdma_drive_eh(ap, hpt374_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
551 | } | |
552 | ||
553 | /** | |
554 | * hpt370_set_piomode - PIO setup | |
555 | * @ap: ATA interface | |
556 | * @adev: device on the interface | |
557 | * | |
85cd7251 | 558 | * Perform PIO mode setup. |
669a5db4 | 559 | */ |
85cd7251 | 560 | |
669a5db4 JG |
561 | static void hpt370_set_piomode(struct ata_port *ap, struct ata_device *adev) |
562 | { | |
563 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
564 | u32 addr1, addr2; | |
565 | u32 reg; | |
566 | u32 mode; | |
567 | u8 fast; | |
568 | ||
569 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
570 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 571 | |
669a5db4 JG |
572 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
573 | pci_read_config_byte(pdev, addr2, &fast); | |
574 | fast &= ~0x02; | |
575 | fast |= 0x01; | |
576 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 577 | |
669a5db4 JG |
578 | pci_read_config_dword(pdev, addr1, ®); |
579 | mode = hpt37x_find_mode(ap, adev->pio_mode); | |
580 | mode &= ~0x8000000; /* No FIFO in PIO */ | |
581 | mode &= ~0x30070000; /* Leave config bits alone */ | |
582 | reg &= 0x30070000; /* Strip timing bits */ | |
583 | pci_write_config_dword(pdev, addr1, reg | mode); | |
584 | } | |
585 | ||
586 | /** | |
587 | * hpt370_set_dmamode - DMA timing setup | |
588 | * @ap: ATA interface | |
589 | * @adev: Device being configured | |
590 | * | |
591 | * Set up the channel for MWDMA or UDMA modes. Much the same as with | |
592 | * PIO, load the mode number and then set MWDMA or UDMA flag. | |
593 | */ | |
85cd7251 | 594 | |
669a5db4 JG |
595 | static void hpt370_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
596 | { | |
597 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
598 | u32 addr1, addr2; | |
599 | u32 reg; | |
600 | u32 mode; | |
601 | u8 fast; | |
602 | ||
603 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
604 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 605 | |
669a5db4 JG |
606 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
607 | pci_read_config_byte(pdev, addr2, &fast); | |
608 | fast &= ~0x02; | |
609 | fast |= 0x01; | |
610 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 611 | |
669a5db4 JG |
612 | pci_read_config_dword(pdev, addr1, ®); |
613 | mode = hpt37x_find_mode(ap, adev->dma_mode); | |
614 | mode |= 0x8000000; /* FIFO in MWDMA or UDMA */ | |
615 | mode &= ~0xC0000000; /* Leave config bits alone */ | |
616 | reg &= 0xC0000000; /* Strip timing bits */ | |
617 | pci_write_config_dword(pdev, addr1, reg | mode); | |
618 | } | |
619 | ||
620 | /** | |
621 | * hpt370_bmdma_start - DMA engine begin | |
622 | * @qc: ATA command | |
623 | * | |
624 | * The 370 and 370A want us to reset the DMA engine each time we | |
625 | * use it. The 372 and later are fine. | |
626 | */ | |
85cd7251 | 627 | |
669a5db4 JG |
628 | static void hpt370_bmdma_start(struct ata_queued_cmd *qc) |
629 | { | |
630 | struct ata_port *ap = qc->ap; | |
631 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
632 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
633 | udelay(10); | |
634 | ata_bmdma_start(qc); | |
635 | } | |
636 | ||
637 | /** | |
638 | * hpt370_bmdma_end - DMA engine stop | |
639 | * @qc: ATA command | |
640 | * | |
641 | * Work around the HPT370 DMA engine. | |
642 | */ | |
85cd7251 | 643 | |
669a5db4 JG |
644 | static void hpt370_bmdma_stop(struct ata_queued_cmd *qc) |
645 | { | |
646 | struct ata_port *ap = qc->ap; | |
647 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
648 | u8 dma_stat = inb(ap->ioaddr.bmdma_addr + 2); | |
649 | u8 dma_cmd; | |
650 | unsigned long bmdma = ap->ioaddr.bmdma_addr; | |
85cd7251 | 651 | |
669a5db4 JG |
652 | if (dma_stat & 0x01) { |
653 | udelay(20); | |
654 | dma_stat = inb(bmdma + 2); | |
655 | } | |
656 | if (dma_stat & 0x01) { | |
657 | /* Clear the engine */ | |
658 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
659 | udelay(10); | |
660 | /* Stop DMA */ | |
661 | dma_cmd = inb(bmdma ); | |
662 | outb(dma_cmd & 0xFE, bmdma); | |
663 | /* Clear Error */ | |
664 | dma_stat = inb(bmdma + 2); | |
665 | outb(dma_stat | 0x06 , bmdma + 2); | |
666 | /* Clear the engine */ | |
667 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); | |
668 | udelay(10); | |
669 | } | |
670 | ata_bmdma_stop(qc); | |
671 | } | |
672 | ||
673 | /** | |
674 | * hpt372_set_piomode - PIO setup | |
675 | * @ap: ATA interface | |
676 | * @adev: device on the interface | |
677 | * | |
85cd7251 | 678 | * Perform PIO mode setup. |
669a5db4 | 679 | */ |
85cd7251 | 680 | |
669a5db4 JG |
681 | static void hpt372_set_piomode(struct ata_port *ap, struct ata_device *adev) |
682 | { | |
683 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
684 | u32 addr1, addr2; | |
685 | u32 reg; | |
686 | u32 mode; | |
687 | u8 fast; | |
688 | ||
689 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
690 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 691 | |
669a5db4 JG |
692 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
693 | pci_read_config_byte(pdev, addr2, &fast); | |
694 | fast &= ~0x07; | |
695 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 696 | |
669a5db4 JG |
697 | pci_read_config_dword(pdev, addr1, ®); |
698 | mode = hpt37x_find_mode(ap, adev->pio_mode); | |
85cd7251 | 699 | |
669a5db4 JG |
700 | printk("Find mode for %d reports %X\n", adev->pio_mode, mode); |
701 | mode &= ~0x80000000; /* No FIFO in PIO */ | |
702 | mode &= ~0x30070000; /* Leave config bits alone */ | |
703 | reg &= 0x30070000; /* Strip timing bits */ | |
704 | pci_write_config_dword(pdev, addr1, reg | mode); | |
705 | } | |
706 | ||
707 | /** | |
708 | * hpt372_set_dmamode - DMA timing setup | |
709 | * @ap: ATA interface | |
710 | * @adev: Device being configured | |
711 | * | |
712 | * Set up the channel for MWDMA or UDMA modes. Much the same as with | |
713 | * PIO, load the mode number and then set MWDMA or UDMA flag. | |
714 | */ | |
85cd7251 | 715 | |
669a5db4 JG |
716 | static void hpt372_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
717 | { | |
718 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
719 | u32 addr1, addr2; | |
720 | u32 reg; | |
721 | u32 mode; | |
722 | u8 fast; | |
723 | ||
724 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
725 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 726 | |
669a5db4 JG |
727 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
728 | pci_read_config_byte(pdev, addr2, &fast); | |
729 | fast &= ~0x07; | |
730 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 731 | |
669a5db4 JG |
732 | pci_read_config_dword(pdev, addr1, ®); |
733 | mode = hpt37x_find_mode(ap, adev->dma_mode); | |
734 | printk("Find mode for DMA %d reports %X\n", adev->dma_mode, mode); | |
735 | mode &= ~0xC0000000; /* Leave config bits alone */ | |
736 | mode |= 0x80000000; /* FIFO in MWDMA or UDMA */ | |
737 | reg &= 0xC0000000; /* Strip timing bits */ | |
738 | pci_write_config_dword(pdev, addr1, reg | mode); | |
739 | } | |
740 | ||
741 | /** | |
742 | * hpt37x_bmdma_end - DMA engine stop | |
743 | * @qc: ATA command | |
744 | * | |
745 | * Clean up after the HPT372 and later DMA engine | |
746 | */ | |
85cd7251 | 747 | |
669a5db4 JG |
748 | static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc) |
749 | { | |
750 | struct ata_port *ap = qc->ap; | |
751 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
6929da44 | 752 | int mscreg = 0x50 + 4 * ap->port_no; |
669a5db4 | 753 | u8 bwsr_stat, msc_stat; |
85cd7251 | 754 | |
669a5db4 JG |
755 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
756 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
757 | if (bwsr_stat & (1 << ap->port_no)) | |
758 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
759 | ata_bmdma_stop(qc); | |
760 | } | |
761 | ||
762 | ||
763 | static struct scsi_host_template hpt37x_sht = { | |
764 | .module = THIS_MODULE, | |
765 | .name = DRV_NAME, | |
766 | .ioctl = ata_scsi_ioctl, | |
767 | .queuecommand = ata_scsi_queuecmd, | |
768 | .can_queue = ATA_DEF_QUEUE, | |
769 | .this_id = ATA_SHT_THIS_ID, | |
770 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
771 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
772 | .emulated = ATA_SHT_EMULATED, | |
773 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
774 | .proc_name = DRV_NAME, | |
775 | .dma_boundary = ATA_DMA_BOUNDARY, | |
776 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 777 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
778 | .bios_param = ata_std_bios_param, |
779 | }; | |
780 | ||
781 | /* | |
782 | * Configuration for HPT370 | |
783 | */ | |
85cd7251 | 784 | |
669a5db4 JG |
785 | static struct ata_port_operations hpt370_port_ops = { |
786 | .port_disable = ata_port_disable, | |
787 | .set_piomode = hpt370_set_piomode, | |
788 | .set_dmamode = hpt370_set_dmamode, | |
789 | .mode_filter = hpt370_filter, | |
85cd7251 | 790 | |
669a5db4 JG |
791 | .tf_load = ata_tf_load, |
792 | .tf_read = ata_tf_read, | |
793 | .check_status = ata_check_status, | |
794 | .exec_command = ata_exec_command, | |
795 | .dev_select = ata_std_dev_select, | |
796 | ||
797 | .freeze = ata_bmdma_freeze, | |
798 | .thaw = ata_bmdma_thaw, | |
799 | .error_handler = hpt37x_error_handler, | |
800 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
801 | ||
802 | .bmdma_setup = ata_bmdma_setup, | |
803 | .bmdma_start = hpt370_bmdma_start, | |
804 | .bmdma_stop = hpt370_bmdma_stop, | |
805 | .bmdma_status = ata_bmdma_status, | |
806 | ||
807 | .qc_prep = ata_qc_prep, | |
808 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 809 | |
669a5db4 JG |
810 | .data_xfer = ata_pio_data_xfer, |
811 | ||
812 | .irq_handler = ata_interrupt, | |
813 | .irq_clear = ata_bmdma_irq_clear, | |
814 | ||
815 | .port_start = ata_port_start, | |
816 | .port_stop = ata_port_stop, | |
817 | .host_stop = ata_host_stop | |
85cd7251 | 818 | }; |
669a5db4 JG |
819 | |
820 | /* | |
821 | * Configuration for HPT370A. Close to 370 but less filters | |
822 | */ | |
85cd7251 | 823 | |
669a5db4 JG |
824 | static struct ata_port_operations hpt370a_port_ops = { |
825 | .port_disable = ata_port_disable, | |
826 | .set_piomode = hpt370_set_piomode, | |
827 | .set_dmamode = hpt370_set_dmamode, | |
828 | .mode_filter = hpt370a_filter, | |
85cd7251 | 829 | |
669a5db4 JG |
830 | .tf_load = ata_tf_load, |
831 | .tf_read = ata_tf_read, | |
832 | .check_status = ata_check_status, | |
833 | .exec_command = ata_exec_command, | |
834 | .dev_select = ata_std_dev_select, | |
835 | ||
836 | .freeze = ata_bmdma_freeze, | |
837 | .thaw = ata_bmdma_thaw, | |
838 | .error_handler = hpt37x_error_handler, | |
839 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
840 | ||
841 | .bmdma_setup = ata_bmdma_setup, | |
842 | .bmdma_start = hpt370_bmdma_start, | |
843 | .bmdma_stop = hpt370_bmdma_stop, | |
844 | .bmdma_status = ata_bmdma_status, | |
845 | ||
846 | .qc_prep = ata_qc_prep, | |
847 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 848 | |
669a5db4 JG |
849 | .data_xfer = ata_pio_data_xfer, |
850 | ||
851 | .irq_handler = ata_interrupt, | |
852 | .irq_clear = ata_bmdma_irq_clear, | |
853 | ||
854 | .port_start = ata_port_start, | |
855 | .port_stop = ata_port_stop, | |
856 | .host_stop = ata_host_stop | |
85cd7251 | 857 | }; |
669a5db4 JG |
858 | |
859 | /* | |
860 | * Configuration for HPT372, HPT371, HPT302. Slightly different PIO | |
861 | * and DMA mode setting functionality. | |
862 | */ | |
85cd7251 | 863 | |
669a5db4 JG |
864 | static struct ata_port_operations hpt372_port_ops = { |
865 | .port_disable = ata_port_disable, | |
866 | .set_piomode = hpt372_set_piomode, | |
867 | .set_dmamode = hpt372_set_dmamode, | |
868 | .mode_filter = ata_pci_default_filter, | |
85cd7251 | 869 | |
669a5db4 JG |
870 | .tf_load = ata_tf_load, |
871 | .tf_read = ata_tf_read, | |
872 | .check_status = ata_check_status, | |
873 | .exec_command = ata_exec_command, | |
874 | .dev_select = ata_std_dev_select, | |
875 | ||
876 | .freeze = ata_bmdma_freeze, | |
877 | .thaw = ata_bmdma_thaw, | |
878 | .error_handler = hpt37x_error_handler, | |
879 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
880 | ||
881 | .bmdma_setup = ata_bmdma_setup, | |
882 | .bmdma_start = ata_bmdma_start, | |
883 | .bmdma_stop = hpt37x_bmdma_stop, | |
884 | .bmdma_status = ata_bmdma_status, | |
885 | ||
886 | .qc_prep = ata_qc_prep, | |
887 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 888 | |
669a5db4 JG |
889 | .data_xfer = ata_pio_data_xfer, |
890 | ||
891 | .irq_handler = ata_interrupt, | |
892 | .irq_clear = ata_bmdma_irq_clear, | |
893 | ||
894 | .port_start = ata_port_start, | |
895 | .port_stop = ata_port_stop, | |
896 | .host_stop = ata_host_stop | |
85cd7251 | 897 | }; |
669a5db4 JG |
898 | |
899 | /* | |
900 | * Configuration for HPT374. Mode setting works like 372 and friends | |
901 | * but we have a different cable detection procedure. | |
902 | */ | |
85cd7251 | 903 | |
669a5db4 JG |
904 | static struct ata_port_operations hpt374_port_ops = { |
905 | .port_disable = ata_port_disable, | |
906 | .set_piomode = hpt372_set_piomode, | |
907 | .set_dmamode = hpt372_set_dmamode, | |
908 | .mode_filter = ata_pci_default_filter, | |
85cd7251 | 909 | |
669a5db4 JG |
910 | .tf_load = ata_tf_load, |
911 | .tf_read = ata_tf_read, | |
912 | .check_status = ata_check_status, | |
913 | .exec_command = ata_exec_command, | |
914 | .dev_select = ata_std_dev_select, | |
915 | ||
916 | .freeze = ata_bmdma_freeze, | |
917 | .thaw = ata_bmdma_thaw, | |
918 | .error_handler = hpt374_error_handler, | |
919 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
920 | ||
921 | .bmdma_setup = ata_bmdma_setup, | |
922 | .bmdma_start = ata_bmdma_start, | |
923 | .bmdma_stop = hpt37x_bmdma_stop, | |
924 | .bmdma_status = ata_bmdma_status, | |
925 | ||
926 | .qc_prep = ata_qc_prep, | |
927 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 928 | |
669a5db4 JG |
929 | .data_xfer = ata_pio_data_xfer, |
930 | ||
931 | .irq_handler = ata_interrupt, | |
932 | .irq_clear = ata_bmdma_irq_clear, | |
933 | ||
934 | .port_start = ata_port_start, | |
935 | .port_stop = ata_port_stop, | |
936 | .host_stop = ata_host_stop | |
85cd7251 | 937 | }; |
669a5db4 JG |
938 | |
939 | /** | |
940 | * htp37x_clock_slot - Turn timing to PC clock entry | |
941 | * @freq: Reported frequency timing | |
942 | * @base: Base timing | |
943 | * | |
944 | * Turn the timing data intoa clock slot (0 for 33, 1 for 40, 2 for 50 | |
945 | * and 3 for 66Mhz) | |
946 | */ | |
85cd7251 | 947 | |
669a5db4 JG |
948 | static int hpt37x_clock_slot(unsigned int freq, unsigned int base) |
949 | { | |
950 | unsigned int f = (base * freq) / 192; /* Mhz */ | |
951 | if (f < 40) | |
952 | return 0; /* 33Mhz slot */ | |
953 | if (f < 45) | |
954 | return 1; /* 40Mhz slot */ | |
955 | if (f < 55) | |
956 | return 2; /* 50Mhz slot */ | |
957 | return 3; /* 60Mhz slot */ | |
958 | } | |
959 | ||
960 | /** | |
961 | * hpt37x_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 962 | * @dev: PCI device |
669a5db4 JG |
963 | * |
964 | * Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this | |
965 | * succeeds | |
966 | */ | |
967 | ||
968 | static int hpt37x_calibrate_dpll(struct pci_dev *dev) | |
969 | { | |
970 | u8 reg5b; | |
971 | u32 reg5c; | |
972 | int tries; | |
85cd7251 | 973 | |
669a5db4 JG |
974 | for(tries = 0; tries < 0x5000; tries++) { |
975 | udelay(50); | |
976 | pci_read_config_byte(dev, 0x5b, ®5b); | |
977 | if (reg5b & 0x80) { | |
978 | /* See if it stays set */ | |
979 | for(tries = 0; tries < 0x1000; tries ++) { | |
980 | pci_read_config_byte(dev, 0x5b, ®5b); | |
981 | /* Failed ? */ | |
982 | if ((reg5b & 0x80) == 0) | |
983 | return 0; | |
984 | } | |
985 | /* Turn off tuning, we have the DPLL set */ | |
986 | pci_read_config_dword(dev, 0x5c, ®5c); | |
987 | pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); | |
988 | return 1; | |
989 | } | |
990 | } | |
991 | /* Never went stable */ | |
992 | return 0; | |
993 | } | |
994 | /** | |
995 | * hpt37x_init_one - Initialise an HPT37X/302 | |
996 | * @dev: PCI device | |
997 | * @id: Entry in match table | |
998 | * | |
999 | * Initialise an HPT37x device. There are some interesting complications | |
1000 | * here. Firstly the chip may report 366 and be one of several variants. | |
1001 | * Secondly all the timings depend on the clock for the chip which we must | |
1002 | * detect and look up | |
1003 | * | |
1004 | * This is the known chip mappings. It may be missing a couple of later | |
1005 | * releases. | |
1006 | * | |
1007 | * Chip version PCI Rev Notes | |
1008 | * HPT366 4 (HPT366) 0 Other driver | |
1009 | * HPT366 4 (HPT366) 1 Other driver | |
1010 | * HPT368 4 (HPT366) 2 Other driver | |
1011 | * HPT370 4 (HPT366) 3 UDMA100 | |
1012 | * HPT370A 4 (HPT366) 4 UDMA100 | |
1013 | * HPT372 4 (HPT366) 5 UDMA133 (1) | |
1014 | * HPT372N 4 (HPT366) 6 Other driver | |
1015 | * HPT372A 5 (HPT372) 1 UDMA133 (1) | |
1016 | * HPT372N 5 (HPT372) 2 Other driver | |
1017 | * HPT302 6 (HPT302) 1 UDMA133 | |
1018 | * HPT302N 6 (HPT302) 2 Other driver | |
1019 | * HPT371 7 (HPT371) * UDMA133 | |
1020 | * HPT374 8 (HPT374) * UDMA133 4 channel | |
1021 | * HPT372N 9 (HPT372N) * Other driver | |
1022 | * | |
1023 | * (1) UDMA133 support depends on the bus clock | |
1024 | */ | |
85cd7251 | 1025 | |
669a5db4 JG |
1026 | static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
1027 | { | |
1028 | /* HPT370 - UDMA100 */ | |
1029 | static struct ata_port_info info_hpt370 = { | |
1030 | .sht = &hpt37x_sht, | |
1031 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
1032 | .pio_mask = 0x1f, | |
1033 | .mwdma_mask = 0x07, | |
1034 | .udma_mask = 0x3f, | |
1035 | .port_ops = &hpt370_port_ops | |
1036 | }; | |
1037 | /* HPT370A - UDMA100 */ | |
1038 | static struct ata_port_info info_hpt370a = { | |
1039 | .sht = &hpt37x_sht, | |
1040 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
1041 | .pio_mask = 0x1f, | |
1042 | .mwdma_mask = 0x07, | |
1043 | .udma_mask = 0x3f, | |
1044 | .port_ops = &hpt370a_port_ops | |
1045 | }; | |
1046 | /* HPT371, 372 and friends - UDMA133 */ | |
1047 | static struct ata_port_info info_hpt372 = { | |
1048 | .sht = &hpt37x_sht, | |
1049 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
1050 | .pio_mask = 0x1f, | |
1051 | .mwdma_mask = 0x07, | |
1052 | .udma_mask = 0x7f, | |
1053 | .port_ops = &hpt372_port_ops | |
1054 | }; | |
1055 | /* HPT371, 372 and friends - UDMA100 at 50MHz clock */ | |
1056 | static struct ata_port_info info_hpt372_50 = { | |
1057 | .sht = &hpt37x_sht, | |
1058 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
1059 | .pio_mask = 0x1f, | |
1060 | .mwdma_mask = 0x07, | |
1061 | .udma_mask = 0x3f, | |
1062 | .port_ops = &hpt372_port_ops | |
1063 | }; | |
1064 | /* HPT374 - UDMA133 */ | |
1065 | static struct ata_port_info info_hpt374 = { | |
1066 | .sht = &hpt37x_sht, | |
1067 | .flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST, | |
1068 | .pio_mask = 0x1f, | |
1069 | .mwdma_mask = 0x07, | |
1070 | .udma_mask = 0x7f, | |
1071 | .port_ops = &hpt374_port_ops | |
1072 | }; | |
1073 | ||
1074 | static const int MHz[4] = { 33, 40, 50, 66 }; | |
1075 | ||
1076 | struct ata_port_info *port_info[2]; | |
1077 | struct ata_port_info *port; | |
1078 | ||
1079 | u8 irqmask; | |
1080 | u32 class_rev; | |
1081 | u32 freq; | |
1082 | ||
1083 | const struct hpt_chip *chip_table; | |
1084 | int clock_slot; | |
1085 | ||
1086 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); | |
1087 | class_rev &= 0xFF; | |
85cd7251 | 1088 | |
669a5db4 JG |
1089 | if (dev->device == PCI_DEVICE_ID_TTI_HPT366) { |
1090 | /* May be a later chip in disguise. Check */ | |
1091 | /* Older chips are in the HPT366 driver. Ignore them */ | |
1092 | if (class_rev < 3) | |
1093 | return -ENODEV; | |
1094 | /* N series chips have their own driver. Ignore */ | |
1095 | if (class_rev == 6) | |
1096 | return -ENODEV; | |
1097 | ||
85cd7251 | 1098 | switch(class_rev) { |
669a5db4 JG |
1099 | case 3: |
1100 | port = &info_hpt370; | |
1101 | chip_table = &hpt370; | |
1102 | break; | |
1103 | case 4: | |
1104 | port = &info_hpt370a; | |
1105 | chip_table = &hpt370a; | |
1106 | break; | |
1107 | case 5: | |
1108 | port = &info_hpt372; | |
1109 | chip_table = &hpt372; | |
1110 | break; | |
1111 | default: | |
1112 | printk(KERN_ERR "pata_hpt37x: Unknown HPT366 subtype please report (%d).\n", class_rev); | |
1113 | return -ENODEV; | |
1114 | } | |
1115 | } else { | |
1116 | switch(dev->device) { | |
1117 | case PCI_DEVICE_ID_TTI_HPT372: | |
1118 | /* 372N if rev >= 2*/ | |
1119 | if (class_rev >= 2) | |
1120 | return -ENODEV; | |
1121 | port = &info_hpt372; | |
1122 | chip_table = &hpt372a; | |
1123 | break; | |
1124 | case PCI_DEVICE_ID_TTI_HPT302: | |
1125 | /* 302N if rev > 1 */ | |
1126 | if (class_rev > 1) | |
1127 | return -ENODEV; | |
1128 | port = &info_hpt372; | |
1129 | /* Check this */ | |
1130 | chip_table = &hpt302; | |
1131 | break; | |
1132 | case PCI_DEVICE_ID_TTI_HPT371: | |
1133 | port = &info_hpt372; | |
1134 | chip_table = &hpt371; | |
1135 | break; | |
1136 | case PCI_DEVICE_ID_TTI_HPT374: | |
1137 | chip_table = &hpt374; | |
1138 | port = &info_hpt374; | |
1139 | break; | |
1140 | default: | |
1141 | printk(KERN_ERR "pata_hpt37x: PCI table is bogus please report (%d).\n", dev->device); | |
1142 | return -ENODEV; | |
1143 | } | |
1144 | } | |
1145 | /* Ok so this is a chip we support */ | |
1146 | ||
1147 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
1148 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
1149 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
1150 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
1151 | ||
1152 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
1153 | irqmask &= ~0x10; | |
1154 | pci_write_config_byte(dev, 0x5a, irqmask); | |
1155 | ||
1156 | /* | |
1157 | * default to pci clock. make sure MA15/16 are set to output | |
1158 | * to prevent drives having problems with 40-pin cables. Needed | |
1159 | * for some drives such as IBM-DTLA which will not enter ready | |
1160 | * state on reset when PDIAG is a input. | |
1161 | */ | |
1162 | ||
85cd7251 JG |
1163 | pci_write_config_byte(dev, 0x5b, 0x23); |
1164 | ||
669a5db4 JG |
1165 | pci_read_config_dword(dev, 0x70, &freq); |
1166 | if ((freq >> 12) != 0xABCDE) { | |
1167 | int i; | |
1168 | u8 sr; | |
1169 | u32 total = 0; | |
85cd7251 | 1170 | |
669a5db4 | 1171 | printk(KERN_WARNING "pata_hpt37x: BIOS has not set timing clocks.\n"); |
85cd7251 | 1172 | |
669a5db4 JG |
1173 | /* This is the process the HPT371 BIOS is reported to use */ |
1174 | for(i = 0; i < 128; i++) { | |
1175 | pci_read_config_byte(dev, 0x78, &sr); | |
1176 | total += sr; | |
1177 | udelay(15); | |
1178 | } | |
1179 | freq = total / 128; | |
1180 | } | |
1181 | freq &= 0x1FF; | |
85cd7251 | 1182 | |
669a5db4 JG |
1183 | /* |
1184 | * Turn the frequency check into a band and then find a timing | |
1185 | * table to match it. | |
1186 | */ | |
85cd7251 | 1187 | |
669a5db4 JG |
1188 | clock_slot = hpt37x_clock_slot(freq, chip_table->base); |
1189 | if (chip_table->clocks[clock_slot] == NULL) { | |
1190 | /* | |
1191 | * We need to try PLL mode instead | |
1192 | */ | |
1193 | unsigned int f_low = (MHz[clock_slot] * chip_table->base) / 192; | |
1194 | unsigned int f_high = f_low + 2; | |
1195 | int adjust; | |
85cd7251 | 1196 | |
669a5db4 JG |
1197 | for(adjust = 0; adjust < 8; adjust++) { |
1198 | if (hpt37x_calibrate_dpll(dev)) | |
1199 | break; | |
1200 | /* See if it'll settle at a fractionally different clock */ | |
1201 | if ((adjust & 3) == 3) { | |
1202 | f_low --; | |
1203 | f_high ++; | |
1204 | } | |
1205 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); | |
1206 | } | |
1207 | if (adjust == 8) { | |
1208 | printk(KERN_WARNING "hpt37x: DPLL did not stabilize.\n"); | |
1209 | return -ENODEV; | |
1210 | } | |
1211 | /* Check if this works for all cases */ | |
1212 | port->private_data = (void *)hpt370_timings_66; | |
85cd7251 | 1213 | |
669a5db4 JG |
1214 | printk(KERN_INFO "hpt37x: Bus clock %dMHz, using DPLL.\n", MHz[clock_slot]); |
1215 | } else { | |
1216 | port->private_data = (void *)chip_table->clocks[clock_slot]; | |
1217 | /* | |
1218 | * Perform a final fixup. The 371 and 372 clock determines | |
1219 | * if UDMA133 is available. | |
1220 | */ | |
85cd7251 | 1221 | |
669a5db4 JG |
1222 | if (clock_slot == 2 && chip_table == &hpt372) { /* 50Mhz */ |
1223 | printk(KERN_WARNING "pata_hpt37x: No UDMA133 support available with 50MHz bus clock.\n"); | |
1224 | if (port == &info_hpt372) | |
1225 | port = &info_hpt372_50; | |
1226 | else BUG(); | |
1227 | } | |
1228 | printk(KERN_INFO "hpt37x: %s: Bus clock %dMHz.\n", chip_table->name, MHz[clock_slot]); | |
1229 | } | |
85cd7251 | 1230 | port_info[0] = port_info[1] = port; |
669a5db4 JG |
1231 | /* Now kick off ATA set up */ |
1232 | return ata_pci_init_one(dev, port_info, 2); | |
1233 | } | |
1234 | ||
2d2744fc JG |
1235 | static const struct pci_device_id hpt37x[] = { |
1236 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
1237 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, | |
1238 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, | |
1239 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), }, | |
1240 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
1241 | ||
1242 | { }, | |
669a5db4 JG |
1243 | }; |
1244 | ||
1245 | static struct pci_driver hpt37x_pci_driver = { | |
2d2744fc | 1246 | .name = DRV_NAME, |
669a5db4 JG |
1247 | .id_table = hpt37x, |
1248 | .probe = hpt37x_init_one, | |
1249 | .remove = ata_pci_remove_one | |
1250 | }; | |
1251 | ||
1252 | static int __init hpt37x_init(void) | |
1253 | { | |
1254 | return pci_register_driver(&hpt37x_pci_driver); | |
1255 | } | |
1256 | ||
669a5db4 JG |
1257 | static void __exit hpt37x_exit(void) |
1258 | { | |
1259 | pci_unregister_driver(&hpt37x_pci_driver); | |
1260 | } | |
1261 | ||
669a5db4 JG |
1262 | MODULE_AUTHOR("Alan Cox"); |
1263 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x"); | |
1264 | MODULE_LICENSE("GPL"); | |
1265 | MODULE_DEVICE_TABLE(pci, hpt37x); | |
1266 | MODULE_VERSION(DRV_VERSION); | |
1267 | ||
1268 | module_init(hpt37x_init); | |
1269 | module_exit(hpt37x_exit); |