[mirror_ubuntu-focal-kernel.git] / drivers / ata / pata_icside.c

// SPDX-License-Identifier: GPL-2.0-only
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/gfp.h>
#include <scsi/scsi_host.h>
#include <linux/ata.h>
#include <linux/libata.h>

#include <asm/dma.h>
#include <asm/ecard.h>

#define DRV_NAME	"pata_icside"

#define ICS_IDENT_OFFSET		0x2280

#define ICS_ARCIN_V5_INTRSTAT		0x0000
#define ICS_ARCIN_V5_INTROFFSET		0x0004

#define ICS_ARCIN_V6_INTROFFSET_1	0x2200
#define ICS_ARCIN_V6_INTRSTAT_1		0x2290
#define ICS_ARCIN_V6_INTROFFSET_2	0x3200
#define ICS_ARCIN_V6_INTRSTAT_2		0x3290

struct portinfo {
	unsigned int dataoffset;
	unsigned int ctrloffset;
	unsigned int stepping;
};

static const struct portinfo pata_icside_portinfo_v5 = {
	.dataoffset	= 0x2800,
	.ctrloffset	= 0x2b80,
	.stepping	= 6,
};

static const struct portinfo pata_icside_portinfo_v6_1 = {
	.dataoffset	= 0x2000,
	.ctrloffset	= 0x2380,
	.stepping	= 6,
};

static const struct portinfo pata_icside_portinfo_v6_2 = {
	.dataoffset	= 0x3000,
	.ctrloffset	= 0x3380,
	.stepping	= 6,
};

struct pata_icside_state {
	void __iomem *irq_port;
	void __iomem *ioc_base;
	unsigned int type;
	unsigned int dma;
	struct {
		u8 port_sel;
		u8 disabled;
		unsigned int speed[ATA_MAX_DEVICES];
	} port[2];
};

struct pata_icside_info {
	struct pata_icside_state *state;
	struct expansion_card	*ec;
	void __iomem		*base;
	void __iomem		*irqaddr;
	unsigned int		irqmask;
	const expansioncard_ops_t *irqops;
	unsigned int		mwdma_mask;
	unsigned int		nr_ports;
	const struct portinfo	*port[2];
	unsigned long		raw_base;
	unsigned long		raw_ioc_base;
};

#define ICS_TYPE_A3IN	0
#define ICS_TYPE_A3USER	1
#define ICS_TYPE_V6	3
#define ICS_TYPE_V5	15
#define ICS_TYPE_NOTYPE	((unsigned int)-1)

/* ---------------- Version 5 PCB Support Functions --------------------- */
/* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct pata_icside_state *state = ec->irq_data;

	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

/* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct pata_icside_state *state = ec->irq_data;

	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
	.irqenable	= pata_icside_irqenable_arcin_v5,
	.irqdisable	= pata_icside_irqdisable_arcin_v5,
};


/* ---------------- Version 6 PCB Support Functions --------------------- */
/* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct pata_icside_state *state = ec->irq_data;
	void __iomem *base = state->irq_port;

	if (!state->port[0].disabled)
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
	if (!state->port[1].disabled)
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
}

/* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct pata_icside_state *state = ec->irq_data;

	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
}

/* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
 * Purpose  : detect an active interrupt from card
 */
static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
{
	struct pata_icside_state *state = ec->irq_data;

	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
	       readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
}

static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
	.irqenable	= pata_icside_irqenable_arcin_v6,
	.irqdisable	= pata_icside_irqdisable_arcin_v6,
	.irqpending	= pata_icside_irqpending_arcin_v6,
};


/*
 * SG-DMA support.
 *
 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 * There is only one DMA controller per card, which means that only
 * one drive can be accessed at one time.  NOTE! We do not enforce that
 * here, but we rely on the main IDE driver spotting that both
 * interfaces use the same IRQ, which should guarantee this.
 */

/*
 * Configure the IOMD to give the appropriate timings for the transfer
 * mode being requested.  We take the advice of the ATA standards, and
 * calculate the cycle time based on the transfer mode, and the EIDE
 * MW DMA specs that the drive provides in the IDENTIFY command.
 *
 * We have the following IOMD DMA modes to choose from:
 *
 *	Type	Active		Recovery	Cycle
 *	A	250 (250)	312 (550)	562 (800)
 *	B	187 (200)	250 (550)	437 (750)
 *	C	125 (125)	125 (375)	250 (500)
 *	D	62  (50)	125 (375)	187 (425)
 *
 * (figures in brackets are actual measured timings on DIOR/DIOW)
 *
 * However, we also need to take care of the read/write active and
 * recovery timings:
 *
 *			Read	Write
 *  	Mode	Active	-- Recovery --	Cycle	IOMD type
 *	MW0	215	50	215	480	A
 *	MW1	80	50	50	150	C
 *	MW2	70	25	25	120	C
 */
static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pata_icside_state *state = ap->host->private_data;
	struct ata_timing t;
	unsigned int cycle;
	char iomd_type;

	/*
	 * DMA is based on a 16MHz clock
	 */
	if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
		return;

	/*
	 * Choose the IOMD cycle timing which ensure that the interface
	 * satisfies the measured active, recovery and cycle times.
	 */
	if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
		iomd_type = 'D', cycle = 187;
	else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
		iomd_type = 'C', cycle = 250;
	else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
		iomd_type = 'B', cycle = 437;
	else
		iomd_type = 'A', cycle = 562;

	ata_dev_info(adev, "timings: act %dns rec %dns cyc %dns (%c)\n",
		     t.active, t.recover, t.cycle, iomd_type);

	state->port[ap->port_no].speed[adev->devno] = cycle;
}

static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pata_icside_state *state = ap->host->private_data;
	unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;

	/*
	 * We are simplex; BUG if we try to fiddle with DMA
	 * while it's active.
	 */
	BUG_ON(dma_channel_active(state->dma));

	/*
	 * Route the DMA signals to the correct interface
	 */
	writeb(state->port[ap->port_no].port_sel, state->ioc_base);

	set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
	set_dma_sg(state->dma, qc->sg, qc->n_elem);
	set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);

	/* issue r/w command */
	ap->ops->sff_exec_command(ap, &qc->tf);
}

static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pata_icside_state *state = ap->host->private_data;

	BUG_ON(dma_channel_active(state->dma));
	enable_dma(state->dma);
}

static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pata_icside_state *state = ap->host->private_data;

	disable_dma(state->dma);

	/* see ata_bmdma_stop */
	ata_sff_dma_pause(ap);
}

static u8 pata_icside_bmdma_status(struct ata_port *ap)
{
	struct pata_icside_state *state = ap->host->private_data;
	void __iomem *irq_port;

	irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
						    ICS_ARCIN_V6_INTRSTAT_1);

	return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
}

static int icside_dma_init(struct pata_icside_info *info)
{
	struct pata_icside_state *state = info->state;
	struct expansion_card *ec = info->ec;
	int i;

	for (i = 0; i < ATA_MAX_DEVICES; i++) {
		state->port[0].speed[i] = 480;
		state->port[1].speed[i] = 480;
	}

	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
		state->dma = ec->dma;
		info->mwdma_mask = ATA_MWDMA2;
	}

	return 0;
}


static struct scsi_host_template pata_icside_sht = {
	ATA_BASE_SHT(DRV_NAME),
	.sg_tablesize		= SG_MAX_SEGMENTS,
	.dma_boundary		= IOMD_DMA_BOUNDARY,
};

static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
{
	struct ata_port *ap = link->ap;
	struct pata_icside_state *state = ap->host->private_data;

	if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE)
		return ata_sff_postreset(link, classes);

	state->port[ap->port_no].disabled = 1;

	if (state->type == ICS_TYPE_V6) {
		/*
		 * Disable interrupts from this port, otherwise we
		 * receive spurious interrupts from the floating
		 * interrupt line.
		 */
		void __iomem *irq_port = state->irq_port +
				(ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
		readb(irq_port);
	}
}

static struct ata_port_operations pata_icside_port_ops = {
	.inherits		= &ata_bmdma_port_ops,
	/* no need to build any PRD tables for DMA */
	.qc_prep		= ata_noop_qc_prep,
	.sff_data_xfer		= ata_sff_data_xfer32,
	.bmdma_setup		= pata_icside_bmdma_setup,
	.bmdma_start		= pata_icside_bmdma_start,
	.bmdma_stop		= pata_icside_bmdma_stop,
	.bmdma_status		= pata_icside_bmdma_status,

	.cable_detect		= ata_cable_40wire,
	.set_dmamode		= pata_icside_set_dmamode,
	.postreset		= pata_icside_postreset,

	.port_start		= ATA_OP_NULL,	/* don't need PRD table */
};

static void pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base,
				     struct pata_icside_info *info,
				     const struct portinfo *port)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	void __iomem *cmd = base + port->dataoffset;

	ioaddr->cmd_addr	= cmd;
	ioaddr->data_addr	= cmd + (ATA_REG_DATA    << port->stepping);
	ioaddr->error_addr	= cmd + (ATA_REG_ERR     << port->stepping);
	ioaddr->feature_addr	= cmd + (ATA_REG_FEATURE << port->stepping);
	ioaddr->nsect_addr	= cmd + (ATA_REG_NSECT   << port->stepping);
	ioaddr->lbal_addr	= cmd + (ATA_REG_LBAL    << port->stepping);
	ioaddr->lbam_addr	= cmd + (ATA_REG_LBAM    << port->stepping);
	ioaddr->lbah_addr	= cmd + (ATA_REG_LBAH    << port->stepping);
	ioaddr->device_addr	= cmd + (ATA_REG_DEVICE  << port->stepping);
	ioaddr->status_addr	= cmd + (ATA_REG_STATUS  << port->stepping);
	ioaddr->command_addr	= cmd + (ATA_REG_CMD     << port->stepping);

	ioaddr->ctl_addr	= base + port->ctrloffset;
	ioaddr->altstatus_addr	= ioaddr->ctl_addr;

	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
		      info->raw_base + port->dataoffset,
		      info->raw_base + port->ctrloffset);

	if (info->raw_ioc_base)
		ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
}

static int pata_icside_register_v5(struct pata_icside_info *info)
{
	struct pata_icside_state *state = info->state;
	void __iomem *base;

	base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
	if (!base)
		return -ENOMEM;

	state->irq_port = base;

	info->base = base;
	info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
	info->irqmask = 1;
	info->irqops = &pata_icside_ops_arcin_v5;
	info->nr_ports = 1;
	info->port[0] = &pata_icside_portinfo_v5;

	info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);

	return 0;
}

static int pata_icside_register_v6(struct pata_icside_info *info)
{
	struct pata_icside_state *state = info->state;
	struct expansion_card *ec = info->ec;
	void __iomem *ioc_base, *easi_base;
	unsigned int sel = 0;

	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (!ioc_base)
		return -ENOMEM;

	easi_base = ioc_base;

	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
		easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
		if (!easi_base)
			return -ENOMEM;

		/*
		 * Enable access to the EASI region.
		 */
		sel = 1 << 5;
	}

	writeb(sel, ioc_base);

	state->irq_port = easi_base;
	state->ioc_base = ioc_base;
	state->port[0].port_sel = sel;
	state->port[1].port_sel = sel | 1;

	info->base = easi_base;
	info->irqops = &pata_icside_ops_arcin_v6;
	info->nr_ports = 2;
	info->port[0] = &pata_icside_portinfo_v6_1;
	info->port[1] = &pata_icside_portinfo_v6_2;

	info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
	info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);

	return icside_dma_init(info);
}

static int pata_icside_add_ports(struct pata_icside_info *info)
{
	struct expansion_card *ec = info->ec;
	struct ata_host *host;
	int i;

	if (info->irqaddr) {
		ec->irqaddr = info->irqaddr;
		ec->irqmask = info->irqmask;
	}
	if (info->irqops)
		ecard_setirq(ec, info->irqops, info->state);

	/*
	 * Be on the safe side - disable interrupts
	 */
	ec->ops->irqdisable(ec, ec->irq);

	host = ata_host_alloc(&ec->dev, info->nr_ports);
	if (!host)
		return -ENOMEM;

	host->private_data = info->state;
	host->flags = ATA_HOST_SIMPLEX;

	for (i = 0; i < info->nr_ports; i++) {
		struct ata_port *ap = host->ports[i];

		ap->pio_mask = ATA_PIO4;
		ap->mwdma_mask = info->mwdma_mask;
		ap->flags |= ATA_FLAG_SLAVE_POSS;
		ap->ops = &pata_icside_port_ops;

		pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
	}

	return ata_host_activate(host, ec->irq, ata_bmdma_interrupt, 0,
				 &pata_icside_sht);
}

static int pata_icside_probe(struct expansion_card *ec,
			     const struct ecard_id *id)
{
	struct pata_icside_state *state;
	struct pata_icside_info info;
	void __iomem *idmem;
	int ret;

	ret = ecard_request_resources(ec);
	if (ret)
		goto out;

	state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
	if (!state) {
		ret = -ENOMEM;
		goto release;
	}

	state->type = ICS_TYPE_NOTYPE;
	state->dma = NO_DMA;

	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (idmem) {
		unsigned int type;

		type = readb(idmem + ICS_IDENT_OFFSET) & 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
		ecardm_iounmap(ec, idmem);

		state->type = type;
	}

	memset(&info, 0, sizeof(info));
	info.state = state;
	info.ec = ec;

	switch (state->type) {
	case ICS_TYPE_A3IN:
		dev_warn(&ec->dev, "A3IN unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_A3USER:
		dev_warn(&ec->dev, "A3USER unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_V5:
		ret = pata_icside_register_v5(&info);
		break;

	case ICS_TYPE_V6:
		ret = pata_icside_register_v6(&info);
		break;

	default:
		dev_warn(&ec->dev, "unknown interface type\n");
		ret = -ENODEV;
		break;
	}

	if (ret == 0)
		ret = pata_icside_add_ports(&info);

	if (ret == 0)
		goto out;

 release:
	ecard_release_resources(ec);
 out:
	return ret;
}

static void pata_icside_shutdown(struct expansion_card *ec)
{
	struct ata_host *host = ecard_get_drvdata(ec);
	unsigned long flags;

	/*
	 * Disable interrupts from this card.  We need to do
	 * this before disabling EASI since we may be accessing
	 * this register via that region.
	 */
	local_irq_save(flags);
	ec->ops->irqdisable(ec, ec->irq);
	local_irq_restore(flags);

	/*
	 * Reset the ROM pointer so that we can read the ROM
	 * after a soft reboot.  This also disables access to
	 * the IDE taskfile via the EASI region.
	 */
	if (host) {
		struct pata_icside_state *state = host->private_data;
		if (state->ioc_base)
			writeb(0, state->ioc_base);
	}
}

static void pata_icside_remove(struct expansion_card *ec)
{
	struct ata_host *host = ecard_get_drvdata(ec);
	struct pata_icside_state *state = host->private_data;

	ata_host_detach(host);

	pata_icside_shutdown(ec);

	/*
	 * don't NULL out the drvdata - devres/libata wants it
	 * to free the ata_host structure.
	 */
	if (state->dma != NO_DMA)
		free_dma(state->dma);

	ecard_release_resources(ec);
}

static const struct ecard_id pata_icside_ids[] = {
	{ MANU_ICS,  PROD_ICS_IDE  },
	{ MANU_ICS2, PROD_ICS2_IDE },
	{ 0xffff, 0xffff }
};

static struct ecard_driver pata_icside_driver = {
	.probe		= pata_icside_probe,
	.remove 	= pata_icside_remove,
	.shutdown	= pata_icside_shutdown,
	.id_table	= pata_icside_ids,
	.drv = {
		.name	= DRV_NAME,
	},
};

static int __init pata_icside_init(void)
{
	return ecard_register_driver(&pata_icside_driver);
}

static void __exit pata_icside_exit(void)
{
	ecard_remove_driver(&pata_icside_driver);
}

MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("ICS PATA driver");

module_init(pata_icside_init);
module_exit(pata_icside_exit);
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
73b6a2be RK	2	#include <linux/kernel.h>
	3	#include <linux/module.h>
	4	#include <linux/init.h>
	5	#include <linux/blkdev.h>
5a0e3ad6	6	#include <linux/gfp.h>
73b6a2be RK	7	#include <scsi/scsi_host.h>
	8	#include <linux/ata.h>
	9	#include <linux/libata.h>
	10
	11	#include <asm/dma.h>
	12	#include <asm/ecard.h>
	13
	14	#define DRV_NAME "pata_icside"
	15
	16	#define ICS_IDENT_OFFSET 0x2280
	17
	18	#define ICS_ARCIN_V5_INTRSTAT 0x0000
	19	#define ICS_ARCIN_V5_INTROFFSET 0x0004
	20
	21	#define ICS_ARCIN_V6_INTROFFSET_1 0x2200
	22	#define ICS_ARCIN_V6_INTRSTAT_1 0x2290
	23	#define ICS_ARCIN_V6_INTROFFSET_2 0x3200
	24	#define ICS_ARCIN_V6_INTRSTAT_2 0x3290
	25
	26	struct portinfo {
	27	unsigned int dataoffset;
	28	unsigned int ctrloffset;
	29	unsigned int stepping;
	30	};
	31
	32	static const struct portinfo pata_icside_portinfo_v5 = {
	33	.dataoffset = 0x2800,
	34	.ctrloffset = 0x2b80,
	35	.stepping = 6,
	36	};
	37
	38	static const struct portinfo pata_icside_portinfo_v6_1 = {
	39	.dataoffset = 0x2000,
	40	.ctrloffset = 0x2380,
	41	.stepping = 6,
	42	};
	43
	44	static const struct portinfo pata_icside_portinfo_v6_2 = {
	45	.dataoffset = 0x3000,
	46	.ctrloffset = 0x3380,
	47	.stepping = 6,
	48	};
	49
73b6a2be RK	50	struct pata_icside_state {
	51	void __iomem *irq_port;
	52	void __iomem *ioc_base;
	53	unsigned int type;
	54	unsigned int dma;
	55	struct {
	56	u8 port_sel;
	57	u8 disabled;
	58	unsigned int speed[ATA_MAX_DEVICES];
	59	} port[2];
73b6a2be RK	60	};
73b6a2be RK	61
f95637d2 RK	62	struct pata_icside_info {
	63	struct pata_icside_state *state;
	64	struct expansion_card *ec;
	65	void __iomem *base;
	66	void __iomem *irqaddr;
	67	unsigned int irqmask;
	68	const expansioncard_ops_t *irqops;
	69	unsigned int mwdma_mask;
	70	unsigned int nr_ports;
	71	const struct portinfo *port[2];
cbcdd875 TH	72	unsigned long raw_base;
cbcdd875 TH	73	unsigned long raw_ioc_base;
f95637d2 RK	74	};
f95637d2 RK	75
73b6a2be RK	76	#define ICS_TYPE_A3IN 0
	77	#define ICS_TYPE_A3USER 1
	78	#define ICS_TYPE_V6 3
	79	#define ICS_TYPE_V5 15
	80	#define ICS_TYPE_NOTYPE ((unsigned int)-1)
	81
	82	/* ---------------- Version 5 PCB Support Functions --------------------- */
	83	/* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	84	* Purpose : enable interrupts from card
	85	*/
	86	static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	87	{
	88	struct pata_icside_state *state = ec->irq_data;
	89
	90	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	91	}
	92
	93	/* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	94	* Purpose : disable interrupts from card
	95	*/
	96	static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	97	{
	98	struct pata_icside_state *state = ec->irq_data;
	99
	100	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	101	}
	102
	103	static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
	104	.irqenable = pata_icside_irqenable_arcin_v5,
	105	.irqdisable = pata_icside_irqdisable_arcin_v5,
	106	};
	107
	108
	109	/* ---------------- Version 6 PCB Support Functions --------------------- */
	110	/* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	111	* Purpose : enable interrupts from card
	112	*/
	113	static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	114	{
	115	struct pata_icside_state *state = ec->irq_data;
	116	void __iomem *base = state->irq_port;
	117
	118	if (!state->port[0].disabled)
	119	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
	120	if (!state->port[1].disabled)
	121	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
	122	}
	123
	124	/* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	125	* Purpose : disable interrupts from card
	126	*/
	127	static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	128	{
	129	struct pata_icside_state *state = ec->irq_data;
	130
	131	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	132	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
	133	}
	134
	135	/* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
	136	* Purpose : detect an active interrupt from card
	137	*/
	138	static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
	139	{
140	struct pata_icside_state *state = ec->irq_data;
141
142	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 \|\|
143	readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
144	}
145
146	static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
147	.irqenable = pata_icside_irqenable_arcin_v6,
148	.irqdisable = pata_icside_irqdisable_arcin_v6,
149	.irqpending = pata_icside_irqpending_arcin_v6,
150	};
151
152
153	/*
154	* SG-DMA support.
155	*
156	* Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
157	* There is only one DMA controller per card, which means that only
158	* one drive can be accessed at one time. NOTE! We do not enforce that
159	* here, but we rely on the main IDE driver spotting that both
160	* interfaces use the same IRQ, which should guarantee this.
161	*/
162
163	/*
164	* Configure the IOMD to give the appropriate timings for the transfer
165	* mode being requested. We take the advice of the ATA standards, and
166	* calculate the cycle time based on the transfer mode, and the EIDE
167	* MW DMA specs that the drive provides in the IDENTIFY command.
168	*
169	* We have the following IOMD DMA modes to choose from:
170	*
171	* Type Active Recovery Cycle
172	* A 250 (250) 312 (550) 562 (800)
173	* B 187 (200) 250 (550) 437 (750)
174	* C 125 (125) 125 (375) 250 (500)
175	* D 62 (50) 125 (375) 187 (425)
176	*
177	* (figures in brackets are actual measured timings on DIOR/DIOW)
178	*
179	* However, we also need to take care of the read/write active and
180	* recovery timings:
181	*
182	* Read Write
183	* Mode Active -- Recovery -- Cycle IOMD type
184	* MW0 215 50 215 480 A
185	* MW1 80 50 50 150 C
186	* MW2 70 25 25 120 C
187	*/
188	static void pata_icside_set_dmamode(struct ata_port ap, struct ata_device adev)
189	{
190	struct pata_icside_state *state = ap->host->private_data;
191	struct ata_timing t;
192	unsigned int cycle;
193	char iomd_type;
194
195	/*
196	* DMA is based on a 16MHz clock
197	*/
198	if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
199	return;
200
201	/*
202	* Choose the IOMD cycle timing which ensure that the interface
203	* satisfies the measured active, recovery and cycle times.
204	*/
205	if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
206	iomd_type = 'D', cycle = 187;
207	else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
208	iomd_type = 'C', cycle = 250;
209	else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
210	iomd_type = 'B', cycle = 437;
211	else
212	iomd_type = 'A', cycle = 562;
213
a9a79dfe JP	214	ata_dev_info(adev, "timings: act %dns rec %dns cyc %dns (%c)\n",
a9a79dfe JP	215	t.active, t.recover, t.cycle, iomd_type);
73b6a2be RK	216
	217	state->port[ap->port_no].speed[adev->devno] = cycle;
	218	}
	219
	220	static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
	221	{
	222	struct ata_port *ap = qc->ap;
	223	struct pata_icside_state *state = ap->host->private_data;
73b6a2be RK	224	unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
	225
	226	/*
	227	* We are simplex; BUG if we try to fiddle with DMA
	228	* while it's active.
	229	*/
	230	BUG_ON(dma_channel_active(state->dma));
	231
73b6a2be RK	232	/*
	233	* Route the DMA signals to the correct interface
	234	*/
	235	writeb(state->port[ap->port_no].port_sel, state->ioc_base);
	236
	237	set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
f6718653	238	set_dma_sg(state->dma, qc->sg, qc->n_elem);
73b6a2be RK	239	set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
	240
	241	/* issue r/w command */
5682ed33	242	ap->ops->sff_exec_command(ap, &qc->tf);
73b6a2be RK	243	}
	244
	245	static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
	246	{
	247	struct ata_port *ap = qc->ap;
	248	struct pata_icside_state *state = ap->host->private_data;
	249
	250	BUG_ON(dma_channel_active(state->dma));
	251	enable_dma(state->dma);
	252	}
	253
	254	static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
	255	{
	256	struct ata_port *ap = qc->ap;
	257	struct pata_icside_state *state = ap->host->private_data;
	258
	259	disable_dma(state->dma);
	260
	261	/* see ata_bmdma_stop */
a57c1bad	262	ata_sff_dma_pause(ap);
73b6a2be RK	263	}
	264
	265	static u8 pata_icside_bmdma_status(struct ata_port *ap)
	266	{
	267	struct pata_icside_state *state = ap->host->private_data;
	268	void __iomem *irq_port;
	269
	270	irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
	271	ICS_ARCIN_V6_INTRSTAT_1);
	272
	273	return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
	274	}
	275
f95637d2	276	static int icside_dma_init(struct pata_icside_info *info)
73b6a2be	277	{
f95637d2 RK	278	struct pata_icside_state *state = info->state;
f95637d2 RK	279	struct expansion_card *ec = info->ec;
73b6a2be RK	280	int i;
	281
	282	for (i = 0; i < ATA_MAX_DEVICES; i++) {
	283	state->port[0].speed[i] = 480;
	284	state->port[1].speed[i] = 480;
	285	}
	286
	287	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
	288	state->dma = ec->dma;
14bdef98	289	info->mwdma_mask = ATA_MWDMA2;
73b6a2be RK	290	}
	291
	292	return 0;
	293	}
	294
	295
73b6a2be	296	static struct scsi_host_template pata_icside_sht = {
68d1d07b	297	ATA_BASE_SHT(DRV_NAME),
65e8617f	298	.sg_tablesize = SG_MAX_SEGMENTS,
5369bea7	299	.dma_boundary = IOMD_DMA_BOUNDARY,
73b6a2be RK	300	};
73b6a2be RK	301
c15fcafe	302	static void pata_icside_postreset(struct ata_link link, unsigned int classes)
73b6a2be	303	{
c15fcafe	304	struct ata_port *ap = link->ap;
73b6a2be RK	305	struct pata_icside_state *state = ap->host->private_data;
73b6a2be RK	306
eba84481	307	if (classes[0] != ATA_DEV_NONE \|\| classes[1] != ATA_DEV_NONE)
9363c382	308	return ata_sff_postreset(link, classes);
73b6a2be RK	309
	310	state->port[ap->port_no].disabled = 1;
	311
	312	if (state->type == ICS_TYPE_V6) {
	313	/*
	314	* Disable interrupts from this port, otherwise we
	315	* receive spurious interrupts from the floating
	316	* interrupt line.
	317	*/
	318	void __iomem *irq_port = state->irq_port +
	319	(ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
	320	readb(irq_port);
	321	}
	322	}
	323
73b6a2be	324	static struct ata_port_operations pata_icside_port_ops = {
8930ff25	325	.inherits = &ata_bmdma_port_ops,
73b6a2be RK	326	/* no need to build any PRD tables for DMA */
73b6a2be RK	327	.qc_prep = ata_noop_qc_prep,
23ebda2f	328	.sff_data_xfer = ata_sff_data_xfer32,
029cfd6b TH	329	.bmdma_setup = pata_icside_bmdma_setup,
	330	.bmdma_start = pata_icside_bmdma_start,
	331	.bmdma_stop = pata_icside_bmdma_stop,
	332	.bmdma_status = pata_icside_bmdma_status,
73b6a2be	333
029cfd6b TH	334	.cable_detect = ata_cable_40wire,
029cfd6b TH	335	.set_dmamode = pata_icside_set_dmamode,
a1efdaba	336	.postreset = pata_icside_postreset,
8930ff25	337
c7087652	338	.port_start = ATA_OP_NULL, /* don't need PRD table */
73b6a2be RK	339	};
73b6a2be RK	340
0ec24914 GKH	341	static void pata_icside_setup_ioaddr(struct ata_port ap, void __iomem base,
	342	struct pata_icside_info *info,
	343	const struct portinfo *port)
73b6a2be	344	{
cbcdd875	345	struct ata_ioports *ioaddr = &ap->ioaddr;
c15fcafe	346	void __iomem *cmd = base + port->dataoffset;
73b6a2be RK	347
73b6a2be RK	348	ioaddr->cmd_addr = cmd;
c15fcafe AV	349	ioaddr->data_addr = cmd + (ATA_REG_DATA << port->stepping);
	350	ioaddr->error_addr = cmd + (ATA_REG_ERR << port->stepping);
	351	ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << port->stepping);
	352	ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << port->stepping);
	353	ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping);
	354	ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << port->stepping);
	355	ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << port->stepping);
	356	ioaddr->device_addr = cmd + (ATA_REG_DEVICE << port->stepping);
	357	ioaddr->status_addr = cmd + (ATA_REG_STATUS << port->stepping);
	358	ioaddr->command_addr = cmd + (ATA_REG_CMD << port->stepping);
	359
	360	ioaddr->ctl_addr = base + port->ctrloffset;
73b6a2be	361	ioaddr->altstatus_addr = ioaddr->ctl_addr;
cbcdd875 TH	362
cbcdd875 TH	363	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
c15fcafe AV	364	info->raw_base + port->dataoffset,
c15fcafe AV	365	info->raw_base + port->ctrloffset);
cbcdd875 TH	366
	367	if (info->raw_ioc_base)
	368	ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
73b6a2be RK	369	}
73b6a2be RK	370
0ec24914	371	static int pata_icside_register_v5(struct pata_icside_info *info)
73b6a2be	372	{
f95637d2	373	struct pata_icside_state *state = info->state;
73b6a2be RK	374	void __iomem *base;
73b6a2be RK	375
10bdaaa0	376	base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
73b6a2be RK	377	if (!base)
	378	return -ENOMEM;
	379
	380	state->irq_port = base;
	381
f95637d2 RK	382	info->base = base;
	383	info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
	384	info->irqmask = 1;
	385	info->irqops = &pata_icside_ops_arcin_v5;
	386	info->nr_ports = 1;
	387	info->port[0] = &pata_icside_portinfo_v5;
73b6a2be	388
c15fcafe	389	info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);
cbcdd875	390
73b6a2be RK	391	return 0;
	392	}
	393
0ec24914	394	static int pata_icside_register_v6(struct pata_icside_info *info)
73b6a2be	395	{
f95637d2 RK	396	struct pata_icside_state *state = info->state;
f95637d2 RK	397	struct expansion_card *ec = info->ec;
73b6a2be RK	398	void __iomem ioc_base, easi_base;
73b6a2be RK	399	unsigned int sel = 0;
73b6a2be	400
10bdaaa0 RK	401	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	402	if (!ioc_base)
	403	return -ENOMEM;
73b6a2be RK	404
	405	easi_base = ioc_base;
	406
	407	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
10bdaaa0 RK	408	easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
	409	if (!easi_base)
	410	return -ENOMEM;
73b6a2be RK	411
	412	/*
	413	* Enable access to the EASI region.
	414	*/
	415	sel = 1 << 5;
	416	}
	417
	418	writeb(sel, ioc_base);
	419
73b6a2be RK	420	state->irq_port = easi_base;
	421	state->ioc_base = ioc_base;
	422	state->port[0].port_sel = sel;
	423	state->port[1].port_sel = sel \| 1;
	424
f95637d2 RK	425	info->base = easi_base;
	426	info->irqops = &pata_icside_ops_arcin_v6;
	427	info->nr_ports = 2;
	428	info->port[0] = &pata_icside_portinfo_v6_1;
	429	info->port[1] = &pata_icside_portinfo_v6_2;
	430
cbcdd875 TH	431	info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
	432	info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);
	433
f95637d2 RK	434	return icside_dma_init(info);
	435	}
	436
0ec24914	437	static int pata_icside_add_ports(struct pata_icside_info *info)
f95637d2 RK	438	{
	439	struct expansion_card *ec = info->ec;
	440	struct ata_host *host;
	441	int i;
	442
	443	if (info->irqaddr) {
	444	ec->irqaddr = info->irqaddr;
	445	ec->irqmask = info->irqmask;
	446	}
	447	if (info->irqops)
	448	ecard_setirq(ec, info->irqops, info->state);
	449
	450	/*
	451	* Be on the safe side - disable interrupts
	452	*/
	453	ec->ops->irqdisable(ec, ec->irq);
	454
	455	host = ata_host_alloc(&ec->dev, info->nr_ports);
	456	if (!host)
	457	return -ENOMEM;
	458
	459	host->private_data = info->state;
	460	host->flags = ATA_HOST_SIMPLEX;
	461
	462	for (i = 0; i < info->nr_ports; i++) {
	463	struct ata_port *ap = host->ports[i];
	464
14bdef98	465	ap->pio_mask = ATA_PIO4;
f95637d2	466	ap->mwdma_mask = info->mwdma_mask;
1d2808fd	467	ap->flags \|= ATA_FLAG_SLAVE_POSS;
f95637d2 RK	468	ap->ops = &pata_icside_port_ops;
f95637d2 RK	469
c15fcafe	470	pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
f95637d2	471	}
73b6a2be	472
c3b28894	473	return ata_host_activate(host, ec->irq, ata_bmdma_interrupt, 0,
f95637d2	474	&pata_icside_sht);
73b6a2be RK	475	}
73b6a2be RK	476
0ec24914 GKH	477	static int pata_icside_probe(struct expansion_card *ec,
0ec24914 GKH	478	const struct ecard_id *id)
73b6a2be RK	479	{
73b6a2be RK	480	struct pata_icside_state *state;
f95637d2	481	struct pata_icside_info info;
73b6a2be RK	482	void __iomem *idmem;
	483	int ret;
	484
	485	ret = ecard_request_resources(ec);
	486	if (ret)
	487	goto out;
	488
f95637d2	489	state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
73b6a2be RK	490	if (!state) {
	491	ret = -ENOMEM;
	492	goto release;
	493	}
	494
	495	state->type = ICS_TYPE_NOTYPE;
	496	state->dma = NO_DMA;
	497
10bdaaa0	498	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
73b6a2be RK	499	if (idmem) {
	500	unsigned int type;
	501
	502	type = readb(idmem + ICS_IDENT_OFFSET) & 1;
	503	type \|= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
	504	type \|= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
	505	type \|= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
10bdaaa0	506	ecardm_iounmap(ec, idmem);
73b6a2be RK	507
	508	state->type = type;
	509	}
	510
f95637d2 RK	511	memset(&info, 0, sizeof(info));
	512	info.state = state;
	513	info.ec = ec;
73b6a2be RK	514
	515	switch (state->type) {
	516	case ICS_TYPE_A3IN:
	517	dev_warn(&ec->dev, "A3IN unsupported\n");
	518	ret = -ENODEV;
	519	break;
	520
	521	case ICS_TYPE_A3USER:
	522	dev_warn(&ec->dev, "A3USER unsupported\n");
	523	ret = -ENODEV;
	524	break;
	525
	526	case ICS_TYPE_V5:
f95637d2	527	ret = pata_icside_register_v5(&info);
73b6a2be RK	528	break;
	529
	530	case ICS_TYPE_V6:
f95637d2	531	ret = pata_icside_register_v6(&info);
73b6a2be RK	532	break;
	533
	534	default:
	535	dev_warn(&ec->dev, "unknown interface type\n");
	536	ret = -ENODEV;
	537	break;
	538	}
	539
	540	if (ret == 0)
f95637d2	541	ret = pata_icside_add_ports(&info);
73b6a2be RK	542
	543	if (ret == 0)
	544	goto out;
	545
73b6a2be RK	546	release:
	547	ecard_release_resources(ec);
	548	out:
	549	return ret;
	550	}
	551
	552	static void pata_icside_shutdown(struct expansion_card *ec)
	553	{
	554	struct ata_host *host = ecard_get_drvdata(ec);
	555	unsigned long flags;
	556
	557	/*
	558	* Disable interrupts from this card. We need to do
	559	* this before disabling EASI since we may be accessing
	560	* this register via that region.
	561	*/
	562	local_irq_save(flags);
c7b87f3d	563	ec->ops->irqdisable(ec, ec->irq);
73b6a2be RK	564	local_irq_restore(flags);
	565
	566	/*
	567	* Reset the ROM pointer so that we can read the ROM
	568	* after a soft reboot. This also disables access to
	569	* the IDE taskfile via the EASI region.
	570	*/
	571	if (host) {
	572	struct pata_icside_state *state = host->private_data;
	573	if (state->ioc_base)
	574	writeb(0, state->ioc_base);
	575	}
	576	}
	577
0ec24914	578	static void pata_icside_remove(struct expansion_card *ec)
73b6a2be RK	579	{
	580	struct ata_host *host = ecard_get_drvdata(ec);
	581	struct pata_icside_state *state = host->private_data;
	582
	583	ata_host_detach(host);
	584
	585	pata_icside_shutdown(ec);
	586
	587	/*
	588	* don't NULL out the drvdata - devres/libata wants it
	589	* to free the ata_host structure.
	590	*/
73b6a2be RK	591	if (state->dma != NO_DMA)
73b6a2be RK	592	free_dma(state->dma);
73b6a2be	593
73b6a2be RK	594	ecard_release_resources(ec);
	595	}
	596
	597	static const struct ecard_id pata_icside_ids[] = {
	598	{ MANU_ICS, PROD_ICS_IDE },
	599	{ MANU_ICS2, PROD_ICS2_IDE },
	600	{ 0xffff, 0xffff }
	601	};
	602
	603	static struct ecard_driver pata_icside_driver = {
	604	.probe = pata_icside_probe,
0ec24914	605	.remove = pata_icside_remove,
73b6a2be RK	606	.shutdown = pata_icside_shutdown,
	607	.id_table = pata_icside_ids,
	608	.drv = {
	609	.name = DRV_NAME,
	610	},
	611	};
	612
	613	static int __init pata_icside_init(void)
	614	{
	615	return ecard_register_driver(&pata_icside_driver);
	616	}
	617
	618	static void __exit pata_icside_exit(void)
	619	{
	620	ecard_remove_driver(&pata_icside_driver);
	621	}
	622
	623	MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
	624	MODULE_LICENSE("GPL");
	625	MODULE_DESCRIPTION("ICS PATA driver");
	626
	627	module_init(pata_icside_init);
	628	module_exit(pata_icside_exit);