[mirror_ubuntu-bionic-kernel.git] / drivers / ata / pata_icside.c

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <scsi/scsi_host.h>
#include <linux/ata.h>
#include <linux/libata.h>

#include <asm/dma.h>
#include <asm/ecard.h>

#define DRV_NAME	"pata_icside"

#define ICS_IDENT_OFFSET		0x2280

#define ICS_ARCIN_V5_INTRSTAT		0x0000
#define ICS_ARCIN_V5_INTROFFSET		0x0004

#define ICS_ARCIN_V6_INTROFFSET_1	0x2200
#define ICS_ARCIN_V6_INTRSTAT_1		0x2290
#define ICS_ARCIN_V6_INTROFFSET_2	0x3200
#define ICS_ARCIN_V6_INTRSTAT_2		0x3290

struct portinfo {
	unsigned int dataoffset;
	unsigned int ctrloffset;
	unsigned int stepping;
};

static const struct portinfo pata_icside_portinfo_v5 = {
	.dataoffset	= 0x2800,
	.ctrloffset	= 0x2b80,
	.stepping	= 6,
};

static const struct portinfo pata_icside_portinfo_v6_1 = {
	.dataoffset	= 0x2000,
	.ctrloffset	= 0x2380,
	.stepping	= 6,
};

static const struct portinfo pata_icside_portinfo_v6_2 = {
	.dataoffset	= 0x3000,
	.ctrloffset	= 0x3380,
	.stepping	= 6,
};

#define PATA_ICSIDE_MAX_SG	128

struct pata_icside_state {
	void __iomem *irq_port;
	void __iomem *ioc_base;
	unsigned int type;
	unsigned int dma;
	struct {
		u8 port_sel;
		u8 disabled;
		unsigned int speed[ATA_MAX_DEVICES];
	} port[2];
	struct scatterlist sg[PATA_ICSIDE_MAX_SG];
};

struct pata_icside_info {
	struct pata_icside_state *state;
	struct expansion_card	*ec;
	void __iomem		*base;
	void __iomem		*irqaddr;
	unsigned int		irqmask;
	const expansioncard_ops_t *irqops;
	unsigned int		mwdma_mask;
	unsigned int		nr_ports;
	const struct portinfo	*port[2];
	unsigned long		raw_base;
	unsigned long		raw_ioc_base;
};

#define ICS_TYPE_A3IN	0
#define ICS_TYPE_A3USER	1
#define ICS_TYPE_V6	3
#define ICS_TYPE_V5	15
#define ICS_TYPE_NOTYPE	((unsigned int)-1)

/* ---------------- Version 5 PCB Support Functions --------------------- */
/* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct pata_icside_state *state = ec->irq_data;

	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

/* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
{
	struct pata_icside_state *state = ec->irq_data;

	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
}

static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
	.irqenable	= pata_icside_irqenable_arcin_v5,
	.irqdisable	= pata_icside_irqdisable_arcin_v5,
};


/* ---------------- Version 6 PCB Support Functions --------------------- */
/* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : enable interrupts from card
 */
static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct pata_icside_state *state = ec->irq_data;
	void __iomem *base = state->irq_port;

	if (!state->port[0].disabled)
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
	if (!state->port[1].disabled)
		writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
}

/* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 * Purpose  : disable interrupts from card
 */
static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
{
	struct pata_icside_state *state = ec->irq_data;

	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
}

/* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
 * Purpose  : detect an active interrupt from card
 */
static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
{
	struct pata_icside_state *state = ec->irq_data;

	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
	       readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
}

static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
	.irqenable	= pata_icside_irqenable_arcin_v6,
	.irqdisable	= pata_icside_irqdisable_arcin_v6,
	.irqpending	= pata_icside_irqpending_arcin_v6,
};


/*
 * SG-DMA support.
 *
 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 * There is only one DMA controller per card, which means that only
 * one drive can be accessed at one time.  NOTE! We do not enforce that
 * here, but we rely on the main IDE driver spotting that both
 * interfaces use the same IRQ, which should guarantee this.
 */

/*
 * Configure the IOMD to give the appropriate timings for the transfer
 * mode being requested.  We take the advice of the ATA standards, and
 * calculate the cycle time based on the transfer mode, and the EIDE
 * MW DMA specs that the drive provides in the IDENTIFY command.
 *
 * We have the following IOMD DMA modes to choose from:
 *
 *	Type	Active		Recovery	Cycle
 *	A	250 (250)	312 (550)	562 (800)
 *	B	187 (200)	250 (550)	437 (750)
 *	C	125 (125)	125 (375)	250 (500)
 *	D	62  (50)	125 (375)	187 (425)
 *
 * (figures in brackets are actual measured timings on DIOR/DIOW)
 *
 * However, we also need to take care of the read/write active and
 * recovery timings:
 *
 *			Read	Write
 *  	Mode	Active	-- Recovery --	Cycle	IOMD type
 *	MW0	215	50	215	480	A
 *	MW1	80	50	50	150	C
 *	MW2	70	25	25	120	C
 */
static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pata_icside_state *state = ap->host->private_data;
	struct ata_timing t;
	unsigned int cycle;
	char iomd_type;

	/*
	 * DMA is based on a 16MHz clock
	 */
	if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
		return;

	/*
	 * Choose the IOMD cycle timing which ensure that the interface
	 * satisfies the measured active, recovery and cycle times.
	 */
	if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
		iomd_type = 'D', cycle = 187;
	else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
		iomd_type = 'C', cycle = 250;
	else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
		iomd_type = 'B', cycle = 437;
	else
		iomd_type = 'A', cycle = 562;

	ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n",
		t.active, t.recover, t.cycle, iomd_type);

	state->port[ap->port_no].speed[adev->devno] = cycle;
}

static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pata_icside_state *state = ap->host->private_data;
	struct scatterlist *sg, *rsg = state->sg;
	unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
	unsigned int si;

	/*
	 * We are simplex; BUG if we try to fiddle with DMA
	 * while it's active.
	 */
	BUG_ON(dma_channel_active(state->dma));

	/*
	 * Copy ATAs scattered sg list into a contiguous array of sg
	 */
	for_each_sg(qc->sg, sg, qc->n_elem, si) {
		memcpy(rsg, sg, sizeof(*sg));
		rsg++;
	}

	/*
	 * Route the DMA signals to the correct interface
	 */
	writeb(state->port[ap->port_no].port_sel, state->ioc_base);

	set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
	set_dma_sg(state->dma, state->sg, rsg - state->sg);
	set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);

	/* issue r/w command */
	ap->ops->exec_command(ap, &qc->tf);
}

static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pata_icside_state *state = ap->host->private_data;

	BUG_ON(dma_channel_active(state->dma));
	enable_dma(state->dma);
}

static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pata_icside_state *state = ap->host->private_data;

	disable_dma(state->dma);

	/* see ata_bmdma_stop */
	ata_altstatus(ap);
}

static u8 pata_icside_bmdma_status(struct ata_port *ap)
{
	struct pata_icside_state *state = ap->host->private_data;
	void __iomem *irq_port;

	irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
						    ICS_ARCIN_V6_INTRSTAT_1);

	return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
}

static int icside_dma_init(struct pata_icside_info *info)
{
	struct pata_icside_state *state = info->state;
	struct expansion_card *ec = info->ec;
	int i;

	for (i = 0; i < ATA_MAX_DEVICES; i++) {
		state->port[0].speed[i] = 480;
		state->port[1].speed[i] = 480;
	}

	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
		state->dma = ec->dma;
		info->mwdma_mask = 0x07;	/* MW0..2 */
	}

	return 0;
}


static struct scsi_host_template pata_icside_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= PATA_ICSIDE_MAX_SG,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ~0, /* no dma boundaries */
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
{
	struct ata_port *ap = link->ap;
	struct pata_icside_state *state = ap->host->private_data;

	if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE)
		return ata_std_postreset(link, classes);

	state->port[ap->port_no].disabled = 1;

	if (state->type == ICS_TYPE_V6) {
		/*
		 * Disable interrupts from this port, otherwise we
		 * receive spurious interrupts from the floating
		 * interrupt line.
		 */
		void __iomem *irq_port = state->irq_port +
				(ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
		readb(irq_port);
	}
}

static void pata_icside_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
			   pata_icside_postreset);
}

static struct ata_port_operations pata_icside_port_ops = {
	.set_dmamode		= pata_icside_set_dmamode,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.exec_command		= ata_exec_command,
	.check_status		= ata_check_status,
	.dev_select		= ata_std_dev_select,

	.cable_detect		= ata_cable_40wire,

	.bmdma_setup		= pata_icside_bmdma_setup,
	.bmdma_start		= pata_icside_bmdma_start,

	.data_xfer		= ata_data_xfer_noirq,

	/* no need to build any PRD tables for DMA */
	.qc_prep		= ata_noop_qc_prep,
	.qc_issue		= ata_qc_issue_prot,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= pata_icside_error_handler,
	.post_internal_cmd	= pata_icside_bmdma_stop,

	.irq_clear		= ata_noop_irq_clear,
	.irq_on			= ata_irq_on,

	.bmdma_stop		= pata_icside_bmdma_stop,
	.bmdma_status		= pata_icside_bmdma_status,
};

static void __devinit
pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base,
			 struct pata_icside_info *info,
			 const struct portinfo *port)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	void __iomem *cmd = base + port->dataoffset;

	ioaddr->cmd_addr	= cmd;
	ioaddr->data_addr	= cmd + (ATA_REG_DATA    << port->stepping);
	ioaddr->error_addr	= cmd + (ATA_REG_ERR     << port->stepping);
	ioaddr->feature_addr	= cmd + (ATA_REG_FEATURE << port->stepping);
	ioaddr->nsect_addr	= cmd + (ATA_REG_NSECT   << port->stepping);
	ioaddr->lbal_addr	= cmd + (ATA_REG_LBAL    << port->stepping);
	ioaddr->lbam_addr	= cmd + (ATA_REG_LBAM    << port->stepping);
	ioaddr->lbah_addr	= cmd + (ATA_REG_LBAH    << port->stepping);
	ioaddr->device_addr	= cmd + (ATA_REG_DEVICE  << port->stepping);
	ioaddr->status_addr	= cmd + (ATA_REG_STATUS  << port->stepping);
	ioaddr->command_addr	= cmd + (ATA_REG_CMD     << port->stepping);

	ioaddr->ctl_addr	= base + port->ctrloffset;
	ioaddr->altstatus_addr	= ioaddr->ctl_addr;

	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
		      info->raw_base + port->dataoffset,
		      info->raw_base + port->ctrloffset);

	if (info->raw_ioc_base)
		ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
}

static int __devinit pata_icside_register_v5(struct pata_icside_info *info)
{
	struct pata_icside_state *state = info->state;
	void __iomem *base;

	base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
	if (!base)
		return -ENOMEM;

	state->irq_port = base;

	info->base = base;
	info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
	info->irqmask = 1;
	info->irqops = &pata_icside_ops_arcin_v5;
	info->nr_ports = 1;
	info->port[0] = &pata_icside_portinfo_v5;

	info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);

	return 0;
}

static int __devinit pata_icside_register_v6(struct pata_icside_info *info)
{
	struct pata_icside_state *state = info->state;
	struct expansion_card *ec = info->ec;
	void __iomem *ioc_base, *easi_base;
	unsigned int sel = 0;

	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (!ioc_base)
		return -ENOMEM;

	easi_base = ioc_base;

	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
		easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
		if (!easi_base)
			return -ENOMEM;

		/*
		 * Enable access to the EASI region.
		 */
		sel = 1 << 5;
	}

	writeb(sel, ioc_base);

	state->irq_port = easi_base;
	state->ioc_base = ioc_base;
	state->port[0].port_sel = sel;
	state->port[1].port_sel = sel | 1;

	info->base = easi_base;
	info->irqops = &pata_icside_ops_arcin_v6;
	info->nr_ports = 2;
	info->port[0] = &pata_icside_portinfo_v6_1;
	info->port[1] = &pata_icside_portinfo_v6_2;

	info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
	info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);

	return icside_dma_init(info);
}

static int __devinit pata_icside_add_ports(struct pata_icside_info *info)
{
	struct expansion_card *ec = info->ec;
	struct ata_host *host;
	int i;

	if (info->irqaddr) {
		ec->irqaddr = info->irqaddr;
		ec->irqmask = info->irqmask;
	}
	if (info->irqops)
		ecard_setirq(ec, info->irqops, info->state);

	/*
	 * Be on the safe side - disable interrupts
	 */
	ec->ops->irqdisable(ec, ec->irq);

	host = ata_host_alloc(&ec->dev, info->nr_ports);
	if (!host)
		return -ENOMEM;

	host->private_data = info->state;
	host->flags = ATA_HOST_SIMPLEX;

	for (i = 0; i < info->nr_ports; i++) {
		struct ata_port *ap = host->ports[i];

		ap->pio_mask = 0x1f;
		ap->mwdma_mask = info->mwdma_mask;
		ap->flags |= ATA_FLAG_SLAVE_POSS;
		ap->ops = &pata_icside_port_ops;

		pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
	}

	return ata_host_activate(host, ec->irq, ata_interrupt, 0,
				 &pata_icside_sht);
}

static int __devinit
pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id)
{
	struct pata_icside_state *state;
	struct pata_icside_info info;
	void __iomem *idmem;
	int ret;

	ret = ecard_request_resources(ec);
	if (ret)
		goto out;

	state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
	if (!state) {
		ret = -ENOMEM;
		goto release;
	}

	state->type = ICS_TYPE_NOTYPE;
	state->dma = NO_DMA;

	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	if (idmem) {
		unsigned int type;

		type = readb(idmem + ICS_IDENT_OFFSET) & 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
		type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
		ecardm_iounmap(ec, idmem);

		state->type = type;
	}

	memset(&info, 0, sizeof(info));
	info.state = state;
	info.ec = ec;

	switch (state->type) {
	case ICS_TYPE_A3IN:
		dev_warn(&ec->dev, "A3IN unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_A3USER:
		dev_warn(&ec->dev, "A3USER unsupported\n");
		ret = -ENODEV;
		break;

	case ICS_TYPE_V5:
		ret = pata_icside_register_v5(&info);
		break;

	case ICS_TYPE_V6:
		ret = pata_icside_register_v6(&info);
		break;

	default:
		dev_warn(&ec->dev, "unknown interface type\n");
		ret = -ENODEV;
		break;
	}

	if (ret == 0)
		ret = pata_icside_add_ports(&info);

	if (ret == 0)
		goto out;

 release:
	ecard_release_resources(ec);
 out:
	return ret;
}

static void pata_icside_shutdown(struct expansion_card *ec)
{
	struct ata_host *host = ecard_get_drvdata(ec);
	unsigned long flags;

	/*
	 * Disable interrupts from this card.  We need to do
	 * this before disabling EASI since we may be accessing
	 * this register via that region.
	 */
	local_irq_save(flags);
	ec->ops->irqdisable(ec, ec->irq);
	local_irq_restore(flags);

	/*
	 * Reset the ROM pointer so that we can read the ROM
	 * after a soft reboot.  This also disables access to
	 * the IDE taskfile via the EASI region.
	 */
	if (host) {
		struct pata_icside_state *state = host->private_data;
		if (state->ioc_base)
			writeb(0, state->ioc_base);
	}
}

static void __devexit pata_icside_remove(struct expansion_card *ec)
{
	struct ata_host *host = ecard_get_drvdata(ec);
	struct pata_icside_state *state = host->private_data;

	ata_host_detach(host);

	pata_icside_shutdown(ec);

	/*
	 * don't NULL out the drvdata - devres/libata wants it
	 * to free the ata_host structure.
	 */
	if (state->dma != NO_DMA)
		free_dma(state->dma);

	ecard_release_resources(ec);
}

static const struct ecard_id pata_icside_ids[] = {
	{ MANU_ICS,  PROD_ICS_IDE  },
	{ MANU_ICS2, PROD_ICS2_IDE },
	{ 0xffff, 0xffff }
};

static struct ecard_driver pata_icside_driver = {
	.probe		= pata_icside_probe,
	.remove 	= __devexit_p(pata_icside_remove),
	.shutdown	= pata_icside_shutdown,
	.id_table	= pata_icside_ids,
	.drv = {
		.name	= DRV_NAME,
	},
};

static int __init pata_icside_init(void)
{
	return ecard_register_driver(&pata_icside_driver);
}

static void __exit pata_icside_exit(void)
{
	ecard_remove_driver(&pata_icside_driver);
}

MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("ICS PATA driver");

module_init(pata_icside_init);
module_exit(pata_icside_exit);
Commit	Line	Data
73b6a2be RK	1	#include <linux/kernel.h>
	2	#include <linux/module.h>
	3	#include <linux/init.h>
	4	#include <linux/blkdev.h>
	5	#include <scsi/scsi_host.h>
	6	#include <linux/ata.h>
	7	#include <linux/libata.h>
	8
	9	#include <asm/dma.h>
	10	#include <asm/ecard.h>
	11
	12	#define DRV_NAME "pata_icside"
	13
	14	#define ICS_IDENT_OFFSET 0x2280
	15
	16	#define ICS_ARCIN_V5_INTRSTAT 0x0000
	17	#define ICS_ARCIN_V5_INTROFFSET 0x0004
	18
	19	#define ICS_ARCIN_V6_INTROFFSET_1 0x2200
	20	#define ICS_ARCIN_V6_INTRSTAT_1 0x2290
	21	#define ICS_ARCIN_V6_INTROFFSET_2 0x3200
	22	#define ICS_ARCIN_V6_INTRSTAT_2 0x3290
	23
	24	struct portinfo {
	25	unsigned int dataoffset;
	26	unsigned int ctrloffset;
	27	unsigned int stepping;
	28	};
	29
	30	static const struct portinfo pata_icside_portinfo_v5 = {
	31	.dataoffset = 0x2800,
	32	.ctrloffset = 0x2b80,
	33	.stepping = 6,
	34	};
	35
	36	static const struct portinfo pata_icside_portinfo_v6_1 = {
	37	.dataoffset = 0x2000,
	38	.ctrloffset = 0x2380,
	39	.stepping = 6,
	40	};
	41
	42	static const struct portinfo pata_icside_portinfo_v6_2 = {
	43	.dataoffset = 0x3000,
	44	.ctrloffset = 0x3380,
	45	.stepping = 6,
	46	};
	47
	48	#define PATA_ICSIDE_MAX_SG 128
	49
	50	struct pata_icside_state {
	51	void __iomem *irq_port;
	52	void __iomem *ioc_base;
	53	unsigned int type;
	54	unsigned int dma;
	55	struct {
	56	u8 port_sel;
	57	u8 disabled;
	58	unsigned int speed[ATA_MAX_DEVICES];
	59	} port[2];
	60	struct scatterlist sg[PATA_ICSIDE_MAX_SG];
	61	};
	62
f95637d2 RK	63	struct pata_icside_info {
	64	struct pata_icside_state *state;
	65	struct expansion_card *ec;
	66	void __iomem *base;
	67	void __iomem *irqaddr;
	68	unsigned int irqmask;
	69	const expansioncard_ops_t *irqops;
	70	unsigned int mwdma_mask;
	71	unsigned int nr_ports;
	72	const struct portinfo *port[2];
cbcdd875 TH	73	unsigned long raw_base;
cbcdd875 TH	74	unsigned long raw_ioc_base;
f95637d2 RK	75	};
f95637d2 RK	76
73b6a2be RK	77	#define ICS_TYPE_A3IN 0
	78	#define ICS_TYPE_A3USER 1
	79	#define ICS_TYPE_V6 3
	80	#define ICS_TYPE_V5 15
	81	#define ICS_TYPE_NOTYPE ((unsigned int)-1)
	82
	83	/* ---------------- Version 5 PCB Support Functions --------------------- */
	84	/* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	85	* Purpose : enable interrupts from card
	86	*/
	87	static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
	88	{
	89	struct pata_icside_state *state = ec->irq_data;
	90
	91	writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	92	}
	93
	94	/* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	95	* Purpose : disable interrupts from card
	96	*/
	97	static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
	98	{
	99	struct pata_icside_state *state = ec->irq_data;
	100
	101	readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
	102	}
	103
	104	static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
	105	.irqenable = pata_icside_irqenable_arcin_v5,
	106	.irqdisable = pata_icside_irqdisable_arcin_v5,
	107	};
	108
	109
	110	/* ---------------- Version 6 PCB Support Functions --------------------- */
	111	/* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	112	* Purpose : enable interrupts from card
	113	*/
	114	static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
	115	{
	116	struct pata_icside_state *state = ec->irq_data;
	117	void __iomem *base = state->irq_port;
	118
	119	if (!state->port[0].disabled)
	120	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
	121	if (!state->port[1].disabled)
	122	writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
	123	}
	124
	125	/* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	126	* Purpose : disable interrupts from card
	127	*/
	128	static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
	129	{
	130	struct pata_icside_state *state = ec->irq_data;
	131
	132	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
	133	readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
	134	}
	135
	136	/* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
	137	* Purpose : detect an active interrupt from card
	138	*/
	139	static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
	140	{
141	struct pata_icside_state *state = ec->irq_data;
142
143	return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 \|\|
144	readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
145	}
146
147	static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
148	.irqenable = pata_icside_irqenable_arcin_v6,
149	.irqdisable = pata_icside_irqdisable_arcin_v6,
150	.irqpending = pata_icside_irqpending_arcin_v6,
151	};
152
153
154	/*
155	* SG-DMA support.
156	*
157	* Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
158	* There is only one DMA controller per card, which means that only
159	* one drive can be accessed at one time. NOTE! We do not enforce that
160	* here, but we rely on the main IDE driver spotting that both
161	* interfaces use the same IRQ, which should guarantee this.
162	*/
163
164	/*
165	* Configure the IOMD to give the appropriate timings for the transfer
166	* mode being requested. We take the advice of the ATA standards, and
167	* calculate the cycle time based on the transfer mode, and the EIDE
168	* MW DMA specs that the drive provides in the IDENTIFY command.
169	*
170	* We have the following IOMD DMA modes to choose from:
171	*
172	* Type Active Recovery Cycle
173	* A 250 (250) 312 (550) 562 (800)
174	* B 187 (200) 250 (550) 437 (750)
175	* C 125 (125) 125 (375) 250 (500)
176	* D 62 (50) 125 (375) 187 (425)
177	*
178	* (figures in brackets are actual measured timings on DIOR/DIOW)
179	*
180	* However, we also need to take care of the read/write active and
181	* recovery timings:
182	*
183	* Read Write
184	* Mode Active -- Recovery -- Cycle IOMD type
185	* MW0 215 50 215 480 A
186	* MW1 80 50 50 150 C
187	* MW2 70 25 25 120 C
188	*/
189	static void pata_icside_set_dmamode(struct ata_port ap, struct ata_device adev)
190	{
191	struct pata_icside_state *state = ap->host->private_data;
192	struct ata_timing t;
193	unsigned int cycle;
194	char iomd_type;
195
196	/*
197	* DMA is based on a 16MHz clock
198	*/
199	if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
200	return;
201
202	/*
203	* Choose the IOMD cycle timing which ensure that the interface
204	* satisfies the measured active, recovery and cycle times.
205	*/
206	if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
207	iomd_type = 'D', cycle = 187;
208	else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
209	iomd_type = 'C', cycle = 250;
210	else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
211	iomd_type = 'B', cycle = 437;
212	else
213	iomd_type = 'A', cycle = 562;
214
215	ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n",
216	t.active, t.recover, t.cycle, iomd_type);
217
218	state->port[ap->port_no].speed[adev->devno] = cycle;
219	}
220
221	static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
222	{
223	struct ata_port *ap = qc->ap;
224	struct pata_icside_state *state = ap->host->private_data;
225	struct scatterlist sg, rsg = state->sg;
226	unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
ff2aeb1e	227	unsigned int si;
73b6a2be RK	228
	229	/*
	230	* We are simplex; BUG if we try to fiddle with DMA
	231	* while it's active.
	232	*/
	233	BUG_ON(dma_channel_active(state->dma));
	234
	235	/*
	236	* Copy ATAs scattered sg list into a contiguous array of sg
	237	*/
ff2aeb1e	238	for_each_sg(qc->sg, sg, qc->n_elem, si) {
73b6a2be RK	239	memcpy(rsg, sg, sizeof(*sg));
	240	rsg++;
	241	}
	242
	243	/*
	244	* Route the DMA signals to the correct interface
	245	*/
	246	writeb(state->port[ap->port_no].port_sel, state->ioc_base);
	247
	248	set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
	249	set_dma_sg(state->dma, state->sg, rsg - state->sg);
	250	set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
	251
	252	/* issue r/w command */
	253	ap->ops->exec_command(ap, &qc->tf);
	254	}
	255
	256	static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
	257	{
	258	struct ata_port *ap = qc->ap;
	259	struct pata_icside_state *state = ap->host->private_data;
	260
	261	BUG_ON(dma_channel_active(state->dma));
	262	enable_dma(state->dma);
	263	}
	264
	265	static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
	266	{
	267	struct ata_port *ap = qc->ap;
	268	struct pata_icside_state *state = ap->host->private_data;
	269
	270	disable_dma(state->dma);
	271
	272	/* see ata_bmdma_stop */
	273	ata_altstatus(ap);
	274	}
	275
	276	static u8 pata_icside_bmdma_status(struct ata_port *ap)
	277	{
	278	struct pata_icside_state *state = ap->host->private_data;
	279	void __iomem *irq_port;
	280
	281	irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
	282	ICS_ARCIN_V6_INTRSTAT_1);
	283
	284	return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
	285	}
	286
f95637d2	287	static int icside_dma_init(struct pata_icside_info *info)
73b6a2be	288	{
f95637d2 RK	289	struct pata_icside_state *state = info->state;
f95637d2 RK	290	struct expansion_card *ec = info->ec;
73b6a2be RK	291	int i;
	292
	293	for (i = 0; i < ATA_MAX_DEVICES; i++) {
	294	state->port[0].speed[i] = 480;
	295	state->port[1].speed[i] = 480;
	296	}
	297
	298	if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
	299	state->dma = ec->dma;
f95637d2	300	info->mwdma_mask = 0x07; /* MW0..2 */
73b6a2be RK	301	}
	302
	303	return 0;
	304	}
	305
	306
73b6a2be RK	307	static struct scsi_host_template pata_icside_sht = {
	308	.module = THIS_MODULE,
	309	.name = DRV_NAME,
	310	.ioctl = ata_scsi_ioctl,
	311	.queuecommand = ata_scsi_queuecmd,
	312	.can_queue = ATA_DEF_QUEUE,
	313	.this_id = ATA_SHT_THIS_ID,
	314	.sg_tablesize = PATA_ICSIDE_MAX_SG,
	315	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	316	.emulated = ATA_SHT_EMULATED,
	317	.use_clustering = ATA_SHT_USE_CLUSTERING,
	318	.proc_name = DRV_NAME,
	319	.dma_boundary = ~0, /* no dma boundaries */
	320	.slave_configure = ata_scsi_slave_config,
	321	.slave_destroy = ata_scsi_slave_destroy,
	322	.bios_param = ata_std_bios_param,
	323	};
	324
c15fcafe	325	static void pata_icside_postreset(struct ata_link link, unsigned int classes)
73b6a2be	326	{
c15fcafe	327	struct ata_port *ap = link->ap;
73b6a2be RK	328	struct pata_icside_state *state = ap->host->private_data;
73b6a2be RK	329
eba84481	330	if (classes[0] != ATA_DEV_NONE \|\| classes[1] != ATA_DEV_NONE)
c15fcafe	331	return ata_std_postreset(link, classes);
73b6a2be RK	332
	333	state->port[ap->port_no].disabled = 1;
	334
	335	if (state->type == ICS_TYPE_V6) {
	336	/*
	337	* Disable interrupts from this port, otherwise we
	338	* receive spurious interrupts from the floating
	339	* interrupt line.
	340	*/
	341	void __iomem *irq_port = state->irq_port +
	342	(ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
	343	readb(irq_port);
	344	}
	345	}
	346
eba84481 RK	347	static void pata_icside_error_handler(struct ata_port *ap)
	348	{
	349	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
	350	pata_icside_postreset);
	351	}
	352
73b6a2be	353	static struct ata_port_operations pata_icside_port_ops = {
73b6a2be RK	354	.set_dmamode = pata_icside_set_dmamode,
	355
	356	.tf_load = ata_tf_load,
	357	.tf_read = ata_tf_read,
	358	.exec_command = ata_exec_command,
	359	.check_status = ata_check_status,
	360	.dev_select = ata_std_dev_select,
	361
f95637d2 RK	362	.cable_detect = ata_cable_40wire,
f95637d2 RK	363
73b6a2be RK	364	.bmdma_setup = pata_icside_bmdma_setup,
	365	.bmdma_start = pata_icside_bmdma_start,
	366
	367	.data_xfer = ata_data_xfer_noirq,
	368
	369	/* no need to build any PRD tables for DMA */
	370	.qc_prep = ata_noop_qc_prep,
	371	.qc_issue = ata_qc_issue_prot,
	372
	373	.freeze = ata_bmdma_freeze,
	374	.thaw = ata_bmdma_thaw,
eba84481	375	.error_handler = pata_icside_error_handler,
73b6a2be RK	376	.post_internal_cmd = pata_icside_bmdma_stop,
73b6a2be RK	377
358f9a77	378	.irq_clear = ata_noop_irq_clear,
73b6a2be	379	.irq_on = ata_irq_on,
73b6a2be	380
73b6a2be RK	381	.bmdma_stop = pata_icside_bmdma_stop,
	382	.bmdma_status = pata_icside_bmdma_status,
	383	};
	384
f95637d2	385	static void __devinit
cbcdd875	386	pata_icside_setup_ioaddr(struct ata_port ap, void __iomem base,
c15fcafe AV	387	struct pata_icside_info *info,
c15fcafe AV	388	const struct portinfo *port)
73b6a2be	389	{
cbcdd875	390	struct ata_ioports *ioaddr = &ap->ioaddr;
c15fcafe	391	void __iomem *cmd = base + port->dataoffset;
73b6a2be RK	392
73b6a2be RK	393	ioaddr->cmd_addr = cmd;
c15fcafe AV	394	ioaddr->data_addr = cmd + (ATA_REG_DATA << port->stepping);
	395	ioaddr->error_addr = cmd + (ATA_REG_ERR << port->stepping);
	396	ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << port->stepping);
	397	ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << port->stepping);
	398	ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping);
	399	ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << port->stepping);
	400	ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << port->stepping);
	401	ioaddr->device_addr = cmd + (ATA_REG_DEVICE << port->stepping);
	402	ioaddr->status_addr = cmd + (ATA_REG_STATUS << port->stepping);
	403	ioaddr->command_addr = cmd + (ATA_REG_CMD << port->stepping);
	404
	405	ioaddr->ctl_addr = base + port->ctrloffset;
73b6a2be	406	ioaddr->altstatus_addr = ioaddr->ctl_addr;
cbcdd875 TH	407
cbcdd875 TH	408	ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
c15fcafe AV	409	info->raw_base + port->dataoffset,
c15fcafe AV	410	info->raw_base + port->ctrloffset);
cbcdd875 TH	411
	412	if (info->raw_ioc_base)
	413	ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
73b6a2be RK	414	}
73b6a2be RK	415
f95637d2	416	static int __devinit pata_icside_register_v5(struct pata_icside_info *info)
73b6a2be	417	{
f95637d2	418	struct pata_icside_state *state = info->state;
73b6a2be RK	419	void __iomem *base;
73b6a2be RK	420
10bdaaa0	421	base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
73b6a2be RK	422	if (!base)
	423	return -ENOMEM;
	424
	425	state->irq_port = base;
	426
f95637d2 RK	427	info->base = base;
	428	info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
	429	info->irqmask = 1;
	430	info->irqops = &pata_icside_ops_arcin_v5;
	431	info->nr_ports = 1;
	432	info->port[0] = &pata_icside_portinfo_v5;
73b6a2be	433
c15fcafe	434	info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);
cbcdd875	435
73b6a2be RK	436	return 0;
	437	}
	438
f95637d2	439	static int __devinit pata_icside_register_v6(struct pata_icside_info *info)
73b6a2be	440	{
f95637d2 RK	441	struct pata_icside_state *state = info->state;
f95637d2 RK	442	struct expansion_card *ec = info->ec;
73b6a2be RK	443	void __iomem ioc_base, easi_base;
73b6a2be RK	444	unsigned int sel = 0;
73b6a2be	445
10bdaaa0 RK	446	ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
	447	if (!ioc_base)
	448	return -ENOMEM;
73b6a2be RK	449
	450	easi_base = ioc_base;
	451
	452	if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
10bdaaa0 RK	453	easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
	454	if (!easi_base)
	455	return -ENOMEM;
73b6a2be RK	456
	457	/*
	458	* Enable access to the EASI region.
	459	*/
	460	sel = 1 << 5;
	461	}
	462
	463	writeb(sel, ioc_base);
	464
73b6a2be RK	465	state->irq_port = easi_base;
	466	state->ioc_base = ioc_base;
	467	state->port[0].port_sel = sel;
	468	state->port[1].port_sel = sel \| 1;
	469
f95637d2 RK	470	info->base = easi_base;
	471	info->irqops = &pata_icside_ops_arcin_v6;
	472	info->nr_ports = 2;
	473	info->port[0] = &pata_icside_portinfo_v6_1;
	474	info->port[1] = &pata_icside_portinfo_v6_2;
	475
cbcdd875 TH	476	info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
	477	info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);
	478
f95637d2 RK	479	return icside_dma_init(info);
	480	}
	481
	482	static int __devinit pata_icside_add_ports(struct pata_icside_info *info)
	483	{
	484	struct expansion_card *ec = info->ec;
	485	struct ata_host *host;
	486	int i;
	487
	488	if (info->irqaddr) {
	489	ec->irqaddr = info->irqaddr;
	490	ec->irqmask = info->irqmask;
	491	}
	492	if (info->irqops)
	493	ecard_setirq(ec, info->irqops, info->state);
	494
	495	/*
	496	* Be on the safe side - disable interrupts
	497	*/
	498	ec->ops->irqdisable(ec, ec->irq);
	499
	500	host = ata_host_alloc(&ec->dev, info->nr_ports);
	501	if (!host)
	502	return -ENOMEM;
	503
	504	host->private_data = info->state;
	505	host->flags = ATA_HOST_SIMPLEX;
	506
	507	for (i = 0; i < info->nr_ports; i++) {
	508	struct ata_port *ap = host->ports[i];
	509
	510	ap->pio_mask = 0x1f;
	511	ap->mwdma_mask = info->mwdma_mask;
1d2808fd	512	ap->flags \|= ATA_FLAG_SLAVE_POSS;
f95637d2 RK	513	ap->ops = &pata_icside_port_ops;
f95637d2 RK	514
c15fcafe	515	pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
f95637d2	516	}
73b6a2be	517
f95637d2 RK	518	return ata_host_activate(host, ec->irq, ata_interrupt, 0,
f95637d2 RK	519	&pata_icside_sht);
73b6a2be RK	520	}
	521
	522	static int __devinit
	523	pata_icside_probe(struct expansion_card ec, const struct ecard_id id)
	524	{
	525	struct pata_icside_state *state;
f95637d2	526	struct pata_icside_info info;
73b6a2be RK	527	void __iomem *idmem;
	528	int ret;
	529
	530	ret = ecard_request_resources(ec);
	531	if (ret)
	532	goto out;
	533
f95637d2	534	state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
73b6a2be RK	535	if (!state) {
	536	ret = -ENOMEM;
	537	goto release;
	538	}
	539
	540	state->type = ICS_TYPE_NOTYPE;
	541	state->dma = NO_DMA;
	542
10bdaaa0	543	idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
73b6a2be RK	544	if (idmem) {
	545	unsigned int type;
	546
	547	type = readb(idmem + ICS_IDENT_OFFSET) & 1;
	548	type \|= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
	549	type \|= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
	550	type \|= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
10bdaaa0	551	ecardm_iounmap(ec, idmem);
73b6a2be RK	552
	553	state->type = type;
	554	}
	555
f95637d2 RK	556	memset(&info, 0, sizeof(info));
	557	info.state = state;
	558	info.ec = ec;
73b6a2be RK	559
	560	switch (state->type) {
	561	case ICS_TYPE_A3IN:
	562	dev_warn(&ec->dev, "A3IN unsupported\n");
	563	ret = -ENODEV;
	564	break;
	565
	566	case ICS_TYPE_A3USER:
	567	dev_warn(&ec->dev, "A3USER unsupported\n");
	568	ret = -ENODEV;
	569	break;
	570
	571	case ICS_TYPE_V5:
f95637d2	572	ret = pata_icside_register_v5(&info);
73b6a2be RK	573	break;
	574
	575	case ICS_TYPE_V6:
f95637d2	576	ret = pata_icside_register_v6(&info);
73b6a2be RK	577	break;
	578
	579	default:
	580	dev_warn(&ec->dev, "unknown interface type\n");
	581	ret = -ENODEV;
	582	break;
	583	}
	584
	585	if (ret == 0)
f95637d2	586	ret = pata_icside_add_ports(&info);
73b6a2be RK	587
	588	if (ret == 0)
	589	goto out;
	590
73b6a2be RK	591	release:
	592	ecard_release_resources(ec);
	593	out:
	594	return ret;
	595	}
	596
	597	static void pata_icside_shutdown(struct expansion_card *ec)
	598	{
	599	struct ata_host *host = ecard_get_drvdata(ec);
	600	unsigned long flags;
	601
	602	/*
	603	* Disable interrupts from this card. We need to do
	604	* this before disabling EASI since we may be accessing
	605	* this register via that region.
	606	*/
	607	local_irq_save(flags);
c7b87f3d	608	ec->ops->irqdisable(ec, ec->irq);
73b6a2be RK	609	local_irq_restore(flags);
	610
	611	/*
	612	* Reset the ROM pointer so that we can read the ROM
	613	* after a soft reboot. This also disables access to
	614	* the IDE taskfile via the EASI region.
	615	*/
	616	if (host) {
	617	struct pata_icside_state *state = host->private_data;
	618	if (state->ioc_base)
	619	writeb(0, state->ioc_base);
	620	}
	621	}
	622
	623	static void __devexit pata_icside_remove(struct expansion_card *ec)
	624	{
	625	struct ata_host *host = ecard_get_drvdata(ec);
	626	struct pata_icside_state *state = host->private_data;
	627
	628	ata_host_detach(host);
	629
	630	pata_icside_shutdown(ec);
	631
	632	/*
	633	* don't NULL out the drvdata - devres/libata wants it
	634	* to free the ata_host structure.
	635	*/
73b6a2be RK	636	if (state->dma != NO_DMA)
73b6a2be RK	637	free_dma(state->dma);
73b6a2be	638
73b6a2be RK	639	ecard_release_resources(ec);
	640	}
	641
	642	static const struct ecard_id pata_icside_ids[] = {
	643	{ MANU_ICS, PROD_ICS_IDE },
	644	{ MANU_ICS2, PROD_ICS2_IDE },
	645	{ 0xffff, 0xffff }
	646	};
	647
	648	static struct ecard_driver pata_icside_driver = {
	649	.probe = pata_icside_probe,
	650	.remove = __devexit_p(pata_icside_remove),
	651	.shutdown = pata_icside_shutdown,
	652	.id_table = pata_icside_ids,
	653	.drv = {
	654	.name = DRV_NAME,
	655	},
	656	};
	657
	658	static int __init pata_icside_init(void)
	659	{
	660	return ecard_register_driver(&pata_icside_driver);
	661	}
	662
	663	static void __exit pata_icside_exit(void)
	664	{
	665	ecard_remove_driver(&pata_icside_driver);
	666	}
	667
	668	MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
	669	MODULE_LICENSE("GPL");
	670	MODULE_DESCRIPTION("ICS PATA driver");
	671
	672	module_init(pata_icside_init);
	673	module_exit(pata_icside_exit);