]>
Commit | Line | Data |
---|---|---|
73b6a2be RK |
1 | #include <linux/kernel.h> |
2 | #include <linux/module.h> | |
3 | #include <linux/init.h> | |
4 | #include <linux/blkdev.h> | |
5 | #include <scsi/scsi_host.h> | |
6 | #include <linux/ata.h> | |
7 | #include <linux/libata.h> | |
8 | ||
9 | #include <asm/dma.h> | |
10 | #include <asm/ecard.h> | |
11 | ||
12 | #define DRV_NAME "pata_icside" | |
13 | ||
14 | #define ICS_IDENT_OFFSET 0x2280 | |
15 | ||
16 | #define ICS_ARCIN_V5_INTRSTAT 0x0000 | |
17 | #define ICS_ARCIN_V5_INTROFFSET 0x0004 | |
18 | ||
19 | #define ICS_ARCIN_V6_INTROFFSET_1 0x2200 | |
20 | #define ICS_ARCIN_V6_INTRSTAT_1 0x2290 | |
21 | #define ICS_ARCIN_V6_INTROFFSET_2 0x3200 | |
22 | #define ICS_ARCIN_V6_INTRSTAT_2 0x3290 | |
23 | ||
24 | struct portinfo { | |
25 | unsigned int dataoffset; | |
26 | unsigned int ctrloffset; | |
27 | unsigned int stepping; | |
28 | }; | |
29 | ||
30 | static const struct portinfo pata_icside_portinfo_v5 = { | |
31 | .dataoffset = 0x2800, | |
32 | .ctrloffset = 0x2b80, | |
33 | .stepping = 6, | |
34 | }; | |
35 | ||
36 | static const struct portinfo pata_icside_portinfo_v6_1 = { | |
37 | .dataoffset = 0x2000, | |
38 | .ctrloffset = 0x2380, | |
39 | .stepping = 6, | |
40 | }; | |
41 | ||
42 | static const struct portinfo pata_icside_portinfo_v6_2 = { | |
43 | .dataoffset = 0x3000, | |
44 | .ctrloffset = 0x3380, | |
45 | .stepping = 6, | |
46 | }; | |
47 | ||
48 | #define PATA_ICSIDE_MAX_SG 128 | |
49 | ||
50 | struct pata_icside_state { | |
51 | void __iomem *irq_port; | |
52 | void __iomem *ioc_base; | |
53 | unsigned int type; | |
54 | unsigned int dma; | |
55 | struct { | |
56 | u8 port_sel; | |
57 | u8 disabled; | |
58 | unsigned int speed[ATA_MAX_DEVICES]; | |
59 | } port[2]; | |
60 | struct scatterlist sg[PATA_ICSIDE_MAX_SG]; | |
61 | }; | |
62 | ||
f95637d2 RK |
63 | struct pata_icside_info { |
64 | struct pata_icside_state *state; | |
65 | struct expansion_card *ec; | |
66 | void __iomem *base; | |
67 | void __iomem *irqaddr; | |
68 | unsigned int irqmask; | |
69 | const expansioncard_ops_t *irqops; | |
70 | unsigned int mwdma_mask; | |
71 | unsigned int nr_ports; | |
72 | const struct portinfo *port[2]; | |
cbcdd875 TH |
73 | unsigned long raw_base; |
74 | unsigned long raw_ioc_base; | |
f95637d2 RK |
75 | }; |
76 | ||
73b6a2be RK |
77 | #define ICS_TYPE_A3IN 0 |
78 | #define ICS_TYPE_A3USER 1 | |
79 | #define ICS_TYPE_V6 3 | |
80 | #define ICS_TYPE_V5 15 | |
81 | #define ICS_TYPE_NOTYPE ((unsigned int)-1) | |
82 | ||
83 | /* ---------------- Version 5 PCB Support Functions --------------------- */ | |
84 | /* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
85 | * Purpose : enable interrupts from card | |
86 | */ | |
87 | static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
88 | { | |
89 | struct pata_icside_state *state = ec->irq_data; | |
90 | ||
91 | writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
92 | } | |
93 | ||
94 | /* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
95 | * Purpose : disable interrupts from card | |
96 | */ | |
97 | static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr) | |
98 | { | |
99 | struct pata_icside_state *state = ec->irq_data; | |
100 | ||
101 | readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); | |
102 | } | |
103 | ||
104 | static const expansioncard_ops_t pata_icside_ops_arcin_v5 = { | |
105 | .irqenable = pata_icside_irqenable_arcin_v5, | |
106 | .irqdisable = pata_icside_irqdisable_arcin_v5, | |
107 | }; | |
108 | ||
109 | ||
110 | /* ---------------- Version 6 PCB Support Functions --------------------- */ | |
111 | /* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
112 | * Purpose : enable interrupts from card | |
113 | */ | |
114 | static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
115 | { | |
116 | struct pata_icside_state *state = ec->irq_data; | |
117 | void __iomem *base = state->irq_port; | |
118 | ||
119 | if (!state->port[0].disabled) | |
120 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1); | |
121 | if (!state->port[1].disabled) | |
122 | writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2); | |
123 | } | |
124 | ||
125 | /* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
126 | * Purpose : disable interrupts from card | |
127 | */ | |
128 | static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr) | |
129 | { | |
130 | struct pata_icside_state *state = ec->irq_data; | |
131 | ||
132 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1); | |
133 | readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2); | |
134 | } | |
135 | ||
136 | /* Prototype: pata_icside_irqprobe(struct expansion_card *ec) | |
137 | * Purpose : detect an active interrupt from card | |
138 | */ | |
139 | static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec) | |
140 | { | |
141 | struct pata_icside_state *state = ec->irq_data; | |
142 | ||
143 | return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 || | |
144 | readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1; | |
145 | } | |
146 | ||
147 | static const expansioncard_ops_t pata_icside_ops_arcin_v6 = { | |
148 | .irqenable = pata_icside_irqenable_arcin_v6, | |
149 | .irqdisable = pata_icside_irqdisable_arcin_v6, | |
150 | .irqpending = pata_icside_irqpending_arcin_v6, | |
151 | }; | |
152 | ||
153 | ||
154 | /* | |
155 | * SG-DMA support. | |
156 | * | |
157 | * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers. | |
158 | * There is only one DMA controller per card, which means that only | |
159 | * one drive can be accessed at one time. NOTE! We do not enforce that | |
160 | * here, but we rely on the main IDE driver spotting that both | |
161 | * interfaces use the same IRQ, which should guarantee this. | |
162 | */ | |
163 | ||
164 | /* | |
165 | * Configure the IOMD to give the appropriate timings for the transfer | |
166 | * mode being requested. We take the advice of the ATA standards, and | |
167 | * calculate the cycle time based on the transfer mode, and the EIDE | |
168 | * MW DMA specs that the drive provides in the IDENTIFY command. | |
169 | * | |
170 | * We have the following IOMD DMA modes to choose from: | |
171 | * | |
172 | * Type Active Recovery Cycle | |
173 | * A 250 (250) 312 (550) 562 (800) | |
174 | * B 187 (200) 250 (550) 437 (750) | |
175 | * C 125 (125) 125 (375) 250 (500) | |
176 | * D 62 (50) 125 (375) 187 (425) | |
177 | * | |
178 | * (figures in brackets are actual measured timings on DIOR/DIOW) | |
179 | * | |
180 | * However, we also need to take care of the read/write active and | |
181 | * recovery timings: | |
182 | * | |
183 | * Read Write | |
184 | * Mode Active -- Recovery -- Cycle IOMD type | |
185 | * MW0 215 50 215 480 A | |
186 | * MW1 80 50 50 150 C | |
187 | * MW2 70 25 25 120 C | |
188 | */ | |
189 | static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
190 | { | |
191 | struct pata_icside_state *state = ap->host->private_data; | |
192 | struct ata_timing t; | |
193 | unsigned int cycle; | |
194 | char iomd_type; | |
195 | ||
196 | /* | |
197 | * DMA is based on a 16MHz clock | |
198 | */ | |
199 | if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1)) | |
200 | return; | |
201 | ||
202 | /* | |
203 | * Choose the IOMD cycle timing which ensure that the interface | |
204 | * satisfies the measured active, recovery and cycle times. | |
205 | */ | |
206 | if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) | |
207 | iomd_type = 'D', cycle = 187; | |
208 | else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) | |
209 | iomd_type = 'C', cycle = 250; | |
210 | else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) | |
211 | iomd_type = 'B', cycle = 437; | |
212 | else | |
213 | iomd_type = 'A', cycle = 562; | |
214 | ||
215 | ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n", | |
216 | t.active, t.recover, t.cycle, iomd_type); | |
217 | ||
218 | state->port[ap->port_no].speed[adev->devno] = cycle; | |
219 | } | |
220 | ||
221 | static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc) | |
222 | { | |
223 | struct ata_port *ap = qc->ap; | |
224 | struct pata_icside_state *state = ap->host->private_data; | |
225 | struct scatterlist *sg, *rsg = state->sg; | |
226 | unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE; | |
ff2aeb1e | 227 | unsigned int si; |
73b6a2be RK |
228 | |
229 | /* | |
230 | * We are simplex; BUG if we try to fiddle with DMA | |
231 | * while it's active. | |
232 | */ | |
233 | BUG_ON(dma_channel_active(state->dma)); | |
234 | ||
235 | /* | |
236 | * Copy ATAs scattered sg list into a contiguous array of sg | |
237 | */ | |
ff2aeb1e | 238 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
73b6a2be RK |
239 | memcpy(rsg, sg, sizeof(*sg)); |
240 | rsg++; | |
241 | } | |
242 | ||
243 | /* | |
244 | * Route the DMA signals to the correct interface | |
245 | */ | |
246 | writeb(state->port[ap->port_no].port_sel, state->ioc_base); | |
247 | ||
248 | set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]); | |
249 | set_dma_sg(state->dma, state->sg, rsg - state->sg); | |
250 | set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ); | |
251 | ||
252 | /* issue r/w command */ | |
253 | ap->ops->exec_command(ap, &qc->tf); | |
254 | } | |
255 | ||
256 | static void pata_icside_bmdma_start(struct ata_queued_cmd *qc) | |
257 | { | |
258 | struct ata_port *ap = qc->ap; | |
259 | struct pata_icside_state *state = ap->host->private_data; | |
260 | ||
261 | BUG_ON(dma_channel_active(state->dma)); | |
262 | enable_dma(state->dma); | |
263 | } | |
264 | ||
265 | static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc) | |
266 | { | |
267 | struct ata_port *ap = qc->ap; | |
268 | struct pata_icside_state *state = ap->host->private_data; | |
269 | ||
270 | disable_dma(state->dma); | |
271 | ||
272 | /* see ata_bmdma_stop */ | |
273 | ata_altstatus(ap); | |
274 | } | |
275 | ||
276 | static u8 pata_icside_bmdma_status(struct ata_port *ap) | |
277 | { | |
278 | struct pata_icside_state *state = ap->host->private_data; | |
279 | void __iomem *irq_port; | |
280 | ||
281 | irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 : | |
282 | ICS_ARCIN_V6_INTRSTAT_1); | |
283 | ||
284 | return readb(irq_port) & 1 ? ATA_DMA_INTR : 0; | |
285 | } | |
286 | ||
f95637d2 | 287 | static int icside_dma_init(struct pata_icside_info *info) |
73b6a2be | 288 | { |
f95637d2 RK |
289 | struct pata_icside_state *state = info->state; |
290 | struct expansion_card *ec = info->ec; | |
73b6a2be RK |
291 | int i; |
292 | ||
293 | for (i = 0; i < ATA_MAX_DEVICES; i++) { | |
294 | state->port[0].speed[i] = 480; | |
295 | state->port[1].speed[i] = 480; | |
296 | } | |
297 | ||
298 | if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) { | |
299 | state->dma = ec->dma; | |
f95637d2 | 300 | info->mwdma_mask = 0x07; /* MW0..2 */ |
73b6a2be RK |
301 | } |
302 | ||
303 | return 0; | |
304 | } | |
305 | ||
306 | ||
73b6a2be | 307 | static struct scsi_host_template pata_icside_sht = { |
68d1d07b | 308 | ATA_BASE_SHT(DRV_NAME), |
73b6a2be | 309 | .sg_tablesize = PATA_ICSIDE_MAX_SG, |
73b6a2be | 310 | .dma_boundary = ~0, /* no dma boundaries */ |
73b6a2be RK |
311 | }; |
312 | ||
c15fcafe | 313 | static void pata_icside_postreset(struct ata_link *link, unsigned int *classes) |
73b6a2be | 314 | { |
c15fcafe | 315 | struct ata_port *ap = link->ap; |
73b6a2be RK |
316 | struct pata_icside_state *state = ap->host->private_data; |
317 | ||
eba84481 | 318 | if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE) |
c15fcafe | 319 | return ata_std_postreset(link, classes); |
73b6a2be RK |
320 | |
321 | state->port[ap->port_no].disabled = 1; | |
322 | ||
323 | if (state->type == ICS_TYPE_V6) { | |
324 | /* | |
325 | * Disable interrupts from this port, otherwise we | |
326 | * receive spurious interrupts from the floating | |
327 | * interrupt line. | |
328 | */ | |
329 | void __iomem *irq_port = state->irq_port + | |
330 | (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1); | |
331 | readb(irq_port); | |
332 | } | |
333 | } | |
334 | ||
eba84481 RK |
335 | static void pata_icside_error_handler(struct ata_port *ap) |
336 | { | |
337 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL, | |
338 | pata_icside_postreset); | |
339 | } | |
340 | ||
73b6a2be | 341 | static struct ata_port_operations pata_icside_port_ops = { |
029cfd6b | 342 | .inherits = &ata_sff_port_ops, |
73b6a2be RK |
343 | /* no need to build any PRD tables for DMA */ |
344 | .qc_prep = ata_noop_qc_prep, | |
029cfd6b TH |
345 | .data_xfer = ata_data_xfer_noirq, |
346 | .bmdma_setup = pata_icside_bmdma_setup, | |
347 | .bmdma_start = pata_icside_bmdma_start, | |
348 | .bmdma_stop = pata_icside_bmdma_stop, | |
349 | .bmdma_status = pata_icside_bmdma_status, | |
73b6a2be | 350 | |
029cfd6b TH |
351 | .cable_detect = ata_cable_40wire, |
352 | .set_dmamode = pata_icside_set_dmamode, | |
eba84481 | 353 | .error_handler = pata_icside_error_handler, |
73b6a2be | 354 | .post_internal_cmd = pata_icside_bmdma_stop, |
73b6a2be RK |
355 | }; |
356 | ||
f95637d2 | 357 | static void __devinit |
cbcdd875 | 358 | pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base, |
c15fcafe AV |
359 | struct pata_icside_info *info, |
360 | const struct portinfo *port) | |
73b6a2be | 361 | { |
cbcdd875 | 362 | struct ata_ioports *ioaddr = &ap->ioaddr; |
c15fcafe | 363 | void __iomem *cmd = base + port->dataoffset; |
73b6a2be RK |
364 | |
365 | ioaddr->cmd_addr = cmd; | |
c15fcafe AV |
366 | ioaddr->data_addr = cmd + (ATA_REG_DATA << port->stepping); |
367 | ioaddr->error_addr = cmd + (ATA_REG_ERR << port->stepping); | |
368 | ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << port->stepping); | |
369 | ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << port->stepping); | |
370 | ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << port->stepping); | |
371 | ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << port->stepping); | |
372 | ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << port->stepping); | |
373 | ioaddr->device_addr = cmd + (ATA_REG_DEVICE << port->stepping); | |
374 | ioaddr->status_addr = cmd + (ATA_REG_STATUS << port->stepping); | |
375 | ioaddr->command_addr = cmd + (ATA_REG_CMD << port->stepping); | |
376 | ||
377 | ioaddr->ctl_addr = base + port->ctrloffset; | |
73b6a2be | 378 | ioaddr->altstatus_addr = ioaddr->ctl_addr; |
cbcdd875 TH |
379 | |
380 | ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", | |
c15fcafe AV |
381 | info->raw_base + port->dataoffset, |
382 | info->raw_base + port->ctrloffset); | |
cbcdd875 TH |
383 | |
384 | if (info->raw_ioc_base) | |
385 | ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base); | |
73b6a2be RK |
386 | } |
387 | ||
f95637d2 | 388 | static int __devinit pata_icside_register_v5(struct pata_icside_info *info) |
73b6a2be | 389 | { |
f95637d2 | 390 | struct pata_icside_state *state = info->state; |
73b6a2be RK |
391 | void __iomem *base; |
392 | ||
10bdaaa0 | 393 | base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0); |
73b6a2be RK |
394 | if (!base) |
395 | return -ENOMEM; | |
396 | ||
397 | state->irq_port = base; | |
398 | ||
f95637d2 RK |
399 | info->base = base; |
400 | info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT; | |
401 | info->irqmask = 1; | |
402 | info->irqops = &pata_icside_ops_arcin_v5; | |
403 | info->nr_ports = 1; | |
404 | info->port[0] = &pata_icside_portinfo_v5; | |
73b6a2be | 405 | |
c15fcafe | 406 | info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC); |
cbcdd875 | 407 | |
73b6a2be RK |
408 | return 0; |
409 | } | |
410 | ||
f95637d2 | 411 | static int __devinit pata_icside_register_v6(struct pata_icside_info *info) |
73b6a2be | 412 | { |
f95637d2 RK |
413 | struct pata_icside_state *state = info->state; |
414 | struct expansion_card *ec = info->ec; | |
73b6a2be RK |
415 | void __iomem *ioc_base, *easi_base; |
416 | unsigned int sel = 0; | |
73b6a2be | 417 | |
10bdaaa0 RK |
418 | ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); |
419 | if (!ioc_base) | |
420 | return -ENOMEM; | |
73b6a2be RK |
421 | |
422 | easi_base = ioc_base; | |
423 | ||
424 | if (ecard_resource_flags(ec, ECARD_RES_EASI)) { | |
10bdaaa0 RK |
425 | easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0); |
426 | if (!easi_base) | |
427 | return -ENOMEM; | |
73b6a2be RK |
428 | |
429 | /* | |
430 | * Enable access to the EASI region. | |
431 | */ | |
432 | sel = 1 << 5; | |
433 | } | |
434 | ||
435 | writeb(sel, ioc_base); | |
436 | ||
73b6a2be RK |
437 | state->irq_port = easi_base; |
438 | state->ioc_base = ioc_base; | |
439 | state->port[0].port_sel = sel; | |
440 | state->port[1].port_sel = sel | 1; | |
441 | ||
f95637d2 RK |
442 | info->base = easi_base; |
443 | info->irqops = &pata_icside_ops_arcin_v6; | |
444 | info->nr_ports = 2; | |
445 | info->port[0] = &pata_icside_portinfo_v6_1; | |
446 | info->port[1] = &pata_icside_portinfo_v6_2; | |
447 | ||
cbcdd875 TH |
448 | info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI); |
449 | info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST); | |
450 | ||
f95637d2 RK |
451 | return icside_dma_init(info); |
452 | } | |
453 | ||
454 | static int __devinit pata_icside_add_ports(struct pata_icside_info *info) | |
455 | { | |
456 | struct expansion_card *ec = info->ec; | |
457 | struct ata_host *host; | |
458 | int i; | |
459 | ||
460 | if (info->irqaddr) { | |
461 | ec->irqaddr = info->irqaddr; | |
462 | ec->irqmask = info->irqmask; | |
463 | } | |
464 | if (info->irqops) | |
465 | ecard_setirq(ec, info->irqops, info->state); | |
466 | ||
467 | /* | |
468 | * Be on the safe side - disable interrupts | |
469 | */ | |
470 | ec->ops->irqdisable(ec, ec->irq); | |
471 | ||
472 | host = ata_host_alloc(&ec->dev, info->nr_ports); | |
473 | if (!host) | |
474 | return -ENOMEM; | |
475 | ||
476 | host->private_data = info->state; | |
477 | host->flags = ATA_HOST_SIMPLEX; | |
478 | ||
479 | for (i = 0; i < info->nr_ports; i++) { | |
480 | struct ata_port *ap = host->ports[i]; | |
481 | ||
482 | ap->pio_mask = 0x1f; | |
483 | ap->mwdma_mask = info->mwdma_mask; | |
1d2808fd | 484 | ap->flags |= ATA_FLAG_SLAVE_POSS; |
f95637d2 RK |
485 | ap->ops = &pata_icside_port_ops; |
486 | ||
c15fcafe | 487 | pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]); |
f95637d2 | 488 | } |
73b6a2be | 489 | |
f95637d2 RK |
490 | return ata_host_activate(host, ec->irq, ata_interrupt, 0, |
491 | &pata_icside_sht); | |
73b6a2be RK |
492 | } |
493 | ||
494 | static int __devinit | |
495 | pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id) | |
496 | { | |
497 | struct pata_icside_state *state; | |
f95637d2 | 498 | struct pata_icside_info info; |
73b6a2be RK |
499 | void __iomem *idmem; |
500 | int ret; | |
501 | ||
502 | ret = ecard_request_resources(ec); | |
503 | if (ret) | |
504 | goto out; | |
505 | ||
f95637d2 | 506 | state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL); |
73b6a2be RK |
507 | if (!state) { |
508 | ret = -ENOMEM; | |
509 | goto release; | |
510 | } | |
511 | ||
512 | state->type = ICS_TYPE_NOTYPE; | |
513 | state->dma = NO_DMA; | |
514 | ||
10bdaaa0 | 515 | idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); |
73b6a2be RK |
516 | if (idmem) { |
517 | unsigned int type; | |
518 | ||
519 | type = readb(idmem + ICS_IDENT_OFFSET) & 1; | |
520 | type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1; | |
521 | type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2; | |
522 | type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3; | |
10bdaaa0 | 523 | ecardm_iounmap(ec, idmem); |
73b6a2be RK |
524 | |
525 | state->type = type; | |
526 | } | |
527 | ||
f95637d2 RK |
528 | memset(&info, 0, sizeof(info)); |
529 | info.state = state; | |
530 | info.ec = ec; | |
73b6a2be RK |
531 | |
532 | switch (state->type) { | |
533 | case ICS_TYPE_A3IN: | |
534 | dev_warn(&ec->dev, "A3IN unsupported\n"); | |
535 | ret = -ENODEV; | |
536 | break; | |
537 | ||
538 | case ICS_TYPE_A3USER: | |
539 | dev_warn(&ec->dev, "A3USER unsupported\n"); | |
540 | ret = -ENODEV; | |
541 | break; | |
542 | ||
543 | case ICS_TYPE_V5: | |
f95637d2 | 544 | ret = pata_icside_register_v5(&info); |
73b6a2be RK |
545 | break; |
546 | ||
547 | case ICS_TYPE_V6: | |
f95637d2 | 548 | ret = pata_icside_register_v6(&info); |
73b6a2be RK |
549 | break; |
550 | ||
551 | default: | |
552 | dev_warn(&ec->dev, "unknown interface type\n"); | |
553 | ret = -ENODEV; | |
554 | break; | |
555 | } | |
556 | ||
557 | if (ret == 0) | |
f95637d2 | 558 | ret = pata_icside_add_ports(&info); |
73b6a2be RK |
559 | |
560 | if (ret == 0) | |
561 | goto out; | |
562 | ||
73b6a2be RK |
563 | release: |
564 | ecard_release_resources(ec); | |
565 | out: | |
566 | return ret; | |
567 | } | |
568 | ||
569 | static void pata_icside_shutdown(struct expansion_card *ec) | |
570 | { | |
571 | struct ata_host *host = ecard_get_drvdata(ec); | |
572 | unsigned long flags; | |
573 | ||
574 | /* | |
575 | * Disable interrupts from this card. We need to do | |
576 | * this before disabling EASI since we may be accessing | |
577 | * this register via that region. | |
578 | */ | |
579 | local_irq_save(flags); | |
c7b87f3d | 580 | ec->ops->irqdisable(ec, ec->irq); |
73b6a2be RK |
581 | local_irq_restore(flags); |
582 | ||
583 | /* | |
584 | * Reset the ROM pointer so that we can read the ROM | |
585 | * after a soft reboot. This also disables access to | |
586 | * the IDE taskfile via the EASI region. | |
587 | */ | |
588 | if (host) { | |
589 | struct pata_icside_state *state = host->private_data; | |
590 | if (state->ioc_base) | |
591 | writeb(0, state->ioc_base); | |
592 | } | |
593 | } | |
594 | ||
595 | static void __devexit pata_icside_remove(struct expansion_card *ec) | |
596 | { | |
597 | struct ata_host *host = ecard_get_drvdata(ec); | |
598 | struct pata_icside_state *state = host->private_data; | |
599 | ||
600 | ata_host_detach(host); | |
601 | ||
602 | pata_icside_shutdown(ec); | |
603 | ||
604 | /* | |
605 | * don't NULL out the drvdata - devres/libata wants it | |
606 | * to free the ata_host structure. | |
607 | */ | |
73b6a2be RK |
608 | if (state->dma != NO_DMA) |
609 | free_dma(state->dma); | |
73b6a2be | 610 | |
73b6a2be RK |
611 | ecard_release_resources(ec); |
612 | } | |
613 | ||
614 | static const struct ecard_id pata_icside_ids[] = { | |
615 | { MANU_ICS, PROD_ICS_IDE }, | |
616 | { MANU_ICS2, PROD_ICS2_IDE }, | |
617 | { 0xffff, 0xffff } | |
618 | }; | |
619 | ||
620 | static struct ecard_driver pata_icside_driver = { | |
621 | .probe = pata_icside_probe, | |
622 | .remove = __devexit_p(pata_icside_remove), | |
623 | .shutdown = pata_icside_shutdown, | |
624 | .id_table = pata_icside_ids, | |
625 | .drv = { | |
626 | .name = DRV_NAME, | |
627 | }, | |
628 | }; | |
629 | ||
630 | static int __init pata_icside_init(void) | |
631 | { | |
632 | return ecard_register_driver(&pata_icside_driver); | |
633 | } | |
634 | ||
635 | static void __exit pata_icside_exit(void) | |
636 | { | |
637 | ecard_remove_driver(&pata_icside_driver); | |
638 | } | |
639 | ||
640 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); | |
641 | MODULE_LICENSE("GPL"); | |
642 | MODULE_DESCRIPTION("ICS PATA driver"); | |
643 | ||
644 | module_init(pata_icside_init); | |
645 | module_exit(pata_icside_exit); |