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669a5db4 | 1 | /* |
c343a839 | 2 | * pata_it821x.c - IT821x PATA for new ATA layer |
669a5db4 | 3 | * (C) 2005 Red Hat Inc |
ab771630 | 4 | * Alan Cox <alan@lxorguk.ukuu.org.uk> |
374abf2c | 5 | * (C) 2007 Bartlomiej Zolnierkiewicz |
669a5db4 JG |
6 | * |
7 | * based upon | |
8 | * | |
9 | * it821x.c | |
85cd7251 | 10 | * |
669a5db4 JG |
11 | * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004 |
12 | * | |
ab771630 | 13 | * Copyright (C) 2004 Red Hat |
669a5db4 JG |
14 | * |
15 | * May be copied or modified under the terms of the GNU General Public License | |
16 | * Based in part on the ITE vendor provided SCSI driver. | |
17 | * | |
631dd1a8 JM |
18 | * Documentation available from IT8212F_V04.pdf |
19 | * http://www.ite.com.tw/EN/products_more.aspx?CategoryID=3&ID=5,91 | |
669a5db4 JG |
20 | * Some other documents are NDA. |
21 | * | |
22 | * The ITE8212 isn't exactly a standard IDE controller. It has two | |
23 | * modes. In pass through mode then it is an IDE controller. In its smart | |
24 | * mode its actually quite a capable hardware raid controller disguised | |
25 | * as an IDE controller. Smart mode only understands DMA read/write and | |
26 | * identify, none of the fancier commands apply. The IT8211 is identical | |
27 | * in other respects but lacks the raid mode. | |
28 | * | |
29 | * Errata: | |
30 | * o Rev 0x10 also requires master/slave hold the same DMA timings and | |
31 | * cannot do ATAPI MWDMA. | |
32 | * o The identify data for raid volumes lacks CHS info (technically ok) | |
33 | * but also fails to set the LBA28 and other bits. We fix these in | |
34 | * the IDE probe quirk code. | |
35 | * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode | |
36 | * raid then the controller firmware dies | |
37 | * o Smart mode without RAID doesn't clear all the necessary identify | |
38 | * bits to reduce the command set to the one used | |
39 | * | |
40 | * This has a few impacts on the driver | |
41 | * - In pass through mode we do all the work you would expect | |
42 | * - In smart mode the clocking set up is done by the controller generally | |
43 | * but we must watch the other limits and filter. | |
44 | * - There are a few extra vendor commands that actually talk to the | |
45 | * controller but only work PIO with no IRQ. | |
46 | * | |
47 | * Vendor areas of the identify block in smart mode are used for the | |
48 | * timing and policy set up. Each HDD in raid mode also has a serial | |
49 | * block on the disk. The hardware extra commands are get/set chip status, | |
50 | * rebuild, get rebuild status. | |
51 | * | |
52 | * In Linux the driver supports pass through mode as if the device was | |
53 | * just another IDE controller. If the smart mode is running then | |
54 | * volumes are managed by the controller firmware and each IDE "disk" | |
55 | * is a raid volume. Even more cute - the controller can do automated | |
56 | * hotplug and rebuild. | |
57 | * | |
58 | * The pass through controller itself is a little demented. It has a | |
59 | * flaw that it has a single set of PIO/MWDMA timings per channel so | |
60 | * non UDMA devices restrict each others performance. It also has a | |
61 | * single clock source per channel so mixed UDMA100/133 performance | |
62 | * isn't perfect and we have to pick a clock. Thankfully none of this | |
63 | * matters in smart mode. ATAPI DMA is not currently supported. | |
64 | * | |
65 | * It seems the smart mode is a win for RAID1/RAID10 but otherwise not. | |
66 | * | |
67 | * TODO | |
68 | * - ATAPI and other speed filtering | |
669a5db4 JG |
69 | * - RAID configuration ioctls |
70 | */ | |
71 | ||
72 | #include <linux/kernel.h> | |
73 | #include <linux/module.h> | |
74 | #include <linux/pci.h> | |
669a5db4 JG |
75 | #include <linux/blkdev.h> |
76 | #include <linux/delay.h> | |
5a0e3ad6 | 77 | #include <linux/slab.h> |
669a5db4 JG |
78 | #include <scsi/scsi_host.h> |
79 | #include <linux/libata.h> | |
80 | ||
81 | ||
82 | #define DRV_NAME "pata_it821x" | |
4a99d95f | 83 | #define DRV_VERSION "0.4.2" |
669a5db4 JG |
84 | |
85 | struct it821x_dev | |
86 | { | |
87 | unsigned int smart:1, /* Are we in smart raid mode */ | |
88 | timing10:1; /* Rev 0x10 */ | |
89 | u8 clock_mode; /* 0, ATA_50 or ATA_66 */ | |
90 | u8 want[2][2]; /* Mode/Pri log for master slave */ | |
91 | /* We need these for switching the clock when DMA goes on/off | |
92 | The high byte is the 66Mhz timing */ | |
93 | u16 pio[2]; /* Cached PIO values */ | |
94 | u16 mwdma[2]; /* Cached MWDMA values */ | |
95 | u16 udma[2]; /* Cached UDMA values (per drive) */ | |
96 | u16 last_device; /* Master or slave loaded ? */ | |
97 | }; | |
98 | ||
99 | #define ATA_66 0 | |
100 | #define ATA_50 1 | |
101 | #define ATA_ANY 2 | |
102 | ||
103 | #define UDMA_OFF 0 | |
104 | #define MWDMA_OFF 0 | |
105 | ||
106 | /* | |
107 | * We allow users to force the card into non raid mode without | |
3a4fa0a2 | 108 | * flashing the alternative BIOS. This is also necessary right now |
669a5db4 JG |
109 | * for embedded platforms that cannot run a PC BIOS but are using this |
110 | * device. | |
111 | */ | |
112 | ||
113 | static int it8212_noraid; | |
114 | ||
669a5db4 JG |
115 | /** |
116 | * it821x_program - program the PIO/MWDMA registers | |
117 | * @ap: ATA port | |
118 | * @adev: Device to program | |
119 | * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8) | |
120 | * | |
121 | * Program the PIO/MWDMA timing for this channel according to the | |
122 | * current clock. These share the same register so are managed by | |
123 | * the DMA start/stop sequence as with the old driver. | |
124 | */ | |
125 | ||
126 | static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing) | |
127 | { | |
128 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
129 | struct it821x_dev *itdev = ap->private_data; | |
130 | int channel = ap->port_no; | |
131 | u8 conf; | |
132 | ||
133 | /* Program PIO/MWDMA timing bits */ | |
134 | if (itdev->clock_mode == ATA_66) | |
135 | conf = timing >> 8; | |
136 | else | |
137 | conf = timing & 0xFF; | |
138 | pci_write_config_byte(pdev, 0x54 + 4 * channel, conf); | |
139 | } | |
140 | ||
141 | ||
142 | /** | |
143 | * it821x_program_udma - program the UDMA registers | |
144 | * @ap: ATA port | |
145 | * @adev: ATA device to update | |
146 | * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz | |
147 | * | |
148 | * Program the UDMA timing for this drive according to the | |
149 | * current clock. Handles the dual clocks and also knows about | |
150 | * the errata on the 0x10 revision. The UDMA errata is partly handled | |
151 | * here and partly in start_dma. | |
152 | */ | |
153 | ||
154 | static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing) | |
155 | { | |
156 | struct it821x_dev *itdev = ap->private_data; | |
157 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
158 | int channel = ap->port_no; | |
159 | int unit = adev->devno; | |
160 | u8 conf; | |
161 | ||
162 | /* Program UDMA timing bits */ | |
163 | if (itdev->clock_mode == ATA_66) | |
164 | conf = timing >> 8; | |
165 | else | |
166 | conf = timing & 0xFF; | |
167 | if (itdev->timing10 == 0) | |
168 | pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf); | |
169 | else { | |
170 | /* Early revision must be programmed for both together */ | |
171 | pci_write_config_byte(pdev, 0x56 + 4 * channel, conf); | |
172 | pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf); | |
173 | } | |
174 | } | |
175 | ||
176 | /** | |
177 | * it821x_clock_strategy | |
178 | * @ap: ATA interface | |
179 | * @adev: ATA device being updated | |
180 | * | |
181 | * Select between the 50 and 66Mhz base clocks to get the best | |
182 | * results for this interface. | |
183 | */ | |
184 | ||
185 | static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev) | |
186 | { | |
187 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
188 | struct it821x_dev *itdev = ap->private_data; | |
189 | u8 unit = adev->devno; | |
190 | struct ata_device *pair = ata_dev_pair(adev); | |
191 | ||
192 | int clock, altclock; | |
193 | u8 v; | |
194 | int sel = 0; | |
195 | ||
196 | /* Look for the most wanted clocking */ | |
197 | if (itdev->want[0][0] > itdev->want[1][0]) { | |
198 | clock = itdev->want[0][1]; | |
199 | altclock = itdev->want[1][1]; | |
200 | } else { | |
201 | clock = itdev->want[1][1]; | |
202 | altclock = itdev->want[0][1]; | |
203 | } | |
204 | ||
205 | /* Master doesn't care does the slave ? */ | |
206 | if (clock == ATA_ANY) | |
207 | clock = altclock; | |
208 | ||
209 | /* Nobody cares - keep the same clock */ | |
210 | if (clock == ATA_ANY) | |
211 | return; | |
212 | /* No change */ | |
213 | if (clock == itdev->clock_mode) | |
214 | return; | |
215 | ||
216 | /* Load this into the controller */ | |
217 | if (clock == ATA_66) | |
218 | itdev->clock_mode = ATA_66; | |
219 | else { | |
220 | itdev->clock_mode = ATA_50; | |
221 | sel = 1; | |
222 | } | |
223 | pci_read_config_byte(pdev, 0x50, &v); | |
224 | v &= ~(1 << (1 + ap->port_no)); | |
225 | v |= sel << (1 + ap->port_no); | |
226 | pci_write_config_byte(pdev, 0x50, v); | |
227 | ||
228 | /* | |
229 | * Reprogram the UDMA/PIO of the pair drive for the switch | |
230 | * MWDMA will be dealt with by the dma switcher | |
231 | */ | |
232 | if (pair && itdev->udma[1-unit] != UDMA_OFF) { | |
233 | it821x_program_udma(ap, pair, itdev->udma[1-unit]); | |
234 | it821x_program(ap, pair, itdev->pio[1-unit]); | |
235 | } | |
236 | /* | |
237 | * Reprogram the UDMA/PIO of our drive for the switch. | |
238 | * MWDMA will be dealt with by the dma switcher | |
239 | */ | |
240 | if (itdev->udma[unit] != UDMA_OFF) { | |
241 | it821x_program_udma(ap, adev, itdev->udma[unit]); | |
242 | it821x_program(ap, adev, itdev->pio[unit]); | |
243 | } | |
244 | } | |
245 | ||
246 | /** | |
247 | * it821x_passthru_set_piomode - set PIO mode data | |
248 | * @ap: ATA interface | |
249 | * @adev: ATA device | |
250 | * | |
251 | * Configure for PIO mode. This is complicated as the register is | |
252 | * shared by PIO and MWDMA and for both channels. | |
253 | */ | |
254 | ||
255 | static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
256 | { | |
257 | /* Spec says 89 ref driver uses 88 */ | |
258 | static const u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 }; | |
259 | static const u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY }; | |
260 | ||
261 | struct it821x_dev *itdev = ap->private_data; | |
262 | int unit = adev->devno; | |
263 | int mode_wanted = adev->pio_mode - XFER_PIO_0; | |
85cd7251 | 264 | |
669a5db4 JG |
265 | /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */ |
266 | itdev->want[unit][1] = pio_want[mode_wanted]; | |
267 | itdev->want[unit][0] = 1; /* PIO is lowest priority */ | |
268 | itdev->pio[unit] = pio[mode_wanted]; | |
269 | it821x_clock_strategy(ap, adev); | |
270 | it821x_program(ap, adev, itdev->pio[unit]); | |
271 | } | |
272 | ||
273 | /** | |
274 | * it821x_passthru_set_dmamode - set initial DMA mode data | |
275 | * @ap: ATA interface | |
276 | * @adev: ATA device | |
277 | * | |
278 | * Set up the DMA modes. The actions taken depend heavily on the mode | |
85cd7251 | 279 | * to use. If UDMA is used as is hopefully the usual case then the |
669a5db4 JG |
280 | * timing register is private and we need only consider the clock. If |
281 | * we are using MWDMA then we have to manage the setting ourself as | |
282 | * we switch devices and mode. | |
283 | */ | |
284 | ||
285 | static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
286 | { | |
287 | static const u16 dma[] = { 0x8866, 0x3222, 0x3121 }; | |
288 | static const u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY }; | |
289 | static const u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 }; | |
290 | static const u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 }; | |
291 | ||
292 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
293 | struct it821x_dev *itdev = ap->private_data; | |
294 | int channel = ap->port_no; | |
295 | int unit = adev->devno; | |
296 | u8 conf; | |
297 | ||
298 | if (adev->dma_mode >= XFER_UDMA_0) { | |
299 | int mode_wanted = adev->dma_mode - XFER_UDMA_0; | |
85cd7251 | 300 | |
669a5db4 JG |
301 | itdev->want[unit][1] = udma_want[mode_wanted]; |
302 | itdev->want[unit][0] = 3; /* UDMA is high priority */ | |
303 | itdev->mwdma[unit] = MWDMA_OFF; | |
304 | itdev->udma[unit] = udma[mode_wanted]; | |
305 | if (mode_wanted >= 5) | |
306 | itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */ | |
307 | ||
308 | /* UDMA on. Again revision 0x10 must do the pair */ | |
309 | pci_read_config_byte(pdev, 0x50, &conf); | |
310 | if (itdev->timing10) | |
311 | conf &= channel ? 0x9F: 0xE7; | |
312 | else | |
313 | conf &= ~ (1 << (3 + 2 * channel + unit)); | |
314 | pci_write_config_byte(pdev, 0x50, conf); | |
315 | it821x_clock_strategy(ap, adev); | |
316 | it821x_program_udma(ap, adev, itdev->udma[unit]); | |
317 | } else { | |
318 | int mode_wanted = adev->dma_mode - XFER_MW_DMA_0; | |
85cd7251 | 319 | |
669a5db4 JG |
320 | itdev->want[unit][1] = mwdma_want[mode_wanted]; |
321 | itdev->want[unit][0] = 2; /* MWDMA is low priority */ | |
322 | itdev->mwdma[unit] = dma[mode_wanted]; | |
323 | itdev->udma[unit] = UDMA_OFF; | |
324 | ||
325 | /* UDMA bits off - Revision 0x10 do them in pairs */ | |
326 | pci_read_config_byte(pdev, 0x50, &conf); | |
327 | if (itdev->timing10) | |
328 | conf |= channel ? 0x60: 0x18; | |
329 | else | |
330 | conf |= 1 << (3 + 2 * channel + unit); | |
331 | pci_write_config_byte(pdev, 0x50, conf); | |
332 | it821x_clock_strategy(ap, adev); | |
333 | } | |
334 | } | |
335 | ||
336 | /** | |
337 | * it821x_passthru_dma_start - DMA start callback | |
338 | * @qc: Command in progress | |
339 | * | |
340 | * Usually drivers set the DMA timing at the point the set_dmamode call | |
85cd7251 | 341 | * is made. IT821x however requires we load new timings on the |
669a5db4 JG |
342 | * transitions in some cases. |
343 | */ | |
344 | ||
345 | static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc) | |
346 | { | |
347 | struct ata_port *ap = qc->ap; | |
348 | struct ata_device *adev = qc->dev; | |
349 | struct it821x_dev *itdev = ap->private_data; | |
350 | int unit = adev->devno; | |
351 | ||
352 | if (itdev->mwdma[unit] != MWDMA_OFF) | |
353 | it821x_program(ap, adev, itdev->mwdma[unit]); | |
354 | else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10) | |
355 | it821x_program_udma(ap, adev, itdev->udma[unit]); | |
356 | ata_bmdma_start(qc); | |
357 | } | |
358 | ||
359 | /** | |
360 | * it821x_passthru_dma_stop - DMA stop callback | |
361 | * @qc: ATA command | |
362 | * | |
363 | * We loaded new timings in dma_start, as a result we need to restore | |
364 | * the PIO timings in dma_stop so that the next command issue gets the | |
365 | * right clock values. | |
366 | */ | |
367 | ||
368 | static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc) | |
369 | { | |
370 | struct ata_port *ap = qc->ap; | |
371 | struct ata_device *adev = qc->dev; | |
372 | struct it821x_dev *itdev = ap->private_data; | |
373 | int unit = adev->devno; | |
374 | ||
375 | ata_bmdma_stop(qc); | |
376 | if (itdev->mwdma[unit] != MWDMA_OFF) | |
377 | it821x_program(ap, adev, itdev->pio[unit]); | |
378 | } | |
379 | ||
380 | ||
381 | /** | |
382 | * it821x_passthru_dev_select - Select master/slave | |
383 | * @ap: ATA port | |
384 | * @device: Device number (not pointer) | |
385 | * | |
3a4fa0a2 | 386 | * Device selection hook. If necessary perform clock switching |
669a5db4 | 387 | */ |
85cd7251 | 388 | |
669a5db4 JG |
389 | static void it821x_passthru_dev_select(struct ata_port *ap, |
390 | unsigned int device) | |
391 | { | |
392 | struct it821x_dev *itdev = ap->private_data; | |
393 | if (itdev && device != itdev->last_device) { | |
9af5c9c9 | 394 | struct ata_device *adev = &ap->link.device[device]; |
669a5db4 JG |
395 | it821x_program(ap, adev, itdev->pio[adev->devno]); |
396 | itdev->last_device = device; | |
397 | } | |
9363c382 | 398 | ata_sff_dev_select(ap, device); |
669a5db4 JG |
399 | } |
400 | ||
401 | /** | |
9363c382 | 402 | * it821x_smart_qc_issue - wrap qc issue prot |
669a5db4 JG |
403 | * @qc: command |
404 | * | |
405 | * Wrap the command issue sequence for the IT821x. We need to | |
406 | * perform out own device selection timing loads before the | |
407 | * usual happenings kick off | |
408 | */ | |
85cd7251 | 409 | |
9363c382 | 410 | static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc) |
669a5db4 JG |
411 | { |
412 | switch(qc->tf.command) | |
413 | { | |
414 | /* Commands the firmware supports */ | |
415 | case ATA_CMD_READ: | |
416 | case ATA_CMD_READ_EXT: | |
417 | case ATA_CMD_WRITE: | |
418 | case ATA_CMD_WRITE_EXT: | |
419 | case ATA_CMD_PIO_READ: | |
420 | case ATA_CMD_PIO_READ_EXT: | |
421 | case ATA_CMD_PIO_WRITE: | |
422 | case ATA_CMD_PIO_WRITE_EXT: | |
423 | case ATA_CMD_READ_MULTI: | |
424 | case ATA_CMD_READ_MULTI_EXT: | |
425 | case ATA_CMD_WRITE_MULTI: | |
426 | case ATA_CMD_WRITE_MULTI_EXT: | |
427 | case ATA_CMD_ID_ATA: | |
963e4975 AC |
428 | case ATA_CMD_INIT_DEV_PARAMS: |
429 | case 0xFC: /* Internal 'report rebuild state' */ | |
669a5db4 JG |
430 | /* Arguably should just no-op this one */ |
431 | case ATA_CMD_SET_FEATURES: | |
360ff783 | 432 | return ata_bmdma_qc_issue(qc); |
669a5db4 JG |
433 | } |
434 | printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command); | |
c5038fc0 | 435 | return AC_ERR_DEV; |
669a5db4 JG |
436 | } |
437 | ||
438 | /** | |
9363c382 | 439 | * it821x_passthru_qc_issue - wrap qc issue prot |
669a5db4 JG |
440 | * @qc: command |
441 | * | |
442 | * Wrap the command issue sequence for the IT821x. We need to | |
443 | * perform out own device selection timing loads before the | |
444 | * usual happenings kick off | |
445 | */ | |
85cd7251 | 446 | |
9363c382 | 447 | static unsigned int it821x_passthru_qc_issue(struct ata_queued_cmd *qc) |
669a5db4 JG |
448 | { |
449 | it821x_passthru_dev_select(qc->ap, qc->dev->devno); | |
360ff783 | 450 | return ata_bmdma_qc_issue(qc); |
669a5db4 JG |
451 | } |
452 | ||
453 | /** | |
454 | * it821x_smart_set_mode - mode setting | |
0260731f | 455 | * @link: interface to set up |
b229a7b0 | 456 | * @unused: device that failed (error only) |
669a5db4 JG |
457 | * |
458 | * Use a non standard set_mode function. We don't want to be tuned. | |
459 | * The BIOS configured everything. Our job is not to fiddle. We | |
460 | * read the dma enabled bits from the PCI configuration of the device | |
85cd7251 | 461 | * and respect them. |
669a5db4 | 462 | */ |
85cd7251 | 463 | |
0260731f | 464 | static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unused) |
669a5db4 | 465 | { |
f58229f8 | 466 | struct ata_device *dev; |
669a5db4 | 467 | |
1eca4365 TH |
468 | ata_for_each_dev(dev, link, ENABLED) { |
469 | /* We don't really care */ | |
470 | dev->pio_mode = XFER_PIO_0; | |
471 | dev->dma_mode = XFER_MW_DMA_0; | |
472 | /* We do need the right mode information for DMA or PIO | |
473 | and this comes from the current configuration flags */ | |
474 | if (ata_id_has_dma(dev->id)) { | |
a9a79dfe | 475 | ata_dev_info(dev, "configured for DMA\n"); |
1eca4365 TH |
476 | dev->xfer_mode = XFER_MW_DMA_0; |
477 | dev->xfer_shift = ATA_SHIFT_MWDMA; | |
478 | dev->flags &= ~ATA_DFLAG_PIO; | |
479 | } else { | |
a9a79dfe | 480 | ata_dev_info(dev, "configured for PIO\n"); |
1eca4365 TH |
481 | dev->xfer_mode = XFER_PIO_0; |
482 | dev->xfer_shift = ATA_SHIFT_PIO; | |
483 | dev->flags |= ATA_DFLAG_PIO; | |
669a5db4 JG |
484 | } |
485 | } | |
b229a7b0 | 486 | return 0; |
669a5db4 JG |
487 | } |
488 | ||
489 | /** | |
490 | * it821x_dev_config - Called each device identify | |
669a5db4 JG |
491 | * @adev: Device that has just been identified |
492 | * | |
493 | * Perform the initial setup needed for each device that is chip | |
494 | * special. In our case we need to lock the sector count to avoid | |
495 | * blowing the brains out of the firmware with large LBA48 requests | |
496 | * | |
669a5db4 | 497 | */ |
85cd7251 | 498 | |
cd0d3bbc | 499 | static void it821x_dev_config(struct ata_device *adev) |
669a5db4 | 500 | { |
8bfa79fc | 501 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
669a5db4 | 502 | |
8bfa79fc | 503 | ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
669a5db4 JG |
504 | |
505 | if (adev->max_sectors > 255) | |
506 | adev->max_sectors = 255; | |
85cd7251 | 507 | |
669a5db4 JG |
508 | if (strstr(model_num, "Integrated Technology Express")) { |
509 | /* RAID mode */ | |
a9a79dfe JP |
510 | ata_dev_info(adev, "%sRAID%d volume", |
511 | adev->id[147] ? "Bootable " : "", | |
512 | adev->id[129]); | |
669a5db4 | 513 | if (adev->id[129] != 1) |
a9a79dfe JP |
514 | pr_cont("(%dK stripe)", adev->id[146]); |
515 | pr_cont("\n"); | |
669a5db4 | 516 | } |
c5038fc0 AC |
517 | /* This is a controller firmware triggered funny, don't |
518 | report the drive faulty! */ | |
519 | adev->horkage &= ~ATA_HORKAGE_DIAGNOSTIC; | |
963e4975 AC |
520 | /* No HPA in 'smart' mode */ |
521 | adev->horkage |= ATA_HORKAGE_BROKEN_HPA; | |
c5038fc0 AC |
522 | } |
523 | ||
524 | /** | |
963e4975 AC |
525 | * it821x_read_id - Hack identify data up |
526 | * @adev: device to read | |
527 | * @tf: proposed taskfile | |
528 | * @id: buffer for returned ident data | |
c5038fc0 | 529 | * |
963e4975 | 530 | * Query the devices on this firmware driven port and slightly |
c5038fc0 AC |
531 | * mash the identify data to stop us and common tools trying to |
532 | * use features not firmware supported. The firmware itself does | |
533 | * some masking (eg SMART) but not enough. | |
c5038fc0 AC |
534 | */ |
535 | ||
963e4975 AC |
536 | static unsigned int it821x_read_id(struct ata_device *adev, |
537 | struct ata_taskfile *tf, u16 *id) | |
c5038fc0 | 538 | { |
963e4975 AC |
539 | unsigned int err_mask; |
540 | unsigned char model_num[ATA_ID_PROD_LEN + 1]; | |
541 | ||
542 | err_mask = ata_do_dev_read_id(adev, tf, id); | |
543 | if (err_mask) | |
544 | return err_mask; | |
545 | ata_id_c_string(id, model_num, ATA_ID_PROD, sizeof(model_num)); | |
546 | ||
547 | id[83] &= ~(1 << 12); /* Cache flush is firmware handled */ | |
548 | id[83] &= ~(1 << 13); /* Ditto for LBA48 flushes */ | |
549 | id[84] &= ~(1 << 6); /* No FUA */ | |
550 | id[85] &= ~(1 << 10); /* No HPA */ | |
551 | id[76] = 0; /* No NCQ/AN etc */ | |
552 | ||
553 | if (strstr(model_num, "Integrated Technology Express")) { | |
554 | /* Set feature bits the firmware neglects */ | |
555 | id[49] |= 0x0300; /* LBA, DMA */ | |
963e4975 | 556 | id[83] &= 0x7FFF; |
054e5f61 | 557 | id[83] |= 0x4400; /* Word 83 is valid and LBA48 */ |
963e4975 AC |
558 | id[86] |= 0x0400; /* LBA48 on */ |
559 | id[ATA_ID_MAJOR_VER] |= 0x1F; | |
7ba07d16 OZ |
560 | /* Clear the serial number because it's different each boot |
561 | which breaks validation on resume */ | |
562 | memset(&id[ATA_ID_SERNO], 0x20, ATA_ID_SERNO_LEN); | |
c5038fc0 | 563 | } |
963e4975 | 564 | return err_mask; |
669a5db4 JG |
565 | } |
566 | ||
669a5db4 JG |
567 | /** |
568 | * it821x_check_atapi_dma - ATAPI DMA handler | |
569 | * @qc: Command we are about to issue | |
570 | * | |
571 | * Decide if this ATAPI command can be issued by DMA on this | |
572 | * controller. Return 0 if it can be. | |
573 | */ | |
85cd7251 | 574 | |
669a5db4 JG |
575 | static int it821x_check_atapi_dma(struct ata_queued_cmd *qc) |
576 | { | |
577 | struct ata_port *ap = qc->ap; | |
578 | struct it821x_dev *itdev = ap->private_data; | |
85cd7251 | 579 | |
bce7d5e0 | 580 | /* Only use dma for transfers to/from the media. */ |
b63b1331 | 581 | if (ata_qc_raw_nbytes(qc) < 2048) |
bce7d5e0 JN |
582 | return -EOPNOTSUPP; |
583 | ||
669a5db4 JG |
584 | /* No ATAPI DMA in smart mode */ |
585 | if (itdev->smart) | |
586 | return -EOPNOTSUPP; | |
587 | /* No ATAPI DMA on rev 10 */ | |
588 | if (itdev->timing10) | |
589 | return -EOPNOTSUPP; | |
590 | /* Cool */ | |
591 | return 0; | |
592 | } | |
85cd7251 | 593 | |
963e4975 AC |
594 | /** |
595 | * it821x_display_disk - display disk setup | |
596 | * @n: Device number | |
597 | * @buf: Buffer block from firmware | |
598 | * | |
599 | * Produce a nice informative display of the device setup as provided | |
600 | * by the firmware. | |
601 | */ | |
602 | ||
603 | static void it821x_display_disk(int n, u8 *buf) | |
604 | { | |
605 | unsigned char id[41]; | |
606 | int mode = 0; | |
3a53b3bc | 607 | const char *mtype = ""; |
963e4975 | 608 | char mbuf[8]; |
3a53b3bc | 609 | const char *cbl = "(40 wire cable)"; |
963e4975 AC |
610 | |
611 | static const char *types[5] = { | |
1c30c027 | 612 | "RAID0", "RAID1", "RAID 0+1", "JBOD", "DISK" |
963e4975 AC |
613 | }; |
614 | ||
615 | if (buf[52] > 4) /* No Disk */ | |
616 | return; | |
617 | ||
4fca377f | 618 | ata_id_c_string((u16 *)buf, id, 0, 41); |
963e4975 AC |
619 | |
620 | if (buf[51]) { | |
621 | mode = ffs(buf[51]); | |
622 | mtype = "UDMA"; | |
623 | } else if (buf[49]) { | |
624 | mode = ffs(buf[49]); | |
625 | mtype = "MWDMA"; | |
626 | } | |
627 | ||
628 | if (buf[76]) | |
629 | cbl = ""; | |
630 | ||
631 | if (mode) | |
632 | snprintf(mbuf, 8, "%5s%d", mtype, mode - 1); | |
633 | else | |
634 | strcpy(mbuf, "PIO"); | |
635 | if (buf[52] == 4) | |
636 | printk(KERN_INFO "%d: %-6s %-8s %s %s\n", | |
637 | n, mbuf, types[buf[52]], id, cbl); | |
638 | else | |
639 | printk(KERN_INFO "%d: %-6s %-8s Volume: %1d %s %s\n", | |
640 | n, mbuf, types[buf[52]], buf[53], id, cbl); | |
641 | if (buf[125] < 100) | |
642 | printk(KERN_INFO "%d: Rebuilding: %d%%\n", n, buf[125]); | |
643 | } | |
644 | ||
645 | /** | |
646 | * it821x_firmware_command - issue firmware command | |
647 | * @ap: IT821x port to interrogate | |
648 | * @cmd: command | |
649 | * @len: length | |
650 | * | |
651 | * Issue firmware commands expecting data back from the controller. We | |
652 | * use this to issue commands that do not go via the normal paths. Other | |
653 | * commands such as 0xFC can be issued normally. | |
654 | */ | |
655 | ||
656 | static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len) | |
657 | { | |
658 | u8 status; | |
659 | int n = 0; | |
660 | u16 *buf = kmalloc(len, GFP_KERNEL); | |
ef59a62a ME |
661 | |
662 | if (!buf) | |
963e4975 | 663 | return NULL; |
ef59a62a | 664 | |
963e4975 AC |
665 | /* This isn't quite a normal ATA command as we are talking to the |
666 | firmware not the drives */ | |
667 | ap->ctl |= ATA_NIEN; | |
668 | iowrite8(ap->ctl, ap->ioaddr.ctl_addr); | |
669 | ata_wait_idle(ap); | |
670 | iowrite8(ATA_DEVICE_OBS, ap->ioaddr.device_addr); | |
671 | iowrite8(cmd, ap->ioaddr.command_addr); | |
672 | udelay(1); | |
673 | /* This should be almost immediate but a little paranoia goes a long | |
674 | way. */ | |
675 | while(n++ < 10) { | |
676 | status = ioread8(ap->ioaddr.status_addr); | |
677 | if (status & ATA_ERR) { | |
678 | kfree(buf); | |
679 | printk(KERN_ERR "it821x_firmware_command: rejected\n"); | |
680 | return NULL; | |
681 | } | |
682 | if (status & ATA_DRQ) { | |
683 | ioread16_rep(ap->ioaddr.data_addr, buf, len/2); | |
684 | return (u8 *)buf; | |
685 | } | |
eada8598 | 686 | usleep_range(500, 1000); |
963e4975 AC |
687 | } |
688 | kfree(buf); | |
689 | printk(KERN_ERR "it821x_firmware_command: timeout\n"); | |
690 | return NULL; | |
691 | } | |
692 | ||
693 | /** | |
694 | * it821x_probe_firmware - firmware reporting/setup | |
695 | * @ap: IT821x port being probed | |
696 | * | |
697 | * Probe the firmware of the controller by issuing firmware command | |
698 | * 0xFA and analysing the returned data. | |
699 | */ | |
700 | ||
701 | static void it821x_probe_firmware(struct ata_port *ap) | |
702 | { | |
703 | u8 *buf; | |
704 | int i; | |
705 | ||
706 | /* This is a bit ugly as we can't just issue a task file to a device | |
707 | as this is controller magic */ | |
708 | ||
709 | buf = it821x_firmware_command(ap, 0xFA, 512); | |
710 | ||
711 | if (buf != NULL) { | |
712 | printk(KERN_INFO "pata_it821x: Firmware %02X/%02X/%02X%02X\n", | |
713 | buf[505], | |
714 | buf[506], | |
715 | buf[507], | |
716 | buf[508]); | |
717 | for (i = 0; i < 4; i++) | |
718 | it821x_display_disk(i, buf + 128 * i); | |
719 | kfree(buf); | |
720 | } | |
721 | } | |
722 | ||
723 | ||
669a5db4 JG |
724 | |
725 | /** | |
726 | * it821x_port_start - port setup | |
727 | * @ap: ATA port being set up | |
728 | * | |
729 | * The it821x needs to maintain private data structures and also to | |
730 | * use the standard PCI interface which lacks support for this | |
85cd7251 | 731 | * functionality. We instead set up the private data on the port |
669a5db4 JG |
732 | * start hook, and tear it down on port stop |
733 | */ | |
85cd7251 | 734 | |
669a5db4 JG |
735 | static int it821x_port_start(struct ata_port *ap) |
736 | { | |
737 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
738 | struct it821x_dev *itdev; | |
739 | u8 conf; | |
740 | ||
c7087652 | 741 | int ret = ata_bmdma_port_start(ap); |
669a5db4 JG |
742 | if (ret < 0) |
743 | return ret; | |
85cd7251 | 744 | |
24dc5f33 TH |
745 | itdev = devm_kzalloc(&pdev->dev, sizeof(struct it821x_dev), GFP_KERNEL); |
746 | if (itdev == NULL) | |
669a5db4 | 747 | return -ENOMEM; |
24dc5f33 | 748 | ap->private_data = itdev; |
669a5db4 JG |
749 | |
750 | pci_read_config_byte(pdev, 0x50, &conf); | |
751 | ||
752 | if (conf & 1) { | |
753 | itdev->smart = 1; | |
754 | /* Long I/O's although allowed in LBA48 space cause the | |
755 | onboard firmware to enter the twighlight zone */ | |
756 | /* No ATAPI DMA in this mode either */ | |
963e4975 AC |
757 | if (ap->port_no == 0) |
758 | it821x_probe_firmware(ap); | |
669a5db4 JG |
759 | } |
760 | /* Pull the current clocks from 0x50 */ | |
761 | if (conf & (1 << (1 + ap->port_no))) | |
762 | itdev->clock_mode = ATA_50; | |
763 | else | |
764 | itdev->clock_mode = ATA_66; | |
765 | ||
766 | itdev->want[0][1] = ATA_ANY; | |
767 | itdev->want[1][1] = ATA_ANY; | |
768 | itdev->last_device = -1; | |
769 | ||
604de6e0 | 770 | if (pdev->revision == 0x10) { |
669a5db4 JG |
771 | itdev->timing10 = 1; |
772 | /* Need to disable ATAPI DMA for this case */ | |
773 | if (!itdev->smart) | |
774 | printk(KERN_WARNING DRV_NAME": Revision 0x10, workarounds activated.\n"); | |
775 | } | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
963e4975 AC |
780 | /** |
781 | * it821x_rdc_cable - Cable detect for RDC1010 | |
782 | * @ap: port we are checking | |
783 | * | |
784 | * Return the RDC1010 cable type. Unlike the IT821x we know how to do | |
785 | * this and can do host side cable detect | |
786 | */ | |
787 | ||
788 | static int it821x_rdc_cable(struct ata_port *ap) | |
789 | { | |
790 | u16 r40; | |
791 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
792 | ||
793 | pci_read_config_word(pdev, 0x40, &r40); | |
794 | if (r40 & (1 << (2 + ap->port_no))) | |
795 | return ATA_CBL_PATA40; | |
796 | return ATA_CBL_PATA80; | |
797 | } | |
798 | ||
669a5db4 | 799 | static struct scsi_host_template it821x_sht = { |
68d1d07b | 800 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
801 | }; |
802 | ||
803 | static struct ata_port_operations it821x_smart_port_ops = { | |
029cfd6b | 804 | .inherits = &ata_bmdma_port_ops, |
85cd7251 | 805 | |
669a5db4 | 806 | .check_atapi_dma= it821x_check_atapi_dma, |
9363c382 | 807 | .qc_issue = it821x_smart_qc_issue, |
bda30288 | 808 | |
963e4975 | 809 | .cable_detect = ata_cable_80wire, |
029cfd6b TH |
810 | .set_mode = it821x_smart_set_mode, |
811 | .dev_config = it821x_dev_config, | |
963e4975 | 812 | .read_id = it821x_read_id, |
669a5db4 JG |
813 | |
814 | .port_start = it821x_port_start, | |
85cd7251 | 815 | }; |
669a5db4 JG |
816 | |
817 | static struct ata_port_operations it821x_passthru_port_ops = { | |
029cfd6b | 818 | .inherits = &ata_bmdma_port_ops, |
85cd7251 | 819 | |
669a5db4 | 820 | .check_atapi_dma= it821x_check_atapi_dma, |
5682ed33 | 821 | .sff_dev_select = it821x_passthru_dev_select, |
669a5db4 JG |
822 | .bmdma_start = it821x_passthru_bmdma_start, |
823 | .bmdma_stop = it821x_passthru_bmdma_stop, | |
9363c382 | 824 | .qc_issue = it821x_passthru_qc_issue, |
bda30288 | 825 | |
029cfd6b TH |
826 | .cable_detect = ata_cable_unknown, |
827 | .set_piomode = it821x_passthru_set_piomode, | |
828 | .set_dmamode = it821x_passthru_set_dmamode, | |
669a5db4 JG |
829 | |
830 | .port_start = it821x_port_start, | |
85cd7251 | 831 | }; |
669a5db4 | 832 | |
963e4975 AC |
833 | static struct ata_port_operations it821x_rdc_port_ops = { |
834 | .inherits = &ata_bmdma_port_ops, | |
835 | ||
836 | .check_atapi_dma= it821x_check_atapi_dma, | |
837 | .sff_dev_select = it821x_passthru_dev_select, | |
838 | .bmdma_start = it821x_passthru_bmdma_start, | |
839 | .bmdma_stop = it821x_passthru_bmdma_stop, | |
840 | .qc_issue = it821x_passthru_qc_issue, | |
841 | ||
842 | .cable_detect = it821x_rdc_cable, | |
843 | .set_piomode = it821x_passthru_set_piomode, | |
844 | .set_dmamode = it821x_passthru_set_dmamode, | |
845 | ||
846 | .port_start = it821x_port_start, | |
847 | }; | |
848 | ||
112cc2b5 | 849 | static void it821x_disable_raid(struct pci_dev *pdev) |
669a5db4 | 850 | { |
963e4975 AC |
851 | /* Neither the RDC nor the IT8211 */ |
852 | if (pdev->vendor != PCI_VENDOR_ID_ITE || | |
853 | pdev->device != PCI_DEVICE_ID_ITE_8212) | |
854 | return; | |
855 | ||
669a5db4 JG |
856 | /* Reset local CPU, and set BIOS not ready */ |
857 | pci_write_config_byte(pdev, 0x5E, 0x01); | |
858 | ||
859 | /* Set to bypass mode, and reset PCI bus */ | |
860 | pci_write_config_byte(pdev, 0x50, 0x00); | |
861 | pci_write_config_word(pdev, PCI_COMMAND, | |
862 | PCI_COMMAND_PARITY | PCI_COMMAND_IO | | |
863 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
864 | pci_write_config_word(pdev, 0x40, 0xA0F3); | |
865 | ||
866 | pci_write_config_dword(pdev,0x4C, 0x02040204); | |
867 | pci_write_config_byte(pdev, 0x42, 0x36); | |
868 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20); | |
869 | } | |
870 | ||
85cd7251 | 871 | |
669a5db4 JG |
872 | static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
873 | { | |
874 | u8 conf; | |
85cd7251 | 875 | |
1626aeb8 | 876 | static const struct ata_port_info info_smart = { |
1d2808fd | 877 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
878 | .pio_mask = ATA_PIO4, |
879 | .mwdma_mask = ATA_MWDMA2, | |
963e4975 | 880 | .udma_mask = ATA_UDMA6, |
669a5db4 JG |
881 | .port_ops = &it821x_smart_port_ops |
882 | }; | |
1626aeb8 | 883 | static const struct ata_port_info info_passthru = { |
1d2808fd | 884 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
885 | .pio_mask = ATA_PIO4, |
886 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 887 | .udma_mask = ATA_UDMA6, |
669a5db4 JG |
888 | .port_ops = &it821x_passthru_port_ops |
889 | }; | |
963e4975 | 890 | static const struct ata_port_info info_rdc = { |
4a99d95f | 891 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
892 | .pio_mask = ATA_PIO4, |
893 | .mwdma_mask = ATA_MWDMA2, | |
4a99d95f AC |
894 | .udma_mask = ATA_UDMA6, |
895 | .port_ops = &it821x_rdc_port_ops | |
896 | }; | |
897 | static const struct ata_port_info info_rdc_11 = { | |
963e4975 | 898 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
899 | .pio_mask = ATA_PIO4, |
900 | .mwdma_mask = ATA_MWDMA2, | |
963e4975 AC |
901 | /* No UDMA */ |
902 | .port_ops = &it821x_rdc_port_ops | |
903 | }; | |
85cd7251 | 904 | |
1626aeb8 | 905 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
3a53b3bc | 906 | static const char *mode[2] = { "pass through", "smart" }; |
f08048e9 TH |
907 | int rc; |
908 | ||
909 | rc = pcim_enable_device(pdev); | |
910 | if (rc) | |
911 | return rc; | |
4fca377f | 912 | |
963e4975 | 913 | if (pdev->vendor == PCI_VENDOR_ID_RDC) { |
4a99d95f AC |
914 | /* Deal with Vortex86SX */ |
915 | if (pdev->revision == 0x11) | |
916 | ppi[0] = &info_rdc_11; | |
917 | else | |
918 | ppi[0] = &info_rdc; | |
963e4975 AC |
919 | } else { |
920 | /* Force the card into bypass mode if so requested */ | |
921 | if (it8212_noraid) { | |
922 | printk(KERN_INFO DRV_NAME ": forcing bypass mode.\n"); | |
923 | it821x_disable_raid(pdev); | |
924 | } | |
925 | pci_read_config_byte(pdev, 0x50, &conf); | |
926 | conf &= 1; | |
669a5db4 | 927 | |
963e4975 AC |
928 | printk(KERN_INFO DRV_NAME": controller in %s mode.\n", |
929 | mode[conf]); | |
930 | if (conf == 0) | |
931 | ppi[0] = &info_passthru; | |
932 | else | |
933 | ppi[0] = &info_smart; | |
669a5db4 | 934 | } |
1c5afdf7 | 935 | return ata_pci_bmdma_init_one(pdev, ppi, &it821x_sht, NULL, 0); |
669a5db4 JG |
936 | } |
937 | ||
58eb8cd5 | 938 | #ifdef CONFIG_PM_SLEEP |
f535d53f AC |
939 | static int it821x_reinit_one(struct pci_dev *pdev) |
940 | { | |
0a86e1c8 | 941 | struct ata_host *host = pci_get_drvdata(pdev); |
f08048e9 TH |
942 | int rc; |
943 | ||
944 | rc = ata_pci_device_do_resume(pdev); | |
945 | if (rc) | |
946 | return rc; | |
f535d53f AC |
947 | /* Resume - turn raid back off if need be */ |
948 | if (it8212_noraid) | |
949 | it821x_disable_raid(pdev); | |
f08048e9 TH |
950 | ata_host_resume(host); |
951 | return rc; | |
f535d53f | 952 | } |
438ac6d5 | 953 | #endif |
f535d53f | 954 | |
2d2744fc JG |
955 | static const struct pci_device_id it821x[] = { |
956 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), }, | |
957 | { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), }, | |
4192be64 | 958 | { PCI_VDEVICE(RDC, PCI_DEVICE_ID_RDC_D1010), }, |
2d2744fc JG |
959 | |
960 | { }, | |
669a5db4 JG |
961 | }; |
962 | ||
963 | static struct pci_driver it821x_pci_driver = { | |
2d2744fc | 964 | .name = DRV_NAME, |
669a5db4 JG |
965 | .id_table = it821x, |
966 | .probe = it821x_init_one, | |
f535d53f | 967 | .remove = ata_pci_remove_one, |
58eb8cd5 | 968 | #ifdef CONFIG_PM_SLEEP |
f535d53f AC |
969 | .suspend = ata_pci_device_suspend, |
970 | .resume = it821x_reinit_one, | |
438ac6d5 | 971 | #endif |
669a5db4 JG |
972 | }; |
973 | ||
2fc75da0 | 974 | module_pci_driver(it821x_pci_driver); |
669a5db4 | 975 | |
669a5db4 JG |
976 | MODULE_AUTHOR("Alan Cox"); |
977 | MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller"); | |
978 | MODULE_LICENSE("GPL"); | |
979 | MODULE_DEVICE_TABLE(pci, it821x); | |
980 | MODULE_VERSION(DRV_VERSION); | |
981 | ||
669a5db4 | 982 | module_param_named(noraid, it8212_noraid, int, S_IRUGO); |
5fe675e2 | 983 | MODULE_PARM_DESC(noraid, "Force card into bypass mode"); |