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669a5db4 JG |
1 | /* |
2 | * pata-legacy.c - Legacy port PATA/SATA controller driver. | |
3 | * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2, or (at your option) | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; see the file COPYING. If not, write to | |
17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * An ATA driver for the legacy ATA ports. | |
20 | * | |
21 | * Data Sources: | |
22 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com | |
23 | * HT6560 series: | |
24 | * Promise 20230/20620: | |
25 | * http://www.ryston.cz/petr/vlb/pdc20230b.html | |
26 | * http://www.ryston.cz/petr/vlb/pdc20230c.html | |
27 | * http://www.ryston.cz/petr/vlb/pdc20630.html | |
28 | * | |
29 | * Unsupported but docs exist: | |
30 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 | |
31 | * Winbond W83759A | |
32 | * | |
33 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found | |
34 | * on PC class systems. There are three hybrid devices that are exceptions | |
35 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and | |
36 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". | |
37 | * | |
38 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ | |
39 | * opti82c465mv/promise 20230c/20630 | |
40 | * | |
41 | * Use the autospeed and pio_mask options with: | |
42 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. | |
43 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with | |
44 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, | |
45 | * Winbond W83759A, Promise PDC20230-B | |
46 | * | |
47 | * For now use autospeed and pio_mask as above with the W83759A. This may | |
48 | * change. | |
49 | * | |
50 | * TODO | |
51 | * Merge existing pata_qdi driver | |
52 | * | |
53 | */ | |
54 | ||
55 | #include <linux/kernel.h> | |
56 | #include <linux/module.h> | |
57 | #include <linux/pci.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/blkdev.h> | |
60 | #include <linux/delay.h> | |
61 | #include <scsi/scsi_host.h> | |
62 | #include <linux/ata.h> | |
63 | #include <linux/libata.h> | |
64 | #include <linux/platform_device.h> | |
65 | ||
66 | #define DRV_NAME "pata_legacy" | |
cb48cab7 | 67 | #define DRV_VERSION "0.5.4" |
669a5db4 JG |
68 | |
69 | #define NR_HOST 6 | |
70 | ||
71 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; | |
8b966ddd | 72 | static int legacy_irq[NR_HOST] = { 14, 15, 11, 10, 8, 12 }; |
669a5db4 JG |
73 | |
74 | struct legacy_data { | |
75 | unsigned long timing; | |
76 | u8 clock[2]; | |
77 | u8 last; | |
78 | int fast; | |
79 | struct platform_device *platform_dev; | |
80 | ||
81 | }; | |
82 | ||
83 | static struct legacy_data legacy_data[NR_HOST]; | |
84 | static struct ata_host *legacy_host[NR_HOST]; | |
85 | static int nr_legacy_host; | |
86 | ||
87 | ||
88 | static int probe_all; /* Set to check all ISA port ranges */ | |
89 | static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */ | |
90 | static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */ | |
91 | static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */ | |
f834e49f | 92 | static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */ |
669a5db4 JG |
93 | static int autospeed; /* Chip present which snoops speed changes */ |
94 | static int pio_mask = 0x1F; /* PIO range for autospeed devices */ | |
f834e49f | 95 | static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ |
669a5db4 JG |
96 | |
97 | /** | |
98 | * legacy_set_mode - mode setting | |
99 | * @ap: IDE interface | |
b229a7b0 | 100 | * @unused: Device that failed when error is returned |
669a5db4 JG |
101 | * |
102 | * Use a non standard set_mode function. We don't want to be tuned. | |
103 | * | |
104 | * The BIOS configured everything. Our job is not to fiddle. Just use | |
105 | * whatever PIO the hardware is using and leave it at that. When we | |
106 | * get some kind of nice user driven API for control then we can | |
107 | * expand on this as per hdparm in the base kernel. | |
108 | */ | |
109 | ||
b229a7b0 | 110 | static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused) |
669a5db4 JG |
111 | { |
112 | int i; | |
113 | ||
114 | for (i = 0; i < ATA_MAX_DEVICES; i++) { | |
115 | struct ata_device *dev = &ap->device[i]; | |
116 | if (ata_dev_enabled(dev)) { | |
f834e49f | 117 | ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); |
669a5db4 JG |
118 | dev->pio_mode = XFER_PIO_0; |
119 | dev->xfer_mode = XFER_PIO_0; | |
120 | dev->xfer_shift = ATA_SHIFT_PIO; | |
121 | dev->flags |= ATA_DFLAG_PIO; | |
122 | } | |
123 | } | |
b229a7b0 | 124 | return 0; |
669a5db4 JG |
125 | } |
126 | ||
127 | static struct scsi_host_template legacy_sht = { | |
128 | .module = THIS_MODULE, | |
129 | .name = DRV_NAME, | |
130 | .ioctl = ata_scsi_ioctl, | |
131 | .queuecommand = ata_scsi_queuecmd, | |
132 | .can_queue = ATA_DEF_QUEUE, | |
133 | .this_id = ATA_SHT_THIS_ID, | |
134 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
135 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
136 | .emulated = ATA_SHT_EMULATED, | |
137 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
138 | .proc_name = DRV_NAME, | |
139 | .dma_boundary = ATA_DMA_BOUNDARY, | |
140 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 141 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
142 | .bios_param = ata_std_bios_param, |
143 | }; | |
144 | ||
145 | /* | |
146 | * These ops are used if the user indicates the hardware | |
147 | * snoops the commands to decide on the mode and handles the | |
148 | * mode selection "magically" itself. Several legacy controllers | |
149 | * do this. The mode range can be set if it is not 0x1F by setting | |
150 | * pio_mask as well. | |
151 | */ | |
152 | ||
153 | static struct ata_port_operations simple_port_ops = { | |
154 | .port_disable = ata_port_disable, | |
155 | .tf_load = ata_tf_load, | |
156 | .tf_read = ata_tf_read, | |
157 | .check_status = ata_check_status, | |
158 | .exec_command = ata_exec_command, | |
159 | .dev_select = ata_std_dev_select, | |
160 | ||
161 | .freeze = ata_bmdma_freeze, | |
162 | .thaw = ata_bmdma_thaw, | |
163 | .error_handler = ata_bmdma_error_handler, | |
164 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
a73984a0 | 165 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
166 | |
167 | .qc_prep = ata_qc_prep, | |
168 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 169 | |
0d5ff566 | 170 | .data_xfer = ata_data_xfer_noirq, |
669a5db4 JG |
171 | |
172 | .irq_handler = ata_interrupt, | |
173 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
174 | .irq_on = ata_irq_on, |
175 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
176 | |
177 | .port_start = ata_port_start, | |
669a5db4 JG |
178 | }; |
179 | ||
180 | static struct ata_port_operations legacy_port_ops = { | |
181 | .set_mode = legacy_set_mode, | |
182 | ||
183 | .port_disable = ata_port_disable, | |
184 | .tf_load = ata_tf_load, | |
185 | .tf_read = ata_tf_read, | |
186 | .check_status = ata_check_status, | |
187 | .exec_command = ata_exec_command, | |
188 | .dev_select = ata_std_dev_select, | |
a73984a0 | 189 | .cable_detect = ata_cable_40wire, |
669a5db4 | 190 | |
bf7551c4 JG |
191 | .freeze = ata_bmdma_freeze, |
192 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 193 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 194 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
669a5db4 JG |
195 | |
196 | .qc_prep = ata_qc_prep, | |
197 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 198 | |
0d5ff566 | 199 | .data_xfer = ata_data_xfer_noirq, |
669a5db4 JG |
200 | |
201 | .irq_handler = ata_interrupt, | |
202 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
203 | .irq_on = ata_irq_on, |
204 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
205 | |
206 | .port_start = ata_port_start, | |
669a5db4 JG |
207 | }; |
208 | ||
209 | /* | |
210 | * Promise 20230C and 20620 support | |
211 | * | |
212 | * This controller supports PIO0 to PIO2. We set PIO timings conservatively to | |
213 | * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to | |
214 | * controller and PIO'd to the host and not supported. | |
215 | */ | |
216 | ||
217 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
218 | { | |
219 | int tries = 5; | |
220 | int pio = adev->pio_mode - XFER_PIO_0; | |
221 | u8 rt; | |
222 | unsigned long flags; | |
85cd7251 | 223 | |
669a5db4 | 224 | /* Safe as UP only. Force I/Os to occur together */ |
85cd7251 | 225 | |
669a5db4 | 226 | local_irq_save(flags); |
85cd7251 | 227 | |
669a5db4 JG |
228 | /* Unlock the control interface */ |
229 | do | |
230 | { | |
231 | inb(0x1F5); | |
232 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
233 | inb(0x1F2); | |
234 | inb(0x3F6); | |
235 | inb(0x3F6); | |
236 | inb(0x1F2); | |
237 | inb(0x1F2); | |
238 | } | |
239 | while((inb(0x1F2) & 0x80) && --tries); | |
240 | ||
241 | local_irq_restore(flags); | |
85cd7251 | 242 | |
669a5db4 JG |
243 | outb(inb(0x1F4) & 0x07, 0x1F4); |
244 | ||
245 | rt = inb(0x1F3); | |
246 | rt &= 0x07 << (3 * adev->devno); | |
247 | if (pio) | |
248 | rt |= (1 + 3 * pio) << (3 * adev->devno); | |
249 | ||
250 | udelay(100); | |
251 | outb(inb(0x1F2) | 0x01, 0x1F2); | |
252 | udelay(100); | |
253 | inb(0x1F5); | |
254 | ||
255 | } | |
256 | ||
257 | static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data) | |
258 | { | |
259 | struct ata_port *ap = adev->ap; | |
260 | int slop = buflen & 3; | |
261 | unsigned long flags; | |
262 | ||
263 | if (ata_id_has_dword_io(adev->id)) { | |
264 | local_irq_save(flags); | |
265 | ||
266 | /* Perform the 32bit I/O synchronization sequence */ | |
0d5ff566 TH |
267 | ioread8(ap->ioaddr.nsect_addr); |
268 | ioread8(ap->ioaddr.nsect_addr); | |
269 | ioread8(ap->ioaddr.nsect_addr); | |
669a5db4 JG |
270 | |
271 | /* Now the data */ | |
272 | ||
273 | if (write_data) | |
0d5ff566 | 274 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
669a5db4 | 275 | else |
0d5ff566 | 276 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
669a5db4 JG |
277 | |
278 | if (unlikely(slop)) { | |
279 | u32 pad; | |
280 | if (write_data) { | |
281 | memcpy(&pad, buf + buflen - slop, slop); | |
0d5ff566 TH |
282 | pad = le32_to_cpu(pad); |
283 | iowrite32(pad, ap->ioaddr.data_addr); | |
669a5db4 | 284 | } else { |
0d5ff566 TH |
285 | pad = ioread32(ap->ioaddr.data_addr); |
286 | pad = cpu_to_le16(pad); | |
669a5db4 JG |
287 | memcpy(buf + buflen - slop, &pad, slop); |
288 | } | |
289 | } | |
290 | local_irq_restore(flags); | |
291 | } | |
292 | else | |
0d5ff566 | 293 | ata_data_xfer_noirq(adev, buf, buflen, write_data); |
669a5db4 JG |
294 | } |
295 | ||
296 | static struct ata_port_operations pdc20230_port_ops = { | |
297 | .set_piomode = pdc20230_set_piomode, | |
298 | ||
299 | .port_disable = ata_port_disable, | |
300 | .tf_load = ata_tf_load, | |
301 | .tf_read = ata_tf_read, | |
302 | .check_status = ata_check_status, | |
303 | .exec_command = ata_exec_command, | |
304 | .dev_select = ata_std_dev_select, | |
305 | ||
bf7551c4 JG |
306 | .freeze = ata_bmdma_freeze, |
307 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 308 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 309 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 310 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
311 | |
312 | .qc_prep = ata_qc_prep, | |
313 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 314 | |
669a5db4 JG |
315 | .data_xfer = pdc_data_xfer_vlb, |
316 | ||
317 | .irq_handler = ata_interrupt, | |
318 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
319 | .irq_on = ata_irq_on, |
320 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
321 | |
322 | .port_start = ata_port_start, | |
669a5db4 JG |
323 | }; |
324 | ||
325 | /* | |
326 | * Holtek 6560A support | |
327 | * | |
328 | * This controller supports PIO0 to PIO2 (no IORDY even though higher timings | |
329 | * can be loaded). | |
330 | */ | |
331 | ||
332 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
333 | { | |
334 | u8 active, recover; | |
335 | struct ata_timing t; | |
336 | ||
337 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
338 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
339 | ||
340 | active = FIT(t.active, 2, 15); | |
341 | recover = FIT(t.recover, 4, 15); | |
342 | ||
343 | inb(0x3E6); | |
344 | inb(0x3E6); | |
345 | inb(0x3E6); | |
346 | inb(0x3E6); | |
347 | ||
0d5ff566 TH |
348 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
349 | ioread8(ap->ioaddr.status_addr); | |
669a5db4 JG |
350 | } |
351 | ||
352 | static struct ata_port_operations ht6560a_port_ops = { | |
353 | .set_piomode = ht6560a_set_piomode, | |
354 | ||
355 | .port_disable = ata_port_disable, | |
356 | .tf_load = ata_tf_load, | |
357 | .tf_read = ata_tf_read, | |
358 | .check_status = ata_check_status, | |
359 | .exec_command = ata_exec_command, | |
360 | .dev_select = ata_std_dev_select, | |
361 | ||
bf7551c4 JG |
362 | .freeze = ata_bmdma_freeze, |
363 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 364 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 365 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 366 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
367 | |
368 | .qc_prep = ata_qc_prep, | |
369 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 370 | |
0d5ff566 | 371 | .data_xfer = ata_data_xfer, /* Check vlb/noirq */ |
669a5db4 JG |
372 | |
373 | .irq_handler = ata_interrupt, | |
374 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
375 | .irq_on = ata_irq_on, |
376 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
377 | |
378 | .port_start = ata_port_start, | |
669a5db4 JG |
379 | }; |
380 | ||
381 | /* | |
382 | * Holtek 6560B support | |
383 | * | |
384 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting | |
385 | * unless we see an ATAPI device in which case we force it off. | |
386 | * | |
387 | * FIXME: need to implement 2nd channel support. | |
388 | */ | |
389 | ||
390 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
391 | { | |
392 | u8 active, recover; | |
393 | struct ata_timing t; | |
394 | ||
395 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
396 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
397 | ||
398 | active = FIT(t.active, 2, 15); | |
399 | recover = FIT(t.recover, 2, 16); | |
400 | recover &= 0x15; | |
401 | ||
402 | inb(0x3E6); | |
403 | inb(0x3E6); | |
404 | inb(0x3E6); | |
405 | inb(0x3E6); | |
406 | ||
0d5ff566 | 407 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
669a5db4 JG |
408 | |
409 | if (adev->class != ATA_DEV_ATA) { | |
410 | u8 rconf = inb(0x3E6); | |
411 | if (rconf & 0x24) { | |
412 | rconf &= ~ 0x24; | |
413 | outb(rconf, 0x3E6); | |
414 | } | |
415 | } | |
0d5ff566 | 416 | ioread8(ap->ioaddr.status_addr); |
669a5db4 JG |
417 | } |
418 | ||
419 | static struct ata_port_operations ht6560b_port_ops = { | |
420 | .set_piomode = ht6560b_set_piomode, | |
421 | ||
422 | .port_disable = ata_port_disable, | |
423 | .tf_load = ata_tf_load, | |
424 | .tf_read = ata_tf_read, | |
425 | .check_status = ata_check_status, | |
426 | .exec_command = ata_exec_command, | |
427 | .dev_select = ata_std_dev_select, | |
428 | ||
bf7551c4 JG |
429 | .freeze = ata_bmdma_freeze, |
430 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 431 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 432 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 433 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
434 | |
435 | .qc_prep = ata_qc_prep, | |
436 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 437 | |
0d5ff566 | 438 | .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */ |
669a5db4 JG |
439 | |
440 | .irq_handler = ata_interrupt, | |
441 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
442 | .irq_on = ata_irq_on, |
443 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
444 | |
445 | .port_start = ata_port_start, | |
669a5db4 JG |
446 | }; |
447 | ||
448 | /* | |
449 | * Opti core chipset helpers | |
450 | */ | |
85cd7251 | 451 | |
669a5db4 JG |
452 | /** |
453 | * opti_syscfg - read OPTI chipset configuration | |
454 | * @reg: Configuration register to read | |
455 | * | |
456 | * Returns the value of an OPTI system board configuration register. | |
457 | */ | |
458 | ||
459 | static u8 opti_syscfg(u8 reg) | |
460 | { | |
461 | unsigned long flags; | |
462 | u8 r; | |
85cd7251 | 463 | |
669a5db4 JG |
464 | /* Uniprocessor chipset and must force cycles adjancent */ |
465 | local_irq_save(flags); | |
466 | outb(reg, 0x22); | |
467 | r = inb(0x24); | |
468 | local_irq_restore(flags); | |
469 | return r; | |
470 | } | |
471 | ||
472 | /* | |
473 | * Opti 82C611A | |
474 | * | |
475 | * This controller supports PIO0 to PIO3. | |
476 | */ | |
477 | ||
478 | static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
479 | { | |
480 | u8 active, recover, setup; | |
481 | struct ata_timing t; | |
482 | struct ata_device *pair = ata_dev_pair(adev); | |
483 | int clock; | |
484 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
485 | u8 rc; | |
486 | ||
487 | /* Enter configuration mode */ | |
0d5ff566 TH |
488 | ioread16(ap->ioaddr.error_addr); |
489 | ioread16(ap->ioaddr.error_addr); | |
490 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
491 | |
492 | /* Read VLB clock strapping */ | |
0d5ff566 | 493 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
669a5db4 JG |
494 | |
495 | /* Get the timing data in cycles */ | |
496 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
497 | ||
498 | /* Setup timing is shared */ | |
499 | if (pair) { | |
500 | struct ata_timing tp; | |
501 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
502 | ||
503 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
504 | } | |
505 | ||
506 | active = FIT(t.active, 2, 17) - 2; | |
507 | recover = FIT(t.recover, 1, 16) - 1; | |
508 | setup = FIT(t.setup, 1, 4) - 1; | |
509 | ||
510 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 511 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
512 | rc &= 0x7F; |
513 | rc |= (adev->devno << 7); | |
0d5ff566 | 514 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
515 | |
516 | /* Write the timings */ | |
0d5ff566 | 517 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
518 | |
519 | /* Select the right bank for read timings, also | |
520 | load the shared timings for address */ | |
0d5ff566 | 521 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
522 | rc &= 0xC0; |
523 | rc |= adev->devno; /* Index select */ | |
524 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 525 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
526 | |
527 | /* Load the read timings */ | |
0d5ff566 | 528 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
529 | |
530 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 531 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
532 | rc &= 0x73; |
533 | rc |= 0x84; | |
0d5ff566 | 534 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
535 | |
536 | /* Exit command mode */ | |
0d5ff566 | 537 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
538 | } |
539 | ||
540 | ||
541 | static struct ata_port_operations opti82c611a_port_ops = { | |
542 | .set_piomode = opti82c611a_set_piomode, | |
543 | ||
544 | .port_disable = ata_port_disable, | |
545 | .tf_load = ata_tf_load, | |
546 | .tf_read = ata_tf_read, | |
547 | .check_status = ata_check_status, | |
548 | .exec_command = ata_exec_command, | |
549 | .dev_select = ata_std_dev_select, | |
550 | ||
bf7551c4 JG |
551 | .freeze = ata_bmdma_freeze, |
552 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 553 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 554 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 555 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
556 | |
557 | .qc_prep = ata_qc_prep, | |
558 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 559 | |
0d5ff566 | 560 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
561 | |
562 | .irq_handler = ata_interrupt, | |
563 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
564 | .irq_on = ata_irq_on, |
565 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
566 | |
567 | .port_start = ata_port_start, | |
669a5db4 JG |
568 | }; |
569 | ||
570 | /* | |
571 | * Opti 82C465MV | |
572 | * | |
573 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB | |
574 | * version is dual channel but doesn't have a lot of unique registers. | |
575 | */ | |
576 | ||
577 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
578 | { | |
579 | u8 active, recover, setup; | |
580 | struct ata_timing t; | |
581 | struct ata_device *pair = ata_dev_pair(adev); | |
582 | int clock; | |
583 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
584 | u8 rc; | |
585 | u8 sysclk; | |
586 | ||
587 | /* Get the clock */ | |
588 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ | |
589 | ||
590 | /* Enter configuration mode */ | |
0d5ff566 TH |
591 | ioread16(ap->ioaddr.error_addr); |
592 | ioread16(ap->ioaddr.error_addr); | |
593 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
594 | |
595 | /* Read VLB clock strapping */ | |
596 | clock = 1000000000 / khz[sysclk]; | |
597 | ||
598 | /* Get the timing data in cycles */ | |
599 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
600 | ||
601 | /* Setup timing is shared */ | |
602 | if (pair) { | |
603 | struct ata_timing tp; | |
604 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
605 | ||
606 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
607 | } | |
608 | ||
609 | active = FIT(t.active, 2, 17) - 2; | |
610 | recover = FIT(t.recover, 1, 16) - 1; | |
611 | setup = FIT(t.setup, 1, 4) - 1; | |
612 | ||
613 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 614 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
615 | rc &= 0x7F; |
616 | rc |= (adev->devno << 7); | |
0d5ff566 | 617 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
618 | |
619 | /* Write the timings */ | |
0d5ff566 | 620 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
621 | |
622 | /* Select the right bank for read timings, also | |
623 | load the shared timings for address */ | |
0d5ff566 | 624 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
625 | rc &= 0xC0; |
626 | rc |= adev->devno; /* Index select */ | |
627 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 628 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
629 | |
630 | /* Load the read timings */ | |
0d5ff566 | 631 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
632 | |
633 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 634 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
635 | rc &= 0x73; |
636 | rc |= 0x84; | |
0d5ff566 | 637 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
638 | |
639 | /* Exit command mode */ | |
0d5ff566 | 640 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
641 | |
642 | /* We need to know this for quad device on the MVB */ | |
643 | ap->host->private_data = ap; | |
644 | } | |
645 | ||
646 | /** | |
647 | * opt82c465mv_qc_issue_prot - command issue | |
648 | * @qc: command pending | |
649 | * | |
650 | * Called when the libata layer is about to issue a command. We wrap | |
651 | * this interface so that we can load the correct ATA timings. The | |
652 | * MVB has a single set of timing registers and these are shared | |
653 | * across channels. As there are two registers we really ought to | |
654 | * track the last two used values as a sort of register window. For | |
655 | * now we just reload on a channel switch. On the single channel | |
656 | * setup this condition never fires so we do nothing extra. | |
657 | * | |
658 | * FIXME: dual channel needs ->serialize support | |
659 | */ | |
660 | ||
661 | static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc) | |
662 | { | |
663 | struct ata_port *ap = qc->ap; | |
664 | struct ata_device *adev = qc->dev; | |
665 | ||
666 | /* If timings are set and for the wrong channel (2nd test is | |
667 | due to a libata shortcoming and will eventually go I hope) */ | |
668 | if (ap->host->private_data != ap->host | |
669 | && ap->host->private_data != NULL) | |
670 | opti82c46x_set_piomode(ap, adev); | |
671 | ||
672 | return ata_qc_issue_prot(qc); | |
673 | } | |
674 | ||
675 | static struct ata_port_operations opti82c46x_port_ops = { | |
676 | .set_piomode = opti82c46x_set_piomode, | |
677 | ||
678 | .port_disable = ata_port_disable, | |
679 | .tf_load = ata_tf_load, | |
680 | .tf_read = ata_tf_read, | |
681 | .check_status = ata_check_status, | |
682 | .exec_command = ata_exec_command, | |
683 | .dev_select = ata_std_dev_select, | |
684 | ||
bf7551c4 JG |
685 | .freeze = ata_bmdma_freeze, |
686 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 687 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 688 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 689 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
690 | |
691 | .qc_prep = ata_qc_prep, | |
692 | .qc_issue = opti82c46x_qc_issue_prot, | |
bda30288 | 693 | |
0d5ff566 | 694 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
695 | |
696 | .irq_handler = ata_interrupt, | |
697 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
698 | .irq_on = ata_irq_on, |
699 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
700 | |
701 | .port_start = ata_port_start, | |
669a5db4 JG |
702 | }; |
703 | ||
704 | ||
705 | /** | |
706 | * legacy_init_one - attach a legacy interface | |
707 | * @port: port number | |
708 | * @io: I/O port start | |
709 | * @ctrl: control port | |
710 | * @irq: interrupt line | |
711 | * | |
712 | * Register an ISA bus IDE interface. Such interfaces are PIO and we | |
713 | * assume do not support IRQ sharing. | |
714 | */ | |
715 | ||
716 | static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq) | |
717 | { | |
718 | struct legacy_data *ld = &legacy_data[nr_legacy_host]; | |
719 | struct ata_probe_ent ae; | |
720 | struct platform_device *pdev; | |
669a5db4 | 721 | struct ata_port_operations *ops = &legacy_port_ops; |
0d5ff566 | 722 | void __iomem *io_addr, *ctrl_addr; |
669a5db4 JG |
723 | int pio_modes = pio_mask; |
724 | u32 mask = (1 << port); | |
f834e49f | 725 | u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; |
24dc5f33 | 726 | int ret; |
669a5db4 JG |
727 | |
728 | pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0); | |
24dc5f33 TH |
729 | if (IS_ERR(pdev)) |
730 | return PTR_ERR(pdev); | |
731 | ||
732 | ret = -EBUSY; | |
733 | if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || | |
734 | devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL) | |
735 | goto fail; | |
669a5db4 | 736 | |
0d5ff566 TH |
737 | ret = -ENOMEM; |
738 | io_addr = devm_ioport_map(&pdev->dev, io, 8); | |
739 | ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1); | |
740 | if (!io_addr || !ctrl_addr) | |
741 | goto fail; | |
742 | ||
669a5db4 JG |
743 | if (ht6560a & mask) { |
744 | ops = &ht6560a_port_ops; | |
745 | pio_modes = 0x07; | |
f834e49f | 746 | iordy = ATA_FLAG_NO_IORDY; |
669a5db4 JG |
747 | } |
748 | if (ht6560b & mask) { | |
749 | ops = &ht6560b_port_ops; | |
750 | pio_modes = 0x1F; | |
751 | } | |
752 | if (opti82c611a & mask) { | |
753 | ops = &opti82c611a_port_ops; | |
754 | pio_modes = 0x0F; | |
755 | } | |
756 | if (opti82c46x & mask) { | |
757 | ops = &opti82c46x_port_ops; | |
758 | pio_modes = 0x0F; | |
759 | } | |
760 | ||
761 | /* Probe for automatically detectable controllers */ | |
85cd7251 | 762 | |
669a5db4 JG |
763 | if (io == 0x1F0 && ops == &legacy_port_ops) { |
764 | unsigned long flags; | |
765 | ||
766 | local_irq_save(flags); | |
767 | ||
768 | /* Probes */ | |
769 | inb(0x1F5); | |
770 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
771 | inb(0x1F2); | |
772 | inb(0x3F6); | |
773 | inb(0x3F6); | |
774 | inb(0x1F2); | |
775 | inb(0x1F2); | |
776 | ||
777 | if ((inb(0x1F2) & 0x80) == 0) { | |
778 | /* PDC20230c or 20630 ? */ | |
779 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n"); | |
780 | pio_modes = 0x07; | |
781 | ops = &pdc20230_port_ops; | |
f834e49f | 782 | iordy = ATA_FLAG_NO_IORDY; |
669a5db4 JG |
783 | udelay(100); |
784 | inb(0x1F5); | |
785 | } else { | |
786 | outb(0x55, 0x1F2); | |
787 | inb(0x1F2); | |
788 | inb(0x1F2); | |
789 | if (inb(0x1F2) == 0x00) { | |
790 | printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n"); | |
791 | } | |
792 | } | |
793 | local_irq_restore(flags); | |
794 | } | |
795 | ||
796 | ||
797 | /* Chip does mode setting by command snooping */ | |
798 | if (ops == &legacy_port_ops && (autospeed & mask)) | |
799 | ops = &simple_port_ops; | |
f834e49f | 800 | |
669a5db4 JG |
801 | memset(&ae, 0, sizeof(struct ata_probe_ent)); |
802 | INIT_LIST_HEAD(&ae.node); | |
803 | ae.dev = &pdev->dev; | |
804 | ae.port_ops = ops; | |
805 | ae.sht = &legacy_sht; | |
806 | ae.n_ports = 1; | |
807 | ae.pio_mask = pio_modes; | |
808 | ae.irq = irq; | |
809 | ae.irq_flags = 0; | |
f834e49f | 810 | ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST|iordy; |
0d5ff566 TH |
811 | ae.port[0].cmd_addr = io_addr; |
812 | ae.port[0].altstatus_addr = ctrl_addr; | |
813 | ae.port[0].ctl_addr = ctrl_addr; | |
669a5db4 JG |
814 | ata_std_ports(&ae.port[0]); |
815 | ae.private_data = ld; | |
816 | ||
24dc5f33 TH |
817 | ret = -ENODEV; |
818 | if (!ata_device_add(&ae)) | |
669a5db4 | 819 | goto fail; |
24dc5f33 | 820 | |
669a5db4 JG |
821 | legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev); |
822 | ld->platform_dev = pdev; | |
823 | return 0; | |
824 | ||
825 | fail: | |
826 | platform_device_unregister(pdev); | |
669a5db4 JG |
827 | return ret; |
828 | } | |
829 | ||
830 | /** | |
831 | * legacy_check_special_cases - ATA special cases | |
832 | * @p: PCI device to check | |
833 | * @master: set this if we find an ATA master | |
834 | * @master: set this if we find an ATA secondary | |
835 | * | |
836 | * A small number of vendors implemented early PCI ATA interfaces on bridge logic | |
837 | * without the ATA interface being PCI visible. Where we have a matching PCI driver | |
838 | * we must skip the relevant device here. If we don't know about it then the legacy | |
839 | * driver is the right driver anyway. | |
840 | */ | |
841 | ||
842 | static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary) | |
843 | { | |
844 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ | |
845 | if (p->vendor == 0x1078 && p->device == 0x0000) { | |
846 | *primary = *secondary = 1; | |
847 | return; | |
848 | } | |
849 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ | |
850 | if (p->vendor == 0x1078 && p->device == 0x0002) { | |
851 | *primary = *secondary = 1; | |
852 | return; | |
853 | } | |
854 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ | |
855 | if (p->vendor == 0x8086 && p->device == 0x1234) { | |
856 | u16 r; | |
857 | pci_read_config_word(p, 0x6C, &r); | |
858 | if (r & 0x8000) { /* ATA port enabled */ | |
859 | if (r & 0x4000) | |
860 | *secondary = 1; | |
861 | else | |
862 | *primary = 1; | |
863 | } | |
864 | return; | |
865 | } | |
866 | } | |
867 | ||
868 | ||
869 | /** | |
870 | * legacy_init - attach legacy interfaces | |
871 | * | |
872 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. | |
873 | * Right now we do not scan the ide0 and ide1 address but should do so | |
874 | * for non PCI systems or systems with no PCI IDE legacy mode devices. | |
875 | * If you fix that note there are special cases to consider like VLB | |
876 | * drivers and CS5510/20. | |
877 | */ | |
878 | ||
879 | static __init int legacy_init(void) | |
880 | { | |
881 | int i; | |
882 | int ct = 0; | |
883 | int primary = 0; | |
884 | int secondary = 0; | |
885 | int last_port = NR_HOST; | |
886 | ||
887 | struct pci_dev *p = NULL; | |
888 | ||
889 | for_each_pci_dev(p) { | |
890 | int r; | |
891 | /* Check for any overlap of the system ATA mappings. Native mode controllers | |
892 | stuck on these addresses or some devices in 'raid' mode won't be found by | |
893 | the storage class test */ | |
894 | for (r = 0; r < 6; r++) { | |
895 | if (pci_resource_start(p, r) == 0x1f0) | |
896 | primary = 1; | |
897 | if (pci_resource_start(p, r) == 0x170) | |
898 | secondary = 1; | |
899 | } | |
900 | /* Check for special cases */ | |
901 | legacy_check_special_cases(p, &primary, &secondary); | |
902 | ||
903 | /* If PCI bus is present then don't probe for tertiary legacy ports */ | |
904 | if (probe_all == 0) | |
905 | last_port = 2; | |
906 | } | |
907 | ||
85cd7251 | 908 | /* If an OPTI 82C46X is present find out where the channels are */ |
669a5db4 JG |
909 | if (opti82c46x) { |
910 | static const char *optis[4] = { | |
911 | "3/463MV", "5MV", | |
912 | "5MVA", "5MVB" | |
913 | }; | |
914 | u8 chans = 1; | |
915 | u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; | |
85cd7251 | 916 | |
669a5db4 JG |
917 | opti82c46x = 3; /* Assume master and slave first */ |
918 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]); | |
919 | if (ctrl == 3) | |
920 | chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; | |
921 | ctrl = opti_syscfg(0xAC); | |
922 | /* Check enabled and this port is the 465MV port. On the | |
923 | MVB we may have two channels */ | |
924 | if (ctrl & 8) { | |
925 | if (ctrl & 4) | |
926 | opti82c46x = 2; /* Slave */ | |
927 | else | |
928 | opti82c46x = 1; /* Master */ | |
929 | if (chans == 2) | |
930 | opti82c46x = 3; /* Master and Slave */ | |
931 | } /* Slave only */ | |
932 | else if (chans == 1) | |
933 | opti82c46x = 1; | |
934 | } | |
935 | ||
936 | for (i = 0; i < last_port; i++) { | |
937 | /* Skip primary if we have seen a PCI one */ | |
938 | if (i == 0 && primary == 1) | |
939 | continue; | |
940 | /* Skip secondary if we have seen a PCI one */ | |
941 | if (i == 1 && secondary == 1) | |
942 | continue; | |
943 | if (legacy_init_one(i, legacy_port[i], | |
944 | legacy_port[i] + 0x0206, | |
945 | legacy_irq[i]) == 0) | |
946 | ct++; | |
947 | } | |
948 | if (ct != 0) | |
949 | return 0; | |
950 | return -ENODEV; | |
951 | } | |
952 | ||
953 | static __exit void legacy_exit(void) | |
954 | { | |
955 | int i; | |
956 | ||
957 | for (i = 0; i < nr_legacy_host; i++) { | |
958 | struct legacy_data *ld = &legacy_data[i]; | |
24dc5f33 TH |
959 | |
960 | ata_host_detach(legacy_host[i]); | |
669a5db4 JG |
961 | platform_device_unregister(ld->platform_dev); |
962 | if (ld->timing) | |
963 | release_region(ld->timing, 2); | |
669a5db4 JG |
964 | } |
965 | } | |
966 | ||
967 | MODULE_AUTHOR("Alan Cox"); | |
968 | MODULE_DESCRIPTION("low-level driver for legacy ATA"); | |
969 | MODULE_LICENSE("GPL"); | |
970 | MODULE_VERSION(DRV_VERSION); | |
971 | ||
972 | module_param(probe_all, int, 0); | |
973 | module_param(autospeed, int, 0); | |
974 | module_param(ht6560a, int, 0); | |
975 | module_param(ht6560b, int, 0); | |
976 | module_param(opti82c611a, int, 0); | |
977 | module_param(opti82c46x, int, 0); | |
978 | module_param(pio_mask, int, 0); | |
f834e49f | 979 | module_param(iordy_mask, int, 0); |
669a5db4 JG |
980 | |
981 | module_init(legacy_init); | |
982 | module_exit(legacy_exit); | |
983 |