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669a5db4 JG |
1 | /* |
2 | * pata-legacy.c - Legacy port PATA/SATA controller driver. | |
3 | * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2, or (at your option) | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; see the file COPYING. If not, write to | |
17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * An ATA driver for the legacy ATA ports. | |
20 | * | |
21 | * Data Sources: | |
22 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com | |
23 | * HT6560 series: | |
24 | * Promise 20230/20620: | |
25 | * http://www.ryston.cz/petr/vlb/pdc20230b.html | |
26 | * http://www.ryston.cz/petr/vlb/pdc20230c.html | |
27 | * http://www.ryston.cz/petr/vlb/pdc20630.html | |
28 | * | |
29 | * Unsupported but docs exist: | |
30 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 | |
31 | * Winbond W83759A | |
32 | * | |
33 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found | |
34 | * on PC class systems. There are three hybrid devices that are exceptions | |
35 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and | |
36 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". | |
37 | * | |
38 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ | |
39 | * opti82c465mv/promise 20230c/20630 | |
40 | * | |
41 | * Use the autospeed and pio_mask options with: | |
42 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. | |
43 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with | |
44 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, | |
45 | * Winbond W83759A, Promise PDC20230-B | |
46 | * | |
47 | * For now use autospeed and pio_mask as above with the W83759A. This may | |
48 | * change. | |
49 | * | |
50 | * TODO | |
51 | * Merge existing pata_qdi driver | |
52 | * | |
53 | */ | |
54 | ||
55 | #include <linux/kernel.h> | |
56 | #include <linux/module.h> | |
57 | #include <linux/pci.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/blkdev.h> | |
60 | #include <linux/delay.h> | |
61 | #include <scsi/scsi_host.h> | |
62 | #include <linux/ata.h> | |
63 | #include <linux/libata.h> | |
64 | #include <linux/platform_device.h> | |
65 | ||
66 | #define DRV_NAME "pata_legacy" | |
67 | #define DRV_VERSION "0.5.3" | |
68 | ||
69 | #define NR_HOST 6 | |
70 | ||
71 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; | |
72 | static int legacy_irq[NR_HOST] = { 15, 14, 11, 10, 8, 12 }; | |
73 | ||
74 | struct legacy_data { | |
75 | unsigned long timing; | |
76 | u8 clock[2]; | |
77 | u8 last; | |
78 | int fast; | |
79 | struct platform_device *platform_dev; | |
80 | ||
81 | }; | |
82 | ||
83 | static struct legacy_data legacy_data[NR_HOST]; | |
84 | static struct ata_host *legacy_host[NR_HOST]; | |
85 | static int nr_legacy_host; | |
86 | ||
87 | ||
88 | static int probe_all; /* Set to check all ISA port ranges */ | |
89 | static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */ | |
90 | static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */ | |
91 | static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */ | |
92 | static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */ | |
93 | static int autospeed; /* Chip present which snoops speed changes */ | |
94 | static int pio_mask = 0x1F; /* PIO range for autospeed devices */ | |
95 | ||
96 | /** | |
97 | * legacy_set_mode - mode setting | |
98 | * @ap: IDE interface | |
b229a7b0 | 99 | * @unused: Device that failed when error is returned |
669a5db4 JG |
100 | * |
101 | * Use a non standard set_mode function. We don't want to be tuned. | |
102 | * | |
103 | * The BIOS configured everything. Our job is not to fiddle. Just use | |
104 | * whatever PIO the hardware is using and leave it at that. When we | |
105 | * get some kind of nice user driven API for control then we can | |
106 | * expand on this as per hdparm in the base kernel. | |
107 | */ | |
108 | ||
b229a7b0 | 109 | static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused) |
669a5db4 JG |
110 | { |
111 | int i; | |
112 | ||
113 | for (i = 0; i < ATA_MAX_DEVICES; i++) { | |
114 | struct ata_device *dev = &ap->device[i]; | |
115 | if (ata_dev_enabled(dev)) { | |
116 | dev->pio_mode = XFER_PIO_0; | |
117 | dev->xfer_mode = XFER_PIO_0; | |
118 | dev->xfer_shift = ATA_SHIFT_PIO; | |
119 | dev->flags |= ATA_DFLAG_PIO; | |
120 | } | |
121 | } | |
b229a7b0 | 122 | return 0; |
669a5db4 JG |
123 | } |
124 | ||
125 | static struct scsi_host_template legacy_sht = { | |
126 | .module = THIS_MODULE, | |
127 | .name = DRV_NAME, | |
128 | .ioctl = ata_scsi_ioctl, | |
129 | .queuecommand = ata_scsi_queuecmd, | |
130 | .can_queue = ATA_DEF_QUEUE, | |
131 | .this_id = ATA_SHT_THIS_ID, | |
132 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
133 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
134 | .emulated = ATA_SHT_EMULATED, | |
135 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
136 | .proc_name = DRV_NAME, | |
137 | .dma_boundary = ATA_DMA_BOUNDARY, | |
138 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 139 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
140 | .bios_param = ata_std_bios_param, |
141 | }; | |
142 | ||
143 | /* | |
144 | * These ops are used if the user indicates the hardware | |
145 | * snoops the commands to decide on the mode and handles the | |
146 | * mode selection "magically" itself. Several legacy controllers | |
147 | * do this. The mode range can be set if it is not 0x1F by setting | |
148 | * pio_mask as well. | |
149 | */ | |
150 | ||
151 | static struct ata_port_operations simple_port_ops = { | |
152 | .port_disable = ata_port_disable, | |
153 | .tf_load = ata_tf_load, | |
154 | .tf_read = ata_tf_read, | |
155 | .check_status = ata_check_status, | |
156 | .exec_command = ata_exec_command, | |
157 | .dev_select = ata_std_dev_select, | |
158 | ||
159 | .freeze = ata_bmdma_freeze, | |
160 | .thaw = ata_bmdma_thaw, | |
161 | .error_handler = ata_bmdma_error_handler, | |
162 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
163 | ||
164 | .qc_prep = ata_qc_prep, | |
165 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 166 | |
0d5ff566 | 167 | .data_xfer = ata_data_xfer_noirq, |
669a5db4 JG |
168 | |
169 | .irq_handler = ata_interrupt, | |
170 | .irq_clear = ata_bmdma_irq_clear, | |
171 | ||
172 | .port_start = ata_port_start, | |
669a5db4 JG |
173 | }; |
174 | ||
175 | static struct ata_port_operations legacy_port_ops = { | |
176 | .set_mode = legacy_set_mode, | |
177 | ||
178 | .port_disable = ata_port_disable, | |
179 | .tf_load = ata_tf_load, | |
180 | .tf_read = ata_tf_read, | |
181 | .check_status = ata_check_status, | |
182 | .exec_command = ata_exec_command, | |
183 | .dev_select = ata_std_dev_select, | |
184 | ||
185 | .error_handler = ata_bmdma_error_handler, | |
186 | ||
187 | .qc_prep = ata_qc_prep, | |
188 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 189 | |
0d5ff566 | 190 | .data_xfer = ata_data_xfer_noirq, |
669a5db4 JG |
191 | |
192 | .irq_handler = ata_interrupt, | |
193 | .irq_clear = ata_bmdma_irq_clear, | |
194 | ||
195 | .port_start = ata_port_start, | |
669a5db4 JG |
196 | }; |
197 | ||
198 | /* | |
199 | * Promise 20230C and 20620 support | |
200 | * | |
201 | * This controller supports PIO0 to PIO2. We set PIO timings conservatively to | |
202 | * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to | |
203 | * controller and PIO'd to the host and not supported. | |
204 | */ | |
205 | ||
206 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
207 | { | |
208 | int tries = 5; | |
209 | int pio = adev->pio_mode - XFER_PIO_0; | |
210 | u8 rt; | |
211 | unsigned long flags; | |
85cd7251 | 212 | |
669a5db4 | 213 | /* Safe as UP only. Force I/Os to occur together */ |
85cd7251 | 214 | |
669a5db4 | 215 | local_irq_save(flags); |
85cd7251 | 216 | |
669a5db4 JG |
217 | /* Unlock the control interface */ |
218 | do | |
219 | { | |
220 | inb(0x1F5); | |
221 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
222 | inb(0x1F2); | |
223 | inb(0x3F6); | |
224 | inb(0x3F6); | |
225 | inb(0x1F2); | |
226 | inb(0x1F2); | |
227 | } | |
228 | while((inb(0x1F2) & 0x80) && --tries); | |
229 | ||
230 | local_irq_restore(flags); | |
85cd7251 | 231 | |
669a5db4 JG |
232 | outb(inb(0x1F4) & 0x07, 0x1F4); |
233 | ||
234 | rt = inb(0x1F3); | |
235 | rt &= 0x07 << (3 * adev->devno); | |
236 | if (pio) | |
237 | rt |= (1 + 3 * pio) << (3 * adev->devno); | |
238 | ||
239 | udelay(100); | |
240 | outb(inb(0x1F2) | 0x01, 0x1F2); | |
241 | udelay(100); | |
242 | inb(0x1F5); | |
243 | ||
244 | } | |
245 | ||
246 | static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data) | |
247 | { | |
248 | struct ata_port *ap = adev->ap; | |
249 | int slop = buflen & 3; | |
250 | unsigned long flags; | |
251 | ||
252 | if (ata_id_has_dword_io(adev->id)) { | |
253 | local_irq_save(flags); | |
254 | ||
255 | /* Perform the 32bit I/O synchronization sequence */ | |
0d5ff566 TH |
256 | ioread8(ap->ioaddr.nsect_addr); |
257 | ioread8(ap->ioaddr.nsect_addr); | |
258 | ioread8(ap->ioaddr.nsect_addr); | |
669a5db4 JG |
259 | |
260 | /* Now the data */ | |
261 | ||
262 | if (write_data) | |
0d5ff566 | 263 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
669a5db4 | 264 | else |
0d5ff566 | 265 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
669a5db4 JG |
266 | |
267 | if (unlikely(slop)) { | |
268 | u32 pad; | |
269 | if (write_data) { | |
270 | memcpy(&pad, buf + buflen - slop, slop); | |
0d5ff566 TH |
271 | pad = le32_to_cpu(pad); |
272 | iowrite32(pad, ap->ioaddr.data_addr); | |
669a5db4 | 273 | } else { |
0d5ff566 TH |
274 | pad = ioread32(ap->ioaddr.data_addr); |
275 | pad = cpu_to_le16(pad); | |
669a5db4 JG |
276 | memcpy(buf + buflen - slop, &pad, slop); |
277 | } | |
278 | } | |
279 | local_irq_restore(flags); | |
280 | } | |
281 | else | |
0d5ff566 | 282 | ata_data_xfer_noirq(adev, buf, buflen, write_data); |
669a5db4 JG |
283 | } |
284 | ||
285 | static struct ata_port_operations pdc20230_port_ops = { | |
286 | .set_piomode = pdc20230_set_piomode, | |
287 | ||
288 | .port_disable = ata_port_disable, | |
289 | .tf_load = ata_tf_load, | |
290 | .tf_read = ata_tf_read, | |
291 | .check_status = ata_check_status, | |
292 | .exec_command = ata_exec_command, | |
293 | .dev_select = ata_std_dev_select, | |
294 | ||
295 | .error_handler = ata_bmdma_error_handler, | |
296 | ||
297 | .qc_prep = ata_qc_prep, | |
298 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 299 | |
669a5db4 JG |
300 | .data_xfer = pdc_data_xfer_vlb, |
301 | ||
302 | .irq_handler = ata_interrupt, | |
303 | .irq_clear = ata_bmdma_irq_clear, | |
304 | ||
305 | .port_start = ata_port_start, | |
669a5db4 JG |
306 | }; |
307 | ||
308 | /* | |
309 | * Holtek 6560A support | |
310 | * | |
311 | * This controller supports PIO0 to PIO2 (no IORDY even though higher timings | |
312 | * can be loaded). | |
313 | */ | |
314 | ||
315 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
316 | { | |
317 | u8 active, recover; | |
318 | struct ata_timing t; | |
319 | ||
320 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
321 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
322 | ||
323 | active = FIT(t.active, 2, 15); | |
324 | recover = FIT(t.recover, 4, 15); | |
325 | ||
326 | inb(0x3E6); | |
327 | inb(0x3E6); | |
328 | inb(0x3E6); | |
329 | inb(0x3E6); | |
330 | ||
0d5ff566 TH |
331 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
332 | ioread8(ap->ioaddr.status_addr); | |
669a5db4 JG |
333 | } |
334 | ||
335 | static struct ata_port_operations ht6560a_port_ops = { | |
336 | .set_piomode = ht6560a_set_piomode, | |
337 | ||
338 | .port_disable = ata_port_disable, | |
339 | .tf_load = ata_tf_load, | |
340 | .tf_read = ata_tf_read, | |
341 | .check_status = ata_check_status, | |
342 | .exec_command = ata_exec_command, | |
343 | .dev_select = ata_std_dev_select, | |
344 | ||
345 | .error_handler = ata_bmdma_error_handler, | |
346 | ||
347 | .qc_prep = ata_qc_prep, | |
348 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 349 | |
0d5ff566 | 350 | .data_xfer = ata_data_xfer, /* Check vlb/noirq */ |
669a5db4 JG |
351 | |
352 | .irq_handler = ata_interrupt, | |
353 | .irq_clear = ata_bmdma_irq_clear, | |
354 | ||
355 | .port_start = ata_port_start, | |
669a5db4 JG |
356 | }; |
357 | ||
358 | /* | |
359 | * Holtek 6560B support | |
360 | * | |
361 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting | |
362 | * unless we see an ATAPI device in which case we force it off. | |
363 | * | |
364 | * FIXME: need to implement 2nd channel support. | |
365 | */ | |
366 | ||
367 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
368 | { | |
369 | u8 active, recover; | |
370 | struct ata_timing t; | |
371 | ||
372 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
373 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
374 | ||
375 | active = FIT(t.active, 2, 15); | |
376 | recover = FIT(t.recover, 2, 16); | |
377 | recover &= 0x15; | |
378 | ||
379 | inb(0x3E6); | |
380 | inb(0x3E6); | |
381 | inb(0x3E6); | |
382 | inb(0x3E6); | |
383 | ||
0d5ff566 | 384 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
669a5db4 JG |
385 | |
386 | if (adev->class != ATA_DEV_ATA) { | |
387 | u8 rconf = inb(0x3E6); | |
388 | if (rconf & 0x24) { | |
389 | rconf &= ~ 0x24; | |
390 | outb(rconf, 0x3E6); | |
391 | } | |
392 | } | |
0d5ff566 | 393 | ioread8(ap->ioaddr.status_addr); |
669a5db4 JG |
394 | } |
395 | ||
396 | static struct ata_port_operations ht6560b_port_ops = { | |
397 | .set_piomode = ht6560b_set_piomode, | |
398 | ||
399 | .port_disable = ata_port_disable, | |
400 | .tf_load = ata_tf_load, | |
401 | .tf_read = ata_tf_read, | |
402 | .check_status = ata_check_status, | |
403 | .exec_command = ata_exec_command, | |
404 | .dev_select = ata_std_dev_select, | |
405 | ||
406 | .error_handler = ata_bmdma_error_handler, | |
407 | ||
408 | .qc_prep = ata_qc_prep, | |
409 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 410 | |
0d5ff566 | 411 | .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */ |
669a5db4 JG |
412 | |
413 | .irq_handler = ata_interrupt, | |
414 | .irq_clear = ata_bmdma_irq_clear, | |
415 | ||
416 | .port_start = ata_port_start, | |
669a5db4 JG |
417 | }; |
418 | ||
419 | /* | |
420 | * Opti core chipset helpers | |
421 | */ | |
85cd7251 | 422 | |
669a5db4 JG |
423 | /** |
424 | * opti_syscfg - read OPTI chipset configuration | |
425 | * @reg: Configuration register to read | |
426 | * | |
427 | * Returns the value of an OPTI system board configuration register. | |
428 | */ | |
429 | ||
430 | static u8 opti_syscfg(u8 reg) | |
431 | { | |
432 | unsigned long flags; | |
433 | u8 r; | |
85cd7251 | 434 | |
669a5db4 JG |
435 | /* Uniprocessor chipset and must force cycles adjancent */ |
436 | local_irq_save(flags); | |
437 | outb(reg, 0x22); | |
438 | r = inb(0x24); | |
439 | local_irq_restore(flags); | |
440 | return r; | |
441 | } | |
442 | ||
443 | /* | |
444 | * Opti 82C611A | |
445 | * | |
446 | * This controller supports PIO0 to PIO3. | |
447 | */ | |
448 | ||
449 | static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
450 | { | |
451 | u8 active, recover, setup; | |
452 | struct ata_timing t; | |
453 | struct ata_device *pair = ata_dev_pair(adev); | |
454 | int clock; | |
455 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
456 | u8 rc; | |
457 | ||
458 | /* Enter configuration mode */ | |
0d5ff566 TH |
459 | ioread16(ap->ioaddr.error_addr); |
460 | ioread16(ap->ioaddr.error_addr); | |
461 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
462 | |
463 | /* Read VLB clock strapping */ | |
0d5ff566 | 464 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
669a5db4 JG |
465 | |
466 | /* Get the timing data in cycles */ | |
467 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
468 | ||
469 | /* Setup timing is shared */ | |
470 | if (pair) { | |
471 | struct ata_timing tp; | |
472 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
473 | ||
474 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
475 | } | |
476 | ||
477 | active = FIT(t.active, 2, 17) - 2; | |
478 | recover = FIT(t.recover, 1, 16) - 1; | |
479 | setup = FIT(t.setup, 1, 4) - 1; | |
480 | ||
481 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 482 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
483 | rc &= 0x7F; |
484 | rc |= (adev->devno << 7); | |
0d5ff566 | 485 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
486 | |
487 | /* Write the timings */ | |
0d5ff566 | 488 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
489 | |
490 | /* Select the right bank for read timings, also | |
491 | load the shared timings for address */ | |
0d5ff566 | 492 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
493 | rc &= 0xC0; |
494 | rc |= adev->devno; /* Index select */ | |
495 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 496 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
497 | |
498 | /* Load the read timings */ | |
0d5ff566 | 499 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
500 | |
501 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 502 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
503 | rc &= 0x73; |
504 | rc |= 0x84; | |
0d5ff566 | 505 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
506 | |
507 | /* Exit command mode */ | |
0d5ff566 | 508 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
509 | } |
510 | ||
511 | ||
512 | static struct ata_port_operations opti82c611a_port_ops = { | |
513 | .set_piomode = opti82c611a_set_piomode, | |
514 | ||
515 | .port_disable = ata_port_disable, | |
516 | .tf_load = ata_tf_load, | |
517 | .tf_read = ata_tf_read, | |
518 | .check_status = ata_check_status, | |
519 | .exec_command = ata_exec_command, | |
520 | .dev_select = ata_std_dev_select, | |
521 | ||
522 | .error_handler = ata_bmdma_error_handler, | |
523 | ||
524 | .qc_prep = ata_qc_prep, | |
525 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 526 | |
0d5ff566 | 527 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
528 | |
529 | .irq_handler = ata_interrupt, | |
530 | .irq_clear = ata_bmdma_irq_clear, | |
531 | ||
532 | .port_start = ata_port_start, | |
669a5db4 JG |
533 | }; |
534 | ||
535 | /* | |
536 | * Opti 82C465MV | |
537 | * | |
538 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB | |
539 | * version is dual channel but doesn't have a lot of unique registers. | |
540 | */ | |
541 | ||
542 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
543 | { | |
544 | u8 active, recover, setup; | |
545 | struct ata_timing t; | |
546 | struct ata_device *pair = ata_dev_pair(adev); | |
547 | int clock; | |
548 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
549 | u8 rc; | |
550 | u8 sysclk; | |
551 | ||
552 | /* Get the clock */ | |
553 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ | |
554 | ||
555 | /* Enter configuration mode */ | |
0d5ff566 TH |
556 | ioread16(ap->ioaddr.error_addr); |
557 | ioread16(ap->ioaddr.error_addr); | |
558 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
559 | |
560 | /* Read VLB clock strapping */ | |
561 | clock = 1000000000 / khz[sysclk]; | |
562 | ||
563 | /* Get the timing data in cycles */ | |
564 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
565 | ||
566 | /* Setup timing is shared */ | |
567 | if (pair) { | |
568 | struct ata_timing tp; | |
569 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
570 | ||
571 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
572 | } | |
573 | ||
574 | active = FIT(t.active, 2, 17) - 2; | |
575 | recover = FIT(t.recover, 1, 16) - 1; | |
576 | setup = FIT(t.setup, 1, 4) - 1; | |
577 | ||
578 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 579 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
580 | rc &= 0x7F; |
581 | rc |= (adev->devno << 7); | |
0d5ff566 | 582 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
583 | |
584 | /* Write the timings */ | |
0d5ff566 | 585 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
586 | |
587 | /* Select the right bank for read timings, also | |
588 | load the shared timings for address */ | |
0d5ff566 | 589 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
590 | rc &= 0xC0; |
591 | rc |= adev->devno; /* Index select */ | |
592 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 593 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
594 | |
595 | /* Load the read timings */ | |
0d5ff566 | 596 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
597 | |
598 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 599 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
600 | rc &= 0x73; |
601 | rc |= 0x84; | |
0d5ff566 | 602 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
603 | |
604 | /* Exit command mode */ | |
0d5ff566 | 605 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
606 | |
607 | /* We need to know this for quad device on the MVB */ | |
608 | ap->host->private_data = ap; | |
609 | } | |
610 | ||
611 | /** | |
612 | * opt82c465mv_qc_issue_prot - command issue | |
613 | * @qc: command pending | |
614 | * | |
615 | * Called when the libata layer is about to issue a command. We wrap | |
616 | * this interface so that we can load the correct ATA timings. The | |
617 | * MVB has a single set of timing registers and these are shared | |
618 | * across channels. As there are two registers we really ought to | |
619 | * track the last two used values as a sort of register window. For | |
620 | * now we just reload on a channel switch. On the single channel | |
621 | * setup this condition never fires so we do nothing extra. | |
622 | * | |
623 | * FIXME: dual channel needs ->serialize support | |
624 | */ | |
625 | ||
626 | static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc) | |
627 | { | |
628 | struct ata_port *ap = qc->ap; | |
629 | struct ata_device *adev = qc->dev; | |
630 | ||
631 | /* If timings are set and for the wrong channel (2nd test is | |
632 | due to a libata shortcoming and will eventually go I hope) */ | |
633 | if (ap->host->private_data != ap->host | |
634 | && ap->host->private_data != NULL) | |
635 | opti82c46x_set_piomode(ap, adev); | |
636 | ||
637 | return ata_qc_issue_prot(qc); | |
638 | } | |
639 | ||
640 | static struct ata_port_operations opti82c46x_port_ops = { | |
641 | .set_piomode = opti82c46x_set_piomode, | |
642 | ||
643 | .port_disable = ata_port_disable, | |
644 | .tf_load = ata_tf_load, | |
645 | .tf_read = ata_tf_read, | |
646 | .check_status = ata_check_status, | |
647 | .exec_command = ata_exec_command, | |
648 | .dev_select = ata_std_dev_select, | |
649 | ||
650 | .error_handler = ata_bmdma_error_handler, | |
651 | ||
652 | .qc_prep = ata_qc_prep, | |
653 | .qc_issue = opti82c46x_qc_issue_prot, | |
bda30288 | 654 | |
0d5ff566 | 655 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
656 | |
657 | .irq_handler = ata_interrupt, | |
658 | .irq_clear = ata_bmdma_irq_clear, | |
659 | ||
660 | .port_start = ata_port_start, | |
669a5db4 JG |
661 | }; |
662 | ||
663 | ||
664 | /** | |
665 | * legacy_init_one - attach a legacy interface | |
666 | * @port: port number | |
667 | * @io: I/O port start | |
668 | * @ctrl: control port | |
669 | * @irq: interrupt line | |
670 | * | |
671 | * Register an ISA bus IDE interface. Such interfaces are PIO and we | |
672 | * assume do not support IRQ sharing. | |
673 | */ | |
674 | ||
675 | static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq) | |
676 | { | |
677 | struct legacy_data *ld = &legacy_data[nr_legacy_host]; | |
678 | struct ata_probe_ent ae; | |
679 | struct platform_device *pdev; | |
669a5db4 | 680 | struct ata_port_operations *ops = &legacy_port_ops; |
0d5ff566 | 681 | void __iomem *io_addr, *ctrl_addr; |
669a5db4 JG |
682 | int pio_modes = pio_mask; |
683 | u32 mask = (1 << port); | |
24dc5f33 | 684 | int ret; |
669a5db4 JG |
685 | |
686 | pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0); | |
24dc5f33 TH |
687 | if (IS_ERR(pdev)) |
688 | return PTR_ERR(pdev); | |
689 | ||
690 | ret = -EBUSY; | |
691 | if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || | |
692 | devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL) | |
693 | goto fail; | |
669a5db4 | 694 | |
0d5ff566 TH |
695 | ret = -ENOMEM; |
696 | io_addr = devm_ioport_map(&pdev->dev, io, 8); | |
697 | ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1); | |
698 | if (!io_addr || !ctrl_addr) | |
699 | goto fail; | |
700 | ||
669a5db4 JG |
701 | if (ht6560a & mask) { |
702 | ops = &ht6560a_port_ops; | |
703 | pio_modes = 0x07; | |
704 | } | |
705 | if (ht6560b & mask) { | |
706 | ops = &ht6560b_port_ops; | |
707 | pio_modes = 0x1F; | |
708 | } | |
709 | if (opti82c611a & mask) { | |
710 | ops = &opti82c611a_port_ops; | |
711 | pio_modes = 0x0F; | |
712 | } | |
713 | if (opti82c46x & mask) { | |
714 | ops = &opti82c46x_port_ops; | |
715 | pio_modes = 0x0F; | |
716 | } | |
717 | ||
718 | /* Probe for automatically detectable controllers */ | |
85cd7251 | 719 | |
669a5db4 JG |
720 | if (io == 0x1F0 && ops == &legacy_port_ops) { |
721 | unsigned long flags; | |
722 | ||
723 | local_irq_save(flags); | |
724 | ||
725 | /* Probes */ | |
726 | inb(0x1F5); | |
727 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
728 | inb(0x1F2); | |
729 | inb(0x3F6); | |
730 | inb(0x3F6); | |
731 | inb(0x1F2); | |
732 | inb(0x1F2); | |
733 | ||
734 | if ((inb(0x1F2) & 0x80) == 0) { | |
735 | /* PDC20230c or 20630 ? */ | |
736 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n"); | |
737 | pio_modes = 0x07; | |
738 | ops = &pdc20230_port_ops; | |
739 | udelay(100); | |
740 | inb(0x1F5); | |
741 | } else { | |
742 | outb(0x55, 0x1F2); | |
743 | inb(0x1F2); | |
744 | inb(0x1F2); | |
745 | if (inb(0x1F2) == 0x00) { | |
746 | printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n"); | |
747 | } | |
748 | } | |
749 | local_irq_restore(flags); | |
750 | } | |
751 | ||
752 | ||
753 | /* Chip does mode setting by command snooping */ | |
754 | if (ops == &legacy_port_ops && (autospeed & mask)) | |
755 | ops = &simple_port_ops; | |
756 | memset(&ae, 0, sizeof(struct ata_probe_ent)); | |
757 | INIT_LIST_HEAD(&ae.node); | |
758 | ae.dev = &pdev->dev; | |
759 | ae.port_ops = ops; | |
760 | ae.sht = &legacy_sht; | |
761 | ae.n_ports = 1; | |
762 | ae.pio_mask = pio_modes; | |
763 | ae.irq = irq; | |
764 | ae.irq_flags = 0; | |
765 | ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST; | |
0d5ff566 TH |
766 | ae.port[0].cmd_addr = io_addr; |
767 | ae.port[0].altstatus_addr = ctrl_addr; | |
768 | ae.port[0].ctl_addr = ctrl_addr; | |
669a5db4 JG |
769 | ata_std_ports(&ae.port[0]); |
770 | ae.private_data = ld; | |
771 | ||
24dc5f33 TH |
772 | ret = -ENODEV; |
773 | if (!ata_device_add(&ae)) | |
669a5db4 | 774 | goto fail; |
24dc5f33 | 775 | |
669a5db4 JG |
776 | legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev); |
777 | ld->platform_dev = pdev; | |
778 | return 0; | |
779 | ||
780 | fail: | |
781 | platform_device_unregister(pdev); | |
669a5db4 JG |
782 | return ret; |
783 | } | |
784 | ||
785 | /** | |
786 | * legacy_check_special_cases - ATA special cases | |
787 | * @p: PCI device to check | |
788 | * @master: set this if we find an ATA master | |
789 | * @master: set this if we find an ATA secondary | |
790 | * | |
791 | * A small number of vendors implemented early PCI ATA interfaces on bridge logic | |
792 | * without the ATA interface being PCI visible. Where we have a matching PCI driver | |
793 | * we must skip the relevant device here. If we don't know about it then the legacy | |
794 | * driver is the right driver anyway. | |
795 | */ | |
796 | ||
797 | static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary) | |
798 | { | |
799 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ | |
800 | if (p->vendor == 0x1078 && p->device == 0x0000) { | |
801 | *primary = *secondary = 1; | |
802 | return; | |
803 | } | |
804 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ | |
805 | if (p->vendor == 0x1078 && p->device == 0x0002) { | |
806 | *primary = *secondary = 1; | |
807 | return; | |
808 | } | |
809 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ | |
810 | if (p->vendor == 0x8086 && p->device == 0x1234) { | |
811 | u16 r; | |
812 | pci_read_config_word(p, 0x6C, &r); | |
813 | if (r & 0x8000) { /* ATA port enabled */ | |
814 | if (r & 0x4000) | |
815 | *secondary = 1; | |
816 | else | |
817 | *primary = 1; | |
818 | } | |
819 | return; | |
820 | } | |
821 | } | |
822 | ||
823 | ||
824 | /** | |
825 | * legacy_init - attach legacy interfaces | |
826 | * | |
827 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. | |
828 | * Right now we do not scan the ide0 and ide1 address but should do so | |
829 | * for non PCI systems or systems with no PCI IDE legacy mode devices. | |
830 | * If you fix that note there are special cases to consider like VLB | |
831 | * drivers and CS5510/20. | |
832 | */ | |
833 | ||
834 | static __init int legacy_init(void) | |
835 | { | |
836 | int i; | |
837 | int ct = 0; | |
838 | int primary = 0; | |
839 | int secondary = 0; | |
840 | int last_port = NR_HOST; | |
841 | ||
842 | struct pci_dev *p = NULL; | |
843 | ||
844 | for_each_pci_dev(p) { | |
845 | int r; | |
846 | /* Check for any overlap of the system ATA mappings. Native mode controllers | |
847 | stuck on these addresses or some devices in 'raid' mode won't be found by | |
848 | the storage class test */ | |
849 | for (r = 0; r < 6; r++) { | |
850 | if (pci_resource_start(p, r) == 0x1f0) | |
851 | primary = 1; | |
852 | if (pci_resource_start(p, r) == 0x170) | |
853 | secondary = 1; | |
854 | } | |
855 | /* Check for special cases */ | |
856 | legacy_check_special_cases(p, &primary, &secondary); | |
857 | ||
858 | /* If PCI bus is present then don't probe for tertiary legacy ports */ | |
859 | if (probe_all == 0) | |
860 | last_port = 2; | |
861 | } | |
862 | ||
85cd7251 | 863 | /* If an OPTI 82C46X is present find out where the channels are */ |
669a5db4 JG |
864 | if (opti82c46x) { |
865 | static const char *optis[4] = { | |
866 | "3/463MV", "5MV", | |
867 | "5MVA", "5MVB" | |
868 | }; | |
869 | u8 chans = 1; | |
870 | u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; | |
85cd7251 | 871 | |
669a5db4 JG |
872 | opti82c46x = 3; /* Assume master and slave first */ |
873 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]); | |
874 | if (ctrl == 3) | |
875 | chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; | |
876 | ctrl = opti_syscfg(0xAC); | |
877 | /* Check enabled and this port is the 465MV port. On the | |
878 | MVB we may have two channels */ | |
879 | if (ctrl & 8) { | |
880 | if (ctrl & 4) | |
881 | opti82c46x = 2; /* Slave */ | |
882 | else | |
883 | opti82c46x = 1; /* Master */ | |
884 | if (chans == 2) | |
885 | opti82c46x = 3; /* Master and Slave */ | |
886 | } /* Slave only */ | |
887 | else if (chans == 1) | |
888 | opti82c46x = 1; | |
889 | } | |
890 | ||
891 | for (i = 0; i < last_port; i++) { | |
892 | /* Skip primary if we have seen a PCI one */ | |
893 | if (i == 0 && primary == 1) | |
894 | continue; | |
895 | /* Skip secondary if we have seen a PCI one */ | |
896 | if (i == 1 && secondary == 1) | |
897 | continue; | |
898 | if (legacy_init_one(i, legacy_port[i], | |
899 | legacy_port[i] + 0x0206, | |
900 | legacy_irq[i]) == 0) | |
901 | ct++; | |
902 | } | |
903 | if (ct != 0) | |
904 | return 0; | |
905 | return -ENODEV; | |
906 | } | |
907 | ||
908 | static __exit void legacy_exit(void) | |
909 | { | |
910 | int i; | |
911 | ||
912 | for (i = 0; i < nr_legacy_host; i++) { | |
913 | struct legacy_data *ld = &legacy_data[i]; | |
24dc5f33 TH |
914 | |
915 | ata_host_detach(legacy_host[i]); | |
669a5db4 JG |
916 | platform_device_unregister(ld->platform_dev); |
917 | if (ld->timing) | |
918 | release_region(ld->timing, 2); | |
669a5db4 JG |
919 | } |
920 | } | |
921 | ||
922 | MODULE_AUTHOR("Alan Cox"); | |
923 | MODULE_DESCRIPTION("low-level driver for legacy ATA"); | |
924 | MODULE_LICENSE("GPL"); | |
925 | MODULE_VERSION(DRV_VERSION); | |
926 | ||
927 | module_param(probe_all, int, 0); | |
928 | module_param(autospeed, int, 0); | |
929 | module_param(ht6560a, int, 0); | |
930 | module_param(ht6560b, int, 0); | |
931 | module_param(opti82c611a, int, 0); | |
932 | module_param(opti82c46x, int, 0); | |
933 | module_param(pio_mask, int, 0); | |
934 | ||
935 | module_init(legacy_init); | |
936 | module_exit(legacy_exit); | |
937 |